NEC 78K-0 User Manual
User’s Manual
78K/0 Series
Instructions
Common to 78K/0 Series
Document No. U12326EJ4V0UM00 (4th edition)
Date Published October 2001 N CP(K)
©
Printed in Japan
1995
[MEMO]
2
User's Manual U12326EJ4V0UM
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Caution: Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I
defined by Philips.
IEBus is a trademark of NEC Corporation.
2
C system, provided that the system conforms to the I2C Standard Specification as
User's Manual U12326EJ4V0UM
3
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
•
The information in this document is current as of August, 2001. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
•
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
•
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
•
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
4
User's Manual U12326EJ4V0UM
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.l.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-3067-5800
Fax: 01-3067-5899
NEC Electronics (France) S.A.
Madrid Office
Madrid, Spain
Tel: 091-504-2787
Fax: 091-504-2860
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 253-8311
Fax: 250-3583
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP, Brasil
Tel: 11-6462-6810
Fax: 11-6462-6829
User's Manual U12326EJ4V0UM
J01.2
5
Major Revisions in This Edition
Page Description
Throughout Deletion of all information except for information common to
the 78K/0 Series (for individual product information, refer to the
user’s manual of each product).
The mark shows major revised points.
6
User's Manual U12326EJ4V0UM
INTRODUCTION
Target Readers This manual is intended for users who wish to understand the functions of
78K/0 Series products and to design and develop its application systems and
programs.
Purpose This manual is intended to give users an understanding of the various kinds of
instruction functions of 78K/0 Series products.
Organization This manual is broadly divided into the following sections.
• CPU functions
• Instruction set
• Explanation of instructions
How to Read This Manual It is assumed that readers of this manual have general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
• To check the details of the functions of an instruction whose mnemonic is known:
→ Refer to APPENDICES B and C.
• To check an instruction whose mnemonic is not known but whose general
function is known:
→ Find the mnemonic in CHAPTER 4 INSTRUCTION SET and then check the
detailed functions in CHAPTER 5 EXPLANATION OF INSTRUCTIONS.
• To learn about the various kinds of 78K/0 Series product instructions in general:
→ Read this manual in the order of CONTENTS.
• To learn about the hardware functions of 78K/0 Series products:
→ See the separate user’s manuals.
Conventions Data significance: Higher digits on the left and lower digits on the right
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numeral representation: Binary................. XXXX or XXXXB
Decimal .............. XXXX
Hexadecimal...... XXXXH
User's Manual U12326EJ4V0UM
7
Related Documents
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
• Documents Common to 78K/0 Series
Document Name Document No.
User’s Manual Instructions This manual
Application Note
Note
Basic I U12704E
Basic II U10121E
Basic III U10182E
Note Some subseries may not be covered.
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
8
User's Manual U12326EJ4V0UM
CONTENTS
CHAPTER 1 MEMORY SPACE ...............................................................................................................12
1.1 Memory Spaces ................................................................................................................12
1.2 Internal Program Memory (Internal ROM) Space .......................................................... 12
1.3 Vector Table Area ............................................................................................................. 12
1.4 CALLT Instruction Table Area.........................................................................................12
1.5 CALLF Instruction Entry Area ......................................................................................... 12
1.6 Internal Data Memory (Internal RAM) Space..................................................................12
1.7 Special Function Register (SFR) Area............................................................................13
1.8 External Memory Space ................................................................................................... 13
TM
1.9 IEBus
Register Area ...................................................................................................... 13
CHAPTER 2 REGISTERS ........................................................................................................................14
2.1 Control Registers .............................................................................................................14
2.1.1 Program counter (PC) ......................................................................................................... 14
2.1.2 Program status word (PSW) ............................................................................................... 14
2.1.3 Stack pointer (SP)................................................................................................................ 16
2.2 General-Purpose Registers .............................................................................................17
2.3 Special Function Registers (SFRs).................................................................................19
CHAPTER 3 ADDRESSING ..................................................................................................................... 20
3.1 Instruction Address Addressing.....................................................................................20
3.1.1 Relative addressing............................................................................................................. 20
3.1.2 Immediate addressing......................................................................................................... 21
3.1.3 Table indirect addressing ................................................................................................... 22
3.1.4 Register addressing ............................................................................................................ 23
3.2 Operand Address Addressing ........................................................................................ 24
3.2.1 Implied addressing .............................................................................................................. 24
3.2.2 Register addressing ............................................................................................................ 25
3.2.3 Direct addressing ................................................................................................................ 26
3.2.4 Short direct addressing ...................................................................................................... 27
3.2.5 Special-function register (SFR) addressing...................................................................... 28
3.2.6 Register indirect addressing .............................................................................................. 29
3.2.7 Based addressing................................................................................................................ 30
3.2.8 Based indexed addressing ................................................................................................. 30
3.2.9 Stack addressing ................................................................................................................. 31
CHAPTER 4 INSTRUCTION SET ............................................................................................................32
4.1 Operation .......................................................................................................................... 32
4.1.1 Operand identifiers and description methods .................................................................. 32
4.1.2 Description of “operation” column.................................................................................... 33
4.1.3 Description of “flag operation” column ............................................................................ 33
4.1.4 Description of number of clocks........................................................................................ 34
4.1.5 Instructions listed by addressing type .............................................................................. 34
4.2 Instruction Codes ............................................................................................................. 38
4.2.1 Description of instruction code table ................................................................................ 38
4.2.2 Instruction code list............................................................................................................. 39
User's Manual U12326EJ4V0UM
9
CHAPTER 5 EXPLANATION OF INSTRUCTIONS .................................................................................46
5.1 8-Bit Data Transfer Instructions......................................................................................48
5.2 16-Bit Data Transfer Instructions....................................................................................51
5.3 8-Bit Operation Instructions ............................................................................................ 54
5.4 16-Bit Operation Instructions .......................................................................................... 63
5.5 Multiply/Divide Instructions ............................................................................................ 67
5.6 Increment/Decrement Instructions .................................................................................70
5.7 Rotate Instructions...........................................................................................................75
5.8 BCD Adjust Instructions .................................................................................................. 82
5.9 Bit Manipulation Instructions .......................................................................................... 85
5.10 Call Return Instructions ...................................................................................................93
5.11 Stack Manipulation Instructions ................................................................................... 101
5.12 Unconditional Branch Instruction ................................................................................105
5.13 Conditional Branch Instructions ...................................................................................107
5.14 CPU Control Instructions ..............................................................................................116
APPENDIX A REVISION HISTORY .....................................................................................................123
APPENDIX B INSTRUCTION INDEX (MNEMONIC: BY FUNCTION) ............................................. 124
APPENDIX C INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER) ...................... 126
10 User's Manual U12326EJ4V0UM
LIST OF FIGURES
Figure No. Title Page
2-1 Program Counter Configuration.............................................................................................................. 14
2-2 Program Status Word Configuration....................................................................................................... 14
2-3 Stack Pointer Configuration .................................................................................................................... 16
2-4 Data to Be Saved to Stack Memory ....................................................................................................... 16
2-5 Data to Be Reset from Stack Memory .................................................................................................... 16
2-6 General-Purpose Register Configuration ............................................................................................... 18
LIST OF TABLES
Table No. Title Page
2-1 General-Purpose Register Absolute Address Correspondence Table ..................................................... 17
4-1 Operand Identifiers and Description Methods .......................................................................................... 32
User's Manual U12326EJ4V0UM
11
CHAPTER 1 MEMORY SPACE
1.1 Memory Spaces
The 78K/0 Series product program memory map varies depending on the internal memory capacity. For details
of memory-mapped address area, refer to the user’s manual of each product.
1.2 Internal Program Memory (Internal ROM) Space
Each 78K/0 Series product has internal ROM in the address space. Program and table data, etc. are stored
in the ROM. Normally, this memory space is addressed by the program counter (PC). For details of the internal
ROM space, refer to the user’s manual of each product.
1.3 Vector Table Area
The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch
upon RESET input or interrupt request generation are stored in the vector table area. Of the 16-bit address, the
lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. For the vector table
area, refer to the user’s manual of each product.
1.4 CALLT Instruction Table Area
The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).
1.5 CALLF Instruction Entry Area
The 2048-byte area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).
1.6 Internal Data Memory (Internal RAM) Space
78K/0 Series products incorporate the following RAMs. For details of these RAMs, refer to the user’s manual
of each product.
(1) Internal high-speed RAM
Each 78K/0 Series product incorporates an internal high-speed RAM. In the 32-byte area FEE0H to FEFFH
of these areas, 4 banks of general-purpose registers, each bank consisting of eight 8-bit registers, are
allocated.
The internal high-speed RAM can also be used as a stack memory.
(2) Buffer RAM
There are some products in the 78K/0 Series to which buffer RAM is allocated. This RAM is used to store
the transfer/receive data of serial interface channel 1 (3-wire serial I/O mode with automatic transfer/receive
function). If not used in this mode, the buffer RAM can also be used as an ordinary RAM area.
12
User's Manual U12326EJ4V0UM
CHAPTER 1 MEMORY SPACE
(3) RAM for VFD display
There are some products in the 78K/0 Series to which RAM for VFD display is allocated. This RAM can
also be used as an ordinary RAM area.
(4) Internal expansion RAM
There are some products in the 78K/0 Series to which internal expansion RAM is allocated.
(5) RAM for LCD display
There are some products in the 78K/0 Series to which RAM for LCD display is allocated. This RAM can
also be used as an ordinary RAM area.
1.7 Special Function Register (SFR) Area
On-chip peripheral hardware special function registers (SFRs) are allocated in the area FF00H to FFFFH (for
details of the special function registers, refer to the user’s manual of each product).
Caution Do not access addresses to which SFRs are not allocated. If an address is erroneously
accessed, the CPU may become deadlocked.
1.8 External Memory Space
This is an external memory space that can be accessed by setting the memory extension mode register. This
space can store program and table data, and be assigned peripheral devices.
For details of the products in which an external memory space can be used, refer to the user’s manual of each
product.
1.9 IEBusTM Register Area
IEBus registers that are used to control the IEBus controller are allocated to the IEBus register area.
For details of the products that incorporate an IEBus controller, refer to the user’s manual of each product.
User's Manual U12326EJ4V0UM
13
CHAPTER 2 REGISTERS
2.1 Control Registers
The control registers control the program sequence, statuses and stack memory. A program counter, a program
status word and a stack pointer are the control registers.
2.1.1 Program counter (PC)
The program counter is a 16-bit register that holds the address information of the next program to be executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction
to be fetched. When a branch instruction is executed, immediate data and register contents are set.
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 2-1. Program Counter Configuration
15 0
PC
2.1.2 Program status word (PSW)
The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.
Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW
instruction execution and are automatically reset upon execution of the RETB, RETI and POP PSW instructions.
RESET input sets the PSW to 02H.
Figure 2-2. Program Status Word Configuration
70
IE
Z RBS1 AC RBS0 0 ISP CY
14
User's Manual U12326EJ4V0UM
CHAPTER 2 REGISTERS
(1) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledgement operations of the CPU.
When IE = 0, the IE flag is set to interrupt disable (DI), and interrupts other than non-maskable interrupts
are all disabled.
When IE = 1, the IE flag is set to interrupt enable (EI), and interrupt request acknowledgement is controlled
by an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority
specification flag.
This flag is reset (0) upon DI instruction execution or interrupt request acknowledgment and is set (1) upon
execution of the EI instruction.
(2) Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
(3) Register bank select flags (RBS0 and RBS1)
These are 2-bit flags used to select one of the four register banks.
In these flags, the 2-bit information that indicates the register bank selected by SBL RBn instruction
execution is stored.
(4) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other
cases.
(5) In-service priority flag (ISP)
This flag manages the priority of acknowledgeable maskable vectored interrupts. When ISP = 0, vectored
interrupt requests specified as low priority by the priority specification flag register (PR) are disabled for
acknowledgment. Actual acknowledgment for interrupt requests is controlled by the state of the interrupt
enable flag (IE).
(6) Carry flag (CY)
This flag stores an overflow or underflow upon add/subtract instruction execution. It stores the shift-out
value upon rotate instruction execution and functions as a bit accumulator during bit manipulation
instruction execution.
User's Manual U12326EJ4V0UM
15
CHAPTER 2 REGISTERS
2.1.3 Stack pointer (SP)
This is a 16-bit register that holds the start address of the memory stack area. Only the internal high-speed
RAM area can be set as the stack area.
Figure 2-3. Stack Pointer Configuration
15 0
SP
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from
the stack memory.
Each stack operation saves/resets data as shown in Figures 2-4 and 2-5.
Caution Since RESET input makes SP contents undefined, be sure to initialize the SP before instruction
execution.
Figure 2-4. Data to Be Saved to Stack Memory
SP SP _ 2
SP _ 2
SP _ 1
SP
PUSH rp
instruction
Lower half
register pairs
Upper half
register pairs
Figure 2-5. Data to Be Reset from Stack Memory
instruction
SP SP _ 2
SP _ 2
SP _ 1
SP
CALL, CALLF and
CALLT instructions
PC7-PC0
PC15-PC8
RET instructionPOP rp
SP SP _ 3
SP _ 3
SP _ 2
SP _ 1
SP
Interrupt and
BRK instructions
PC7-PC0
PC15-PC8
PSW
RETI and RETB
instructions
SP SP + 2
16
SP
SP + 1
Lower half
register pairs
Upper half
register pairs
SP
SP + 1
SP SP + 2
User's Manual U12326EJ4V0UM
PC7-PC0
PC15-PC8
SP
SP + 1
SP + 2
SP SP + 3
PC7-PC0
PC15-PC8
PSW
CHAPTER 2 REGISTERS
2.2 General-Purpose Registers
General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. These
registers consist of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L and H).
In addition that each register can be used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-
bit register (AX, BC, DE and HL).
General-purpose registers can be described in terms of functional names (X, A, C, B, E, D, L, H, AX, BC, DE
and HL) and absolute names (R0 to R7 and RP0 to RP3).
Register banks to be used for instruction execution are set with the CPU control instruction (SEL RBn). Because
of the 4-register bank configuration, an efficient program can be created by switching between a register for normal
processing and a register for processing upon interrupt generation for each bank.
Table 2-1. General-Purpose Register Absolute Address Correspondence Table
Bank Name Register Absolute Address Bank Name Register Absolute Address
Functional Absolute Functional Absolute
Name Name Name Name
BANK0 H R7 FEFFH BANK2 H R7 FEEFH
L R6 FEFEH L R6 FEEEH
D R5 FEFDH D R5 FEEDH
E R4 FEFCH E R4 FEECH
B R3 FEFBH B R3 FEEBH
C R2 FEFAH C R2 FEEAH
A R1 FEF9H A R1 FEE9H
X R0 FEF8H X R0 FEE8H
BANK1 H R7 FEF7H BANK3 H R7 FEE7H
L R6 FEF6H L R6 FEE6H
D R5 FEF5H D R5 FEE5H
E R4 FEF4H E R4 FEE4H
B R3 FEF3H B R3 FEE3H
C R2 FEF2H C R2 FEE2H
A R1 FEF1H A R1 FEE1H
X R0 FEF0H X R0 FEE0H
User's Manual U12326EJ4V0UM
17
FEFFH
FEF8H
FEF7H
FEF0H
FEEFH
FEE8H
FEE7H
FEE0H
BANK0
BANK1
BANK2
BANK3
CHAPTER 2 REGISTERS
Figure 2-6. General-Purpose Register Configuration
(a) Absolute names
16-bit processing 8-bit processing
R7
RP3
R6
R5
RP2
R4
R3
RP1
R2
R1
RP0
R0
15 0 7 0
FEFFH
FEF8H
FEF7H
FEF0H
FEEFH
FEE8H
FEE7H
FEE0H
BANK0
BANK1
BANK2
BANK3
(b) Functional names
16-bit processing 8-bit processing
H
HL
L
D
DE
E
B
BC
C
A
AX
X
15 0 7 0
18
User's Manual U12326EJ4V0UM
CHAPTER 2 REGISTERS
2.3 Special Function Registers (SFRs)
Unlike a general-purpose register, each special-function register has a special function.
Special function registers are allocated in the 256-byte area FF00H to FFFFH.
Special function registers can be manipulated, like general-purpose registers, by operation, transfer and bit
manipulation instructions. The manipulatable bit units (1, 8, and 16) differ depending on the special function
register type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describes a symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This
manipulation can also be specified by an address.
• 8-bit manipulation
Describes a symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This
manipulation can also be specified by an address.
• 16-bit manipulation
Describes a symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp). When
addressing an address, describe an even address.
For details of the special function registers, refer to the user’s manual of each product.
Caution Do not access addresses to which SFRs are not allocated. If an address is erroneously
accessed, the CPU may become deadlocked.
User's Manual U12326EJ4V0UM
19
CHAPTER 3 ADDRESSING
3.1 Instruction Address Addressing
An instruction address is determined by program counter (PC) contents. The PC contents are normally
incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each
time another instruction is executed. When a branch instruction is executed, the branch destination information
is set to the PC and branched by the following addressing (for details of each instruction, refer to CHAPTER 5
EXPLANATION OF INSTRUCTIONS).
3.1.1 Relative addressing
[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to
the start address of the following instruction is transferred to the program counter (PC) and branched. The
displacement value is treated as signed two’s complement data (–128 to +127) and bit 7 becomes a sign
bit. In other words, in relative addressing, the value is relatively transferred to the range between –128 and
+127 from the start address of the following instruction.
This function is carried out when the “BR $addr16” instruction or a conditional branch instruction is executed.
[Illustration]
PC
15 0
PC
+
15 0
α
15 0
When S = 0, α indicates all bits "0".
When S = 1, α indicates all bits "1".
87 6
S
jdisp8
...
PC is the start address of
the next instruction of
a BR instruction.
20
User's Manual U12326EJ4V0UM
CHAPTER 3 ADDRESSING
3.1.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) and branched.
This function is carried out when the “CALL !addr16” or “BR !addr16” or “CALLF !addr11” instruction is
executed. The CALL !addr16 and BR !addr16 instructions can be branched to all memory spaces. The
CALLF !addr11 instruction is branched to the area of 0800H to 0FFFH.
[Illustration]
CALL !addr16, BR !addr16 instruction
70
CALL or BR
Low Addr.
High Addr.
PC
CALLF !addr11 instruction
PC
15 0
70
643
fa
10
to fa
8
CALLF
7
to fa
0
fa
15 0
11 10
87
87
00001
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CHAPTER 3 ADDRESSING
3.1.3 Table indirect addressing
[Function]
Table contents (branch destination address) of the particular location to be addressed by the lower-5-bit
immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and
branched.
When the “CALLT [addr5]” instruction is executed, table indirect addressing is performed. Executing this
instruction enables the value to be branched to all memory spaces referencing the address stored in the
memory table of 40H to 7FH.
[Illustration]
765 10
Instruction code
ta
4–0
111
Effective address
Effective address+1
15 1
00000000
01
70
Memory (Table)
Low addr.
High addr.
15 0
PC
87
65 0
87
0
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CHAPTER 3 ADDRESSING
3.1.4 Register addressing
[Function]
The register pair (AX) contents to be specified by an instruction word are transferred to the program counter
(PC) and branched.
This function is carried out when the “BR AX” instruction is executed.
[Illustration]
70
rp
15 0
PC
AX
07
87
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CHAPTER 3 ADDRESSING
3.2 Operand Address Addressing
The following methods are available to specify the register and memory (addressing) to undergo manipulation
during instruction execution.
3.2.1 Implied addressing
[Function]
This addressing automatically specifies the address of the registers that function as an accumulator (A and
AX) in the general-purpose register area.
Of the 78K/0 Series instruction words, the following instructions employ implied addressing.
Instruction Register to Be Specified by Implied Addressing
MULU A register for multiplicand and AX register for product storage
DIVUW AX register for dividend and quotient storage
ADJBA/ADJBS A register for storage of numeric values targeted for decimal correction
ROR4/ROL4 A register for storage of digit data that undergoes digit rotation
[Operand format]
Because implied addressing can be automatically employed with an instruction, no particular operand format
is necessary.
[Description example]
In the case of MULU X
With an 8-bit x 8-bit multiply instruction, the product of the A register and X register is stored in AX. In this
example, the A and AX registers are specified by implied addressing.
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CHAPTER 3 ADDRESSING
3.2.2 Register addressing
[Function]
Register addressing accesses a general-purpose register as an operand. The general-purpose register to
be accessed is specified by the register bank selection flags (RBS0 and RBS1) and the register specification
codes (Rn and RPn) in the instruction codes.
Register addressing is carried out when an instruction with the following operand format is executed. When
an 8-bit register is specified, one of the eight registers is specified by 3 bits in the instruction code.
[Operand format]
Identifier Description
r X, A, C, B, E, D, L, H
rp AX, BC, DE, HL
‘r’ and ‘rp’ can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names
(X, A, C, B, E, D, L, H, AX, BC, DE and HL).
[Description example]
MOV A, C; When selecting the C register for r
Instruction code 01100010
INCW DE; When selecting the DE register pair for rp
Instruction code 10000100
Register specification code
Register specification code
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CHAPTER 3 ADDRESSING
3.2.3 Direct addressing
[Function]
Direct addressing directly addresses the memory indicated by the immediate data in the instruction word.
[Operand format]
Identifier Description
addr16 Label or 16-bit immediate data
[Description example]
MOV A, !FE00H; When setting !addr16 to FE00H
Instruction code 1 0 001110OP code
0000000000H
11111110FEH
[Illustration]
07
OP code
addr16 (lower)
addr16 (upper)
Memory
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CHAPTER 3 ADDRESSING
3.2.4 Short direct addressing
[Function]
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
This addressing is applied to the 256-byte fixed space FE20H to FF1FH. An internal high-speed RAM and
special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the entire SFR area.
Ports that are frequently accessed in a program, a compare register of the timer/event counter and a capture
register of the timer/event counter are mapped in the area FF00H through FF1FH, and these SFRs can be
manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to
1FH, bit 8 is set to 1. See [Illustration] below.
[Operand format]
Identifier Description
saddr Label or FE20H to FF1FH immediate data
saddrp Label or FE20H to FF1FH immediate data (even address only)
[Description example]
MOV FE30H, #50H; When setting saddr to FE30H and the immediate data to 50H
Instruction code 00010001OP code
0011000030H (saddr-offset)
0101000050H (immediate data)
[Illustration]
07
OP code
saddr-offset
Short direct memory
Effective
address
15
1
111111
When 8-bit immediate data is 20H to FFH, α = 0.
When 8-bit immediate data is 00H to 1FH, α = 1.
87
α
0
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CHAPTER 3 ADDRESSING
3.2.5 Special-function register (SFR) addressing
[Function]
A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction
word.
This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the
SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing.
[Operand format]
Identifier Description
sfr Special function register name
sfrp 16-bit-manipulatable special function register name (even address only)
[Description example]
MOV PM0, A; When selecting PM0 for sfr
Instruction code 11110110OP code
[Illustration]
15
Effective
address
OP code
sfr-offset
1
111111
0010000020H (sfr-offset)
07
87
1
0
SFR
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CHAPTER 3 ADDRESSING
3.2.6 Register indirect addressing
[Function]
Register indirect addressing addresses memory with register pair contents specified as an operand. The
register pair to be accessed is specified by the register bank selection flags (RBS0 and RBS1) and the
register pair specification in instruction codes.
[Operand format]
Identifier Description
—
[DE], [HL]
[Description example]
MOV A, [DE]; When selecting register pair [DE]
Instruction code 10000101
[Illustration]
15 08D7
DE
Contents of memory to be
addressed are transferred
7 0
A
E
Memory
07
Memory address specified
by register pair DE
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CHAPTER 3 ADDRESSING
3.2.7 Based addressing
[Function]
8-bit immediate data is added to the contents of the HL register pair as a base register and the sum is used
to address the memory. The HL register pair to be accessed is in the register bank specified by the register
bank select flag (RBS0 and RBS1). Addition is performed by expanding the offset data as a positive number
to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier Description
—
[HL+byte]
[Description example]
MOV A, [HL+10H]; When setting byte to 10H
Instruction code 10101110
00010000
3.2.8 Based indexed addressing
[Function]
The B or C register contents specified in an instruction word are added to the contents of the HL register
pair as a base register and the sum is used to address the memory. The HL, B, and C registers to be accessed
are registers in the register bank specified by the register bank select flag (RBS0 to RBS1). Addition is
performed by expanding the B or C register as a positive number to 16 bits. A carry from the 16th bit is
ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier Description
—
[HL+B], [HL+C]
[Description example]
In the case of MOV A, [HL+B]
Instruction code 10101011
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