This 4-to-1 line multiplexer utilizes advanced silicon-gate
CMOS technology. It has the low power consumption and
high noise immunity of standard CMOS integrated circuits.
This device is fully buffered, allowing it to drive 10 LS-TTL
loads. Information on the data inputs of each multiplexer is
selected by the address on the A and B inputs, and is presented on the Y outputs. Each multiplexer possesses a
strobe input which enables it when taken to a low logic level. When a high logic level is applied to a strobe input, the
output of its associated multiplexer is taken low.
The 54HC/74HC logic family is functionally and pinout compatible with the standard 54LS/74LS logic family. All inputs
January 1988
are protected from damage due to static discharge by internal diode clamps to V
and ground.
CC
Features
Y
Typical propagation delay: 24 ns
Y
Wide power supply range: 2V –6V
Y
Low quiescent current: 80 mA maximum (74HC Series)
Y
Low input current: 1 mA maximum
Y
Fanout of 10 LS-TTL loads
MM54HC153/MM74HC153 Dual 4-Input Multiplexer
Connection Diagram
Truth Table
Select inputs A and B are common to both sections.
1995 National Semiconductor CorporationRRD-B30M105/Printed in U. S. A.
TL/F/5107
Page 2
Absolute Maximum Ratings (Notes1&2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (IIK,IOK)
DC Output Current, per pin (I
OUT
)
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
STG
Power Dissipation (PD)
b
b
)
b
0.5 toa7.0V
1.5 to V
CC
0.5 to V
CC
g
g
b
g
65§Ctoa150§C
a
1.5V
a
0.5V
20 mA
25 mA
50 mA
Operating Conditions
Supply Voltage (V
DC Input or Output Voltage0V
(V
IN,VOUT
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
)26V
CC
)
e
V
2.0V(tr,tf)1000ns
CC
e
V
4.5V500ns
CC
e
V
6.0V400ns
CC
(Note 3)600 mW
S.O. Package only500 mW
Lead Temperature (T
(Soldering 10 seconds)260
)
L
C
§
DC Electrical Characteristics (Note 4)
SymbolParameterConditionsV
CC
A
e
T
25§C
TypGuaranteed Limits
V
IH
Minimum High Level2.0V1.51.51.5V
Input Voltage4.5V3.153.153.15V
6.0V4.24.24.2V
V
IL
Maximum Low Level2.0V0.50.50.5V
Input Voltage**4.5V1.351.351.35V
6.0V1.81.81.8V
V
OH
Minimum High LevelV
Output Voltage
e
VIHor V
l
I
IN
OUT
IL
s
20 mA2.0V2.01.91.91.9V
l
4.5V4.54.44.44.4V
6.0V6.05.95.95.9V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
l
I
IN
OUT
e
V
OL
Maximum Low LevelV
Output Voltage
IL
s
4.0 mA4.5V4.23.983.843.7V
l
s
5.2 mA6.0V5.35.485.345.2V
l
VIHor V
IL
s
20 mA2.0V00.10.10.1V
l
4.5V00.10.10.1V
6.0V00.10.10.1V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
I
IN
I
CC
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
with this supply. Worst case V
I
**V
Maximum InputV
Current
Maximum QuiescentV
Supply CurrentI
g
and VILoccur at V
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
OZ
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
IH
e
IN
e
IN
OUT
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
IL
s
4.0 mA4.5V0.20.260.330.4V
l
s
5.2 mA6.0V0.20.260.330.4V
l
VCCor GND6.0V
g
0.1
VCCor GND6.0V8.080160mA
e
0 mA
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICC, and
CC
74HC54HC
eb
T
40 to 85§CT
A
g
1.0
MinMaxUnits
V
§
§
Units
b
b
40
55
eb
A
55 to 125§C
g
CC
a
85
a
125
1.0mA
C
C
2
Page 3
AC Electrical Characteristics V
CC
5V, T
e
A
25§C, C
e
L
15 pF, t
e
e
t
6ns
r
f
e
SymbolParameterConditionsTypGuaranteed LimitUnits
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
Maximum Propagation Delay, Select A or B to Y2630ns
Maximum Propagation Delay, any Data to Y2023ns
Maximum Propagation Delay, Strobe to Y815ns
AC Electrical Characteristics C
e
L
50 pF, t
SymbolParameterConditionsV
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
t
TLH,tTHL
C
C
Maximum Propagation2.0V131158198237ns
Delay, Select A or B to Y4.5V29354452ns
Maximum Propagation2.0V99126158189ns
Delay, any Data to Y4.5V22283542ns
Maximum Propagation2.0V5086108129ns
Delay, Strobe to Y4.5V12192429ns
Maximum Output2.0V307595110ns
Rise and Fall Time4.5V8151922ns
Maximum Input Capacitance5101010pF
IN
Power Dissipation(Note 5)(per package)
PD
CapacitanceOutputs Enabled90pF
Note 5: CPDdetermines the no load dynamic power consumption, P
Outputs Disabled25pF
e
CPDV
D
Logic Diagram
e
e
t
6 ns (unless otherwise specified)
r
f
74HC54HC
eb
T
40 to 85§CT
A
A
eb
55 to 125§C
Units
CC
e
T
25§C
A
TypGuaranteed Limits
6.0V25303845ns
6.0V19232935ns
6.0V10162024ns
6.0V7131619ns
2
faICCVCC, and the no load dynamic current consumption, I
CC
e
CPDVCCfaICC.
S
TL/F/5107– 2
3
Page 4
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54HC153J or MM74HC153J
NS Package J16A
MM54HC153/MM74HC153 Dual 4-Input Multiplexer
Molded Dual-In-Line Package (N)
Order Number MM74HC153N
NS Package N16E
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SEMICONDUCTOR CORPORATION. As used herein:
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systems which, (a) are intended for surgical implantsupport device or system whose failure to perform can
into the body, or (b) support or sustain life, and whosebe reasonably expected to cause the failure of the life
failure to perform, when properly used in accordancesupport device or system, or to affect its safety or
with instructions for use provided in the labeling, caneffectiveness.
be reasonably expected to result in a significant injury
to the user.
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