National Semiconductor MM54HC153, MM74HC153 Service Manual

Page 1
MM54HC153/MM74HC153 Dual 4-Input Multiplexer
General Description
This 4-to-1 line multiplexer utilizes advanced silicon-gate CMOS technology. It has the low power consumption and high noise immunity of standard CMOS integrated circuits. This device is fully buffered, allowing it to drive 10 LS-TTL loads. Information on the data inputs of each multiplexer is selected by the address on the A and B inputs, and is pre­sented on the Y outputs. Each multiplexer possesses a strobe input which enables it when taken to a low logic lev­el. When a high logic level is applied to a strobe input, the output of its associated multiplexer is taken low.
The 54HC/74HC logic family is functionally and pinout com­patible with the standard 54LS/74LS logic family. All inputs
January 1988
are protected from damage due to static discharge by inter­nal diode clamps to V
and ground.
CC
Features
Y
Typical propagation delay: 24 ns
Y
Wide power supply range: 2V –6V
Y
Low quiescent current: 80 mA maximum (74HC Series)
Y
Low input current: 1 mA maximum
Y
Fanout of 10 LS-TTL loads
MM54HC153/MM74HC153 Dual 4-Input Multiplexer
Connection Diagram
Truth Table
Select inputs A and B are common to both sections.
H
Dual-In-Line Package
Top View
Order Number MM54HC153 or MM74HC153
Select Inputs
B A C0 C1 C2 C3 G Y
XXXXXX H L LLLXXX L L LLHXXX L H LHXLXX L L LHXHXX L H HLXXLX L L HLXXHX L H HHXXXL L L HHXXXH L H
e
high level, Lelow level, Xedon’t care.
Data Inputs Strobe Output
TL/F/5107– 1
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/5107
Page 2
Absolute Maximum Ratings (Notes1&2)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (IIK,IOK)
DC Output Current, per pin (I
OUT
)
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
STG
Power Dissipation (PD)
b
b
)
b
0.5 toa7.0V
1.5 to V
CC
0.5 to V
CC
g
g
b
g
65§Ctoa150§C
a
1.5V
a
0.5V
20 mA
25 mA
50 mA
Operating Conditions
Supply Voltage (V
DC Input or Output Voltage 0 V
(V
IN,VOUT
Operating Temp. Range (TA)
MM74HC MM54HC
Input Rise or Fall Times
)26V
CC
)
e
V
2.0V(tr,tf) 1000 ns
CC
e
V
4.5V 500 ns
CC
e
V
6.0V 400 ns
CC
(Note 3) 600 mW S.O. Package only 500 mW
Lead Temperature (T
(Soldering 10 seconds) 260
)
L
C
§
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions V
CC
A
e
T
25§C
Typ Guaranteed Limits
V
IH
Minimum High Level 2.0V 1.5 1.5 1.5 V Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
IL
Maximum Low Level 2.0V 0.5 0.5 0.5 V Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
OH
Minimum High Level V Output Voltage
e
VIHor V
l
I
IN
OUT
IL
s
20 mA 2.0V 2.0 1.9 1.9 1.9 V
l
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
l
I
IN
OUT
e
V
OL
Maximum Low Level V Output Voltage
IL
s
4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
l
s
5.2 mA 6.0V 5.3 5.48 5.34 5.2 V
l
VIHor V
IL
s
20 mA 2.0V 0 0.1 0.1 0.1 V
l
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
I
IN
I
CC
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
with this supply. Worst case V I
**V
Maximum Input V Current
Maximum Quiescent V Supply Current I
g
and VILoccur at V
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
OZ
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
IH
e
IN
e
IN
OUT
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
IL
s
4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
l
s
5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
l
VCCor GND 6.0V
g
0.1
VCCor GND 6.0V 8.0 80 160 mA
e
0 mA
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICC, and
CC
74HC 54HC
eb
T
40 to 85§CT
A
g
1.0
Min Max Units
V
§
§
Units
b b
40 55
eb
A
55 to 125§C
g
CC
a
85
a
125
1.0 mA
C C
2
Page 3
AC Electrical Characteristics V
CC
5V, T
e
A
25§C, C
e
L
15 pF, t
e
e
t
6ns
r
f
e
Symbol Parameter Conditions Typ Guaranteed Limit Units
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
Maximum Propagation Delay, Select A or B to Y 26 30 ns
Maximum Propagation Delay, any Data to Y 20 23 ns
Maximum Propagation Delay, Strobe to Y 8 15 ns
AC Electrical Characteristics C
e
L
50 pF, t
Symbol Parameter Conditions V
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
t
TLH,tTHL
C
C
Maximum Propagation 2.0V 131 158 198 237 ns Delay, Select A or B to Y 4.5V 29 35 44 52 ns
Maximum Propagation 2.0V 99 126 158 189 ns Delay, any Data to Y 4.5V 22 28 35 42 ns
Maximum Propagation 2.0V 50 86 108 129 ns Delay, Strobe to Y 4.5V 12 19 24 29 ns
Maximum Output 2.0V 30 75 95 110 ns Rise and Fall Time 4.5V 8 15 19 22 ns
Maximum Input Capacitance 5 10 10 10 pF
IN
Power Dissipation (Note 5)(per package)
PD
Capacitance Outputs Enabled 90 pF
Note 5: CPDdetermines the no load dynamic power consumption, P
Outputs Disabled 25 pF
e
CPDV
D
Logic Diagram
e
e
t
6 ns (unless otherwise specified)
r
f
74HC 54HC
eb
T
40 to 85§CT
A
A
eb
55 to 125§C
Units
CC
e
T
25§C
A
Typ Guaranteed Limits
6.0V 25 30 38 45 ns
6.0V 19 23 29 35 ns
6.0V 10 16 20 24 ns
6.0V 7 13 16 19 ns
2
faICCVCC, and the no load dynamic current consumption, I
CC
e
CPDVCCfaICC.
S
TL/F/5107– 2
3
Page 4
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54HC153J or MM74HC153J
NS Package J16A
MM54HC153/MM74HC153 Dual 4-Input Multiplexer
Molded Dual-In-Line Package (N)
Order Number MM74HC153N
NS Package N16E
LIFE SUPPORT POLICY
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