Page 1
MM54HC137/MM74HC137 3-to-8 Line
Decoder With Address Latches
(Inverted Output)
General Description
This device utilizes advanced silicon-gate CMOS technology, to implement a three-to-eight line decoder with latches
on the three address inputs. When GL
high, the address present at the select inputs (A, B and C) is
stored in the latches. As long as GL
dress changes will be recognized. Output enable controls,
G1 and G2
the select or latch-enable inputs. All of the outputs are high
unless G1 is high and G2
for the implementation of glitch-free decoders in stored-address applications in bus oriented systems.
, control the state of the outputs independently of
is low. The HC137 is ideally suited
goes from low to
remains high no ad-
Connection and Functional Block Diagrams
Dual-In-Line Package
The 54HC/74HC logic family is speed, function and pin-out
compatible with the standard 54LS/74LS logic family. All
inputs are protected from damage due to static discharge by
diodes to V
CC
Features
Y
Typical propagation delay: 20 ns
Y
Wide supply range: 2– 6V
Y
Latched inputs for easy interfacing.
Y
Fanout of 10 LS-TTL loads.
and ground.
November 1995
MM54HC137/MM74HC137 3-to-8 Line
Decoder With Address Latches (Inverted Output)
TL/F/5310– 1
Order Number MM54HC137
or MM74HC137
C
1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
TL/F/5310
TL/F/5310– 2
Page 2
Absolute Maximum Ratings (Notes1&2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (IIK,IOK)
DC Output Current, per pin (I
OUT
)
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
STG
b
b
)
b
0.5 toa7.0V
1.5 to V
CC
0.5 to V
CC
g
g
b
g
65§Ctoa150§C
a
1.5V
a
0.5V
20 mA
25 mA
50 mA
Operating Conditions
Supply Voltage (V
DC Input or Output Voltage 0 V
(V
IN,VOUT
Operating Temp. Range (T
MM74HC
MM54HC
Input Rise or Fall Times
)26V
CC
)
e
2.0V(tr,tf) 1000 ns
V
CC
e
4.5V 500 ns
V
CC
e
6.0V 400 ns
V
CC
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
)
L
(Soldering 10 seconds) 260§C
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions V
CC
A
e
T
25§C
Typ Guaranteed Limits
V
IH
Minimum High Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
IL
Maximum Low Level 2.0V 0.5 0.5 0.5 V
Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
OH
Minimum High Level V
Output Voltage
e
VIHor V
l
I
IN
OUT
IL
s
20 mA 2.0V 2.0 1.9 1.9 1.9 V
l
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
l
I
IN
OUT
e
V
OL
Maximum Low Level V
Output Voltage
IL
s
4.0 mA 4.5V 3.98 3.84 3.7 V
l
s
5.2 mA 6.0V 5.48 5.34 5.2 V
l
VIHor V
IL
s
20 mA 2.0V 0 0.1 0.1 0.1 V
l
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
I
IN
I
CC
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
with this supply. Worst case V
I
**V
Maximum Input V
Current
Maximum Quiescent V
Supply Current I
g
and VILoccur at V
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
OZ
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
IH
e
IN
e
IN
OUT
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
IL
s
4.0 mA 4.5V 0.26 0.33 0.4 V
l
s
5.2 mA 6.0V 0.26 0.33 0.4 V
l
VCCor GND 6.0V
g
0.1
VCCor GND 6.0V 8.0 80 160 mA
e
0 mA
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICC, and
CC
74HC 54HC
eb
T
40 to 85§CT
A
g
1.0
Min Max Units
)
A
b
b
40
55
eb
A
55 to 125§C
g
a
a
1.0 mA
CC
85
125
V
C
§
C
§
Units
2
Page 3
AC Electrical Characteristics V
CC
5V, T
e
A
25§C, C
e
L
15 pF, t
e
e
t
6ns
r
f
e
Symbol Parameter Conditions Typ
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
S
t
H
t
W
AC Electrical Characteristics C
Symbol Parameter Conditions V
Maximum Propagation Delay, A, B or C to any Y Output 14 29 ns
Maximum Propagation Delay, A, B or C to any Y Output 20 42 ns
Maximum Propagation Delay G2 to any Y Output 12 22 ns
Maximum Propagation Delay G2 to any Y Output 15 34 ns
Maximum Propagation Delay G1 to any Output 13 25 ns
Maximum Propagation Delay GL to any Output 17 34 ns
Maximum Propagation GL to Output 15 30 ns
Maximum Propagation Delay GL to Output 22 34 ns
Minimum Setup Time at A, B and C Inputs 20 ns
Minimum Hold Time at A, B and C Inputs 0 ns
Minimum Pulse Width of Enabling Pulse at GL 16 ns
e
L
50 pF, t
e
e
t
6 ns (unless otherwise specified)
r
f
e
T
25§C
CC
A
T
74HC 54HC
eb
40 to 85§CT
A
Typ Guaranteed Limits
t
PLH
t
PHL
t
PLH
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
S
t
H
t
TLH,tTHL
t
W
C
PD
C
IN
Note 5: CPDdetermines the no load dynamic power consumption, P
Maximum Propagation Delay 2.0V 85 170 214 253 ns
A, B or C to any Y Output 4.5V 17 34 43 51 ns
Maximum Propagation Delay 2.0V 120 240 302 358 ns
A, B or C to any Y Output 4.5V 24 48 60 72 ns
Maximum Propagation Delay 2.0V 65 130 164 194 ns
2 to any Y Output 4.5V 13 26 33 39 ns
G
Maximum Propagation 2.0V 75 150 189 224 ns
Delay G1 to Output 4.5V 15 30 38 45 ns
Maximum Propagation 2.0V 98 195 246 291 ns
Delay G1 to Output 4.5V 20 39 49 58 ns
Maximum Propagation 2.0V 88 175 221 261 ns
Delay GL to Output 4.5V 18 35 44 52 ns
Maximum Propagation 2.0V 125 250 315 373 ns
Delay GL to Output 4.5V 25 50 63 75 ns
Maximum Propagation Delay 2.0V 98 195 246 291 ns
G2, to any Y Output 4.5V 20 39 49 58 ns
Minimum Setup Time 2.0V 100 125 150 ns
at A, B and C inputs 4.5V 20 25 30 ns
Minimum Hold Time 2.0V 50 63 75 ns
at A, B and C inputs 4.5V 10 13 15 ns
Output Rise and 2.0V 30 75 95 110 ns
Fall Time 4.5V 8 15 19 22 ns
Minimum Pulse Width 2.0V 80 100 120 ns
of Enabling Pulse at GL
Power Dissipation 75 pF
Capacitance (Note 5)
6.0V 14 29 36 43 ns
6.0V 20 41 51 61 ns
6.0V 11 22 28 33 ns
6.0V 13 26 32 38 ns
6.0V 17 33 42 49 ns
6.0V 15 30 37 44 ns
6.0V 21 43 54 63 ns
6.0V 17 33 42 49 ns
6.0V 17 21 25 ns
6.0V 8 11 13 ns
6.0V 7 13 16 19 ns
4.5V 16 20 24 ns
6.0V 14 18 21 ns
Maximum Input Capacitance 5 10 10 10 pF
2
e
CPDV
D
faICCVCC, and the no load dynamic current consumption, I
CC
Guaranteed
Limit
eb
55 to 125§C
A
S
e
CPDVCCfaICC.
Units
Units
3
Page 4
Typical Application
Truth Table
6-Line to 64-Line Decoder with Input Address Storage
Inputs
Enable Select
GL G1 G2 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X X HXXXHHHHHHHH
X L XXXXHHHHHHHH
L H LLLLLHHHHHHH
L H LLLHH LHHHHHH
L H LLHLHHLHHHHH
L H LLHHHHHL HHHH
L H LHLLHHHHLHHH
L H LHLHHHHHHL HH
L H LHHLHHHHHHL H
L H LHHHHHHHHHH L
H H L XXX
Hehigh level, Lelow level, Xeirrelevant
Output corresponding to stored
address L; all others, H
Outputs
TL/F/5310– 3
4
Page 5
5
Page 6
Physical Dimensions inches (millimeters)
MM54HC137/MM74HC137 3-to-8 Line
Decoder With Address Latches (Inverted Output)
Ceramic Dual-In-Line Package (J)
Order Number MM54HC137J or MM74HC137J
NS Package J16A
Molded Dual-In-Line Package (N)
Order Number MM74HC137N
NS Package N16E
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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