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MM54HC08/MM74HC08
Quad 2-Input AND Gate
MM54HC08/MM74HC08 Quad 2-Input AND Gate
January 1988
General Description
These AND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates
with the low power consumption of standard CMOS integrated circuits. The HC08 has buffered outputs, providing
high noise immunity and the ability to drive 10 LS-TTL loads.
The 54HC/74HC logic family is functionally as well as pinout compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static discharge by internal diode clamps to V
and ground.
CC
Connection Diagram
Dual-In-Line Package
Features
Y
Typical propagation delay: 7 ns (t
Y
Fanout of 10 LS-TTL loads
Y
Quiescent power consumption: 2 m A maximum at room
temperature
Y
Low input current: 1 mA maximum
), 12 ns (t
PHL
PLH
)
Top View
Order Number MM54HC08 or MM74HC08
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/5297
TL/F/5297– 1
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Absolute Maximum Ratings (Notes1&2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (IIK,IOK)
DC Output Current, per pin (I
OUT
)
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
STG
b
b
)
b
0.5 toa7.0V
1.5 to V
CC
0.5 to V
CC
g
g
b
g
65§Ctoa150§C
a
1.5V
a
0.5V
20 mA
25 mA
50 mA
Power Dissipation (PD)
(Note 3) 600 mW
Supply Voltage (V
)26V
CC
DC Input or Output Voltage 0 V
(V
IN,VOUT
)
Operating Temp. Range (T
MM74HC
MM54HC
Input Rise or Fall Times
e
2.0V(tr,tf) 1000 ns
V
CC
e
V
4.5V 500 ns
CC
e
V
6.0V 400 ns
CC
S.O. Package only 500 mW
Lead Temp. (T
) (Soldering 10 seconds) 260§C
L
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions V
CC
A
e
T
25§C
Typ Guaranteed Limits
V
IH
Minimum High Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
IL
Maximum Low Level 2.0V 0.5 0.5 0.5 V
Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
OH
Minimum High Level V
Output Voltage
e
V
IN
IH
s
I
20 mA 2.0V 2.0 1.9 1.9 1.9 V
l
l
OUT
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
e
V
V
IN
IH
s
I
4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
l
l
OUT
s
I
5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
l
l
OUT
V
OL
Maximum Low Level V
Output Voltage
e
VIHor V
l
I
IN
OUT
IL
s
20 mA 2.0V 0 0.1 0.1 0.1 V
l
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
I
IN
I
CC
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
with this supply. Worst case V
I
**V
Maximum Input V
Current
Maximum Quiescent V
Supply Current I
g
and VILoccur at V
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
OZ
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
IH
e
IN
e
IN
OUT
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
IL
s
4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
l
s
5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
l
VCCor GND 6.0V
g
0.1
VCCor GND 6.0V 2.0 20 40 mA
e
0 mA
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICC, and
CC
74HC 54HC
eb
T
40 to 85§CT
A
g
1.0
Min Max Units
)
A
b
b
40
55
eb
A
55 to 125§C
g
a
a
1.0 mA
CC
85
125
V
C
§
C
§
Units
2
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AC Electrical Characteristics V
CC
e
5V, T
Symbol Parameter Conditions Typ
t
t
PHL
PLH
Maximum Propagation 12 20 ns
Delay, Output High to Low
Maximum Propagation 7 15 ns
Delay, Output Low to High
e
A
25§C, C
Guaranteed
e
L
Limit
15 pF, t
e
r
e
t
f
Units
6ns
AC Electrical Characteristics V
CC
e
Symbol Parameter Conditions V
t
t
PHL
PLH
Maximum Propagation 2.0V 77 121 151 175 ns
Delay, Output High to Low 4.5V 15 24 30 35 ns
Maximum Propagation 2.0V 30 90 113 134 ns
Delay, Output 4.5V 10 18 23 27 ns
Low to High 6.0V 8 15 19 23 ns
t
TLH,tTHL
C
PD
C
IN
Note 5: CPDdetermines the no load dynamic power consumption, P
Maximum Output Rise 2.0V 30 75 95 110 ns
and Fall Time 4.5V 8 15 19 22 ns
Power Dissipation (per gate) 38 pF
Capacitance (Note 5)
Maximum Input 4 10 10 10 pF
Capacitance
D
2.0V to 6.0V, C
e
T
A
CC
e
L
25§C
50 pF, t
e
e
t
6 ns (unless otherwise specified)
r
f
74HC 54HC
eb
T
40 to 85§CT
A
eb
A
55 to 125§C
Typ Guaranteed Limits
6.0V 13 20 25 30 ns
6.0V 7 13 16 19 ns
2
e
CPDV
faICCVCC, and the no load dynamic current consumption, I
CC
e
CPDVCCfaICC.
S
Units
3
Page 4
Physical Dimensions inches (millimeters)
Order Number MM54HC08J or MM74HC08J
NS Package J14A
MM54HC08/MM74HC08 Quad 2-Input AND Gate
Order Number MM74HC08N
NS Package N14A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
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systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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