National Semiconductor MM54HC354, MM54HC356, MM74HC354, MM74HC356 Service Manual
MM54HC354/MM74HC354/
MM54HC356/MM74HC356
8-Channel TRI-STATE
General Description
The MM54HC354/MM74HC354 and MM54HC356/
MM74HC356 utilize advanced silicon-gate CMOS technology. They exhibit the high noise immunity and low power dissipation of standard CMOS integrated circuits, along with
the ability to drive 15 LS-TTL loads. Due to the large output
drive capability and the TRI-STATE feature, these devices
are ideally suited for interfacing with bus lines in a bus organized system.
These data selectors/multiplexers contain full on-chip binary decoding to select one of eight data sources. The data
select address is stored in transparent latches that are enabled by a low level address on pin 11, SC
input lines is stored in a parallel input/output register which
in the MM54HC354/MM74HC354 is composed of 8 transparent latches enabled by a low level on pin 9, DC
the MM54HC356/MM74HC356 is composed of 8 edge-triggered flip-flops, clocked by a low to high transition on pin 9,
CLK. Both true (Y) and complementary (W) TRI-STATE outputs are available on both devices.
Multiplexers with Latches
É
. Data on the 8
, and in
June 1992
The 54HC/74HC logic family is functionally as well as pinout compatible with the standard 54LS/74LS-TTL logic family. All inputs are protected from damage due to static discharge by internal diode clamps to V
and ground.
CC
Features
Y
Transparent latches on data select inputs
Y
Choice of data registers:
Transparent (’354)
Edge-triggered (’356)
Y
TRI-STATE complementary outputs with fanout
of 15 LS-TTL loads
Y
Typical propagation delay:
Data to output (’354): 32 ns
Clock to output (’346): 35 ns
Y
Wide power supply range: 2V –6V
Y
Low quiescent supply current: 80 mA maximum
Y
Low input current: 1 mA maximum
MM54HC354/MM74HC354/MM54HC356/MM74HC356
8-Channel TRI-STATE Multiplexers with Latches
Connection Diagram
Dual-In-Line Package
Top View
Order Number MM54HC354/356 or MM74HC354/356
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/5208
TL/F/5208– 1
Absolute Maximum Ratings (Notes1&2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (ICD)
DC Output Current, per pin (I
OUT
)
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
STG
b
b
)
b
0.5V toa7.0V
1.5V to V
CC
0.5V to V
CC
g
g
b
g
65§Ctoa150§C
a
1.5V
a
0.5V
20 mA
35 mA
70 mA
Supply Voltage (V
)26V
CC
DC Input or Output Voltage 0 V
(V
IN,VOUT
)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
e
V
2.0V(tr,tf) 1000 ns
CC
e
V
4.5V 500 ns
CC
e
V
6.0V 400 ns
CC
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temp. (T
)
L
(Soldering 10 seconds) 260§C
DC Electrical Characteristics (Note 4)
e
T
25§C
Symbol Parameter Conditions V
CC
A
Typ Guaranteed Limits
V
Minimum High Level Input 2.0V 1.5 1.5 1.5 V
IH
Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
Maximum Low Level Input 2.0V 0.5 0.5 0.5 V
IL
Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
Minimum High Level Output V
OH
Voltage
e
VIHor V
l
I
OUT
IN
IL
s
20 mA 2.0V 2.0 1.9 1.9 1.9 V
l
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
l
I
OUT
e
IN
V
Maximum Low Level Output V
OL
Voltage
IL
s
6.0 mA 4.5V 4.2 3.98 3.84 3.7 V
l
s
7.8 mA 6.0V 5.7 5.48 5.34 5.2 V
l
VIHor V
IL
k
20 mA 2.0V 0 0.1 0.1 0.1 V
l
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
I
IN
I
OZ
I
CC
Maximum Input Current V
Maximum TRI-STATE Output V
Leakage Current G
Maximum Quiescent Supply V
Current I
Note 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
with this supply. Worst case V
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
I
OZ
**V
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
g
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
and VILoccur at V
IH
IN
OUT
1eV
IN
OUT
CC
e
e
e
IL
s
6.0 mA 4.5V 0.2 0.26 0.33 0.4 V
l
s
7.8 mA 6.0V 0.2 0.26 0.33 0.4 V
l
VCCor GND 6.0V
e
VCCor GND
IH
6.0V
g
0.1
g
0.5
VCCor GND 6.0V 8.0 80 160 mA
e
0 mA
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICC, and
74HC 54HC
eb
T
40 to 85§CT
A
g
1.0
g
5.0
Min Max Units
CC
b
b
40
55
eb
A
a
85
a
125
55 to 125§C
g
1.0 mA
g
10 mA
V
§
§
Units
C
C
2
AC Electrical Characteristics V
CC
5V, T
e
A
25§C, t
e
e
t
6ns
r
f
e
MM54HC354/MM74HC354
Symbol Parameter Conditions Typ
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
t
PZH,tPZL
t
PHZ,tPLZ
t
S
t
H
t
W
Maximum Propagation C
Delay D0–D7 to either Output
Maximum Propagation C
Delay DC
to either Output
Maximum Propagation C
Delay S0–S2 to either Output
Maximum Propagation C
Delay SC
to either Output
Maximum Output Enable Time R
Maximum Output Disable Time R
Minimum Setup Time 3 10 ns
D0–D7toDC
,S0–S2toSC
Minimum Hold Time 0 5 ns
D0–D7toDC
,S0–S2toSC
Minimum Pulse Width, SC or DC 10 15 ns
e
45 pF 32 46 ns
L
e
45 pF 38 53 ns
L
e
45 pF 40 56 ns
L
e
45 pF 42 58 ns
L
e
1kX 17 24 ns
L
e
C
45 pF
L
e
1kX 23 32 ns
L
e
C
5pF
L
MM54HC356/MM74HC356
Symbol Parameter Conditions Typ
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
t
PZH,tPZL
t
PHZ,tPLZ
t
S
t
H
t
W
Maximum Propagation C
Delay CLK to either Output
Maximum Propagation C
Delay S0–S2 to either Output
Maximum Propagation C
Delay SC
to either Output
Maximum Output Enable Time R
Maximum Output Disable Time R
Minimum Setup Time 3 10 ns
D0–D7 to CLK, S0–S2 to SC
Minimum Hold Time 0 5 ns
D0–D7 to CLK, S0–S2 to SC
Minimum Pulse Width, SC or CLK 10 15 ns
e
45 pF 35 50 ns
L
e
45 pF 40 56 ns
L
e
45 pF 42 58 ns
L
e
1kX 17 24 ns
L
e
C
45 pF
L
e
1kX 23 32 ns
L
e
C
5pF
L
Guaranteed
Limit
Guaranteed
Limit
Units
Units
3
Loading...