National Semiconductor MM54HC34, MM74HC34 Service Manual
MM54HC34/MM74HC34 Non-Inverter
General Description
The MM54HC34/MM74HC34 are logic functions fabricated
by using advanced silicon-gate CMOS technology which
provides the inherent benefits of CMOSÐlow quiescent
power and wide power supply range, but are functionally as
well as pin-out compatible with standard DM54LS/74LS devices. The MM54HC34/MM74HC34 feature low power dis-
Connection Diagram
Dual-In-Line Package
sipation and fast switching times. All inputs are protected
from static discharge by internal diodes to V
Features
Y
Fast switching: t
Y
High fanout:t10 LS loads
PLH,tPHL
e
10 ns (typ)
January 1988
and ground.
CC
MM54HC34/MM74HC34 Non-Inverter
Top View
Order Number MM54HC34 or MM74HC34
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/9389
TL/F/9389– 1
Absolute Maximum Ratings (Notes1&2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
ICC
)
)
b
0.5V toa7.0V
b
1.5V to V
b
0.5V to V
b
65§Ctoa150§C
CC
CC
a
a
g
g
g
1.5V
0.5V
20 mA
25 mA
50 mA
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (IIK,IOK)
DC Output Current, per pin (I
OUT
DC VCCor GND Current, per pin (I
Storage Temperature Range (T
STG
)
Power Dissipation (PD)
Supply Voltage (V
DC Input or Output Voltage 0 V
(V
IN,VOUT
Operating Temp. Range (T
)26V
CC
)
MM74HC
MM54HC
Input Rise or Fall Times
)V
V
V
e
2.0V 1000 ns
CC
e
4.5V 500 ns
CC
e
6.0V 400 ns
CC
(t
r,tf
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
(Soldering 10 seconds) 260
)
L
C
§
DC Electrical Characteristics (Note 4)
e
T
25§C
Symbol Parameter Conditions V
CC
A
Typ Guaranteed Limits
V
Minimum High Level 2.0V 1.5 1.5 1.5 V
IH
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
Maximum Low Level 2.0V 0.5 0.5 0.5 V
IL
Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
Minimum High Level V
OH
Output Voltage
e
V
IN
IL
s
I
20 mA 2.0V 2.0 1.9 1.9 1.9 V
l
l
OUT
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
e
V
V
IN
IL
s
I
4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
l
l
OUT
s
I
5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
l
l
OUT
V
Maximum Low Level V
OL
Output Voltage
e
V
IN
IH
s
I
20 mA 2.0V 0 0.1 0.1 0.1 V
l
l
OUT
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
e
V
V
IN
IH
s
I
4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
l
l
OUT
s
I
5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
l
l
OUT
I
IN
I
CC
Maximum Input V
Current
Maximum Quiescent V
Supply Current I
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature deratingÐplastic ‘‘N’’ package:
Note 4: For a power supply of 5V
with this supply. Worst case V
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
I
OZ
**V
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
and VILoccur at V
IH
e
VCCor GND 6.0V
IN
e
VCCor GND 6.0V 2.0 20 40 mA
IN
e
0 mA
OUT
g
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICCand
CC
b
g
0.1
12 mW/§C from 65§Cto85§C, ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
74HC 54HC
eb
T
40 toa85§CT
A
g
1.0
Min Max Units
)
A
b40a
b55a
eb
55 toa125§C Units
A
g
1.0 mA
CC
85§C
125§C
V
2
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