National Semiconductor MM54HC299, MM74HC299 Service Manual
MM54HC299/MM74HC299
8-Bit TRI-STATE
General Description
This 8-bit TRI-STATE shift/storage register utilizes advanced
silicon-gate CMOS technology. Along with the low power
consumption and high noise immunity of standard CMOS
integrated circuits, it has the ability to drive 15 LS-TTL
loads. This circuit also features operating speeds comparable to the equivalent low power Schottky device.
The MM54HC299/MM74HC299 features multiplexed inputs/outputs to achieve full 8-bit data handling in a single
20-pin package. Due to the large output drive capability and
TRI-STATE feature, this device is ideally suited for interfacing with bus lines in a bus oriented system.
Two function select inputs and two output control inputs are
used to choose the mode of operation as listed in the function table. Synchronous parallel loading is accomplished by
taking both function select lines S0 and S1 high. This places
the TRI-STATE outputs in a high impedance state, which
Connection Diagram
Universal Shift Register
É
January 1988
permits data applied to the input/output lines to be clocked
into the register. Reading out of the register can be done
while the outputs are enabled in any mode. A direct overriding CLEAR input is provided to clear the register whether
the outputs are enabled or disabled.
The 54HC/74HC logic family is functionally as well as pinout
compatible with the standard 54LS/74LS logic family. All
inputs are protected from damage due to static discharge by
internal diode clamps to V
and ground.
CC
Features
Y
Typical operating frequency 40 MHz
Y
Typical propagation delay: 20 ns
Y
Low quiescent current: 80 mA maximum (74HC)
Y
High output drive for bus applications
Y
Low quiescent current: 1 mA maximum
MM54HC299/MM74HC299 8-Bit TRI-STATE Universal Shift Register
Dual-In-Line Package
TL/F/5207– 1
Order Number MM54HC299 or MM74HC299
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/5207
Absolute Maximum Ratings (Notes1&2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
DC Input Voltage (V
DC Output Voltage (V
Clamp Diode Current (I
DC Output Current, per pin (I
DC V
or GND Current, per pin (ICC)
CC
Storage Temperature Range (T
Power Dissipation (P
(Note 3) 600 mW
CC
)
)
IN
)
OUT
)
CD
)
OUT
STG
)
D
b
b
g
b
)
b
0.5 toa7.0V
CC
CC
a
a
g
1.5V
0.5V
20 mA
1.5 to V
0.5 to V
25 mA (QA’,QH’)
g
35 mA (others)
g
70 mA
65§Ctoa150§C
Supply Voltage (V
)26V
CC
DC Input or Output Voltage 0 V
(V
IN,VOUT
)
Operating Temp. Range (T
MM74HC
MM54HC
Input Rise or Fall Times
e
V
2.0V(tr,tf) 1000 ns
CC
e
V
4.5V 500 ns
CC
e
V
6.0V 400 ns
CC
S.O. Package only 500 mW
Lead Temp. (T
) (Soldering 10 seconds) 260§C
L
DC Electrical Characteristics (Note 4)
e
T
25§C
Symbol Parameter Conditions V
CC
A
Typ Guaranteed Limits
V
Minimum High Level Input 2.0V 1.5 1.5 1.5 V
IH
Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
Maximum Low Level Input 2.0V 0.5 0.5 0.5 V
IL
Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
Minimum High Level V
OH
Output Voltage
e
VIHor V
l
I
OUT
IN
IL
s
20 mA 2.0V 2.0 1.9 1.9 1.9 V
l
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
QA'&QH'Outputs V
A/QAthru H/QHOutputs V
V
Maximum Low Level V
OL
Output Voltage
e
VIHor V
l
l
l
l
l
I
OUT
I
OUT
I
OUT
I
OUT
I
OUT
IN
e
IN
e
IN
IL
s
4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
l
s
5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
l
VIHor V
IL
s
6.0 mA 4.5V 4.2 3.98 3.84 3.7 V
l
s
7.8 mA 6.0V 5.7 5.48 5.34 5.2 V
l
VIHor V
IL
s
20 mA 2.0V 0 0.1 0.1 0.1 V
l
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
QA'and QH'Outputs V
A/QAthru H/QHOutputs V
I
I
Maximum Input Current V
IN
Maximum TRI-STATE Output V
OZ
Leakage Currrent GeV
I
Maximum Quiescent Supply V
CC
Current I
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
designing with this supply. Worst-case V
, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
I
CC
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
** V
IL
g
10% the worst-case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
and VILoccur at V
IH
e
VIHor V
IN
I
l
OUT
I
l
OUT
IN
I
l
OUT
I
l
OUT
IN
OUT
GND
IN
OUT
e
e
e
IL
s
4 mA 4.5V 0.2 0.26 0.33 0.4 V
l
s
5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
l
VIHor V
IL
s
6 mA 4.5V 0.2 0.26 0.33 0.4 V
l
s
7.8 mA 6.0V 0.2 0.26 0.33 0.4 V
l
VCCor GND 6.0V
e
VCCor 6.0V
IH
VCCor GND 6.0V 8.0 80 160 mA
e
0 mA
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst-case leakage current (IIN,
CC
g
0.1
g
0.5
74HC 54HC
eb
T
40 to 85§CT
A
g
1.0
g
0.5
Min Max Units
)
A
b
b
40
55
eb
A
a
a
55 to 125§C
g
1.0 mA
g
1.0 mA
CC
85
125
V
C
§
C
§
Units
V
V
V
V
2
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