National Semiconductor MM54HC283, MM74HC283 Service Manual

MM54HC283/MM74HC283 4-Bit Binary Adder with Fast Carry
MM54HC283/MM74HC283 4-Bit Binary Adder with Fast Carry
January 1988
General Description
This full adder performs the addition of two 4-bit binary num­bers utilizing advanced silicon-gate CMOS technology. The sum (R) outputs are provided for each bit and the resultant carry (C4) is obtained from the fourth bit. These adders fea­ture full internal look ahead across all four bits. This pro­vides the system designer with partial look-ahead perform­ance at the economy and reduced package count of a rip­ple-carry implementation.
The adder logic, including the carry, is implemented in its true form meaning that the end-around carry can be accom­plished without the need for logic or level inversion. All in­puts are protected from damage due to static discharge by internal diode clamps to V
and ground.
CC
Connection Diagram
Dual-In-Line Package
Features
Y
Full-carry look-ahead across the four bits
Y
Systems achieve partial look-ahead performance with the economy of ripple carry
Y
Wide supply range: 2V to 6V
Y
Low quiescent power consumption: 8 mAat25§C
Y
Low input current: 1 mA maximum
Top View
Order Number MM54HC283 or MM74HC283
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/5332
TL/F/5332– 1
Absolute Maximum Ratings (Notes1&2)
Operating Conditions
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (IIK,IOK)
DC Output Current, per pin (I
OUT
)
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
STG
b
b
)
b
0.5 toa7.0V
1.5 to V
CC
0.5 to V
CC
g
g
b
g
65§Ctoa150§C
a
1.5V
a
1.5V
20 mA
25 mA
50 mA
Power Dissipation (PD)
(Note 3) 600 mW
Supply Voltage (V
)26V
CC
DC Input or Output Voltage 0 V
(V
IN,VOUT
)
Operating Temp. Range (T
MM74HC MM54HC
Input Rise or Fall Times
e
V
2.0V(tr,tf) 1000 ns
CC
e
V
4.5V 500 ns
CC
e
V
6.0V 400 ns
CC
S.O. Package only 500 mW
Lead Temperature (T
)
L
(Soldering 10 seconds) 260§C
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions V
CC
A
e
T
25§C
Typ Guaranteed Limits
V
IH
Minimum High Level 2.0V 1.5 1.5 1.5 V Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
IL
Maximum Low Level 2.0V 0.5 0.5 0.5 V Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
OH
Minimum High Level V Output Voltage
e
VIHor V
IN
I
l
OUT
IL
s
20 mA 2.0V 2.0 1.9 1.9 1.9 V
l
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
V
OL
Maximum Low Level V Output Voltage
e
IN
I
l
OUT
IL
s
4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
l
s
5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
l
VIHor V
IL
s
20 mA 2.0V 0 0.1 0.1 0.1 V
l
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
I
IN
I
CC
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
with this supply. Worst case V I
**V
Maximum Input V Current
Maximum Quiescent V Supply Current I
g
and VILoccur at V
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
OZ
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
IH
e
IN
e
IN
OUT
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
IL
s
4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
l
s
5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
l
VCCor GND 6.0V
g
0.1
VCCor GND 6.0V 8.0 80 160 mA
e
0 mA
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICC, and
CC
74HC 54HC
eb
T
40 to 85§CT
A
g
1.0
Min Max Units
)
A
b b
40 55
eb
A
55 to 125§C
g
a
a
1.0 mA
CC
85
125
V
C
§
C
§
Units
2
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