National Semiconductor MM54HC280, MM74HC280 Service Manual

MM54HC280/MM74HC280
9-Bit Odd/Even Parity Generator/Checker

MM54HC280/MM74HC280 9-Bit Odd/Even Parity Generator/Checker

January 1988

General Description

The MM54HC280/MM74HC280 utilizes advanced silicon­gate CMOS technology to achieve the high noise immunity
and low power consumption of standard CMOS integrated
circuits. It possesses the ability to drive 10 LS-TTL loads.

This parity generator/checker features odd/even outputs to
facilitate operation of either odd or even parity applications.
The word length capability is easily expanded by cascading
devices. The 54HC/74HC logic family is speed, function,
and pinout compatible with the standard 54LS/74LS family.
All inputs are protected from damage due to static dis­charge by internal diode clamps to V

and ground.

CC

Connection Diagram

Dual-In-Line Package

Features

Y

Typical propagation delay: 28 ns

Y

Wide power supply range: 2V –6V

Y

Low quiescent current: 80 mA maximum (74HC)

Y

Low input current: 1 mA maximum

Y

Fanout of 10 LS-TTL loads

TL/F/5121– 1

Order Number MM54HC280 or MM74HC280

Function Table

Numbers of Inputs A Outputs

thru 1 that are High

0, 2, 4, 6, 8 H L
1, 3, 5, 7, 9 L H

Hehigh level, Lelow level

C

1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

TL/F/5121

R Even R Odd

Absolute Maximum Ratings (Notes1&2)

Operating Conditions

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage (V

CC

)

DC Input Voltage (VIN)

DC Output Voltage (V

OUT

)

Clamp Diode Current (IIK,IOK)

DC Output Current, per pin (I

OUT

)

DC VCCor GND Current, per pin (ICC)

Storage Temperature Range (T

STG

b

b

)

b

0.5 toa7.0V

1.5 to V

CC

0.5 to V

CC

g

g

b

g

65§Ctoa150§C

a

1.5V

a

0.5V

20 mA

25 mA

50 mA

Supply Voltage (V

)26V

CC

DC Input or Output Voltage 0 V

(V

IN,VOUT

)

Operating Temp. Range (TA)

MM74HC
MM54HC

Input Rise or Fall Times

e

V

2.0V(tr,tf) 1000 ns

CC

e

V

4.5V 500 ns

CC

e

V

6.0V 400 ns

CC

Power Dissipation (PD)

(Note 3) 600 mW
S.O. Package only 500 mW

Lead Temp. (T

) (Soldering 10 seconds) 260§C

L

DC Electrical Characteristics (Note 4)

Symbol Parameter Conditions V

CC

A

e

T

25§C

Typ Guaranteed Limits

V

IH

Minimum High Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V

6.0V 4.2 4.2 4.2 V

V

IL

Maximum Low Level 2.0V 0.5 0.5 0.5 V
Input Voltage** 4.5V 1.35 1.35 1.35 V

6.0V 1.8 1.8 1.8 V

V

OH

Minimum High Level V
Output Voltage

e

VIHor V

l

I

IN

OUT

IL

s

20 mA 2.0V 2.0 1.9 1.9 1.9 V

l

4.5V 4.5 4.4 4.4 4.4 V

6.0V 6.0 5.9 5.9 5.9 V

e

V

VIHor V

IN

I

l

OUT

I

l

OUT

l

I

IN

OUT

e

V

OL

Maximum Low Level V
Output Voltage

IL

s

4.0 mA 4.5V 4.2 3.98 3.84 3.7 V

l

s

5.2 mA 6.0V 5.7 5.48 5.34 5.2 V

l

VIHor V

IL

s

20 mA 2.0V 0 0.1 0.1 0.1 V

l

4.5V 0 0.1 0.1 0.1 V

6.0V 0 0.1 0.1 0.1 V

e

V

VIHor V

IN

I

l

OUT

I

l

OUT

I

IN

I

CC

Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.

Note 2: Unless otherwise specified all voltages are referenced to ground.

Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:

Note 4: For a power supply of 5V

designing with this supply. Worst case V
I

**V

Maximum Input V
Current

Maximum Quiescent V
Supply Current I

, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.

CC

limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.

IL

e

IN

e

IN

OUT

g

10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when

and VILoccur at V

IH

IL

s

4.0 mA 4.5V 0.2 0.26 0.33 0.4 V

l

s

5.2 mA 6.0V 0.2 0.26 0.33 0.4 V

l

VCCor GND 6.0V

g

0.1

VCCor GND 6.0V 8.0 80 160 mA

e

0 mA

b

12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.

e

5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,

CC

74HC 54HC

eb

T

40 to 85§CT

A

g

1.0

Min Max Units

V

§

§

Units

b
b

40
55

eb

A

55 to 125§C

g

CC

a

85

a

125

1.0 mA

C
C

2

AC Electrical Characteristics V

CC

e

Symbol Parameter Conditions Typ

t

PHL,tPLH

t

PHL,tPLH

AC Electrical Characteristics V

Maximum Propagation 28 35 ns
Delay, Data to R Even

Maximum Propagation 28 35 ns
Delay, Data to R Odd

e

CC

Symbol Parameter Conditions V

t

PHL,tPLH

t

PHL,tPLH

t

TLH,tTHL

C

PD

C

IN

Note 5: CPDdetermines the no load dynamic power consumption, P

Maximum Propagation 2.0V 103 205 258 305 ns
Delay, Data to R Even 4.5V 21 41 52 61 ns

Maximum Propagation 2.0V 103 205 258 305 ns
Delay, Data to R Odd 4.5V 21 41 52 61 ns

Maximum Output Rise 2.0V 30 75 95 110 ns
and Fall Time 4.5V 8 15 19 22 ns

Power Dissipation 83 pF
Capacitance (Note 5)

Maximum Input Capacitance 5 10 10 10 pF

e

D

Logic Diagram

e

5V, T

A

2.0V to 6.0V, C

CC

25§C, C

Guaranteed

L

e

T

A

e

L

Limit

e

25§C

15 pF, t

50 pF, t

e

e

t

6ns

r

f

Units

e

e

t

6 ns (unless otherwise specified)

r

f

74HC 54HC

eb

T

40 to 85§CT

A

eb

A

55 to 125§C

Typ Guaranteed Limits

6.0V 17 35 44 52 ns

6.0V 17 35 44 52 ns

6.0V 7 13 16 19 ns

2

CPDV

faICCVCC, and the no load dynamic current consumption, I

CC

V

GND

CC

e

e

pin 14

pin 7

e

CPDVCCfaICC.

S

Units

’HC280 TL/F/5121– 2

3

Physical Dimensions inches (millimeters)

Order Number MM54HC280J or MM74HC280J

Dual-In-Line Package

NS Package J14A

Dual-In-Line Package

Order Number MM74HC280J,N

MM54HC280/MM74HC280 9-Bit Odd/Even Parity Generator/Checker

LIFE SUPPORT POLICY

NS Package N14A

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.

National Semiconductor National Semiconductor National Semiconductor National Semiconductor
Corporation Europe Hong Kong Ltd. Japan Ltd.

1111 West Bardin Road Fax: (
Arlington, TX 76017 Email: [e-mail] Ocean Centre, 5 Canton Rd. Fax: [phone]
Tel: [phone] Deutsch Tel: (
Fax: [phone] English Tel: (

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

Fran3ais Tel: (
Italiano Tel: (

a

49) 0-180-530 85 86 13th Floor, Straight Block, Tel: [phone]

a

49) 0-180-530 85 85 Tsimshatsui, Kowloon

a

49) 0-180-532 78 32 Hong Kong

a

49) 0-180-532 93 58 Tel: [phone]

a

49) 0-180-534 16 80 Fax: [phone]