National Semiconductor MM54HC251, MM74HC251 Service Manual
MM54HC251/MM74HC251
8-Channel TRI-STATE
General Description
This 8-channel digital multiplexer with TRI-STATE outputs
utilizes advanced silicon-gate CMOS technology. Along with
the high noise immunity and low power consumption of
standard CMOS integrated circuits, it possesses the ability
to drive 10 LS-TTL loads. The large output drive capability
and TRI-STATE feature make this part ideally suited for interfacing with bus lines in a bus oriented system.
This multiplexer features both true (Y) and complement (W)
outputs as well as a STROBE input. The STROBE must be
at a low logic level to enable this device. When the STROBE
input is high, both outputs are in the high impedance state.
When enabled, address information on the data select inputs determines which data input is routed to the Y and W
Multiplexer
É
January 1988
outputs. The 54HC/74HC logic family is speed, function, as
well as pinout compatible with the standard 54LS/74LS logic family. All inputs are protected from damage due to static
discharge by internal diode clamps to V
and ground.
CC
Features
Y
Typical propagation delay
Data select to Y: 26 ns
Y
Wide supply range: 2 –6V
Y
Low power supply quiescent current: 80 mA maximum
(74HC)
Y
TRI-STATE outputs for interface to bus oriented
systems
MM54HC251/MM74HC251 8-Channel TRI-STATE Multiplexer
Connection and Logic Diagrams
Dual-in-Line Package
TL/F/5328– 1
Top View
Order Number MM54HC251 or MM74HC251
Truth Table
Inputs Outputs
Select
CBA S
XXX H Z Z
L L L L D0 D0
L L H L D1 D1
L H L L D2 D2
L H H L D3 D3
H L L L D4 D4
H L H L D5 D5
H H L L D6 D6
H H H L D7 D7
Hehigh logic level, Lelogic level
e
X
irrelevant, Zehigh impedance (off)
D0, D1 . . . D7
Strobe Y W
e
the level of the respective D input
TL/F/5328– 2
TRI-STATEÉis a registered trademark of National Semiconductor Corp.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/5328
Absolute Maximum Ratings (Notes1&2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (IIK,IOK)
DC Output Current, per pin (I
OUT
)
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
STG
b
b
)
b
0.5 toa7.0V
1.5 to V
CC
0.5 to V
CC
g
g
b
g
65§Ctoa150§C
a
1.5V
a
0.5V
20 mA
25 mA
50 mA
Supply Voltage (V
)26V
CC
DC Input or Output Voltage 0 V
(V
IN,VOUT
)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
e
V
2.0V(tr,tf) 1000 ns
CC
e
V
4.5V 500 ns
CC
e
V
6.0V 400 ns
CC
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temp. (T
) (Soldering 10 seconds) 260§C
L
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions V
CC
A
e
T
25§C
Typ Guaranteed Limits
V
Minimum High Level 2.0V 1.5 1.5 1.5 V
IH
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
Maximum Low Level 2.0V 0.5 0.5 0.5 V
IL
Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
Minimum High Level V
OH
Output Voltage
e
VIHor V
l
IN
I
OUT
IL
s
20 mA 2.0V 2.0 1.9 1.9 1.9 V
l
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
l
IN
I
OUT
e
V
Maximum Low Level V
OL
Output Voltage
IL
s
4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
l
s
5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
l
VIHor V
IL
s
20 mA 2.0V 0 0.1 0.1 0.1 V
l
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
I
IN
I
OZ
Maximum Input V
Current
Maximum TRI- StrobeeV
STATE Leakage V
Current
I
CC
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
this supply. Worst case V
CMOS at the higher voltage and so the 6.0V values should be used.
**V
Maximum Quiescent V
Supply Current I
g
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with
and VILoccur at V
IH
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
e
IN
OUT
e
IN
OUT
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICC, and IOZ) occur for
CC
IL
s
4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
l
s
5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
l
VCCor GND 6.0V
CC
e
VCCor GND
6.0V
g
0.1
g
0.5
VCCor GND 6.0V 8.0 80 160 mA
e
0 mA
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
74HC 54HC
eb
T
40 to 85§CT
A
g
1.0
g
5
Min Max Units
V
§
§
Units
b
b
40
55
A
eb
55 to 125§C
g
g
CC
a
85
a
125
1.0 mA
10 mA
C
C
2
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