This 8-channel digital multiplexer with TRI-STATE outputs
utilizes advanced silicon-gate CMOS technology. Along with
the high noise immunity and low power consumption of
standard CMOS integrated circuits, it possesses the ability
to drive 10 LS-TTL loads. The large output drive capability
and TRI-STATE feature make this part ideally suited for interfacing with bus lines in a bus oriented system.
This multiplexer features both true (Y) and complement (W)
outputs as well as a STROBE input. The STROBE must be
at a low logic level to enable this device. When the STROBE
input is high, both outputs are in the high impedance state.
When enabled, address information on the data select inputs determines which data input is routed to the Y and W
Multiplexer
É
January 1988
outputs. The 54HC/74HC logic family is speed, function, as
well as pinout compatible with the standard 54LS/74LS logic family. All inputs are protected from damage due to static
discharge by internal diode clamps to V
and ground.
CC
Features
Y
Typical propagation delay
Data select to Y: 26 ns
Y
Wide supply range: 2 –6V
Y
Low power supply quiescent current: 80 mA maximum
(74HC)
Y
TRI-STATE outputs for interface to bus oriented
systems
XXX H Z Z
LLLLD0D0
LLHLD1D1
LHLLD2D2
LHHLD3D3
HLLLD4D4
HLHLD5D5
HHLLD6D6
HHHLD7D7
Hehigh logic level, Lelogic level
e
X
irrelevant, Zehigh impedance (off)
D0, D1 . . . D7
StrobeYW
e
the level of the respective D input
TL/F/5328– 2
TRI-STATEÉis a registered trademark of National Semiconductor Corp.
C
1995 National Semiconductor CorporationRRD-B30M105/Printed in U. S. A.
TL/F/5328
Page 2
Absolute Maximum Ratings (Notes1&2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (IIK,IOK)
DC Output Current, per pin (I
OUT
)
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
STG
b
b
)
b
0.5 toa7.0V
1.5 to V
CC
0.5 to V
CC
g
g
b
g
65§Ctoa150§C
a
1.5V
a
0.5V
20 mA
25 mA
50 mA
Supply Voltage (V
)26V
CC
DC Input or Output Voltage0V
(V
IN,VOUT
)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
e
V
2.0V(tr,tf)1000ns
CC
e
V
4.5V500ns
CC
e
V
6.0V400ns
CC
Power Dissipation (PD)
(Note 3)600 mW
S.O. Package only500 mW
Lead Temp. (T
) (Soldering 10 seconds)260§C
L
DC Electrical Characteristics (Note 4)
SymbolParameterConditionsV
CC
A
e
T
25§C
TypGuaranteed Limits
V
Minimum High Level2.0V1.51.51.5V
IH
Input Voltage4.5V3.153.153.15V
6.0V4.24.24.2V
V
Maximum Low Level2.0V0.50.50.5V
IL
Input Voltage**4.5V1.351.351.35V
6.0V1.81.81.8V
V
Minimum High Level V
OH
Output Voltage
e
VIHor V
l
IN
I
OUT
IL
s
20 mA2.0V2.01.91.91.9V
l
4.5V4.54.44.44.4V
6.0V6.05.95.95.9V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
l
IN
I
OUT
e
V
Maximum Low Level V
OL
Output Voltage
IL
s
4.0 mA4.5V4.23.983.843.7V
l
s
5.2 mA6.0V5.75.485.345.2V
l
VIHor V
IL
s
20 mA2.0V00.10.10.1V
l
4.5V00.10.10.1V
6.0V00.10.10.1V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
I
IN
I
OZ
Maximum InputV
Current
Maximum TRI-StrobeeV
STATE LeakageV
Current
I
CC
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
this supply. Worst case V
CMOS at the higher voltage and so the 6.0V values should be used.
**V
Maximum Quiescent V
Supply CurrentI
g
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with
and VILoccur at V
IH
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
e
IN
OUT
e
IN
OUT
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICC, and IOZ) occur for
CC
IL
s
4.0 mA4.5V0.20.260.330.4V
l
s
5.2 mA6.0V0.20.260.330.4V
l
VCCor GND6.0V
CC
e
VCCor GND
6.0V
g
0.1
g
0.5
VCCor GND6.0V8.080160mA
e
0 mA
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
74HC54HC
eb
T
40 to 85§CT
A
g
1.0
g
5
MinMaxUnits
V
§
§
Units
b
b
40
55
A
eb
55 to 125§C
g
g
CC
a
85
a
125
1.0mA
10mA
C
C
2
Page 3
AC Electrical Characteristics V
CC
e
5V, T
SymbolParameterConditions Typ
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
t
PZH,tPZL
t
PZH,tPZL
t
PHZ,tPLZ
t
PHZ,tPLZ
Maximum Propagation Delay2635ns
A,BorCtoY
Maximum Propagation2735ns
Delay, A, B or C to W
Maximum Propagation2229ns
Delay, Any D to Y
Maximum Propagation2432ns
Delay, Any D to W
Maximum Output EnableR
Time, W OutputC
Maximum Output EnableR
Time, Y OutputC
Maximum Output Disable Time R
W OutputC
Maximum Output Disable Time R
Y OutputC
e
1kX1927ns
L
e
50 pF
L
e
1kX1926ns
L
e
50 pF
L
e
1kX2640ns
L
e
5pF
L
e
1kX2735ns
L
e
5pF
L
e
A
25§C, C
e
15 pF, t
L
Guaranteed
Limit
r
e
e
t
f
Units
6ns
AC Electrical Characteristics C
e
L
50 pF, t
SymbolParameterConditionsV
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
t
PZH,tPZL
t
PZH,tPZL
t
PHZ,tPLZ
t
PHZ,tPLZ
t
THL,tTLH
C
PD
C
IN
Note 5: CPDdetermines the no load dynamic power consumption, P
Maximum Propagation Delay2.0V 90205256300ns
A, B or C to Y4.5V 31415160ns
Maximum Propagation2.0V 95205256300ns
Delay, A, B or C to W4.5V 32415160ns
Maximum Propagation2.0V 70195244283ns
Delay, any D to Y4.5V 27394957ns
Maximum Propagation2.0V 75185231268ns
Delay, any D to W4.5V 29374654ns
Maximum Output Enable Time R
W Output4.5V 21303844ns
Maximum Output Enable Time R
Y Output4.5V 21293642ns
Maximum Output Disable Time R
W Output4.5V 29445564ns
Maximum Output Disable Time R
Y Output4.5V 30394957ns
Maximum Output Rise2.0V 307595110ns
and Fall Time4.5V8151922ns
Power Dissipation(per package)110pF
Capacitance (Note 5)
Maximum Input5101010pF
Capacitance
e
1kX2.0V 45150188218ns
L
e
1kX2.0V 45145181210ns
L
e
1kX2.0V 60220275319ns
L
e
1kX2.0V 60195244283ns
L
e
CPDV
D
e
e
t
6 ns (unless otherwise specified)
r
CC
f
e
T
25§C
A
74HC54HC
eb
T
40 to 85§CT
A
A
eb
55 to 125§C
TypGuaranteed Limits
6.0V 26354451ns
6.0V 27354451ns
6.0V 23334148ns
6.0V 25324046ns
6.0V 18263338ns
6.0V 18253136ns
6.0V 25374654ns
6.0V 26334148ns
6.0V7131619ns
2
faICCVCC, and the no load dynamic current consumption, I
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implantsupport device or system whose failure to perform can
into the body, or (b) support or sustain life, and whosebe reasonably expected to cause the failure of the life
failure to perform, when properly used in accordancesupport device or system, or to affect its safety or
with instructions for use provided in the labeling, caneffectiveness.
be reasonably expected to result in a significant injury
to the user.
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.