National Semiconductor MM54HC242, MM74HC242, MM54HC243, MM74HC243 Service Manual
January 1988
MM54HC242/MM74HC242
Inverting Quad TRI-STATE
Transceiver
É
MM54HC243/MM74HC243 Quad TRI-STATE Transceiver
General Description
These TRI-STATE bidirectional inverting and non-inverting
buffers utilize advanced silicon-gate CMOS technology and
are intended for two-way asynchronous communication between data buses. They have high drive current outputs
which enable high speed operation when driving large bus
capacitances. These circuits possess the low power dissipation and high noise immunity associated with CMOS circuits, but speeds comparable to low power Schottky TTL
circuits. They can also drive 15 LS-TTL loads.
The MM54HC243/MM74HC243 is a non-inverting buffer
and the MM54HC242/MM74HC242 is an inverting buffer.
Each device has one active high enable (GBA), and one
active low enable (G
AB). GBA enables the A outputs and
Connection Diagrams
G
AB enables the B outputs. This device does not have
Schmitt trigger inputs.
All inputs are protected from damage due to static discharge by diodes to V
and ground.
CC
Features
Y
Typical propagation delay: 12 ns
Y
TRI-STATE outputs
Y
Two way asynchronous communication
Y
High output current: 6 mA (74HC)
Y
Wide power supply range: 2– 6V
Y
Low quiescent supply current: 80 mA (74HC)
MM54HC242/MM74HC242 Inverting Quad TRI-STATE Transceiver
MM54HC243/MM74HC243 Quad TRI-STATE Transceiver
Dual-In-Line Package
Top View
Order Number MM54HC242 or MM74HC242
Truth Tables
’HC242
Control Inputs Data Port Status
GAB GBA A B
H H OUTPUT Input
L H Isolated Isolated
H L Isolated Isolated
L L Input OUTPUT
TL/L/5019– 1
Dual-In-Line Package
TL/L/5019– 2
Top View
Order Number MM54HC243 or MM74HC243
’HC243
Control Inputs Data Port Status
GAB GBA A B
H H OUTPUT Input
L H Isolated Isolated
H L Isolated Isolated
L L Input OUTPUT
TRI-STATEÉis a registered trademark of National Semiconductor Corp.
C
1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
TL/L/5019
Absolute Maximum Ratings (Notes1&2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (IIK,IOK)
DC Output Current, per pin (I
OUT
)
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
STG
b
b
)
b
0.5 toa7.0V
1.5 to V
CC
0.5 to V
CC
g
g
b
g
65§Ctoa150§C
a
1.5V
a
0.5V
20 mA
35 mA
70 mA
Operating Conditions
Supply Voltage (V
DC Input or Output Voltage 0 V
(V
IN,VOUT
Operating Temp. Range (T
MM74HC
MM54HC
Input Rise or Fall Times
)26V
CC
)
e
2.0V(tr,tf) 1000 ns
V
CC
e
4.5V 500 ns
V
CC
e
6.0V 400 ns
V
CC
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temp. (T
) (Soldering 10 seconds) 260§C
L
DC Electrical Characteristics (Note 4)
e
T
25§C
Symbol Parameter Conditions V
CC
A
Typ Guaranteed Limits
V
Minimum High Level 2.0V 1.5 1.5 1.5 V
IH
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
Maximum Low Level 2.0V 0.5 0.5 0.5 V
IL
Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
Minimum High Level V
OH
Output Voltage
e
VIHor V
l
I
OUT
IN
IL
s
20 mA 2.0V 2.0 1.9 1.9 1.9 V
l
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
l
I
OUT
e
IN
V
Maximum Low Level V
OL
Output Voltage
IL
s
6.0 mA 4.5V 4.2 3.98 3.84 3.7 V
l
s
7.8 mA 6.0V 5.7 5.48 5.34 5.2 V
l
VIHor V
IL
s
20 mA 2.0V 0 0.1 0.1 0.1 V
l
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
I
IN
I
OZ
I
CC
Maximum Input V
Current
Maximum TRI-STATE V
Output Leakage Current GABeVIH, GBAeV
Maximum Quiescent V
Supply Current I
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
designing with this supply. Worst case V
, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
I
CC
**V
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
g
e
IN
OUT
e
IN
OUT
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
and VILoccur at V
IH
IL
s
6.0 mA 4.5V 0.2 0.26 0.33 0.4 V
l
s
7.8 mA 6.0V 0.2 0.26 0.33 0.4 V
l
VCCor GND 6.0V
e
VCCor GND 6.0V
IL
g
0.1
g
0.5
VCCor GND 6.0V 8.0 80 160 mA
e
0 mA
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,
CC
74HC 54HC
eb
T
40 to 85§CT
A
g
1.0
g
5.0
Min Max Units
)
A
b
b
40
55
eb
A
a
a
55 to 125§C
g
1.0 mA
g
10 mA
CC
85
125
V
C
§
C
§
Units
2
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