National Semiconductor MM54HC194, MM74HC194 Service Manual
MM54HC194/MM74HC194
4-Bit Bidirectional Universal Shift Register
General Description
This 4-bit high speed bidirectional shift register utilizes advanced silicon-gate CMOS technology to achieve the low
power consumption and high noise immunity of standard
CMOS integrated circuits, along with the ability to drive 10
LS-TTL loads. This device operates at speeds similar to the
equivalent low power Schottky part.
This bidirectional shift register is designed to incorporate
virtually all of the features a system designer may want in a
shift register. It features parallel inputs, parallel outputs,
right shift and left shift serial inputs, operating mode control
inputs, and a direct overriding clear line. The register has
four distinct modes of operation: PARALLEL (broadside)
LOAD; SHIFT RIGHT (in the direction Q
SHIFT LEFT; INHIBIT CLOCK (do nothing).
toward QD);
A
Synchronous parallel loading is accomplished by applying
the four bits of data and taking both mode control inputs, S0
and S1, high. The data are loaded into their respective flip
flops and appear at the outputs after the positive transition
of the CLOCK input. During loading, serial data flow is inhibited. Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low.
Serial data for this mode is entered at the SHIFT RIGHT
data input. When S0 is low and S1 is high, data shifts left
synchronously and new data is entered at the SHIFT LEFT
serial input. Clocking of the flip flops is inhibited when both
mode control inputs are low. The mode control inputs
should be changed only when the CLOCK input is high.
The 54HC/74HC logic family is functionally as well as pinout compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static discharge by internal diode clamps to V
Features
Y
Typical operating frequency: 45 MHz
Y
Typical propagation delay: ns (clock to Q)
Y
Wide operating supply voltage range: 2 –6V
Y
Low input current: 1 mA maximum
Y
Low quiescent supply current: 160 mA maximum
(74HC Series)
Y
Fanout of 10 LS-TTL loads
November 1995
and ground.
CC
MM54HC194/MM74HC194 4-Bit Bidirectional Universal Shift Register
Connection Diagram Dual-In Line Package
TL/F/5323– 1
Function Table
Inputs Outputs
Mode Serial Parallel
Clear
LXXX X XXXXXLLLL
HXX L X XXXXXQ
HHH
HLH
HLH
HHL
HHL
HLL X X XXXXXQ
C
1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
S1 S2
Clock
Left Right A B C D
XXabcdabcd
u
XHXXXXHQAnQBnQ
u
XLXXXXLQAnQBnQ
u
HXXXXXQBnQCnQDnH
u
LXXXXXQBnQCnQDnL
u
TL/F/5323
QAQBQCQ
A0QB0QC0QD0
A0QB0QC0QD0
Order Number MM54HC194 or MM74HC194
Hehigh level (steady state)
e
L
D
Cn
Cn
low level (steady state)
e
X
irrelevant (any input, including transitions)
e
transition from low to high level
u
e
a, b, c, d
respectively.
Q
before the indicated steady-state input conditions were established.
Q
the most-recent
the level of steady-state input at inputs A, B, C, or D,
e
A0,QB0,QC0,QD0
An,QBn,QCn,QDn
the level of QA,QB,QC,orQD, respectively,
e
the level of QA,QB,QC, respectively, before
transition of the clock.
u
Absolute Maximum Ratings (Notes1&2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
)
b
0.5 toa7.0V
b
1.5 to V
b
CC
0.5 to V
CC
b
65§Ctoa150§C
a
a
g
g
g
1.5V
0.5V
20 mA
25 mA
50 mA
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (IIK,IOK)
DC Output Current, per pin (I
OUT
)
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
STG
Supply Voltage (V
)26V
CC
DC Input or Output Voltage 0 V
(V
IN,VOUT
)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
e
V
2.0V(tr,tf) 1000 ns
CC
e
V
4.5V 500 ns
CC
e
V
6.0V 400 ns
CC
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
)
L
(Soldering 10 seconds) 260§C
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions V
CC
A
e
T
25§C
Typ Guaranteed Limits
V
IH
Minimum High Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
IL
Maximum Low Level 2.0V 0.5 0.5 0.5 V
Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
OH
Minimum High Level V
Output Voltage
e
VIHor V
l
I
IN
OUT
IL
s
20 mA 2.0V 2.0 1.9 1.9 1.9 V
l
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
l
I
IN
OUT
e
V
OL
Maximum Low Level V
Output Voltage
IL
s
4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
l
s
5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
l
VIHor V
IL
s
20 mA 2.0V 0 0.1 0.1 0.1 V
l
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
I
IN
I
CC
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
with this supply. Worst case V
I
**V
Maximum Input V
Current
Maximum Quiescent V
Supply Current I
g
and VILoccur at V
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
OZ
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
IH
e
IN
e
IN
OUT
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
IL
s
4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
l
s
5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
l
VCCor GND 6.0V
g
0.1
VCCor GND 6.0V 8.0 80 160 mA
e
0 mA
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICC, and
CC
74HC 54HC
eb
T
40 to 85§CT
A
g
1.0
Min Max Units
V
§
§
Units
b
40
b
55
eb
A
CC
a
85
a
125
55 to 125§C
g
1.0 mA
C
C
2
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