Page 1
MM54HC174/MM74HC174
Hex D Flip-Flops with Clear
MM54HC174/MM74HC174 Hex D Flip-Flops with Clear
January 1988
General Description
These edge triggered flip-flops utilize advanced silicon-gate
CMOS technology to implement D-type flip-flops. They possess high noise immunity, low power, and speeds comparable to low power Schottky TTL circuits. This device contains
6 master-slave flip-flops with a common clock and common
clear. Data on the D input having the specified setup and
hold times is transferred to the Q output on the low to high
transition of the CLOCK input. The CLEAR input when low,
sets all outputs to a low state.
Each output can drive 10 low power Schottky TTL equivalent loads. The MM54HC174/MM74HC174 is functionally
as well as pin compatible to the 54LS174/74LS174. All inputs are protected from damage due to static discharge by
diodes to V
and ground.
CC
Connection and Logic Diagrams
Dual-In-Line Package
Features
Y
Typical propagation delay: 16 ns
Y
Wide operating voltage range: 2 –6V
Y
Low input current: 1 mA maximum
Y
Low quiescent current: 80 mA (74HC Series)
Y
Output drive: 10 LSTTL loads
TL/F/5318– 1
Order Number MM54HC174 or MM74HC174
Truth Table
(Each Flip-Flop)
Inputs Outputs
Clear Clock D Q
LXXL
H
H
HLXQ
e
H
High level (steady state)
e
Low level (steady state)
L
e
Don’t Care
X
e
Transition from low to high level
u
e
The level of Q before the indicated steady state
Q
0
input conditions were established.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
HH
u
LL
u
TL/F/5318
0
TL/F/5318– 2
Page 2
Absolute Maximum Ratings (Notes1&2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (IIK,IOK)
DC Output Current, per pin (I
OUT
)
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
STG
b
b
)
b
0.5 toa7.0V
1.5 to V
CC
0.5 to V
CC
g
g
b
g
65§Ctoa150§C
a
1.5V
a
0.5V
20 mA
25 mA
50 mA
Supply Voltage (V
)26V
CC
DC Input or Output Voltage 0 V
(V
IN,VOUT
)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
e
V
2.0V(tr,tf) 1000 ns
CC
e
V
4.5V 500 ns
CC
e
V
6.0V 400 ns
CC
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
(Soldering 10 seconds) 260
)
L
C
§
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions V
CC
A
e
T
25§C
Typ Guaranteed Limits
V
IH
Minimum High Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
IL
Maximum Low Level 2.0V 0.5 0.5 0.5 V
Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
OH
Minimum High Level V
Output Voltage
e
VIHor V
l
IN
I
OUT
IL
s
20 mA 2.0V 2.0 1.9 1.9 1.9 V
l
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
l
IN
I
OUT
e
V
OL
Maximum Low Level V
Output Voltage
IL
s
4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
l
s
5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
l
VIHor V
IL
s
20 mA 2.0V 0 0.1 0.1 0.1 V
l
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
I
IN
I
CC
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
designing with this supply. Worst case V
I
**V
Maximum Input V
Current
Maximum Quiescent V
Supply Current I
, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
CC
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
e
IN
e
IN
OUT
g
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
and VILoccur at V
IH
IL
s
4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
l
s
5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
l
VCCor GND 6.0V
g
0.1
VCCor GND 6.0V 8.0 80 160 mA
e
0 mA
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,
CC
74HC 54HC
eb
T
40 to 85§CT
A
g
1.0
Min Max Units
V
§
§
Units
b
b
40
55
eb
A
55 to 125§C
g
CC
a
85
a
125
1.0 mA
C
C
2
Page 3
AC Electrical Characteristics V
CC
e
5V, T
Symbol Parameter Conditions Typ
f
MAX
t
PHL,tPLH
t
REM
t
S
t
H
t
W
Maximum Operating 50 30 MHz
Frequency
Maximum Propagation 16 30 ns
Delay, Clock or Clear to Output
Minimum Removal Time,
Clear to Clock
Minimum Setup Time 10 20 ns
Data to Clock
Minimum Hold Time 0 5 ns
Clock to Data
Minimum Pulse Width 10 16 ns
Clock or Clear
e
A
b
25§C, C
e
L
Guaranteed
Limit
15 pF, t
r
e
t
f
Units
25 ns
e
6ns
AC Electrical Characteristics C
e
L
50 pF, t
Symbol Parameter Conditions V
f
MAX
t
PHL,tPLH
t
REM
t
S
t
H
t
W
t
TLH,tTHL
tr,t
C
PD
C
IN
Note 5: CPDdetermines the no load dynamic power consumption, P
Maximum Operating 2.0V 5 4 3 MHz
Frequency 4.5V 27 21 18 MHz
Maximum Propagation 2.0V 55 165 206 248 ns
Delay Clock or Clear to Output 4.5V 18 33 41 49 ns
Minimum Removal Time 2.0V 1 5 5 5 ns
Clear to Clock 4.5V 1 5 5 5 ns
Minimum Setup Time 2.0V 42 100 125 150 ns
Data to Clock 4.5V 12 20 25 30 ns
Minimum Hold Time 2.0V 1 5 5 5 ns
Clock to Data 4.5V 1 5 5 5 ns
Minimum Pulse Width 2.0V 35 80 106 120 ns
Clock or Clear 4.5V 10 16 20 24 ns
Maximum Output Rise 2.0V 30 75 95 110 ns
and Fall Time 4.5V 8 15 19 22 ns
Maximum Input Rise and 2.0V 1000 1000 1000 ns
f
Fall Time 4.5V 500 500 500 ns
Power Dissipation (per package) 136 pF
Capacitance (Note 5)
Maximum Input 5 10 10 10 pF
Capacitance
e
CPDV
D
e
e
t
6 ns (unless otherwise specified)
r
f
74HC 54HC
eb
T
40 to 85§CT
A
A
eb
55 to 125§C
Units
CC
e
T
25§C
A
Typ Guaranteed Limits
6.0V 31 24 20 MHz
6.0V 16 28 35 42 ns
6.0V 1 5 5 5 ns
6.0V 10 17 21 25 ns
6.0V 1 5 5 5 ns
6.0V 8 14 18 20 ns
6.0V 7 13 16 19 ns
6.0V 400 400 400 ns
2
faICCVCC, and the no load dynamic current consumption, I
CC
e
CPDVCCfaICC.
S
3
Page 4
Physical Dimensions inches (millimeters)
Order Number MM54HC174J or MM74HC174J
Dual-In Line Package (J)
See NS Package J16A
MM54HC174/MM74HC174 Hex D Flip-Flops with Clear
Dual-In Line Package (N)
Order Number MM74HC174N
See NS Package N16E
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
National Semiconductor National Semiconductor National Semiconductor National Semiconductor
Corporation Europe Hong Kong Ltd. Japan Ltd.
1111 West Bardin Road Fax: (
Arlington, TX 76017 Email: cnjwge@tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408
Tel: 1(800) 272-9959 Deutsch Tel: (
Fax: 1(800) 737-7018 English Tel: (
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
Fran3ais Tel: (
Italiano Tel: (
a
49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309
a
49) 0-180-530 85 85 Tsimshatsui, Kowloon
a
49) 0-180-532 78 32 Hong Kong
a
49) 0-180-532 93 58 Tel: (852) 2737-1600
a
49) 0-180-534 16 80 Fax: (852) 2736-9960
Loading...