MM74HC160 Synchronous
Decade Counter with Asynchronous Clear
MM54HC161/MM74HC161 Synchronous
Binary Counter with Asynchronous Clear
MM54HC162/MM74HC162 Synchronous
Decade Counter with Synchronous Clear
MM54HC163/MM74HC163 Synchronous
Binary Counter with Synchronous Clear
General Description
The MM54HC160/MM74HC160, MM54HC161/
MM74HC161, MM54HC162/MM74HC162, and
MM54HC163/MM74HC163 synchronous presettable counters utilize advanced silicon-gate CMOS technology and internal look-ahead carry logic for use in high speed counting
applications. They offer the high noise immunity and low
power consumption inherent to CMOS with speeds similar
to low power Schottky TTL. The ’HC160 and the ’HC162 are
4 bit decade counters, and the ’HC161 and the ’HC163 are
4 bit binary counters. All flip-flops are clocked simultaneously on the low to high transition (positive edge) of the CLOCK
input waveform.
These counters may be preset using the LOAD input. Presetting of all four flip-flops is synchronous to the rising edge
of CLOCK. When LOAD is held low counting is disabled and
the data on the A, B, C, and D inputs is loaded into the
counter on the rising edge of CLOCK. If the load input is
taken high before the positive edge of CLOCK the count
operation will be unaffected.
All of these counters may be cleared by utilizing the CLEAR
input. The clear function on the MM54HC162/MM74HC162
and MM54HC163/MM74HC163 counters are synchronous
to the clock. That is, the counters are cleared on the positive edge of CLOCK while the clear input is held low.
The MM54HC160/MM74HC160 and MM54HC161/
MM74HC161 counters are cleared asynchronously. When
the CLEAR is taken low the counter is cleared immediately
regardless of the CLOCK.
Two active high enable inputs (ENP and ENT) and a RIPPLE CARRY (RC) output are provided to enable easy cascading of counters. Both ENABLE inputs must be high to
count. The ENT input also enables the RC output. When
enabled, the RC outputs a positive pulse when the counter
overflows. This pulse is approximately equal in duration to
the high level portion of the Q
to successive cascaded stages to facilitate easy implementation of N-bit counters.
All inputs are protected from damage due to static discharge by diodes to V
CC
Features
Y
Typical operating frequency: 40 MHz
Y
Typical propagation delay; clock to Q: 18 ns
Y
Low quiescent current: 80 mA maximum (74HC Series)
Y
Low input current: 1 mA maximum
Y
Wide power supply range: 2–6V
output. The RC output is fed
A
and ground.
74HC160/MM54/74HC161/MM54/74HC162/MM54/74HC163
January 1992
Connection Diagram
Order Number MM54HC161/162/163
or MM74HC160/161/162/163
C
1995 National Semiconductor CorporationRRD-B30M115/Printed in U. S. A.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (IIK,IOK)
DC Output Current, per pin (I
OUT
)
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
STG
b
b
)
b
0.5 toa7.0V
1.5 to V
CC
0.5 to V
CC
g
g
b
g
65§Ctoa150§C
a
1.5V
a
0.5V
20 mA
25 mA
50 mA
Power Dissipation (PD)
Supply Voltage (V
DC Input or Output Voltage0V
(V
IN,VOUT
Operating Temp. Range (T
MM74HC
MM54HC
Input Rise or Fall Times
)26V
CC
)
e
V
2.0V(tr,tf)1000ns
CC
e
4.5V500ns
V
CC
e
6.0V400ns
V
CC
(Note 3)600 mW
S.O. Package only500 mW
Lead Temp. (T
) (Soldering 10 seconds)260§C
L
DC Electrical Characteristics (Note 4)
SymbolParameterConditionsV
CC
A
e
T
25§C
TypGuaranteed Limits
V
IH
Minimum High Level2.0V1.51.51.5V
Input Voltage4.5V3.153.153.15V
6.0V4.24.24.2V
V
IL
Maximum Low Level2.0V0.50.50.5V
Input Voltage**4.5V1.351.351.35V
6.0V1.81.81.8V
V
OH
Minimum High LevelV
Output Voltage
e
VIHor V
l
I
IN
OUT
IL
s
20 mA2.0V2.01.91.91.9V
l
4.5V4.54.44.44.4V
6.0V6.05.95.95.9V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
l
I
IN
OUT
e
V
OL
Maximum Low LevelV
Output Voltage
IL
s
4.0 mA4.5V4.23.983.843.7V
l
s
5.2 mA6.0V5.75.485.345.2V
l
VIHor V
IL
s
20 mA2.0V00.10.10.1V
l
4.5V00.10.10.1V
6.0V00.10.10.1V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
I
IN
I
CC
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
with this supply. Worst case V
I
**V
Maximum InputV
Current
Maximum QuiescentV
Supply CurrentI
g
and VILoccur at V
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
OZ
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
IH
e
IN
e
IN
OUT
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
IL
s
4.0 mA4.5V0.20.260.330.4V
l
s
5.2 mA6.0V0.20.260.330.4V
l
VCCor GND6.0V
g
0.1
VCCor GND6.0V8.080160mA
e
0 mA
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICC, and
CC
74HC54HC
eb
T
40 to 85§CT
A
g
1.0
MinMaxUnits
)
A
b
b
40
55
eb
A
55 to 125§C
g
a
a
1.0mA
CC
85
125
V
C
§
C
§
Units
2
Page 3
AC Electrical Characteristics V
CC
5V, T
e
A
25§C, C
e
L
15 pF, t
e
e
t
6ns
r
f
e
SymbolParameterConditionsTypGuaranteed LimitUnits
f
MAX
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
t
PHL
t
REM
t
S
t
H
t
W
Maximum Operating Frequency4330MHz
Maximum Propagation Delay, Clock to RC3035ns
Maximum Propagation Delay, Clock to Q2934ns
Maximum Propagation Delay, ENT to RC1832ns
Maximum Propagation Delay, Clear to Q or RC2738ns
Minimum Removal Time, Clear to Clock1020ns
Minimum Set Up Time Clear, Load,30ns
Enable or Data to Clock
Minimum Hold Time, Data from Clock5ns
Minimum Pulse Width Clock,16ns
Clear, or Load
AC Electrical Characteristics C
e
L
SymbolParameterConditionsV
f
MAX
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
REM
t
S
t
S
t
S
t
H
Maximum Operating2.0V10544MHz
Frequency4.5V40272118MHz
Maximum Propagation2.0V100215271320ns
Delay, Clock to RC4.5V32435464ns
Maximum Propagation2.0V88175220260ns
Delay, Clock to RC4.5V18354452ns
Maximum Propagation2.0V95205258305ns
Delay, Clock to Q4.5V30415261ns
Maximum Propagation2.0V85170214253ns
Delay, Clock to Q4.5V17344351ns
Maximum Propagation2.0V90195246291ns
Delay, ENT to RC4.5V28394958ns
Maximum Propagation2.0V80160202238ns
Delay, ENT to RC4.5V16324048ns
Maximum Propagation2.0V100220275325ns
Delay, Clear to RC4.5V32445566ns
Maximum Propagation2.0V100210260315ns
Delay, Clear to Q4.5V32425263ns
Minimum Removal Time2.0V125158186ns
Clear to Clock4.5V253237ns
Minimum Setup2.0V150190225ns
Time Clear or Data4.5V303845ns
to Clock6.0V263238ns
Minimum Setup2.0V135170200ns
Time Load4.5V273441ns
to Clock6.0V232935ns
Minimum Setup2.0V175220260ns
Time Enable4.5V354452ns
to Clock6.0V303744ns
Minimum Hold Time2.0V506375ns
Data from Clock4.5V101315ns
e
50 pF, t
CC
e
t
6 ns (unless otherwise specified)
r
f
e
T
25§C
A
74HC54HC
eb
T
A
40 to 85§CT
A
eb
55 to 125§C
Units
TypGuaranteed Limits
6.0V45322521MHz
6.0V28374654ns
6.0V15303744ns
6.0V26354452ns
6.0V14293643ns
6.0V24334249ns
6.0V14273441ns
6.0V28374755ns
6.0V28364554ns
6.0V212732ns
6.0V91113ns
3
Page 4
AC Electrical Characteristics (Continued) C
SymbolParameterConditions V
t
H
t
W
t
TLH,tTHL
tr,t
C
PD
C
IN
Note 5: CPDdetermines the no load dynamic power consumption, P
e
I
S
Minimum Hold Time2.0V000ns
Enable, Load or Clear4.5V000ns
to Clock6.0V000ns
(1) Clear outputs to zero
(2) Preset to binary twelve
(3) Count to thirteen, fourteen, fifteen, zero, one and two
(4) Inhibit
5
Page 6
Physical Dimensions inches (millimeters)
Order Number MM54HC160J, MM54HC161J, MM54HC162J, MM54HC163J,
MM74HC160J, MM74HC161J, MM74HC162J, MM74HC163J
NS Package J16A
74HC160/MM54/74HC161/MM54/74HC162/MM54/74HC163
Order Number MM74HC160N, MM74HC161N, MM74HC162N, MM74HC163N
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or2. A critical component is any component of a life
systems which, (a) are intended for surgical implantsupport device or system whose failure to perform can
into the body, or (b) support or sustain life, and whosebe reasonably expected to cause the failure of the life
failure to perform, when properly used in accordancesupport device or system, or to affect its safety or
with instructions for use provided in the labeling, caneffectiveness.
be reasonably expected to result in a significant injury
to the user.
National SemiconductorNational SemiconductorNational SemiconductorNational Semiconductor
CorporationEuropeHong Kong Ltd.Japan Ltd.
1111 West Bardin RoadFax: (
Arlington, TX 76017Email: cnjwge@tevm2.nsc.comOcean Centre, 5 Canton Rd.Fax: 81-043-299-2408
Tel: 1(800) 272-9959Deutsch Tel: (
Fax: 1(800) 737-7018English Tel: (
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.