National Semiconductor CD4027BM, CD4027BC Service Manual
CD4027BM/CD4027BC Dual J-K Master/Slave
Flip-Flop with Set and Reset
CD4027BM/CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset
February 1988
General Description
These dual J-K flip-flops are monolithic complementary
MOS (CMOS) integrated circuits constructed with N- and Pchannel enhancement mode transistors. Each flip-flop has
independent J, K, set, reset, and clock inputs and buffered
Q and Q
outputs. These flip-flops are edge sensitive to the
clock input and change state on the positive-going transition
of the clock pulses. Set or reset is independent of the clock
and is accomplished by a high level on the respective input.
All inputs are protected against damage due to static discharge by diode clamps to V
DD
and VSS.
Schematic and Connection Diagrams
Features
Y
Wide supply voltage range 3.0V to 15V
Y
High noise immunity 0.45 VDD(typ.)
Y
Low power TTL Fan out of 2 driving 74L
compatibility or 1 driving 74LS
Y
Low power 50 nW (typ.)
Y
Medium speed operation 12 MHz (typ.)
with 10V supply
TL/F/5958– 1
Dual-In-Line Package
Order Number CD4027B
Top View
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/5958
TL/F/5958– 2
Absolute Maximum Ratings (Note 1 and 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
DC Supply Voltage (V
DD
)
Input Voltage (VIN)
Storage Temperature Range (TS)
b
0.5 VDCtoa18 V
b
0.5V to V
b
65§Ctoa150§C
DD
a
0.5 V
DC
DC
Recommended Operating
Conditions
DC Supply Voltage (VDD) 3Vto15V
Input Voltage (VIN) 0VtoVDDV
Operating Temperature Range (TA)
CD4027BM
CD4027BC
(Note 2)
b
55§Ctoa125§C
b
40§Ctoa85§C
Power Dissipation (PD)
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature (T
(Soldering, 10 seconds) 260
)
L
C
§
DC Electrical Characteristics CD4027BM (Note 2)
b
Symbol Parameter Conditions
55§C
Min Max Min Typ Max Min Max
I
V
V
V
V
I
I
I
Quiescent Device Current V
DD
Low Level
OL
Output Voltage V
High Level
OH
Output Voltage V
Low Level V
IL
Input Voltage V
High Level V
IH
Input Voltage V
Low Level Output V
OL
Current (Note 3) V
High Level Output V
OH
Current (Note 3) V
Input Current V
IN
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2: V
Note 3: I
e
0V unless otherwise specified.
SS
and IOLare tested one output at a time.
OH
e
DD
e
V
DD
e
V
DD
k
I
l
l
O
e
DD
e
V
DD
e
V
DD
k
I
l
l
O
e
DD
e
V
DD
e
V
DD
e
DD
e
DD
e
V
DD
e
DD
e
DD
e
V
DD
e
DD
e
DD
e
V
DD
e
DD
e
DD
e
V
DD
e
DD
e
V
DD
e
5V, V
10V, V
15V, V
IN
IN
IN
VDDor V
e
VDDor V
e
VDDor V
SS
SS
SS
1130mA
2260mA
4 4 120 m A
1 mA
5V 0.05 0 0.05 0.05 V
10V 0.05 0 0.05 0.05 V
15V 0.05 0 0.05 0.05 V
1 mA
5V 4.95 4.95 5 4.95 V
10V 9.95 9.95 10 9.95 V
15V 14.95 14.95 15 14.95 V
e
5V, V
10V, V
15V, V
5V, V
10V, V
15V, V
5V, V
10V, V
15V, V
5V, V
10V, V
15V, V
15V, V
15V, V
0.5V or 4.5V 1.5 1.5 1.5 V
O
e
1V or 9V 3.0 3.0 3.0 V
O
e
1.5V or 13.5V 4.0 4.0 4.0 V
O
e
0.5V or 4.5V 3.5 3.5 3.5 V
O
e
1V or 9V 7.0 7.0 7.0 V
O
e
1.5V or 13.5V 11.0 11.0 11.0 V
O
e
0.4V 0.64 0.51 0.88 0.36 mA
O
e
0.5V 1.6 1.3 2.25 0.9 mA
O
e
1.5V 4.2 3.4 8.8 2.4 mA
O
e
4.6V
O
e
9.5V
O
e
13.5V
O
e
0V
IN
e
15V 0.1 10
IN
b
0.64
b
1.6
b
4.2
b
0.1
a
b
0.51b0.88
b
1.3b2.25
b
3.4b8.8
b
25§C
b
5
b
10
0.1
b
5
0.1 1.0 mA
a
125§C
b
0.36 mA
b
0.9 mA
b
2.4 mA
b
1.0 mA
DC
DC
Units
2
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