3.Manufacturing site ................................................................................................................................. 3
4.Part Number ........................................................................................................................................... 3
19.8. Input Power Capacity: ........................................................................................................ 35
20.PRECONDITION TO USE OUR PRODUCTS ............................................................................... 36
Please be aware that an important notice concerning availability, standard warranty and use in critical applications of
Murata products and disclaimers thereto appears at the end of this specification sheet.
Stresses in excess of the absolute ratings may cause permanent damage. Functional operation
is not implied under these conditions. Exposure to absolute ratings for extended periods of time
may adversely affect reliability. No damage assuming only one parameter is set at limit at a time
with all other parameters are set within operating condition.
10. OPERATING CONDITION
*2)
8 / 44
*2)
Functionality is guaranteed but the specifications require the derating at over-temperatures,
over-voltage condition.
Preliminary & Confidential
< Specification may be changed by Murata without notice >
Murata(China) Investment Co., Ltd.
Preliminary Specification Number : SP-ZZ1PJ-331-J
9 / 44
11. External low–power 32.768 kHz clock
The 32 kHz clock is used in low-power modes such as IEEE power-save and sleep. It serves as a timer
to determine when to wake up to receive beacons in various power-save schemes and to maintain
basic logic operations when in sleep.
Type1PJ module does not require an external 32 kHz clock. By default, Type1PJ module utilizes its
internal 200 kHz clock shared with the WLAN and BT subsystem.
If the end application has a more accurate 32 kHz clock, then it can be supplied externally via the
LF_CLK_IN pin. The LF_CLK_IN pin must be grounded when using the default internal clock mode. If
an external 32 kHz clock is used, the requirements are:
Preliminary & Confidential
< Specification may be changed by Murata without notice >
Murata(China) Investment Co., Ltd.
Preliminary Specification Number : SP-ZZ1PJ-331-J
Symbol
Parameter
Min
Max
Units
ta1
No requirement if VDDIO_AO connected to 3.3 V
0 - μs
ta2
90% of 3.3 V to 10% of 1.8 V
0 - μs
ta3
90% of VDDIO_GPIO to 0.7 V of both WLAN_EN and BT_EN
10 - μs
ta4
WLAN_EN valid to LF_CLK_IN input
0 - μs
ta5
WLAN_EN de-assert (“low”) to LF_CLK_IN de-assert
(tristate or low)
0 - μs
ta6
Both WLAN_EN = low and BT_EN = low to 90% of 1.8 V
10 - μs
ta7
3.3 V always higher than 1.8 V during operation, with power
off by removing battery or unplugging AC/DC
0 - μs
ta8
VDDIO_AO and VDDIO_XTAL should be connected to 3.3 V
power rail
0 - μs
12. POWER SEQUENCE Timing
12.1. Case 1: 3.3 V power down after 1.8 V
If the battery source can be removed from the end user device (battery removed, AC/DC plugged
in), this is the recommended power sequence. It will avoid violating the power off sequence by
allowing the 3.3 V rail to shut down after the 1.8 V rail.
Notes:
1. VDDIO_GPIO voltage should match VIO voltage from the host. In some applications,
VDDIO_GPIO may connected to 3.3 V upon Host VIO voltage.
2. In this case, both WLAN_EN and BT_EN on the 1PJ are at 3.3 V due to using the VDD_AO
power rail. If the host VIO voltage is 1.8 V, it must have level shifters to interface with host.
3. All host interface signals must stay floating or low before valid power on sequence (WLAN_EN
and BT-EN goes high).
10 / 44
Preliminary & Confidential
< Specification may be changed by Murata without notice >
Murata(China) Investment Co., Ltd.
Preliminary Specification Number : SP-ZZ1PJ-331-J
Symbol
Parameter
Min
Max
Units
tb1
No requirement if VDDIO_AO connected to 1.8 V
0 - μs
tb2
90% of 1.8 V to 10% of 3.3 V
0 - μs
tb3
90% of 3.3 V to 0.7 V of both WLAN_EN and BT_EN
10 - μs
tb4
WLAN_EN valid to LF_CLK_IN input
0 - μs
tb5
WLAN_EN de-assert (“low”) to LF_CLK_IN de-assert
(tristate or low)
0 - μs
tb6
Both WLAN_EN = low and BT_EN = low to 90% of 3.3 V
10 - μs
tb7
10% of 3.3 V to 90% of 1.8 V
0 - μs
tb8
VDDIO_AO and VDDIO_XTAL should be connected to 1.8 V
power rail
0 - μs
12.2. Case 2: 1.8 V power down after 3.3 V
If the battery source cannot be removed from the end user device, this is the recommended
power sequence for this application. This sequence allows the software to control the power
on/off sequence.
Notes:
1. VDDIO_GPIO voltage should match VIO voltage from the host. In some applications,
VDDIO_GPIO may connected to 3.3 V upon host VIO voltage.
2. Both WLAN_EN and BT_EN of 1PJ are 1.8 V. If host VIO voltage is 1.8 V, it does
not need level shifter to interface with host.
3. All host interface signals must stay floating or low before WLAN_EN/BT_EN =”high”, and
after WLAN_EN/BT_EN = Low.
11 / 44
Preliminary & Confidential
< Specification may be changed by Murata without notice >
Murata(China) Investment Co., Ltd.
Preliminary Specification Number : SP-ZZ1PJ-331-J
Symbol
Parameter
Min
Max
Units
tc1
90% of 3.3 V to 0.7 V of both WLAN_EN and BT_EN
0 - μs
tc4
WLAN_EN valid to LF_CLK_IN input
0 - μs
tc5
WLAN_EN de-assert (“low”) to LF_CLK_IN de-assert (tristate
or low)
0 - μs
tc6
Both WLAN_EN = low and BT_EN = low to 90% of 3.3 V
10 - μs
Symbol
Parameter
Comments
Minimum
Type
Maximum
Unit
VIH
High-level input voltage
0.7x
VDDIO
-
VDDIO +
0.3
V
VIL
Low-level input voltage
-0.3 - 0.3x
VDDIO
V
VSHYS
Schmitt hysteresis
-
1.8 V IO: 375
3.3 V IO: 645
-
mV
IIL
Input low leakage current
VIN = 0 V
Supply = VIO
max
-5 - 5
uA
RPULL
Input pull resistor
Up or down
-
1.8 V IO: 120
3.3 V IO: 70
-
kohm
VOH
High-level output voltage
0.9x
VDDIO
-
VDDIO
V
VOL
Low-level output voltage
0 - 0.1x
VDDIO
V
IOH
High-level output current
3 - -
mA
IOL
Low-level output current
- - -11
mA
CIN
Input capacitance
- - 3
pF
12.3. Case 3: All power rails supplied with 3.3 V
All power pins are connected to 3.3 V only include VDDIO_AO, VDDIO_XTAL, VDDIO_GPIOx.
Notes:
All host signals are either GND or floating before WLAN_EN/BT_EN =”high”, and after
WLAN_EN/BT_EN = Low.
12 / 44
13. Digital I/O Requirements
Preliminary & Confidential
< Specification may be changed by Murata without notice >
Murata(China) Investment Co., Ltd.
Preliminary Specification Number : SP-ZZ1PJ-331-J
Parameter
Description
Min
Typ
Max
Unit
toff
txd
Delay from CTS to TXD stop
- - 8
byte
Parameter
Description
Min
Typ
Max
Unit
toff
rxd
Delay from RTS to RXD stop
- - 8
byte
Transmitter
Receiver
Lower Limit
Upper Limit
Lower Limit
Upper Limit
Min
Max
Min
Max
Min
Max
Min
Max
Notes
Clock Period T
Ttr - - - Ttr - - - a
Master Mode: Clock generated by transmitter or receiver
HIGH tHC
0.35Ttr - - - 0.35Ttr - - - b
LOW tLC
0.35Ttr - - - 0.35Ttr - - - b
Slave Mode: Clock accepted by transmitter or receiver
HIGH hTC
-
0.35Ttr - - - 0.35Ttr - - c LOW tLC
-
0.35Ttr - - - 0.35Ttr - - c Rise time tRC
- - 0.15Ttr - - - - - d
Transmitter
Delay t
dtr
- - - 0.8T - - - - e Hold time t
htr
0 - - - - - - - d
Receiver
Setup time tsr
- - - - -
0.2Tr - - f Hold time thr
- - - - - 0 - - f
toff
txd
toff
rxd
14. INTERFACE TIMING
14.1. Bluetooth UART Timing
14.1.1. UART transmit Timing
14.1.2. UART Receiver Timing
13 / 44
14.2. I2S Timing
Notes:
a. The system clock period T must be greater than T
able to handle the data transfer rate.
b. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space
ratio. For this reason, tHC and t
are specified with respect to T.
LC
c. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH a nd LOW periods so that
they can detect the signal. So long as the minimum periods are greater than 0.35Tr, any clock that meets the
requirements can be used.
d. Because the delay(t
) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter
dtr
driven by a slow clock edge can result in t
Therefore, the transmitter has to guarantee that t
rise-time tRC is not more than t
RCmax
, where t
and Tr because both the transmitter and receiver have to be
tr
not exceeding tRC which means t
dtr
RCmax
is greater than or equal to zero, so long as the clock
htr
is not less than 0.15Ttr.
becomes zero or negative.
htr
e.To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the
clock signal and T, always giving the receiver sufficient setup time.
f.The data setup and hold time must not be less than the specified receiver setup and hold time.
< Specification may be changed by Murata without notice >
Preliminary & Confidential
Murata(China) Investment Co., Ltd.
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