MSI MS-6791 Schematics 30A
8
7
6
5
4
3
2
1
MS-6791
D D
C C
Willamette/Northwood 478pin mPGA-B
Processor Schematics
* Northwood / Prescott mPGA-478B Processor
*SIS 648FX / 661+964 / 964L
*REALTEK 8100C LAN
*Winbond 83687THF I/O
*USB 2.0 support x8
*ALC 655 AC97 CODEC
*VIA 1394 6307
ERP BOM Function Description
501/601-6791
19S
501/601-6791
20S
Opt : SG
Opt : SD
04/14/2004 Update
661FX+964L,W/LAN, WO/1394, ALC655
Intel pin define
648FX+964L,W/LAN, WO/1394, ALC655
Intel pin define
Cover Sheet
Block Diagram
MAIN CLOCK GEN & DDR CLOCK BUFFER
mPGA478-B INTEL CPU Sockets
SIS 648FX / 661
DDR SLOT
DDR TERMINATOR
SIS 964 / 964L
AGP SLOT
PCI SLOTS
LAN CONTROLLER
RJ45 CONNECTOR
IDE CONNECTOR
USB CONNECTOR
AC'97 CODEC
AUDIO CONNECTOR & VGA
1
2
3
4 - 5
6 - 8
9
10
11 - 14
15
16
17
18
19
20
21
22
Version 30A
Title
23
24
25
26
27
28
29
30
31
MS-6791
Cover Sheet
Sheet of
1 31
1
Rev
300
FAN
B B
LPC I/O(W83697HF)
PARALLEL & SERIAL PORT
ACPI CONTROLLER
VRM 10
ATX POWER CON
FRONT PANEL
1394
Decoupling Capacitor
A A
Micro-Star
Document Number
Last Revision Date:
8
7
6
5
4
3
Friday, May 14, 2004
2
5
4
3
2
1
GPIO_0
GPIO_1
System Block Diagram
D D
SOCKET 478
Host Bus
Support Dual Monitor
VGA
1.5 V ONLY
C C
Support Max to six-PCI Devices
Lan
IDE 1
B B
IDE 2
PCI SLOT 3 PCI SLOT 2 PCI SLOT 1
KEYBOARD
/MOUSE
VIA
6307 1394
PS/2
AGP SLOT
SIS 648FX
SIS 661 FX
HYPERZIP
SIS 964
LPC BUS
DDR SDRAM
AUDIO CODEC
USB 0
USB 1
DDR1 DDR2 RTT
AC'97
USB 2 USB 3
USB 5
ANALOG IN
ANALOG OUT
6 CHANNEL
USB 4
USB 6
USB 7
GPIO_2
GPIO_3 EXTSMI#
GPIO_4
GPIO_5
GPIO_6
GPI_7 RESUME
GPI_8 RING
GPI_9
GPI_10
GPIO_11
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
GPIO_18
GPIO_19
GPIO_20
GPIO_21
GPIO_22
GPIO_23
GPIO_24
PCI Config.
DEVICE
PCI Slot 2
PCI Slot 3 PCI_REQ#2 AD19
1394_1
FAN1 FAN2 FAN3
LEGACY
ROM
FAN CONTROL
LPC SUPER I/O
H/W MONITOR
SATA_1
SATA_2
LAN PIRQ#C PCI_REQ#3
I/O
MAIN
I/O
MAIN
MAIN
I/O
MAIN
I/O
I/O
MAIN
I/O
MAIN
I/O
MAIN
I/O
RESUME
I/O
RESUME
I/O
RESUME
I/O
RESUME
I/O
I/O
RESUME
I/O
RESUME
I/O
I/O
RESUME
O
RESUME
O
RESUME
O
RESUME
I/O
MAIN
I/O
MAIN
I
RESUME
I
RESUME
I
RESUME
I RESUME
PIRQ#B
PIRQ#C
PIRQ#D
PIRQ#A
PIRQ#C
PIRQ#D
PIRQ#A
PIRQ#B
PIRQ#D
PIRQ#A
PIRQ#B
PIRQ#C
1394 PIRQ#D PCI_REQ#4
Flash Rom protection
Pull-Up
THERM#
Pull-Up
RESERVED
RESERVED
Prescott ratio
RESERVED
RESERVED
Pull-Down
Pull-DownGPIO_12 RESUME
Pull-Up
Pull-Down
KBDAT
KBCLK
MSDAT
MSCLK
SMBCLK
SMBDAT
RESERVED
RESERVED
RESERVED
RESERVED
IDSEL
PCI_REQ#0PCI Slot 1
AD17
PCI_GNT#0
PCI_REQ#1 AD18 PCICLK2
PCI_GNT#1
PCI_GNT#2
AD22 LAN_PCLK
PCI_GNT#3
AD23 1394_PCLK
PCI_GNT#4
CLOCKREQ#/GNT#MCP1 INT Pin
PCICLK1
PCICLK3
GPIO Table on SIS964
GPIOS IR/CIR COM PRINTER FLOPPY
A A
PCI RESET DEVICE
Signals
PCIRST#1
PCIRST_964
HDDRST#
5
4
3
Northbridge,LAN,1394,S/IO
PCI1~3PCIRST#2
AGP
Primary, Scondary IDE
Target
2
Micro-Star
Document Number
Last Revision Date:
Wednesday, April 14, 2004
Title
MS-6791
System Block Diagram
Sheet of
1
Rev
300
2 31
5
VCC3
VCC3
D D
VCC3 VCC3
C C
VCCP
R259
10K
B B
C210
X_10p
VCCM
CB117
X_0.1u
R269
10K
Q40
2N3904S
C244
X_4.7U/0805
CB125
0.1u
CB62
0.1u
CB116
0.1u
R268
10K
Q39
2N3904S
C54
4.7U/0805
CB126
0.1u
CB114
0.1u
R260
CB73
0.1u
CB109
X_0.1u
VCC3
CB108
X_0.1u
CB72
0.1u
CB127
0.1u
FS2
475RST
4
Main Clock Generator
U16
ICS952019
1
VDDREF
11
VDDZ
13
VDDPCI
19
VDDPCI
28
VDD48
29
VDDAGP
42
VDDCPU
48
VDDSD
5
VSSREF
8
VSSZ
18
VSSPCI
24
VSSPCI
25
VSS48
32
VSSAGP
41
VSSCPU
45
GNDSRC
12
PCICLK5/FS2*
33
PD#/VTT_PWRGD
38
IREF
36
VDDA
CB113
102p
37
VSSA
XIN
6
C233
14M-32pf-HC49S-D
27p
Y1
CPUCLK0
CPUCLK#0
CPUCLK1
CPUCLK#1
AGPCLK0
AGPCLK1
ZCLK0
ZCLK1
PCICLK6/FS3**
PCICLK7/FS4
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK8
REF0/FS0
REF1/FS1
RESET#
12/48M
24_48M/MULTISEL
SCLK
SDATA
SRCCLKT
SRCCLKC
XOUT
7
C226
27p
3
R275
R278
R276
R277
40
39
44
43
31
30
9
10
FS3
14
FS4
15
16
17
20
21
22
23
FS0
2
FS1
3
4
27
26
35
34
47
46
R270
R271
R296
R297
RN51 8P4R-33
RN76 8P4R-33
RN52 8P4R-33
SEL12_48
MULTISEL
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
R261
R272
R424
R425
CPUCLK1
33
CPUCLK-1
33
CPUCLK0
33
CPUCLK-0
33
AGPCLK0
33
AGPCLK1
33
ZCLK0
22
ZCLK1
22
96XPCLK
SIOPCLK
PCICLK1
PCICLK2
PCICLK3
LAN_PCLK
1394_PCLK
REFCLK1
DCLK
REFCLK2
12MHz
OSC12
22
22
33
33
48MHz
SIO48M
SMBCLK
SMBDAT
SATACLK
SATACLK-
F0~F4 internal Pull-Down 120K
VCC3
R305
R304
FS2
0
0
0 133
0
1
1
CPUCLK1 6
CPUCLK-1 6
CPUCLK0 4
CPUCLK-0 4
AGPCLK0 6
AGPCLK1 15
ZCLK0 8
ZCLK1 11
96XPCLK 11
SIOPCLK 24
PCICLK1 16
PCICLK2 16
PCICLK3 16
LAN_PCLK 17
1394_PCLK 30
REFCLK1 12
DCLK 8
REFCLK2 21
FP_RST# 26,29
OSC12 13
SIO48M 24
SMBCLK 9,12,17,26
SMBDAT 9,12,17,26
SATACLK 13
SATACLK- 13
2.7K
2.7K R300
FS0
FS1FS4
0 100
0
0
000 0
2
MULTISEL internal Pull-Up 120K
MULTISEL
0=48MHZ,1=24MHZ
SEL12_48
0=48MHZ,1=12MHZ
R301
SRC
CPU
100
ZCLK
133
133
100
133 66 33100200
VCC3
R285 4.7K
R274 4.7K
BSEL1 4
BSEL0 4
FS2
10K
FS3
10K
AGP
660
66
CB69
X_0.1u
EMI
PCIFS3
330
33
X_0.1u
VCC3
CB129
CPUCLK0
CPUCLK-0
CPUCLK1
CPUCLK-1
SATACLK
SATACLK-
PCICLK2
PCICLK1
SIOPCLK
96XPCLK
1394_PCLK
LAN_PCLK
PCICLK3
REFCLK2
DCLK
REFCLK1
SIO48M
OSC12
1
R262
R263
R264
R265
R422
R423
CN12 X_8P4C_10p
1 2
3 4
5 6
7 8
CN17 X_8P4C_10p
1 2
3 4
5 6
7 8
CN13 X_8P4C_10p
1 2
3 4
5 6
7 8
C220 X_10p
C215 X_10p
DDRCLK0
DDRCLK1
DDRCLK2
DDRCLK3
DDRCLK8
DDRCLK7
49.9RST
49.9RST
49.9RST
49.9RST
49.9RST
49.9RST
C71 X_10p
C49 X_10p
C56 X_10p
C72 X_10p
C47 X_10p
C45 X_10p
U6
CBVDD
VCCM
A A
5
CB66
CB71
X_0.1u
0.1u
SMBCLK
SMBDAT
FWDSDCLKO7
FWDSDCLKO
ICS93732
3
VDD
12
VDD
23
VDD
10
AVDD
7
SCLK
22
SDATA
8
CLK_IN
20
FB_IN
9
NC
18
NC
21
NC
GND
GND
GND
GND
111528
6
4
Clock Buffer (DDR)
DDRCLK0
2
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK#0
CLK#1
CLK#2
CLK#3
CLK#4
CLK#5
FB_OUT
DDRCLK3
4
DDRCLK2
13
DDRCLK1
17
DDRCLK8
24
DDRCLK7
26
DDRCLK-0
1
DDRCLK-3
5
DDRCLK-2
14
DDRCLK-1
16
DDRCLK-8
25
DDRCLK-7
27
R106
19
DDRCLK0 9
DDRCLK3 9
DDRCLK2 9
DDRCLK1 9
DDRCLK8 9
DDRCLK7 9
DDRCLK-0 9
DDRCLK-3 9
DDRCLK-2 9
DDRCLK-1 9
DDRCLK-8 9
DDRCLK-7 9
10
FB_OUT
C48
10p
3
CB61
X_0.1u
VCC3
CB74
X_0.1u
FOR EMI
X_0.1u
CB55
CB77
X_0.1u
Micro-Star
Document Number
Last Revision Date:
2
Monday, April 26, 2004
DDRCLK-0
DDRCLK-1
DDRCLK-2
DDRCLK-3
DDRCLK-8
DDRCLK-7
Title
C70 X_10p
C50 X_10p
C57 X_10p
C73 X_10p
C46 X_10p
C44 X_10p
MS-6791
MAIN CLOCK GEN & BUFFER
Sheet of
1
3 31
Rev
300
8
HA#[3..31]6
D D
HDBI#[0..3]6
STPCLK#12
HDBSY#6
HDRDY#6
HTRDY#6
HLOCK#6
HDEFER#6
C C
CPU_TMPA24
VTIN_GND24
THERMTRIP#12
PROCHOT#12
CPUSLP#12
CPUVID_GD27
B B
CPURST#6
HDBI#0
HDBI#1
HDBI#2
HDBI#3
FERR#
FERR#12
STPCLK#
HINIT#
HINIT#12
HDBSY#
HDRDY#
HTRDY#
HADS#
HADS#6
HLOCK#
HBNR#
HBNR#6
HIT#
HIT#6
HITM#
HITM#6
HBPRI#
HBPRI#6
HDEFER#
TDI_CPU
TDO_CPU
TMS_CPU
TRST#_CPU
TCK_CPU
THERMTRIP#
AF26
PROCHOT#
IGNNE#
IGNNE#12
SMI#
SMI#12
A20M#
A20M#12
CPUSLP#
AB26
CPUVID_GD
AE21
AF24
AF25
PGD_CPU
AB23
CPURST#
AB25
HD#63
AA24
HD#62
AA22
HD#61
AA25
HD#59
HD#58
HD#57
W25
HD#56
HD#55
W26
HD#54
U4A
E21
G25
P26
V21
AC3
V6
B6
Y4
AA3
W5
AB2
H5
H2
J6
G1
G4
G2
F3
E3
D2
E2
C1
D5
F7
E6
D4
B3
C4
A2
C3
B2
B5
C6
A22
A7
AD2
Y21
Y24
Y23
Y26
V24
7
HA#[3..31]
HA#27
HA#26
HA#25
HA#31
AB1Y1W2V3U4T5W1R6V2T4U3P6U1T2R3P4P3R2T1N5N4N2M1N1M4M3L2M6L3K1L6K4K2
A35#
A34#
A33#
DBI0#
DBI1#
DBI2#
DBI3#
IERR#
MCERR#
FERR#
STPCLK#
BINIT#
INIT#
RSP#
DBSY#
DRDY#
TRDY#
ADS#
LOCK#
BNR#
HIT#
HITM#
BPRI#
DEFER#
TDI
TDO
TMS
TRST#
TCK
THERMDA
THERMDC
THERMTRIP#
SKTOCC#
PROCHOT#
IGNNE#
SMI#
A20M
SLP#
RESERVED
RESERVED
CPU_VIDPWRGD
RESERVED
RESERVED
RESERVED
PWRGOOD
RESET#
D63#
D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#
A32#
D53#
D52#
D51#
D50#
D49#
D48#
D47#
V22
U21
V25
U23
U24
U26
T23
T22
HA#24
HA#23
HA#22
HA#21
HA#20
HA#19
HA#18
A24#
A23#
A22#
A21#
A20#
A19#
A18#
HA#17
A17#
HA#30
A31#
A30#
HA#29
HA#28
A29#
A28#
A27#
A26#
A25#
Socket478-1
D46#
D45#
D44#
D43#
D42#
D41#
D40#
D39#
D38#
D37#
D36#
D35#
D34#
D33#
T25
T26
R24
R25
P24
R21
N25
D32#
N26
M26
N23
M24
P21
N22
M23
6
HA#16
A16#
D31#
H25
HA#15
A15#
D30#
K23
5
VCC_SENSE 27
VSS_SENSE 27
VID5 27
VID4 27
VID3 27
VID2 27
VID1 27
VID0 27
VSS_SENSE
HA#13
HA#12
HA#11
HA#10
HA#14
HA#9
HA#8
HA#7
HA#6
A9#
A8#
A7#
A14#
A13#
D29#
D28#
J24
L22
A6#
A12#
A11#
A10#
D27#
D26#
D25#
D24#
D23#
D22#
D21#
M21
H24
G26
L21
D26
F26
E25
HA#5
F24
HA#4
A5#
D20#
VCC_SENSE
HA#3
AE25A5A4
A4#
A3#
DBR
VCC_SENSE
D19#
D18#
D17#
D16#
D15#
D14#
D13#
F23
G23
E24
H22
D25
J21
D23
C26
AD26
AC26
ITP_CLK1
ITP_CLK0
VSS_SENSE
D12#
D11#
D10#
D9#
H21
G22
B25
C24
VID3
VID4
VID5
AE1
AE2
AD3
VID4#
VID5#
D8#
D7#
D6#
C23
B24
D22
VID2
AE3
VID3#
D5#
C21
VID1
AE4
VID2#
D4#
A25
VID0
AE5
VID1#
D3#
A23
VID0#
GTLREF3
GTLREF2
GTLREF1
GTLREF0
TESTHI12
TESTHI11
TESTHI10
TESTHI9
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0
ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#
D2#
D1#
B22
B21
BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#
REQ4#
REQ3#
REQ2#
REQ1#
REQ0#
BCLK1#
BCLK0#
RS2#
RS1#
RS0#
AP1#
AP0#
BR0#
COMP1
COMP0
DP3#
DP2#
DP1#
DP0#
LINT1
LINT0
D0#
BSEL0
AD6
Open-D
BSEL1
AD5
AA21
AA6
F20
F6
AB4
AA5
Y6
AC4
AB5
AC6
H3
J3
J4
K5
J1
AD25
A6
Y3
W4
U6
AB22
AA20
AC23
AC24
AC20
AC21
AA2
AD24
AF23
AF22
F4
G5
F1
V5
AC1
H6
P1
L24
L25
K26
K25
J26
R5
L5
W23
P23
J23
F21
W22
R22
K22
E22
E5
D1
4
GTLREF1
BPM#5
BPM#4
BPM#3
BPM#2
BPM#1
BPM#0
HREQ#4
HREQ#3
HREQ#2
HREQ#1
HREQ#0
RN71 62_8P4R
3 4
RN71 62_8P4R
1 2
RN72 62_8P4R
1 2
RN72 62_8P4R
3 4
RN72 62_8P4R
5 6
RN71 62_8P4R
5 6
RN71 62_8P4R
7 8
HRS#2
HRS#1
HRS#0
BREQ#0
R58 61.9RST
R101 61.9RST
HADSTB#1
HADSTB#0
HDSTB3
HDSTB2
HDSTB1
HDSTB0
HDSTB#3
HDSTB#2
HDSTB#1HD#60
HDSTB#0
NMI
INTR
HREQ#4 6
HREQ#3 6
HREQ#2 6
HREQ#1 6
HREQ#0 6
VCCP
CPUCLK-0 3
CPUCLK0 3
HRS#2 6
HRS#1 6
HRS#0 6
BREQ#0 6
* Short trace
HADSTB#1 6
HADSTB#0 6
HDSTB3 6
HDSTB2 6
HDSTB1 6
HDSTB0 6
HDSTB#3 6
HDSTB#2 6
HDSTB#1 6
HDSTB#0 6
NMI 12
INTR 12
3
FERR#, STPCLK#, SMI#,
CPUSLP#, A20M#, INTR, NMI,
IGNNE#, INIT#
-----REGISTER CONTROLLER
NEED SETTING
2
1
CPU GTL REFERNCE VOLTAGE BLOCK
Length < 1.5inch.
GTLREF1
2/3*Vccp
Every pin put one 220pF cap near it.
Trace Width 15mils, Space 15mils.
Keep the voltage dividers within 1.5 inches of the
first GTLREF Pin
CPU STRAPPING RESISTORS
CLOSED TO SOCKET478
THERMTRIP#
FERR#
PROCHOT#
BREQ#0
CPURST#
PWRGD_CPU
STPCLK#
HINIT#
SMI#
CPUSLP#
A20M#
INTR
NMI
IGNNE#
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
PGD_CPU
CPURST#
CPUSLP#
VCCP
C39
C38 R92
1u-0805220p
R70 62
R23 62
R33 120
R67 200KST
R96 62
R103 300RST
R28 49.9RST
R29 49.9RST
R22 49.9RST
R21 49.9RST
RN3
7 8
5 6
3 4
1 2
8P4R-56
RN73 62_8P4R
1 2
RN73 62_8P4R
5 6
RN73 62_8P4R
3 4
RN72 62_8P4R
7 8
RN73 62_8P4R
7 8
R50 62
X_150pC40
X_150pC41
X_150pC5
R91
49.9RST
100RST
VCCP
HD#7
HD#6
HD#5
HD#9
HD#52
HD#51
HD#53
HD#50
HD#49
HD#48
HD#47
HD#46
HD#45
HD#44
HD#[0..63]6
HD#[0..63]
SOCKET478-15U
HD#43
VIDPWRGD DC Specifications
VIL
VIH
It must rout to the enable pin of PWM and CK-409.
VIDGD to Vccp delay time is from 1ms to 10ms.
A A
VIDGD rising time is 150ns.
Min MaxTyp
0.9
8
0.3
GPIO712
PWRGD_CPU6
PWRGD_CPU PGD_CPU
7
HD#41
HD#39
HD#42
HD#40
Q53 2N3904S
HD#38
HD#37
VCC3
HD#36
HD#35
R445
R446
470
1K
HD#34
HD#33
HD#30
HD#29
HD#31
HD#32
Plase near CPU
6
HD#28
HD#27
VCCP
HD#26
HD#25
R447
HD#24
HD#23
62
HD#22
HD#21
HD#19
HD#20
HD#18
HD#17
HD#15
HD#16
HD#14
HD#13
HD#12
BSEL03
BSEL13
HD#11
HD#10
HD#8
5
HD#0
HD#4
HD#3
HD#2
HD#1
Micro-Star
Document Number
Last Revision Date:
4
3
Tuesday, April 20, 2004
2
CPU ITP BLOCK
CLOSED TO SOCKET478
TDO_CPU
TMS_CPU
TDI_CPU
TCK_CPU
TRST#_CPU
Title
R46 75RST
R45 39
R69 150RST
R32 27
R31 680
MS-6791
mPGA478 CPU-1
VCCP
Sheet of
4 31
1
Rev
300
8
U4B
D D
C C
BOOT27
B B
D10
VSS
A11
VSS
A13
VSS
A15
VSS
A17
VSS
A19
VSS
A21
VSS
A24
VSS
A26
VSS
A3
VSS
A9
VSS
AA1
VSS
AA11
VSS
AA13
VSS
AA15
VSS
AA17
VSS
AA19
VSS
AA23
VSS
AA26
VSS
AA4
VSS
AA7
VSS
AA9
VSS
AB10
VSS
AB12
VSS
AB14
VSS
AB16
VSS
AB18
VSS
AB20
VSS
AB21
VSS
AB24
VSS
AB3
VSS
AB6
VSS
AB8
VSS
AC11
VSS
AC13
VSS
AC15
VSS
AC17
VSS
AC19
VSS
AC2
VSS
AC22
VSS
AC25
VSS
AC5
VSS
AC7
VSS
AC9
VSS
AD1
BOOTSELECT
AD10
VSS
AD12
VSS
AD14
VSS
AD16
VSS
AD18
VSS
AD21
VSS
AD23
VSS
AD4
VSS
AD8
VSS
AE11
VSS
P2
VSS
P22
VSS
P25
VSS
P5
VSS
R1
VSS
R23
VSS
R26
VSS
R4
VSS
T21
VSS
T24
VSS
T3
VSS
T6
VSS
U2
VSS
U22
VSS
U25
VSS
U5
VSS
V1
VSS
V23
VSS
SOCKET478-15U
VCCP
A10
AE13
A12
VCC
VSS
AE15
VCC
VSS
A14
VCC
VSS
AE17
A16
AE19
A18
VCC
VSS
AE22
7
A20A8AA10
AA12
AA14
AA16
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
OPTIMIZED/COMPAT#
VSS
VSS
VSS
AE24
AE26
AE7
AE9
AF1
AF10
VCC
VSS
AA18
AF12
VCC
VSS
AA8
AF14
VCC
VSS
AB11
AF16
VCC
VSS
AB13
AF18
VCC
VSS
AB15
AF20
VCC
VSS
AB17
VCC
AB19
AF6
VCC
VSS
6
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
AE16
AE18
AE20
AE6
AE8
AF11
AF13
AF15
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF8
B10
B12
B14
B16
B18
B23
B20
B26B4B8
C11
C13
C15
C17C2C19
C22
C25C5C7C9D12
VSS
D14
D16
D18
AF17
AF19
AF2
AF21
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
D20
D21D3D24D6D8E1E11
5
VCC_VID26,27
AF5
AF7
AF9
B11
B13
B15
B17
B19B7B9
C10
C12
AF4
AF3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCVID
VCCVIDPRG
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E13
E15
E17
E19
E23
V26V4W21
W24W3W6Y2Y22
VSS
Y25
C17
X_0.1u
VCC-IOPLL
VSS
VSS
Y5
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCA
VSSA
AD22
4
3
2
1
CPU DECOUPLING CAPACITORS
VCCP
VCCP
F19
F9
C14
C16
C18
C20
C8
D11
D13
D15
D17
D19
D7
D9
E10
E12
E14
E16
E18
E20
E8
F11
F13
F15
F17
E26
VSS
E4
VSS
E7
VSS
E9
VSS
F10
VSS
F12
VSS
F14
VSS
F16
VSS
F18
VSS
F2
VSS
F22
VSS
F25
VSS
F5
VSS
F8
VSS
G21
VSS
G24
VSS
G3
VSS
G6
VSS
H1
VSS
H23
VSS
H26
VSS
H4
VSS
J2
VSS
J22
VSS
J25
VSS
J5
VSS
K21
VSS
K24
VSS
K3
VSS
K6
VSS
L1
VSS
L23
VSS
L26
VSS
L4
VSS
M2
VSS
M22
VSS
M25
VSS
M5
VSS
N21
VSS
N24
VSS
N3
VSS
N6
VSS
AE23
AD20
C34
C37
1u
10u/1206
L6 4.7UH/0805
L5 4.7UH/0805
C36
10u/1206
CB36
220U/SP
CB37
220U/SP
CB25
X_10u/1206
CB26
X_10u/1206
CB27
X_10u/1206
CB28
X_10u/1206
CB42
X_47U/1210
VCCP
VCCP
CB47
X_10u/1206
CB38
X_10u/1206
CB23
X_10u/1206
CB12
X_10u/1206
Place these caps within north/south side of processorPlace these caps within socket cavity
VCCP
CB24
X_10u/1206
CB13
X_10u/1206
CB48
X_10u/1206
CB39
X_10u/1206
VCCP
CB18
100u/1210
CB41
X_10u/1206
CB34
X_10u/1206
CB30
X_10u/1206
CB21
X_10u/1206
CB44
X_47U/1210
R104
OPTIMIZED
COMPAT#
A A
49.9RST
OPEN
8
OPEN
0
R1 R1R2
X_49.9RST
R94
X_0
7
VCCP
R2
Title
Micro-Star
Document Number
Last Revision Date:
6
5
4
3
Tuesday, April 20, 2004
2
MS-6791
mPGA478 CPU-2
Sheet of
1
Rev
300
5 31
5
4
3
2
1
AGPST[0..2]15
NB_VREF
C4XAVSS
C4XAVDD
C1XAVSS
C1XAVDD
D D
CPUCLK13
CPUCLK-13
HLOCK#4
HDEFER#4
HTRDY#4
CPURST#4
PWRGD_CPU4
BREQ#04
HDRDY#4
HDBSY#4
HREQ#44
HREQ#34
HREQ#24
HREQ#14
C C
HA#[3..31]4
B B
HREQ#04
HADSTB#14
HADSTB#04
CPUCLK1
CPUCLK-1
HLOCK#
HDEFER#
HTRDY#
CPURST#
HBPRI#
HBPRI#4
BREQ#0
HRS#2
HRS#24
HRS#1
HRS#14
HRS#0
HRS#04
HADS#
HADS#4
HITM#
HITM#4
HIT#
HIT#4
HDRDY#
HDBSY#
HBNR#
HBNR#4
HREQ#4
HREQ#3
HREQ#2
HREQ#1
HREQ#0
HADSTB#1
HADSTB#0
HA#31
HA#30
HA#29
HA#28
HA#27
HA#26
HA#25
HA#24
HA#23
HA#22
HA#21
HA#20
HA#19
HA#18
HA#17
HA#16
HA#15
HA#14
HA#13
HA#12
HA#11
HA#10
HA#9
HA#8
HA#7
HA#6
HA#5
HA#4
HA#3
AJ31
AJ33
W34
W35
W31
W33
AG31
AA33
AH33
AG33
AJ35
AF32
AJ34
AH32
AG35
AE31
AH35
AF35
AE35
AE33
AE34
AF33
AG34
AC33
AD32
AD33
AC35
AD35
AC31
AC34
AB35
AB32
AB33
AA35
AA31
AA34
T33
T35
V32
B23
F22
R34
U31
R33
T32
U35
V35
R35
U34
U33
V33
Y33
Y35
Y32
U9A
CPUCLK
CPUCLK#
HLOCK#
DEFER#
HTRDY#
CPURST#
CPUPWRGD
BPRI#
BREQ0#
RS#2
RS#1
RS#0
ADS#
HITM#
HIT#
DRDY#
DBSY#
BNR#
HREQ4#
HREQ3#
HREQ2#
HREQ1#
HREQ0#
HASTB1#
HASTB0#
HA31#
HA30#
HA29#
HA28#
HA27#
HA26#
HA25#
HA24#
HA23#
HA22#
HA21#
HA20#
HA19#
HA18#
HA17#
HA16#
HA15#
HA14#
HA13#
HA12#
HA11#
HA10#
HA9#
HA8#
HA7#
HA6#
HA5#
HA4#
HA3#
648FX
C24
HD63#
E23
HD62#
B24
AL36
C1XAVSS
HD61#
HD60#
D23
AK34
AJ36
AK35
C4XAVSS
C1XAVDD
C4XAVDD
HOST
HD59#
HD58#
HD57#
HD56#
HD55#
D25
F24
C26
B25
B26
AA26
W26
HVREF0
HD54#
D27
D26
HNCVREF
HNCOMP
HPCOMP
AGPST0
AGPST2
AGPST1
D22
C22
B22B6F7B5Y5W4V2W6V4U2V5U4R2T4R3T5P2R4N2R6L3L4K2L6J2J3K4J4J6H4G3H5F2G4E2G6E3F4D2F5E4B2E6
U26
R26
L20
ST0
HCOMP_P
HCOMP_N
HCOMPVREF_N
ST1
HVREF1
HVREF2
HVREF3
HVREF4
GAD6
GAD5
GAD3
GAD4
GAD2
GAD1
GAD0
ST2
AAD0
AAD1
AAD2
AAD3
AAD4
AAD5
GAD7
AAD6
GAD8
AAD7
GAD9
AAD8
GAD10
AAD9
GAD11
AAD10
AAD11
GAD13
GAD12
AAD12
GAD14
AAD13
AAD14
GAD15
GAD16
AAD15
AAD16
GAD18
GAD17
AAD17
GAD19
AAD18
AAD19
GAD20
GAD21
AAD20
AAD21
GAD22
GAD23
AAD22
GAD24
AAD23
AAD24
GAD25
SIS648-1
HD53#
HD52#
HD51#
HD50#
HD49#
HD48#
HD47#
HD46#
HD45#
HD44#
HD43#
HD42#
HD41#
HD40#
HD39#
HD38#
HD37#
HD36#
HD35#
HD34#
HD33#
HD32#
HD31#
HD30#
HD29#
HD28#
HD27#
HD26#
HD25#
HD24#
HD23#
HD22#
HD21#
HD20#
HD19#
HD18#
E27
B27
D28
C28
B28
E29
F28
B29
C30
B30
B31
C32
D29
C33
B33
B35
D32
B34
E31
D31
D33
D35
G31
C35
F33
E33
D34
E35
F32
HD17#
J34
G34
H35
F35
J33
J31
G35
H33
GAD26
GAD28
GAD27
AAD25
AAD26
AAD27
AAD28
AGP
HD16#
HD15#
HD14#
HD13#
J35
K32
N33
GAD29
GAD30
AAD29
HD12#
K33
L31
GAD[0..31] 15 SBA[0..7] 15
GAD31
SBA6
SBA4
SBA2
SBA5
SBA0
SBA1
SBA3
SBA7
B3
GC/BE#3
K5
AAD30
AAD31
HD11#
HD10#
L33
SBA7
SBA6
SBA5
SBA4
HD9#
HD8#
HD7#
HD6#
HD5#
K35
L35
M35
M33
P32
AC/BE3#
SBA3
SBA2
SBA1
SBA0
AC/BE2#
AC/BE1#
AC/BE0#
AREQ#
AGNT#
AFRAME#
AIRDY#
ATRDY#
ADEVSEL#
ASERR#
ASTOP#
APAR
RBF#
WBF#
AGP8XDET#
ADBIH/PIPE#
ADBIL
SB_STB
SB_STB#
AD_STB0
AD_STB0#
AD_STB1
AD_STB1#
AGPCLK
AGPCOMP_P
AGPCOMP_N
A1XAVDD
A1XAVSS
A4XAVDD
A4XAVSS
AGPVREF
AGPVSSREF
HDSTBN3#
HDSTBN2#
HDSTBN1#
HDSTBN0#
HDSTBP3#
HDSTBP2#
HDSTBP1#
HDSTBP0#
HD4#
HD3#
HD2#
HD1#
HD0#
DBI3#
DBI2#
P33
L34
DBI1#
N34
N35
P35
F26
B32
E34
R31
DBI0#
M5
P4
U6
C6
E8
N6
M4
N4
L2
P5
M2
N3
D7
B4
C7
C4
D6
C2
D3
T2
U3
G2
H2
D8
R205 44.2RST
W2
R206 49.9RST
Y2
B8
C8
A7
B7
W3
Y4
HDSTB#3
D24
HDSTB#2
F30
HDSTB#1
G33
HDSTB#0
N31
HDSTB3
E25
HDSTB2
D30
HDSTB1
H32
HDSTB0
M32
GC/BE#2
GC/BE#1
GC/BE#0
GREQ#
GGNT#
GFRAME#
GIRDY#
GTRDY#
GDEVSEL#
GSERR#
GSTOP#
GPAR
RBF#
WBF#
8X_DET
DBIH
DBIL
A1XAVDD
A1XAVSS
A4XAVDD
A4XAVSS
GREQ# 15
GGNT# 15
GFRAME# 15
GIRDY# 15
GTRDY# 15
GDEVSEL# 15
GSERR# 15
GSTOP# 15
GPAR 15
RBF# 15
WBF# 15
8X_DET 15
DBIH 15
DBIL 15
SBSTB
SBSTB#
ADSTB0
ADSTB#0
ADSTB1
ADSTB#1
AGPCLK0 3
VREF4X_IN 15
HDSTB#3 4
HDSTB#2 4
HDSTB#1 4
HDSTB#0 4
HDSTB3 4
HDSTB2 4
HDSTB1 4
HDSTB0 4
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
GC/BE#[0..3] 15
SBSTB 15
SBSTB# 15
ADSTB0 15
ADSTB#0 15
ADSTB1 15
ADSTB#1 15
VDDQ
AGP3.0 = 50 ohm
VCC3
L16
CP8
X_COPPER
C1XAVDD
X_80S/0603
CB80
C79
0.1u
X_103P
C1XAVSS
CP9
L17
X_80S/0603
VCC3 VCC3
X_COPPER
L15
CP7
X_COPPER
C4XAVDD A4XAVDD
X_80S/0603
CB79
C78
0.1u
X_103P
C4XAVSS
CP6
L14
X_80S/0603
X_COPPER
Closed to SIS648(U8)
VCC3
X_80S/0603
X_80S/0603
L30
C127
X_103P
L29
L31
X_80S/0603
C135
X_103P
L32
X_80S/0603
CP23
X_COPPER
A1XAVDDPWRGD_CPU
CB96
0.1u
A1XAVSS
CP22
X_COPPER
CP24
X_COPPER
CB99
0.1u
A4XAVSS
CP25
X_COPPER
HD#47
HD#46
HD#45
HD#44
HD#41
HD#39
HD#34
HD#36
HD#42
HD#40
HD#38
HD#43
HD#37
4
HD#35
HD#33
HD#32
HD#31
HD#30
HD#59
HD#63
HD#58
HD#[0..63]4
A A
5
HD#50
HD#51
HD#52
HD#56
HD#48
HD#49
HD#53
HD#54
HD#60
HD#57
HD#62
HD#61
HD#55
HD#23
HD#22
HD#24
HD#25
HD#21
C104
X_103P
C101
0.1u
HD#19
HD#20
HD#18
HD#16
HD#17
C96
X_103P
HD#14
HD#15
NB_VREF
HD#26
HD#28
HD#27
HD#29
VCCP VCCP
R145
75RST
R137
150RST
HD#13
HD#12
HD#11
HD#10
HD#7
HDBI#0
HDBI#3
HDBI#1
HDBI#2
R132
C95
X_103P
150RST
HNCVREF
R134
C100
103P
75RST
3
HDBI#[0..3] 4
VCCP
R140 15RST
R147 100RST
648 use 20RST
648 use 113RST
Rds-on(n) = 10 ohm
HNCOMP
HNCVERF = 1/3 VCCP
Rds-on(p) = 56 ohm
HPCOMP
HPCVERF = 2/3 VCCP
2
Micro-Star
Document Number
Last Revision Date:
Tuesday, April 20, 2004
Title
MS-6791
SIS648FX-Host & AGP
Sheet of
1
Rev
300
6 31
HD#6
HD#8
HD#9
HD#5
HD#3
HD#4
HD#0
HD#2
HD#1
5
RMD1
RN6
RMD5
RMD4
RMD0
RMD3
RMD7
RMD6
D D
RMD2
RMD13
RMD12
RMD9
RMD8
RMD11
RMD10
RMD15
RMD14
RMD21
RMD17
RMD16
RMD20
RMD23
RMD19
RMD22
RMD18
RMD25
RMD29
RMD28
RMD24
RMD27
RMD31
RMD30
RMD26
RMD33
RMD37
RMD36
RMD32
RMD35
C C
RMD39
RMD38
RMD34
RMD41
RMD45
RMD44
RMD40
RMD47
RMD46
RMD43
RMD42
RMD51
RMD50
RMD55
RMD54
RMD52
RMD53
RMD49
RMD48
RMD57
RMD61
RMD56
RMD60
RMD59
RMD58
RMD63
RMD62
RDQS0
RDQS1
B B
RDQS2
RDQS3
RDQS4
RDQS5
RDQS6
RDQS7
RDQM0
RDQM1
RDQM2
RDQM3
RDQM4
RDQM5
RDQM6
RDQM7
1 2
3 4
5 6
X_8P4R-10
7 8
RN8
1 2
3 4
5 6
X_8P4R-10
7 8
RN11
1 2
3 4
5 6
X_8P4R-10
7 8
RN14
1 2
3 4
5 6
X_8P4R-10
7 8
RN17
1 2
3 4
5 6
X_8P4R-10
7 8
RN20
1 2
3 4
5 6
X_8P4R-10
7 8
RN22
1 2
3 4
5 6
X_8P4R-10
7 8
RN27
1 2
3 4
5 6
X_8P4R-10
7 8
RN31
1 2
3 4
5 6
X_8P4R-10
7 8
RN33
1 2
3 4
5 6
X_8P4R-10
7 8
RN34
1 2
3 4
5 6
X_8P4R-10
7 8
RN36
1 2
3 4
5 6
X_8P4R-10
7 8
RN41
1 2
3 4
5 6
X_8P4R-10
7 8
RN38
1 2
3 4
5 6
X_8P4R-10
7 8
RN44
1 2
3 4
5 6
X_8P4R-10
7 8
1 2
3 4
RN46
5 6
X_8P4R-10
7 8
R68 X_10
R74 X_10
R81 X_10
R88 X_10
R116 X_10
R146 X_10
R167 X_10
R196 X_10
R65 X_10
R76 X_10
R83 X_10
R93 X_10
R122 X_10
R143 X_10
R159 X_10
R192 X_10
RMD1
RMD5
RMD4
RMD0
RMD3
RMD7
RMD6
RMD2
RMD13
RMD12
RMD9
RMD8
RMD11
RMD10
RMD15
RMD14
RMD21
RMD17
RMD16
RMD20
RMD23
RMD19
RMD22
RMD18
RMD25
RMD29
RMD28
RMD24
RMD27
RMD31
RMD30
RMD26
RMD33
RMD37
RMD36
RMD32
RMD35
RMD39
RMD38
RMD34
RMD41
RMD45
RMD44
RMD40
RMD47
RMD46
RMD43
RMD42
RMD51
RMD50
RMD55
RMD54
RMD52
RMD53
RMD49
RMD48
RMD57
RMD61
RMD56
RMD60
RMD59
RMD58
RMD63
RMD62
RDQS0
RDQS1
RDQS2
RDQS3
RDQS4
RDQS5
RDQS6
RDQS7
RDQM0
RDQM1
RDQM2
RDQM3
RDQM4
RDQM5
RDQM6
RDQM7
RMD0
RMD1
RMD2
RMD3
RMD4
RMD5
RMD6
RMD7
RDQM0
RDQS0
RMD8
RMD9
RMD10
RMD11
RMD12
RMD13
RMD14
RMD15
RDQM1
RDQS1
RMD16
RMD17
RMD18
RMD19
RMD20
RMD21
RMD22
RMD23
RDQM2
RDQS2
RMD24
RMD25
RMD26
RMD27
RMD28
RMD29
RMD30
RMD31
RDQM3
RDQS3
RMD32
RMD33
RMD34
RMD35
RMD36
RMD37
RMD38
RMD39
RDQM4
RDQS4
RMD40
RMD41
RMD42
RMD43
RMD44
RMD45
RMD46
RMD47
RDQM5
RDQS5
RMD48
RMD49
RMD50
RMD51
RMD52
RMD53
RMD54
RMD55
RDQM6
RDQS6
RMD56
RMD57
RMD58
RMD59
RMD60
RMD61
RMD62
RMD63
RDQM7
RDQS7
AN35
AP36
AK33
AM33
AN34
AK32
AR34
AN33
AR35
AP34
AM32
AL31
AR31
AL30
AN32
AR33
AN31
AM31
AR32
AP32
AP30
AR30
AM29
AL27
AN30
AN29
AL28
AN28
AL29
AR29
AP26
AN25
AR24
AL24
AL25
AR26
AM25
AN24
AP24
AR25
AN21
AP20
AN20
AL18
AM21
AR21
AL19
AM19
AL20
AR20
AL15
AL14
AN15
AR15
AN16
AM15
AN14
AL13
AP16
AR16
AM13
AL12
AL11
AR12
AP14
AR14
AN13
AP12
AN12
AR13
AL10
AR11
AM11
AN11
AP10
AN10
AR10
4
VDDQ
AA1
AA2
AA3
U9B
MD0
VDDQ
VDDQ
VDDQ
MD1
MD2
MD3
MD4
MD5
MD6
MD7
DQM0
DQS0/CSB0#
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
DQM1
DQS1/CSB1#
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
DQM2
DQS2/CSB2#
MD24
MD25
MD26
MD27
MD28
MD29
SIS648-2
MD30
MD31
DQM3
DQS3/CSB3#
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
DQM4
DQS4/CSB4#
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
DQM5
DQS5/CSB5#
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
DQM6
DQS6/CSB6#
MD56
MD57
AM9
MD58
AR9
MD59
MD60
MD61
MD62
AN9
MD63
DQM7
DQS7/CSB7#
F11
NC
E16
NC
E11
NC
VSS
VSS
VSS
A22
A24
A26
AA4
AA5
AA6
AB1
AB2
AB3
AB4
AB5
AB6
AC1
AC2
AC3
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
Memory
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A28
A30
A32
A34
VSS
C23
C25
C27
C29
C31
C34
C36
E22
AC4
AC5
VDDQ
VDDQ
VDDQ
S3AUXSW#
FWDSDCLKO
DDRVREFA
DDRVREFB
DRAM_SEL
DDRCOMP_P
DDRCOMP_N
VSS
VSS
VSS
E24
E26
AC6
L11
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
MA10
MA11
MA12
MA13
MA14
MA15
SRAS#
SCAS#
SWE#
CS0#
CS1#
CS2#
CS3#
CS4#
CS5#
CKE0
CKE1
CKE2
CKE3
CKE4
CKE5
SDRCLKI
DLLAVDD
DLLAVSS
DDRAVDD
DDRAVSS
VSS
VSS
E28
E30
3
RMD[0..63]
RDQM[0..7]
RDQS[0..7]
RMA[0..15]
L12
L13
M11
M12
M13
M14
M15
M16
N11
N12
P12
R12
T12
U12
V12
RMA0
AR23
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
NC
NC
NC
NC
NC
NC
NCNC
NC
AN23
AN22
AM23
AL23
AL26
AN26
AN27
AR27
AR28
AP22
AN18
AR22
AP28
AM27
AL33
AL17
AR19
AN19
AM17
AL16
AN17
AR17
AP18
AR18
AP4
AT3
AR3
AP3
AR2
AN4
AP2
AL21
AL22
AL35
AL34
AM35
AN36
AF16
AF23
AP1
AR8
AP8
D4
D5
AM5
AM34
B16
F15
F13C16
D16
648FX
R194 22
R151 33
RMA1
RMA2
RMA3
RMA4
RMA5
RMA6
RMA7
RMA8
RMA9
RMA10
RMA11
RMA12
RMA13
RMA14
RMA15
RSRAS#
RSCAS#
RSWE#
RCS-0
RCS-1
RCS-2
RCS-3
CKE0
CKE1
CKE2
CKE3
10p
C111
DLLAVDD
DLLAVSS
DDRAVDD
DDRAVSS
DDRVREFA
DDRVREFB
R198 X_4.7K
R186 40.2RST
R187 40.2RST
RSRAS# 9,10
RSCAS# 9,10
RSWE# 9,10
S3AUXSW#
FWDSDCLKO
VCCM
S3AUXSW# 26
FWDSDCLKO 3
RCS-[0..3]
CKE[0..3]
RMD[0..63] 9,10
RDQM[0..7] 9,10
RDQS[0..7] 9,10
RMA[0..15] 9,10
RCS-[0..3] 9,10
CKE[0..3] 9
2
VCC3 VCC3
CP10
L18
X_COPPER
DLLAVDD
X_80S/0603
CB64
X_1u-0805
150RST_8P4R
150RST_8P4R
RN70
RN70
C75
0.1u
X_80S/0603
5 6
78
DLLAVSS
C138
X_103P
C133
103P
CB78
X_103P
CB67
X_1u-0805
CP12
X_COPPERL20
150RST_8P4R
RN70
DDRVREFA DDRVREFB
150RST_8P4R
RN70
VCCMVCCM
X_80S/0603
X_80S/0603
3 4
12
1
L12
C74
X_103P
L13
C125
103P
DDRAVDD
DDRAVSS
C128
X_103P
CP4
X_COPPER
CB76
0.1u
CP5
X_COPPER
Place these capacitors under SIS648 solder side
VCC1_8
A A
VCCM
C150
X_0.1u
C29
X_0.1u
C151
0.1u
C76
X_0.1u
C152
0.1u
C90
X_0.1u
5
C52
X_0.1u
C64
X_1u
VCCP
C149
X_1u
C77
X_4.7U/0805
C103
X_0.1u
C98
X_10u/0805
C392
4.7U/0805
C110
0.1u
VDDQ
C87
10u/1206
C198
X_0.1u
4
C199
0.1u
C154
0.1u
C148
1u-0805
VCCP
VCCM VCC1_8
3
C348
X_0.1u
C350
X_0.1u
C349
X_0.1u
C352
X_0.1u
C357
X_0.1u
C358
X_0.1u
VDDQ
X_1u
C362
X_0.1u
C353
X_1u
C361
X_0.1u
C355
2
Micro-Star
Document Number
Last Revision Date:
Tuesday, April 20, 2004
Title
MS-6791
SIS648FX-Memory
1
Sheet of
7 31
Rev
300
5
VCCP
A17
A18
A19
A20
A21
B17
B18
B19
B20
B21
C17
C18
C19
C20
C21
D17
D18
D19
D20
D21
E17
E18
E19
E20
E21
F17
F18
F19
F20
F21
VTT
VSS
AA21
VTT
VSS
AA22
VTT
VSS
L25
VTT
VTT
VTT
VTT
VTT
VSS
VSS
VSS
VSS
VSS
V23
W14
W15
W16
W17
VCCM
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
AL8
VDDM
AL9
VDDM
AM6
VDDM
AM7
AB24
AC13
AD14
AD16
AD18
AD20
AD22
AB25
AC25
AD12
AD25
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AF11
AF12
AF25
AF26
VDDM
AM8
VDDM
AN5
VDDM
AN6
VDDM
AN7
VDDM
AN8
VDDM
AP5
VDDM
AP6
VDDM
AP7
VDDM
AR4
VDDM
AR5
VDDM
AR6
VDDM
AR7
VDDM
AT4
VDDM
AT5
VDDM
AT6
VDDM
AT7
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
P14
VSS
P15
VSS
P16
VSS
P17
VSS
P18
VSS
P19
VSS
P20
VSS
P21
VSS
P22
VSS
P23
VSS
R14
VSS
R15
VSS
R16
VSS
R17
VSS
R18
VSS
R19
VSS
R20
VSS
R21
VSS
R22
VSS
R23
VSS
T14
VSS
T15
VSS
T16
VSS
T17
VSS
T18
VSS
T19
VSS
T20
VSS
T21
VSS
T22
VSS
T23
VSS
U14
VSS
U15
VSS
U16
VSS
U17
VSS
U18
VSS
U19
VSS
U20
VSS
U21
VSS
U22
VSS
U23
VSS
V14
VSS
V15
VSS
V16
VSS
V17
VSS
V18
VSS
V19
VSS
V20
VSS
V21
VSS
V22
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AT26
5
AT28
AT30
AT32
AT34
AL32
VSS
Y14
Y15
AT24
SIS648-3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Y16
Y17
Y18
Y19
Y20
Y21
Y22
D D
C C
B B
A A
VTT
Power
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Y23
AA14
AA15
AA16
AA17
AA18
AA19
AA20
L26
W18
VTT
VSS
M18
W19
VTT
VSS
M19
W20
VTT
VSS
M20
W21
VTT
VSS
M21
W22
VTT
VSS
M22
W23
VTT
VSS
M23
AC32
4
VTT
VSS
4
M24
VTT
VSS
AC36
M25
AD34
VTT
VSS
M26
AE32
VTT
VSS
N25
AE36
VTT
VSS
P25
AF34
VTT
VSS
R25
AG32
VTT
VSS
T25
AG36
VTT
VSS
U25
AH34
VTT
VSS
V25
AJ32
VTT
VSS
W25
VTT
VDD3.3
VDD3.3
VDD3.3
VDD3.3
AUX1.8
AUX3.3
Y25
VTT
VDDZVDDM
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
AA25
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
3
VCC1_8
ZUREQ
ZSTB-0
ZSTB-1
C354
G_1u
L34
C144
X_0.1u
L36
ZDREQ
ZSTB0
ZSTB1
VCC3
C351
CB104
0.1u
CP29
L33
X_80S/0603
C145
X_0.1u
L35
X_80S/0603
IVDD
AL6
AL4
AK5
AJ2
AJ3
AE3
AF2
AH5
AK2
AJ4
AJ6
AH2
AH4
AG3
AG6
AF4
AG2
AF5
AG4
AD2
AE6
AE2
AE4
AL3
AK4
AD5
AD4
AN1
AM2
AL2
AL1
G_1u
50205020
X_COPPER
Z4XAVDD
Z4XAVSS
X_COPPER
N13
N14
N16
N18
N19
N20
N21
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
ZCLK
ZUREQ
ZDREQ
ZSTB0
ZSTB0#
ZSTB1
ZSTB1#
ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15
ZAD16
ZVREF
ZCOMP_N
ZCOMP_P
Z1XAVDD
Z1XAVSS
Z4XAVDD
Z4XAVSS
CP26
X_COPPER
Z1XAVDD
CB102
0.1u
Z1XAVSS
CP28
X_COPPER
PVDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A3A5C1C3C5E1E5E7E9F3G1G5H3J1J5K3L1L5M3N1N5P3R1R5T3U1U5V3W1W5Y3
VCC1_8
X_80S/0603
X_80S/0603
U9D
VTT
AD3AL7
AE1
AF3
AG1
AH3
AJ1
AK3
AM3
W11
W12
Y11
Y12
AA12
A9
L17
M17
N17
AB12
AC12
AA23
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
E32
E36
F34
G32
G36
H34
J32
J36
K34
L32
L36
M34
N32
N36
P34
R32
R36
T34
U32
U36
V34
W32
W36
Y34
AA32
AA36
AB34
AM10
AM12
AM14
AM16
AM18
AM20
AM22
AM24
AM26
AM28
AM30
AP9
AP11
AP13
AP15
AP17
AP19
AP21
AP23
AP25
AP27
AP29
AP31
AP33
AP35
AT8
AT10
AT12
AT14
AT16
AT18
AT20
AT22
648FX
VCC1_8
IVDD
IVDD
X_1u-0805
VCC3
SB1.8V
VCC3SBY
C137
0.1u
C132
ZAD[0..16]11
VCC5
C102
C121
0.1u
0.1u
C131
C136
X_0.1u
X_0.1u
VCC3
C119
C129
0.1u
0.1u
SB1.8V
C164
0.1u
VCC3SBY
C161
C162
0.1u
X_1u
Closed to SIS648
VCC3 SB1.8VVCC3SBY
C356
C359
X_0.1u
X_0.1u
ZCLK03
ZUREQ11
ZDREQ11
ZSTB-011
ZSTB-111
C140
C360
X_0.1u
ZSTB011
ZSTB111
X_0.1u
ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15
ZAD16
ZVREF
ZCMP_N
ZCMP_P
Z1XAVDD
Z1XAVSS
Z4XAVDD
Z4XAVSS
VCC3
X_80S/0603
X_80S/0603
Place under 648 solder side
3
2
N22
N23
N24
P13
P24
R24
T13
T24
U24
V13
V24
W13
W24
Y13
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
PVDD
PVDD
PVDD
PVDD
IVDD
PVDD
PVDD
PVDD
SIS648-4
HyperZip
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L37
CP30
X_COPPERCP27
R209 56.2RST
CB106
C158
0.1u
X_0.1u
L38
VCC1_8
R204
150RST
R208
49.9RST
R210 56.2RST
CP31
X_COPPER
C157
X_0.1u
ZVREF
C147
0.1u
2
Y24
IVDD
VSS
AA24
IVDD
VSS
AB13
IVDD
VSS
AC24
IVDD
VSS
AD13
IVDD
VSS
AD15
AD17
IVDD
IVDD
VSS
VSS
ZCMP_N
ZCMP_P
AD19
IVDD
VSS
AD21
IVDD
VSS
AD23
IVDD
VSS
AD24
AE5
RSYNC
LSYNC
CSYNC VB
N15
R13
U13
AA13
VOSCI
IVDD
IVDD
IVDD
IVDD
PVDD
ROUT
GOUT
BOUT
HSYNC
VSYNC
VGPIO0
VGPIO1
INT#A
CSYNC
RSYNC
LSYNC
VCOMP
VRSET
VVBWN
DACAVDD1
DACAVDD2
DACAVSS1
DACAVSS2
DCLKAVDD
DCLKAVSS
ECLKAVDD
ECLKAVSS
AUXOK
PWROK
PCIRST#
ENTEST
DLLEN#
TESTMODE0
TESTMODE1
TESTMODE2
TRAP0
TRAP1
VSS
VSS
VSS
VSS
AG5
AJ5
AL5
U9C
648FX
VCC1_8
L24
X_80S/0603
C113
G_0.1u
L23
X_80S/0603
L27
X_80S/0603
C115
X_0.1u
L28
X_80S/0603
Micro-Star
Document Number
Last Revision Date:
Tuesday, April 20, 2004
1
VGA
panel link
A15
R160
B12
R157
B13
R154
A13
R171 G_33
A11
R173 G_33
B11
R179 G_100
E13
R183 G_100
C11
R175
C10
CSYNC
D12
RSYNC
E12
LSYNC
D11
VCOMP
E15
VRSET
D15
VVBWN
E14
DACAVDD
D13
DACAVDD
D14
DACAVSS
C12
DACAVSS
C13
DCLKAVDD
B15
DCLKAVSS
C15
ECLKAVDD
B14
ECLKAVSS
C14
RSMRST#
AN3
MS7_POK
AM4
PCIRST1#
AN2
R182 4.7K
D9
E10
B10
B9
C9
D10
R181 X_4.7K
F9
CP17
X_COPPER
C109
G_1u
CP16
X_COPPER
R150 G_130RST
CP20
X_COPPER
ECLKAVDD
CB91
G_0.1u
ECLKAVSS
CP21
X_COPPER
Title
MS-6791
SIS648FX-Power & HyperZip
1
Enable Disable
1
1
1
DCLK 3
G_0
ROUT 22
G_0
GOUT 22
G_0
BOUT 22
HSYNC 22
VSYNC 22
DDC1CLK 22
DDC1DATA 22
G_0
INTA# 11,15,16
R189 G_4.7K
R185 G_4.7K
R180 G_4.7K
RSMRST# 12,26
MS7_POK 12,26
PCIRST1# 17,24,26,30
VCC3
C112 G_0.1u
C108 G_0.1u
DACAVDD
DACAVSS
VRSET
VCC3VCC3
L26
CP19
X_COPPER
CB89
C114
G_0.1u
X_0.1u
L25
CP18
Sheet of
DCLKAVDD
DCLKAVSS
X_COPPER
8 31
X_80S/0603
X_80S/0603
0
0
0
VCC3
VVBWN
VCOMP
Rev
300
5
4
3
2
1
RMD[0..63]7,10
RMA[0..15]7,10
RDQM[0..7]7,10
D D
C C
DDRVREF GEN. & DECOUPLING
VCCM
R59
75RST
R62
75RST
B B
A A
CB3
X_103P
RDQS[0..7]7,10
NOTE:
VDDID IS A TRAP ON THE DIMM
MODULE TO INDICATE:
VDDID
OPEN
GND
MEMORY MUX TABLE:
SDR
CS0
CS1
CS2
CS3
CS4
CS5 CS5
CSB0
CSB1
CSB2
CSB3
CSB4
CSB5
CSB6
CSB7
CB2
0.1u
DDRVREF
CB4
0.1u
RMA[0..15]
RDQM[0..7] RDQM[0..7]
RDQS[0..7] RDQS[0..7]
104
112
128
136
143
156
164
172
180738467085108
VDD
VDD
VDD
VDD
VDD
REQUIRED POWER
VDD=VDDQ
VDD!=VDDQ
DDR
CS0
CS1
CS2
CS3
CS4
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
RCS-[0..3]7,10
CKE[0..3]7
VDD
120
VDD
148
VDD
168
VDD
184
48
43
41
130
37
32
125
29
122
27
141
118
115
103
59
52
113
97
107
119
129
149
159
169
177
140
14
25
36
56
67
78
86
47
44
45
49
51
134
135
142
144
10
101
102
173
167
154
65
63
157
158
71
163
21
111
137
16
76
138
17
75
VDDSPD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
BA0
BA1
BA2
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
5
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
9
NC
NC(RESET#)
NC
NC
NC
NC(FETEN)
RAS#
CAS#
WE#
S0#
S1#
NC(S2#)
NC(S3#)
CKE0
CKE1
CK0
CK1
CK2
CK0#
CK1#
CK2#
VSS
VSS
160
176
RMA0
RMA1
RMA2
RMA3
RMA4
RMA6
RMA7
RMA8
RMA9
RMA13
RMA14
RMA15
RMA11
RDQM0 RMD23
RDQM1 RMD24
RDQM2 RMD25
RDQM3 RMD26
RDQM4 RMD27
RDQM5 RMD28
RDQM6 RMD29
RDQM7 RMD30
RDQS0 RMD33
RDQS1 RMD34
RDQS2 RMD35
RDQS3 RMD36
RDQS4 RMD37
RDQS5 RMD38
RDQS6 RMD39
RDQS7 RMD40
RSRAS# RSRAS# RMD59
RSRAS#7,10
RSCAS# RSCAS# RMD60
RSCAS#7,10
RSWE# RSWE# RMD61
RSWE#7,10
RCS-0 RCS-2 RMD63
RCS-1 RCS-3
CKE0 WP CKE2
CKE1 SMBCLK CKE3
DDRCLK1
DDRCLK13
DDRCLK8
DDRCLK23 DDRCLK33
DDRCLK-1
DDRCLK-8
DDRCLK-23 DDRCLK-33
RCS-[0..3]
CKE[0..3]
DDRCLK-2
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
100
116
124
132
139
145
152
VDDQ
VDDQ
addr =
1010000b
VSS
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
VREF
VDDID
VSS
VDDQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
WP
SCL
SDA
SA0
SA1
SA2
VSS
VDDQ
VSS
DDR1
15223054627796
VDDQ
RMD0
2
RMD1
4
RMD2
6
RMD3
8
RMD4
94
RMD5
95
RMD6
98
RMD7
99
RMD8
12
RMD9
13
RMD10
19
RMD11
20
RMD12
105
RMD13
106
RMD14
109
RMD15
110
RMD16
23
RMD17
24
RMD18
28
RMD19
31
RMD20
114
RMD21
117
RMD22
121
RMD23
123
RMD24
33
RMD25
35
RMD26
39
RMD27
40
RMD28
126
RMD29
127
RMD30
131
RMD31
133
RMD32
53
RMD33
55
RMD34
57
RMD35
60
RMD36
146
RMD37
147
RMD38
150
RMD39
151
RMD40
61
RMD41
64
RMD42
68
RMD43
69
RMD44
153
RMD45
155
RMD46
161
RMD47
162
RMD48
72
RMD49
73
RMD50
79
RMD51
80
RMD52
165
RMD53
166
RMD54
170
RMD55
171
RMD56
83
RMD57
84
RMD58
87
RMD59
88
RMD60
174
RMD61
175
RMD62
178
RMD63
179
DDRVREF DDRVREF
1
82
90
92
SMBDAT
91
181
182
183
VSS
DIMM-D184-BK
3111826344250586674818993
RMD[0..63]
RMA[0..15]
VCCMVCCM
DDR2
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
VREF
VDDID
VSS
VDDQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
WP
SCL
SDA
SA0
SA1
SA2
VSS
15223054627796
VDDQ
VSS
3111826344250586674818993
VDDQ
VSS
RMD0
2
RMD1
4
RMD2
6
RMD3
8
RMD4
94
RMD5
95
RMD6
98
RMD7
99
RMD8
12
RMD9
13
RMD10
19
RMD11
20
RMD12
105
RMD13
106
RMD14
109
RMD15
110
RMD16
23
RMD17
24
RMD18
28
RMD19
31
RMD20
114
RMD21
117
RMD22
121
123
33
35
39
40
126
127
131
RMD31
133
RMD32
53
55
57
60
146
147
150
151
61
RMD41
64
RMD42
68
RMD43
69
RMD44
153
RMD45
155
RMD46
161
RMD47
162
RMD48
72
RMD49
73
RMD50
79
RMD51
80
RMD52
165
166
170
RMD55
171
RMD56
83
RMD57
84
RMD58
87
88
174
175
RMD62
178
179
1
82
90
92
91
181
182
183
DIMM-D184-BK
RMD53
RMD54
R207 4.7K
WP
SMBCLK
SMBDAT
DIMM DECOUPLING
VCCM
CB93
0.1u
CB11
X_0.1u
CB35
0.1u
CB81
0.1u
CB1
X_0.1u
CB15
X_0.1u
VCCM
SMBCLK 3,12,17,26
SMBDAT 3,12,17,26
VCCM
104
112
128
136
143
156
164
172
180738467085108
VDD
VDD
VDD
VDD
VDD
VDD
120
VDD
148
VDD
168
VDD
184
RMA0
RMA1
RMA2
RMA3
RMA4
RMA5RMA5
RMA6
RMA7
RMA8
RMA9
RMA10RMA10
RMA13
RMA14
RMA15
RMA11
RMA12RMA12
RDQM0
RDQM1
RDQM2
RDQM3
RDQM4
RDQM5
RDQM6
RDQM7
RDQS0
RDQS1
RDQS2
RDQS3
RDQS4
RDQS5
RDQS6
RDQS7
DDRCLK0
DDRCLK03
DDRCLK7
DDRCLK73DDRCLK83
DDRCLK3DDRCLK2
DDRCLK-03DDRCLK-13
DDRCLK-73DDRCLK-83
DDRCLK-0
DDRCLK-7
DDRCLK-3
48
43
41
130
37
32
125
29
122
27
141
118
115
103
59
52
113
97
107
119
129
149
159
169
177
140
14
25
36
56
67
78
86
47
44
45
49
51
134
135
142
144
10
101
102
173
167
154
65
63
157
158
71
163
21
111
137
16
76
138
17
75
VDDSPD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
BA0
BA1
BA2
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
5
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
9
NC
NC(RESET#)
NC
NC
NC
NC(FETEN)
RAS#
CAS#
WE#
S0#
S1#
NC(S2#)
NC(S3#)
CKE0
CKE1
CK0
CK1
CK2
CK0#
CK1#
CK2#
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
124
132
139
145
152
160
176
VDDQ
VSS
116
VDDQ
VDDQ
addr =
1010001b
VSS
VSS
100
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
Title
Micro-Star
Document Number
Last Revision Date:
5
4
3
2
Tuesday, April 20, 2004
MS-6791
DDR1 & DDR2
Sheet of
1
Rev
300
9 31
5
4
3
2
1
DDR TERMINATOR
SSTL-2 Termination Resistors
RMD[0..63]
RDQM[0..7]
D D
RDQS[0..7]
RMA[0..15]
RCS-[0..3]
RMD[0..63] 7,9
RDQM[0..7] 7,9
RDQS[0..7] 7,9
RMA[0..15] 7,9
RCS-[0..3] 7,9
DDR_VTT
MD/DQM(/DQS)
MA/Control
CS
CKE
SDR
LV-CMOS
LV-CMOS
LV-CMOS
OD 3.3V OD 2.5V
DDR
Rs
SSTL-2
0/10/- 33
SSTL-2
10
SSTL-2
0
DDR_VTT
Rs
Rtt
10
0
33
0
47
RMD1
RMD5
RMD4
RMD0
RMD3
RMD7
RMD6
RMD2
RMD13
RMD12
RMD8
RMD9
RMA15
C C
B B
A A
RMD10
RMD15
RMD14
RMD18
RMA9
RMA13
RMD21
RMD17
RMA14
RMD16
RMD20
RMD24
RMA6
RMA5
RMD23
RMD31
RMD30
RMD26 RMD58
RMA3
RMD19
RMA8
RMA7
RMD22
RMA4
RMD25
RMD29
RMD28
RMA0
RMA1
RMA2
RMD27
RMD40
RMD35
RMD39
RMA11
RDQM0
RDQM1
RDQM2
RDQM3
RDQM4
RDQM5
RDQM6
RDQM7
RDQS0
RDQS1
RDQS2
RDQS3
RDQS4
RDQS5
RDQS6
RDQS7
RN5 8P4R-47
RN7 8P4R-47
RN10 8P4R-47
R71 47
RN13 8P4R-47
RN19 8P4R-47
RN16 8P4R-47
RN24 8P4R-47
RN28 8P4R-47
RN21 8P4R-47
RN26 8P4R-47
RN29 8P4R-47
RN32 8P4R-47
R64
R75
R84
R102
R117
R148
R170
R201
R66
R72
R82
R98
R115
R149
R174
R202
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
RMD36
RMD32
RMA12
RMA10
RMD38
RMD34
RMD37
RMD33
RSRAS#7,9
RMD44
RMD47
RMD46RMD11
RMD43
RMD42
RCS-3
RCS-1
RCS-2
RCS-0
RSCAS#7,9
RMD52
RMD53
RMD49
RMD48
RMD51
RMD50
RMD55
RMD54
RMD59
RMD63
RMD62
RMD57
RMD61
RMD56
RMD60
RMD41
RMD45
RSWE#7,9
RSRAS#
RSCAS#
RSWE#
RN30 8P4R-47
R123 47
R119 47
R113 47
R114 47
R128 47
R126 47
RN37 8P4R-47
RN35 8P4R-47
R136 47
RN39 8P4R-47
RN43 8P4R-47
RN47 8P4R-47
RN45 8P4R-47
R133
R131
R130
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
47
47
47
DDR_VTT
DECOUPLING CAPACITOR FOR SSTL-2 END TERMIANTION VTT ISLAND
DDR_VTT
CB5 X_0.1u
CB20 X_0.1u
CB17 1u
CB14 X_0.1u
CB103 X_0.1u
CB101 1u
CB100 X_0.1u
CB97 1u
CB95 X_0.1u
CB94 1u
CB92 X_0.1u
CB90 1u
CB87 1u
CB88 X_0.1u
CB86 X_0.1u
CB85 1u
CB84 X_0.1u
CB82 1u
CB75 X_0.1u
CB70 1u
CB68 X_0.1u
CB65 1u
CB63 X_0.1u
CB60 1u
CB56 X_0.1u
CB50 X_0.1u
CB49 0.1u
CB46 X_0.1u
CB45 1u
CB43 X_0.1u
CB40 1u
CB33 X_0.1u
CB29 1u
DDR_VTT
CB10
10u/1206
CB105
10u/1206
CB54
10u/1206
Title
Micro-Star
Document Number
Last Revision Date:
5
4
3
2
Monday, April 26, 2004
MS-6791
DDR TERMINATOR
Sheet of
1
Rev
300
10 31
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