MSI MS-6756 Schematics
1
Cover Sheet 1
Block Diagram
GPIO
Intel mPGA478B CPU - Signals
Intel Springdale - Host Signals
Intel Springdale - Memory Signals
Intel Springdale - AGP & LAN Signals
DDR DIMM 1,2
82547EI/82562EX-1
82547EI/82562EX-2
Intel ICH5 - PCI & IDE & AC97 Signals
Intel ICH5 - Other Signals
A A
CY28404 & FWH & FDD
AC97 Audio
AGP 4X/8X Slot
PCI Slots 1 & 2 & 3
ATA33/66/100 IDE & Video Connectors
USB Connectors
ATX & Front Panel
2
3
4
5Intel mPGA478B CPU - Power
6
7
8
9
10
11
12
13
14
15LPC I/O -W83627HF
16
17
18
19
20
21W83302 ACPI controller
22
MS(6756)
Intel (R) Springdale (GMCH) + ICH5 Chipset
Intel Northwood & Prescott mPGA478B Processor
CPU:
Intel Northwood/Prescott
System Chipset:
Intel Springdale - GMCH (North Bridge)
Intel ICH5 (South Bridge)
On Board Chipset:
BIOS -- FWH EEPRO M
AC'97 Codec -- ALC202A/ALC650
LPC Super I/O -- W83627SF
LAN --82547EI/83562EX
CLOCK -- Cypress CY28404
Main Memory:
DDR * 2 (Max 2GB)
Expansion Slots:
PCI2.3 SLOT * 3
Intersil PWM:
Controller: Intersil 6556B
Driver: Intersil 6601B,6602B
Version 100
VRM 10
ADM1027 FAN Control
Manual Part
23
24
25
MICRO-STAR INt'L CO., LTD.
MSI
Title
Size Document Number Rev
星期二, 二月
1
Date: Sheet of
11, 2003
COVER SHEET
MS-6756
1 25
100
1
VRM 10
Intersil 6556
Intel mPAG478B Processor
Block Diagram
3-Phas e PWM
FSB
AGP 1.5V
4X/8X
Connec tor
Analog
Video
Out
Kenai II
/
Kinnereth R
IDE Primary
CSA
LCI
UltraDMA 33/66/100
Springdale
Link
64bit DDR
Channel 1
64bit DDR
Channel 2
HUB
2 DDR
DIMM
Modules
(1+1)
PCI CNTRL
PCI Slot 1
PCI Slot 2
PCI Slot 3
IDE Secondary
ICH5
A A
USB Port 0
PCI ADDR/DATA
USB Port 1
USB Port 2
USB
LPC Bus
USB Port 3
USB Port 4
LP C SIO
USB Port 5
Winbond
83627HF
USB Port 6
USB Port 7
ALC202A
AC'97 Codec
Serial ATA 0
Serial ATA 1
AC'97 Link
Serial ATA
Flas h
Keyboard
Mous e
Floopy Parallel Serial
1
MSI
Title
Size Document Number Rev
Date: Sheet of
MICRO-STAR INt'L CO., LTD.
BLOCK DIAGRAM
11, 2003
MS-6756
星期二, 二月
2 25
100
1
ICH5
GPIO 0
GPIO 1
GPIO 2
GPIO 3
GPIO 4
GPIO 5
GPIO 6
GPIO 7
GPIO 8
GPIO 9
GPIO 10
GPIO 11
GPIO 12
GPIO 13
GPIO 14
GPIO 15
GPIO 16
GPIO 17
GPIO 18
GPIO 19
GPIO 20
GPIO 21
GPIO 22 GPO22
GPIO 23
I
PREQ#B
I
PREQ#B
I
PIRQ#E
I
PIRQ#F
I
PIRQ#G
I
PIRQ#H
I
GPI6
I
GPI7
I
CSA_PME#
I
OC4#
I
OC5#
I
SIO_SMI#
I
LAN_WAKE#
I
SIO_PME#
I OC#6
OC#7
I
PGNT#A
O
O
PGNT#B
O GPO18
BIOS_WP#
O
O
GPO20
O GPO21
OD
O
GPO23
GPIO 24 I/O GPIO24
FunctionTypeGPIO Pin
GPIO 25 I/O
A A
*
GPIO 27
GPIO 28
GPIO 32
GPIO 33
GPIO 34
GPIO 40 PREQ#4
GPIO 41
GPIO 48
GPIO 49
LAN_DISABLE#
I/O
GPIO27
I/O GPIO28
I/O
GPIO32
I/O
GPIO33
I/O
GPIO34
I
GPI41
I
O PGNT#4
CPUPWRGD
OD
Power well
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
RESUME
RESUME
RESUME
RESUME
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
default output
default output
default output
default output
default output
default output
default output
PCI Config.
DEVICE
INTA#
INTB#
PCI_REQ#0PCI Slot 1
PCI_GNT#0
INTC#
INTD#
PCI Slot 2
INTB#
INTC#
PCI_REQ#1 AD17 PCICLK1
PCI_GNT#1
INTD#
INTA#
PCI Slot 3 PCI_REQ#2 AD18
INTC#
INTD#
PCI_GNT#2
INTA#
INTB#
IDSEL
AD16
DDR DIMM Config.
DEVICE
DIMM 1 MCLK_A0/MCLK_A0#
DIMM 2
1010000B
1010001B
CLOCKADDRESS
MCLK_A1/MCLK_A1#
MCLK_A2/MCLK_A2#
MCLK_B0/MCLK_B0#
MCLK_B1/MCLK_B1#
MCLK_B2/MCLK_B2#
PCI RESET DEVICE
Signals
PCIRST#1
HD_RST#
Springdale,LAN,FWH, Super I/O
PCI slot 1-3, AGP slotPCIRST#2
Primary, Scondary IDE
Target
CLOCKREQ#/GNT#
PCICLK0
PCICLK2
CLK GEN PIN OUTMCP1 INT Pin
13 (PCI_CLK0)
14 (PCI_CLK1)
15 (PCI_CLK2)
FWH
TypeGPIO Pin
GP I 0 PD_DET
GP I 1
*
GP I 3
*
Function
I
I
SD_DET
I
Pull down through 1K ohms (unused)GP I 2
Pull down through 1K ohms (unused)
I
Pull down through 1K ohms (unused)GP I 4
I
MSI
Title
Size Document Number Rev
1
Date: Sheet of
MICRO-STAR INt'L CO., LTD.
General Purpose Spec
11, 2003
MS-6756
星期二, 二月
3 25
100
8
7
6
5
4
3
2
1
CPU SIGNAL BLOCK
HA#[3..31]6
HA#17
A18#
D33#
M23
HA#16
A17#
D32#
H25
HA#15
A16#
D31#
K23
HA#14
A15#
D30#
J24
HA#13
A14#
D29#
L22
HA#12
A13#
D28#
M21
HA#11
A12#
D27#
H24
HA#25
HA#27
HA#30
HA#26
HA#29
HA#31
D D
CPU1A
HDBI#0
HDBI#[0..3]6
FERR#13
STPCLK#13
HINIT#13,14
HDBSY#6
HDRDY#6
HTRDY#6
HADS#6
HLOCK#6
HBNR#6
HIT#6
HITM#6
HBPRI#6
C C
B B
HDEFER#6
CPU_TMPA25
VTIN_GND25
TRMTRIP#13
PROCHOT#6
IGNNE#13
SMI#13
A20M#13
SLP#13
BOOT24
BSEL014
BSEL114
CPU_GD13
CPURST#6
HD#[0..63]6
HDBI#1
HDBI#2
HDBI#3
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_TCK
PROCHOT#
BOOT
CPU_GD
CPURST#
HD#63
HD#62
HD#61
HD#60
HD#59
HD#58
HD#57
HD#56
HD#55
HD#54
E21
DBI0#
G25
DBI1#
P26
DBI2#
V21
DBI3#
AC3
IERR#
V6
MCERR#
B6
FERR#
Y4
STPCLK#
AA3
BINIT#
W5
INIT#
AB2
RSP#
H5
DBSY#
H2
DRDY#
J6
TRDY#
G1
ADS#
G4
LOCK#
G2
BNR#
F3
HIT#
E3
HITM#
D2
BPRI#
E2
DEFER#
C1
TDI
D5
TDO
F7
TMS
E6
TRST#
D4
TCK
B3
THERMDA
C4
THERMDC
A2
THERMTRIP#
AF26
GND/SKTOCC#
C3
PROCHOT#
B2
IGNNE#
B5
SMI#
C6
A20M#
AB26
SLP#
A22
RESERVED0
A7
RESERVED1
AE21
RESERVED2
AF24
RESERVED3
AF25
RESERVED4
AD1
BOOTSELECT
AE26
OPTIMIZED/COMPAT#
AD6
BSEL0
AD5
BSEL1
AB23
PWRGOOD
AB25
RESET#
AA24
D63#
AA22
D62#
AA25
D61#
Y21
D60#
Y24
D59#
Y23
D58#
W25
D57#
Y26
D56#
W26
D55#
V24
D54#
D53#
D52#
D51#
V22
U21
V25
HA#28
AB1Y1W2V3U4T5W1R6V2T4U3P6U1T2R3P4P3R2T1N5N4N2M1N1M4M3L2M6L3K1L6K4K2
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
A26#
D50#
D49#
D48#
D47#
D46#
D45#
D44#
D43#
D42#
D41#
U23
U24
U26
T23
T22
T25
T26
R24
R25
P24
HA#18
HA#22
HA#20
HA#23
HA#24
HA#19
HA#21
A25#
A24#
A23#
A22#
A21#
A20#
A19#
D40#
D39#
D38#
D37#
D36#
D35#
D34#
R21
N25
N26
M26
N23
M24
P21
N22
HA#10
A11#
D26#
G26
HA#9
A10#
D25#
L21
HA#8
A9#
D24#
D26
HA#7
A8#
D23#
F26
HA#6
A7#
D22#
E25
HA#5
A6#
D21#
F24
HA#4
A5#
D20#
F23
HA#3
A4#
D19#
G23
A3#
D18#
E24
D17#
H22
AE25A5A4
DBR#
D16#
D15#
D25
J21
VCC_SENSE
VSS_SENSE
D14#
D13#
D12#
D23
C26
H21
AD26
ITP_CLK1
D11#
D10#
G22
AC26
ITP_CLK0
D9#
B25
C24
VID5
AD2
AD3
VIDPWRGD
D8#
D7#
C23
B24
VID4
AE1
VID5#
D6#
D22
VID3
AE2
VID4#
D5#
C21
VID2
AE3
VID3#
D4#
A25
VID1
VID0
AE4
AE5
VID2#
VID1#
VID0#
GTLREF3
GTLREF2
GTLREF1
GTLREF0
BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#
REQ4#
REQ3#
REQ2#
REQ1#
REQ0#
TESTHI12
TESTHI11
TESTHI10
TESTHI9
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0
BCLK1#
BCLK0#
COMP1
COMP0
ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#
LINT1/NMI
LINT0/INTR
D3#
D2#
D1#
D0#
PGA-S478-GD10-F02
CRITICAL
A23
B22
B21
VCC_SENSE 24
VSS_SENSE 24
VID_GD 21,24
VID[0..5] 24
AA21
AA6
F20
F6
AB4
AA5
Y6
AC4
AB5
AC6
H3
J3
J4
K5
J1
AD25
A6
Y3
W4
U6
AB22
AA20
AC23
AC24
AC20
AC21
AA2
AD24
AF23
AF22
F4
RS2#
G5
RS1#
F1
RS0#
V5
AP1#
AC1
AP0#
H6
BR0#
P1
L24
L25
DP3#
K26
DP2#
K25
DP1#
J26
DP0#
R5
L5
W23
P23
J23
F21
W22
R22
K22
E22
E5
D1
BPM#5
BPM#4
BPM#3
BPM#2
BPM#1
BPM#0
HREQ#4
HREQ#3
HREQ#2
HREQ#1
HREQ#0
TESTHI12
TESTHI11
TESTHI10
TESTHI9
TESTHI8
TESTHI2
TESTHI1
TESTHI0
HRS#2
HRS#1
HRS#0
HBR#0
COMP1
COMP0
C116 220p
VIDPWRGD DC Specifications
GTLREF 6
HREQ#[0..4] 6
VCCP
CPU_CLK# 14
CPU_CLK 14
HRS#[0..2] 6
HBR#0 6
HADSTB#1 6
HADSTB#0 6
HDSTBP#3 6
HDSTBP#2 6
HDSTBP#1 6
HDSTBP#0 6
HDSTBN#3 6
HDSTBN#2 6
HDSTBN#1 6
HDSTBN#0 6
NMI 13
INTR 13
Min MaxTyp
0.9
0.3
VIL
VIH
I t must rout to the enable pin of PWM and CK-409.
VIDGD to Vccp delay time is from 1ms to 10ms.
VIDGD rising time is 150ns.
X7R
16V
R69 62
R137 62
R93 62
R97 62
R102 62 R92 680
R87 62
R78 62
R106 61.9
R109 61.9
CPU GTL REFERNCE VOLTAGE BLOCK
GTLREF
X7R X7R
C147
0.1u
16V
0.63*Vccp
C197
0.1u
CPU ITP BLOCK
ITP_TDI
ITP_TRST#
ITP_TMS
ITP_TDO
ITP_TCK
R76 150
R104 39
R77 75
R81 27R82 62
R142
200
R153
169
VCCP
VCCP
VTTVCCP
R189
200
HD#53
HD#52
HD#51
HD#50
HD#49
HD#48
HD#47
HD#46
HD#45
HD#43
HD#44
HD#42
HD#41
HD#40
HD#38
HD#39
HD#37
HD#36
HD#35
HD#33
HD#34
HD#32
HD#31
HD#30
HD#29
HD#28
HD#27
HD#26
HD#25
HD#23
HD#24
HD#22
HD#21
HD#20
HD#18
HD#19
HD#17
HD#16
HD#15
HD#14
HD#13
HD#12
HD#11
HD#10
HD#9
HD#8
HD#7
HD#6
HD#5
HD#4
HD#3
HD#2
HD#1
HD#0
CPU STRAPPING RESISTORS
A A
8
7
BPM#4
R91 62
BPM#5
R83 62
BPM#2 CPU_GD
R80 62
BPM#3
R95 62
BPM#1
R89 62
BPM#0
R85 62
VCCP
6
ALL COMPONENTS CLOSE TO CPU
5
PROCHOT#
HBR#0
CPURST#
R140 62
R75 300
R101 220
R86 62
VCCP
4
MSI
Title
Size Document Number Rev
3
Date: Sheet of
MICRO-STAR INt'L CO., LTD.
Intel mPGA478B - Signals
21, 2003
MS-6756
2
星期五, 二月
4 25
1
100
8
7
6
5
4
3
2
1
D15
D17
VCC
VCC
VSS
VSS
E7E9F10
D19D7D9
VCC
VSS
VCC_VID
C33
1u
E10
E12
E14
E16
E18
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F12
F14
F16
F18F2F22
F25F5F8
CPU VOLTAGE BLOCK
VCC_VID21
VID Voltage is from 1.14V to 1.32V.
It is derived from 3.3V.
It should be able to source 150mA.
D D
VCCP
A10
A12
A14
A16
A18
A20A8AA10
AA12
AA14
AA16
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
AE16
AE18
AE20
AE6
AE8
AF11
AF13
AF15
AF17
CPU1B
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
D10
VSS
A11
VSS
A13
VSS
A15
VSS
A17
VSS
A19
VSS
A21
VSS
A24
VSS
A26
VSS
A3
VSS
A9
VSS
AA1
VSS
AA11
VSS
AA13
VSS
AA15
VSS
AA17
VSS
AA19
VSS
AA23
C C
B B
AA26
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
AC11
AC13
AC15
AC17
AC19
AC2
AC22
AC25
AC5
AC7
AC9
VSS
VSS
AA4
VSS
AA7
VSS
AA9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AB3
VSS
AB6
VSS
AB8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AD10
AD12
AD14
AD16
AD18
AD21
AD4
AD23
AD8
AE11
AE13
AE15
AE17
AE19
AE22
AE24
AE7
AE9
AF1
AF10
AF12
AF14
AF16
AF18
AF20
AF6
AF8
B10
B12
B14
B16
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B18
B23
B20
B26B4B8
C11
C13
AF19
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C15
C17C2C19
C22
C25C5C7C9D12
It d rives the power logic of BSEL[1:0] and VID[5:0].
VID to VIDGD delay time is from 1ms to 10ms.
VID to VIDGD deassertion time is 1ms for max.
AF2
AF21
AF5
AF7
AF9
B11
B13
B15
B17
B19B7B9
C10
C12
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D14
D16
D18
D20
D21D3D24D6D8E1E11
C14
C16
C18
C20C8D11
D13
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E13
E15
E17
E19
E23
E4
E26
E20E8F11
VCC
VCC
VSS
VSS
Near processor
F13
F15
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
G21G6G24
G3H1H23
1.2V 150mA
C41
0.1u
F17
F19
F9
VCC
VCC
VSS
VSS
VCC
VSS
H26H4J2
AF4
VSS
VCC-VID
VSS
AF3
VCC-VIDPRG
VSS
VSS
VSS
J22
J25J5K21
AD20
VCC-IOPLL
VSS
C42
X_1u
AE23
VCCA
AD22
VSSA
Y5
VSS
Y25
VSS
Y22
VSS
Y2
VSS
W6
VSS
W3
VSS
W24
VSS
W21
VSS
V4
VSS
V26
VSS
V23
VSS
V1
VSS
U5
VSS
U25
VSS
U22
VSS
U2
VSS
T6
VSS
T3
VSS
T24
VSS
T21
VSS
R4
VSS
R26
VSS
R23
VSS
R1
VSS
P5
VSS
P25
VSS
P22
VSS
P2
VSS
N6
VSS
N3
VSS
N24
VSS
N21
VSS
M5
VSS
M25
VSS
M22
VSS
M2
VSS
L4
VSS
L26
VSS
L23
VSS
L1
VSS
K6
VSS
K3
VSS
K24
VSS
VSS
PGA-S478-GD10-F02
CRITICAL
X_1u
It support DC current if 100mA.
CPU_IOPLL
C46
C43
22u-1206
10V
VSSA
The ESL is less than 5nH, and the ESR is less than 0.3ohm.
L2 10u
L3 10u
C38
X_10u-1206
10V
VCCP
DC voltage drop should
be less than 70mV.
CPU DECOUPLING CAPACITORS
VCCP
A A
Place these caps within socket cavity Place these caps within south side of processor
VCCP VCCP VCCP VCCPVCCP VCCP
C93
10u-1206
C89
10u-1206
C85
10u-1206
C77
10u-1206
C72
10u-1206
C67
10u-1206
8
C94
10u-1206
C90
10u-1206
C86
10u-1206
C78
10u-1206
C73
10u-1210
C68
10u-1210
7
C24
10u-1206
C12
X_10u-1206
C21
X_10u-1206
C29
10u-1206
C16
X_10u-1206
C8
X_10u-1206
Place these caps within north side of processor
C23
10u-1206
C13
X_10u-1206
C15
X_10u-1206
C27
10u-1210
C10
X_10u-1206
C25
10u-1210
6
C22
X_10u-1206
C14
X_10u-1206
C11
X_10u-1206
C28
10u-1206
C9
X_10u-1206
C118
X_10u-1206
C119
X_10u-1210
C121
X_10u-1210
5
C117
X_10u-1206
MSI
Title
Size Document Number Rev
4
3
Date: Sheet of
MICRO-STAR INt'L CO., LTD.
Intel mPGA478B - Power
21, 2003
MS-6756
2
星期五, 二月
5 25
1
100
8
HA#[3..31]4
D D
HADSTB#04
HADSTB#14
HBR#04
C C
B B
HBPRI#4
HBNR#4
HLOCK#4
HADS#4
HREQ#[0..4]4
HIT#4
HITM#4
HDEFER#4
HTRDY#4
HDBSY#4
HDRDY#4
HRS#[0..2]4
MCH_CLK14
MCH_CLK#14
CPURST#4
PCIRST#110,15,21
PROCHOT#4
BSEL0_SPG14
BSEL1_SPG14
ICH_SYNC#
R162 20
GTLREF4
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HRS#0
HRS#1
HRS#2
MS5_POK
HRCOMP
HSWING
VCCA_FSB
C143 0.1u
VCCA_DPLL
U10A
D26
D30
L23
E29
B32
K23
C30
C31
J25
B31
E30
B33
J24
F25
D34
C32
F28
C34
J27
G27
F29
E28
H27
K24
E32
F31
G30
J26
G26
B30
D28
B24
B26
B28
E25
F27
B29
J23
L22
C29
J21
K21
E23
L21
D24
E27
G24
G22
C27
B27
B7
C7
AE14
E8
AK4
AJ8
L20
L13
L12
E24
C25
F23
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HAD_STB0#
HAD_STB1#
BREQ0#
BPRI#
BNR#
HLOCK#
ADS#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HIT#
HITM#
DEFER#
HTRDY#
DBSY#
DRDY#
RS0#
RS1#
RS2#
HCLKP
HCLKN
PWROK
CPURST#
RSTIN#
ICH_SYNC#
PROCHOT#
BSEL0
BSEL1
HDRCOMP
HDSWING
HDVREF
7
B3
A31
VCCA_FSB
VCCA_DPLL
VSS
VSS
C10
C8
B4
VCCA_FSB
VSS
C12
C14
VCC_AGP
J6J7J8J9K6K7K8K9L6L7L9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C16
C18
C20
C22
C24
C26
C28D1D11
D9
6
N11N9P10
P11
R11
T16
T17
T18
T19
U16
U17
U20
V16
V18
V20
N10
M10
M11M8M9
L10
L11
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
D13
D15
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D17
D19
D21
D23
D25
D27
D29
D31
T20
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D33
D35
F3F5F8
E3
F1
E1
W16
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F18
F20
F22
F14
F16
F10
F12
W19
F24
5
W20
Y16
Y17
Y18
Y19
Y20
A3
A33
A35B2B25
B34C1C23
C35
E26
M31
AF13
AF23
AJ12
VCC
VCC
VSS
VSS
F26
NCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G31
G35
H12
H14
H16H2H20
H5
G28
H18
H8
H9
R25
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H22
VSS
H24
H26
H30
H33
J10
J12
J14
J16
4
VTT
AN1
AP2
AR3
AR33
AR35
A7A9A11
A13
A16
A20
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J18
J20
J22
J28
J32
J35
K11
K12
K14
K16
K18
K20
A23
K22
A25
VSS
VSS
VSS
VSS
K25
A27
A29
A32
VSS
VSS
VSS
VSS
K33
K27
K29
D5D6D7E6E7
C4
VTT
VTT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L24M3M6
L25
L26
L35
L31
VTT
VTT
VSS
VSS
F7
A4A5A6B5B6C5C6
VTT
VTT
VTT
VTT
VSS
VSS
VSS
VSS
M26
M27
M28
M30
VTT
VSS
M33N1N4
3
VTT
VSS
VTT
VTT
VSS
VSS
SpringDale
CRITICAL
VTT_FSB1
VTT_FSB2
A15
A21
VTT
VTT_FSB
VTT_FSB
DINV_0#
DINV_1#
DINV_2#
DINV_3#
HD_STBP0#
HD_STBN0#
HD_STBP1#
HD_STBN1#
HD_STBP2#
HD_STBN2#
HD_STBP3#
HD_STBN3#
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
C179 0.47u
C165 0.47u
HD#0
B23
HD#1
E22
HD#2
B21
D20
HD#3
HD#4
B22
HD#5
D22
HD#6
B20
HD#7
C21
E18
HD#8
HD#9
E20
HD#10
B16
HD#11
D16
HD#12
B18
B17
HD#13
HD#14
E16
HD#15
D18
HD#16
G20
HD#17
F17
E19
HD#18
HD#19
F19
HD#20
J17
HD#21
L18
HD#22
G16
G18
HD#23
HD#24
F21
HD#25
F15
HD#26
E15
HD#27
E21
J19
HD#28
HD#29
G14
HD#30
E17
HD#31
K17
HD#32
J15
L16
HD#33
HD#34
J13
HD#35
F13
HD#36
F11
HD#37
E13
K15
HD#38
HD#39
G12
HD#40
G10
HD#41
L15
HD#42
E11
K13
HD#43
HD#44
J11
HD#45
H10
HD#46
G8
HD#47
E9
B13
HD#48
HD#49
E14
HD#50
B14
HD#51
B12
HD#52
B15
D14
HD#53
HD#54
C13
HD#55
B11
HD#56
D10
HD#57
C11
E10
HD#58
HD#59
B10
HD#60
C9
HD#61
B9
HD#62
D8
B8
HD#63
HDBI#0
C17
HDBI#1
L17
HDBI#2
L14
C15
HDBI#3
B19
C19
L19
K19
G9
F9
D12
E12
2
HD#[0..63] 4
HDBI#[0..3] 4
HDSTBP#0 4
HDSTBN#0 4
HDSTBP#1 4
HDSTBN#1 4
HDSTBP#2 4
HDSTBN#2 4
HDSTBP#3 4
HDSTBN#3 4
1
VCC3
0.1u
I=30mA
VCCA_FSB
I=35mA
VCCA_DPLL
C208
+
C205
0.1u
ESR is 0.1mohm to GMCH
+
EC26
100u
6
L5 0.82u
EC24
100u
L7 100nH
FSB
DPLL
VCC_AGP
R200 1
VCC_AGP
5
VCCP
A A
X7R
C191
0.01u
HSWING
C149
0.01u
X7R
16V
8
1/4*Vccp
R186
301
R150
100
7
ICH_SYNC# MS5_POK ICH_PWROK
0 0
1
1 1 1
10
0
0
0
0
MS5_POK10,21
4
ICH_SYNC#
MS5_POK
VCC3
Q45 X_2N3904S
Q47 X_2N3904S
R383 X_220
R331 0
3
R333
X_220
R332
X_1K
ICH_PWROK 13
MSI
Title
Size Document Number Rev
Date: Sheet of
MICRO-STAR INt'L CO., LTD.
Intel Springdale - CPU Signals
21, 2003
MS-6756
2
星期五, 二月
6 25
1
100
8
MCS_A#09
MCS_A#19
D D
C C
B B
A A
MA_A[0..12]9
MDQM_A[0..7]9
MDQS_A[0..7]9
MRAS_A#9
MCAS_A#9
MWE_A#9
MBA_A09
MBA_A19
MCLK_A09
MCLK_A#09
MCLK_A19
MCLK_A#19
MCLK_A29
MCLK_A#29
0.01uC269
0.01uC263
0.01uC270
0.1uC136
C135 2.2u
8
MDQ_A[0..63]9 MCKE_A[0..1] 9
U10B
AA34
SCS_A0#
Y31
SCS_A1#
Y32
SCS_A2#
W34
SCS_A3#
AC33
SRAS_A#
Y34
SCAS_A#
AB34
SWE_A#
AJ34
MA_A0
MA_A1
MA_A2
MA_A3
MA_A4
MA_A5
MA_A6
MA_A7
MA_A8
MA_A9
MA_A10
MA_A11
MA_A12
MDQM_A0
MDQM_A1
MDQM_A2
MDQM_A3
MDQM_A4
MDQM_A5
MDQM_A6
MDQM_A7
MDQS_A0
MDQS_A1
MDQS_A2
MDQS_A3
MDQS_A4
MDQS_A5
MDQS_A6
MDQS_A7
XRCOMP
XCOMPH
XCOMPL
XVREF
AL33
AK29
AN31
AL30
AL26
AL28
AN25
AP26
AP24
AJ33
AN23
AN21
AL34
AM34
AP32
AP31
AM26
AE33
AH34
AP12
AP16
AM24
AP30
AF31
W33
M34
H32
AN11
AP15
AP23
AM30
AF34
V34
M32
H31
AK32
AK31
AP17
AN17
N33
N34
AK33
AK34
AM16
AL16
P31
P32
AK9
AN9
AL9
E34
C144 0.47u
C162 0.22u
C170 0.01u
C234 0.22u
C241 0.1u
SMAA_A0
SMAA_A1
SMAA_A2
SMAA_A3
SMAA_A4
SMAA_A5
SMAA_A6
SMAA_A7
SMAA_A8
SMAA_A9
SMAA_A10
SMAA_A11
SMAA_A12
SMAB_A1
SMAB_A2
SMAB_A3
SMAB_A4
SMAB_A5
SBA_A0
SBA_A1
SDM_A0
SDM_A1
SDM_A2
SDM_A3
SDM_A4
SDM_A5
SDM_A6
SDM_A7
SDQS_A0
SDQS_A1
SDQS_A2
SDQS_A3
SDQS_A4
SDQS_A5
SDQS_A6
SDQS_A7
SMDCLK_A0
SMDCLK_A0#
SMDCLK_A1
SMDCLK_A1#
SMDCLK_A2
SMDCLK_A2#
SMDCLK_A3
SMDCLK_A3#
SMDCLK_A4
SMDCLK_A4#
SMDCLK_A5
SMDCLK_A5#
SMXRCOMP
SMXCOMPVOH
SMXCOMPVOL
SMVREF_A
7
MDQ_A1
MDQ_A0
AP10
AP11
SDQ_A0
E35
XRCOMP
YRCOMP
7
MDQ_A2
MDQ_A3
AM12
AN13
SDQ_A1
SDQ_A2
SDQ_A3
VCC_DDR
VCC_DDR
VCC_DDR
AA35
R35
MDQ_A4
AM10
AR21
MDQ_A9
MDQ_A6
MDQ_A8
MDQ_A7
MDQ_A5
AL10
AL12
AP13
AP14
AM14
SDQ_A4
SDQ_A5
SDQ_A6
SDQ_A7
SDQ_A8
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
AM1
AM2
AL7
AR15
AL6
VCC_DDR_C3
VCC_DDR_C2
R290 42.2
R287 42.2
R180 42.2
R161 42.2
MDQ_A11
MDQ_A10
AL18
AP19
SDQ_A9
SDQ_A10
SDQ_A11
VCC_DDR
VCC_DDR
VCC_DDR
AN8
AP3
VCC_DDR
MDQ_B[0..63]9
MDQ_A14
MDQ_A12
MDQ_A13
AL14
AN15
AP18
SDQ_A12
SDQ_A13
VCC_DDR
VCC_DDR
AP4
AP5
AP6
VCC_DDR_C3
6
MDQ_A17
MDQ_A15
MDQ_A16
AM18
AP22
AM22
SDQ_A14
SDQ_A15
SDQ_A16
VCC_DDR
VCC_DDR
VCC_DDR
AR4
AR5
AP7
values still need verification
VCC_DDR
AA35AA33
MDQ_A18
MDQ_A19
AL24
AN27
SDQ_A17
SDQ_A18
SDQ_A19
VCC_DDR
VCC_DDR
VCC_DDR
AR7
AR31
MDQ_A21
MDQ_A20
MDQ_A22
AP21
AL22
AP25
SDQ_A20
SDQ_A21
SDQ_B0
AJ10
AE15
MDQ_B0
MDQ_B1
XCOMPL
XCOMPH
MDQ_A24
MDQ_A23
AP27
AP28
SDQ_A22
SDQ_A23
SDQ_B1
SDQ_B2
AL11
AE16
MDQ_B2
MDQ_B3
6
MDQ_A25
MDQ_A27
MDQ_A26
AP29
AP33
AM33
SDQ_A24
SDQ_A25
SDQ_A26
SDQ_B3
SDQ_B4
SDQ_B5
AL8
AF12
AK11
MDQ_B5
MDQ_B6
MDQ_B4
MDQ_A29
MDQ_A30
MDQ_A28
MDQ_A31
AM28
AN29
AM31
AN34
SDQ_A27
SDQ_A28
SDQ_A29
SDQ_A30
SDQ_A31
SDQ_B6
SDQ_B7
SDQ_B8
SDQ_B9
SDQ_B10
AG12
AE17
AL13
AK17
MDQ_B9
MDQ_B8
MDQ_B7
MDQ_B10
R289 31.6K
R283 10.2K
R251 10.2K
R252 31.6K
MDQ_A33
MDQ_A32
MDQ_A34
AH32
AG34
AF32
SDQ_A32
SDQ_A33
SDQ_B11
SDQ_B12
AL17
AK13
AJ14
MDQ_B11
MDQ_B12
MDQ_B13
MDQ_A36
MDQ_A37
MDQ_A35
AD32
AH31
AG33
SDQ_A34
SDQ_A35
SDQ_A36
SDQ_B13
SDQ_B14
SDQ_B15
AJ16
AJ18
AE19
MDQ_B15
MDQ_B14
MDQ_B16
MDQ_A39
MDQ_A38
AE34
AD34
SDQ_A37
SDQ_A38
SDQ_A39
SDQ_B16
SDQ_B17
SDQ_B18
AE20
AG23
MDQ_B18
MDQ_B17
VCC_DDR
VCC_DDR
MDQ_A40
MDQ_A41
MDQ_A42
AC34
AB31
V32
SDQ_A40
SDQ_A41
SDQ_B19
SDQ_B20
AK23
AL19
AK21
MDQ_B20
MDQ_B19
MDQ_B21
MDQ_A43
MDQ_A44
V31
AD31
SDQ_A42
SDQ_A43
SDQ_A44
SDQ_B21
SDQ_B22
SDQ_B23
AJ24
AE22
MDQ_B22
MDQ_B23
5
MDQ_A45
MDQ_A46
MDQ_A47
AB32
U34
U33
SDQ_A45
SDQ_A46
SDQ_B24
SDQ_B25
AK25
AH26
AG27
MDQ_B24
MDQ_B26
MDQ_B25
YCOMPL
R33
YCOMPH
R34
5
MDQ_A49
MDQ_A48
T34
T32
SDQ_A47
SDQ_A48
SDQ_A49
SDQ_B26
SDQ_B27
SDQ_B28
AF27
AJ26
MDQ_B27
MDQ_B28
MDQ_A52
MDQ_A53
MDQ_A51
MDQ_A50
K34
K32
T31
P34
SDQ_A50
SDQ_A51
SDQ_A52
SDQ_A53
SDQ_B29
SDQ_B30
SDQ_B31
SDQ_B32
AJ27
AD25
AF28
AE30
MDQ_B31
MDQ_B30
MDQ_B29
MDQ_B32
R143 31.6K
R145 10.2K
R166 10.2K
R146 31.6K
MDQ_A56
MDQ_A55
MDQ_A54
L34
L33
J33
SDQ_A54
SDQ_A55
SDQ_B33
SDQ_B34
AC27
AC30
Y29
MDQ_B33
MDQ_B35
MDQ_B34
MDQ_A57
MDQ_A58
H34
E33
SDQ_A56
SDQ_A57
SDQ_A58
SDQ_B35
SDQ_B36
SDQ_B37
AE31
AB29
MDQ_B37
MDQ_B36
MDQ_A59
MDQ_A61
MDQ_A60
F33
K31
J34
SDQ_A59
SDQ_A60
SDQ_B38
SDQ_B39
AA26
AA27
AA30
MDQ_B38
MDQ_B40
MDQ_B39
MCKE_A1
MCKE_A0
MDQ_A62
MDQ_A63
G34
F34
AL20
AN19
SCKE_A0
SDQ_A61
SDQ_A62
SDQ_A63
SDQ_B40
SDQ_B41
SDQ_B42
SDQ_B43
SDQ_B44
W30
U27
T25
AA31
V29
MDQ_B44
MDQ_B45
MDQ_B41
MDQ_B43
MDQ_B42
VCC_DDR_C2
R35
4
AM20
AP20
SCKE_A1
SCKE_A2
SCKE_A3
SDQ_B45
SDQ_B46
SDQ_B47
U25
R27
MDQ_B47
MDQ_B46
4
AB25
AC25
VCCA_DDR
SDQ_B48
SDQ_B49
P29
R30
K28
MDQ_B49
MDQ_B48
MDQ_B50
VCCA_DDR
AC26
AL35
VCCA_DDR
VCCA_DDR
VCCA_DDR
SDQ_B50
SDQ_B51
SDQ_B52
L30
R31
R26
MDQ_B53
MDQ_B52
MDQ_B51
AN4
AM3
AN5
VCC_DDR
VCC_DDR
SDQ_B53
SDQ_B54
SDQ_B55
P25
L32
K30
MDQ_B55
MDQ_B56
MDQ_B54
0.1uC200
AM5
AM6
AM7
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
SDQ_B56
SDQ_B57
SDQ_B58
SDQ_B59
H29
F32
G33
MDQ_B59
MDQ_B57
MDQ_B58
VCCA_DDR
C239
0.1u
VCC_DDR
AM8
AN2
AN6
VCC_DDR
VCC_DDR
SDQ_B60
SDQ_B61
N25
M25
J29
MDQ_B62
MDQ_B61
MDQ_B60
AN7
N32
VCC_DDR
VCC_DDR
SDQ_B62
SDQ_B63
G32
AK19
MDQ_B63
+
P3P6P8
N35
VSS
VSS
VSS
VSS
SCMDCLK_B0
SCMDCLK_B0#
SCMDCLK_B1
SCMDCLK_B1#
SCMDCLK_B2
SCMDCLK_B2#
SCMDCLK_B3
SCMDCLK_B3#
SCMDCLK_B4
SCMDCLK_B4#
SCMDCLK_B5
SCMDCLK_B5#
SMYCOMPVOH
SMYCOMPVOL
SCKE_B0
SCKE_B1
SCKE_B2
SCKE_B3
SpringDale
CRITICAL
AF19
AG19
AE18
MCKE_B0
MCKE_B1
L10 1uH
EC29
100u
ALE
3
SCS_B0#
VSS
SCS_B1#
SCS_B2#
SCS_B3#
SRAS_B#
SCAS_B#
SWE_B#
SMAA_B0
SMAA_B1
SMAA_B2
SMAA_B3
SMAA_B4
SMAA_B5
SMAA_B6
SMAA_B7
SMAA_B8
SMAA_B9
SMAA_B10
SMAA_B11
SMAA_B12
SMAB_B1
SMAB_B2
SMAB_B3
SMAB_B4
SMAB_B5
SBA_B0
SBA_B1
SDM_B0
SDM_B1
SDM_B2
SDM_B3
SDM_B4
SDM_B5
SDM_B6
SDM_B7
SDQS_B0
SDQS_B1
SDQS_B2
SDQS_B3
SDQS_B4
SDQS_B5
SDQS_B6
SDQS_B7
SMYRCOMP
SMVREF_B
3
Its current is 5.1A.
U26
T29
V25
W25
W26
W31
W27
AG31
AJ31
AD27
AE24
AK27
AG25
AL25
AF21
AL23
AJ22
AF29
AL21
AJ20
AE27
AD26
AL29
AL27
AE23
Y25
AA25
AG11
AG15
AE21
AJ28
AC31
U31
M29
J31
AF15
AG13
AG21
AH27
AD29
U30
L27
J30
AG29
AG30
AF17
AG17
N27
N26
AJ30
AH29
AK15
AL15
N31
N30
AA33
R34
R33
AP9
MCKE_B[0..1] 9
MA_B0
MA_B1
MA_B2
MA_B3
MA_B4
MA_B5
MA_B6
MA_B7
MA_B8
MA_B9
MA_B10
MA_B11
MA_B12
MDQM_B0
MDQM_B1
MDQM_B2
MDQM_B3
MDQM_B4
MDQM_B5
MDQM_B6
MDQM_B7
MDQS_B0
MDQS_B1
MDQS_B2
MDQS_B3
MDQS_B4
MDQS_B5
MDQS_B6
MDQS_B7
YRCOMP
YCOMPH
YCOMPL
YVREF
VCC_AGP
2
MCS_B#0 9
MCS_B#1 9
MRAS_B# 9
MCAS_B# 9
MWE_B# 9
MA_B[0..12] 9
MBA_B0 9
MBA_B1 9
MDQM_B[0..7] 9
MDQS_B[0..7] 9
MCLK_B0 9
MCLK_B#0 9
MCLK_B1 9
MCLK_B#1 9
MCLK_B2 9
MCLK_B#2 9
0.01uC160
0.01uC159
0.01uC132
0.1uC262
R291 150
R286 150
C268 2.2u
MSI
Title
Size Document Number Rev
Date: Sheet of
MICRO-STAR INt'L CO., LTD.
Intel Springdale - Memory Signals
星期一, 二月
24, 2003
2
VCC_DDR
6.3V
MS-6756
1
7 25
1
100
8
AE6
GAD[0..31]17
D D
VCC_AGP
VCC_AGP
GC_BE#[0..3]17
AD_STB017
AD_STB#017
AD_STB117
AD_STB#117
ST[0..2]17
GFRAME#17
GIRDY#17
GTRDY#17
GDEVSEL#17
GSTOP#17
MCH_6614
SBA[0..7]17
SB_STB17
SB_STB#17
DBI_LO17
R243 43.2
GSWING17
AGP_REF17
R345 226
R344 147
R342 113
8
GGNT#17
0.01uC251
0.01uC265
C C
B B
A A
GAD0
GAD1
AC11
AD5
GAD3
AE5
GAD4
AA10
AC9
GAD5
GAD6
AB11
GAD7
AB7
GAD8
AA9
GAD9
AA6
AA5
GAD10
GAD11
W10
GAD12
AA11
GAD13
W6
GAD14
W9
V7
GAD15
GAD16
AA2
GAD17
Y4
GAD18
Y2
GAD19
W2
Y5
GAD20
GAD21
V2
GAD22
W3
GAD23
U3
GAD24
T2
T4
GAD25
GAD26
T5
GAD27
R2
GAD28
P2
GAD29
P5
P4
GAD30
GAD31
M2
GC_BE#0
Y7
GC_BE#1
W5
AA3
GC_BE#2
GC_BE#3
U2
AC6
AC5
V4
V5
N6
M7
ST0
N3
ST1
N5
ST2
N2
RBF#
RBF#17
WBF#17
GPAR17
PIPE#17
R10
WBF#
R9
U6
V11
AB5
AB4
W11
AB2
H4
SBA0
R6
P7
SBA1
SBA2
R3
SBA3
R5
SBA4
U9
SBA5
U10
U5
SBA6
SBA7
T7
U11
T11
M4
M5
GRCOMP
AC2
AC3
GSWING
AD2
H_SWING=(0.8*VCC_AGP)+-2%
C317 0.1u
C324 0.1u
H_SWING=(0.233*VCC_AGP)+-2%
7
U10C
GAD0/DVOB_HSYNC
GAD1/DVOB_VSYNC
GAD2/DVOB_D1
GAD3/DVOB_D0
GAD4/DVOB_D3
GAD5/DVOB_D2
GAD6/DVOB_D5
GAD7/DVOB_D4
GAD8/DVOB_D6
GAD9/DVOB_D9
GAD10/DVOB_D8
GAD11/DVOB_D11
GAD12/DVOB_D10
GAD13/DVOBC_CLKINT
GAD14/DVOB_FLDSTL
GAD15/MDDC_DATA
GAD16/DVOC_VSYNC
GAD17/DVOC_HSYNC
GAD18/DVOC_BLANK#
GAD19/DVOC_D0
GAD20/DVOC_D1
GAD21/DVOC_D2
GAD22/DVOC_D3
GAD23/DVOC_D4
GAD24/DVOC_D7
GAD25/DVOC_D6
GAD26/DVOC_D9
GAD27/DVOC_D8
GAD28/DVOC_D11
GAD29/DVOC_D10
GAD30/DVOBC_INTR#
GAD31/DVOC_FLDSTL
GCBE0/DVOB_D7
GCBE1/DVOB_BLANK#
GCBE2
GCBE3/DVOC_D5
GADSTBF0/DVOB_CLK
GADSTBS0/DVOB_CLK#
GADSTBF1/DVOC_CLK
GADSTBS1/DVOC_CLK#
GREQ
GGNT
GST0
GST1
GST2
GRBF
GWBF
GFRAME/MDVI_DATA
GIRDY/MI2CCLK
GTRDY/MDVI_CLK
GDEVSEL/MI2CDATA
GSTOP/MDDC_CLK
GPAR/ADD_DETECT
GCLKIN
GSBA0#/ADD_ID0
GSBA1#/ADD_ID1
GSBA2#/ADD_ID2
GSBA3#/ADD_ID3
GSBA4#/ADD_ID4
GSBA5#/ADD_ID5
GSBA6#/ADD_ID6
GSBA7#/ADD_ID7
GSBSTBF
GSBSTBS
DBI_HI
DBI_LO
GRCOMP/DVOBC_RCOMP
GVSWING
GVREF
VSS
VSS
VSS
AE1
AD30
AD33
AD28
HL_SWING
H_SWING
HL_VREF
H_VREF
7
P26
P9
VSS
VSS
VSS
VSS
VSS
AE10
AE11
AE12
AE4
800mV
H_SWING 13
350mV
H_VREF 13
VSS
VSS
P27
AE13
VSS
VSS
P28
AE25
P30
VSS
VSS
AE26
P33R1R4
VSS
VSS
AE32
VSS
VSS
AE35
6
R32T1T3
T6T8T9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF3
AF11
AF14
AF6
AF9
VSS
VSS
AF16
VSS
VSS
AF18
T10
VSS
VSS
AF20
VCCP
VSS
VSS
T26
AF22
VSS
VSS
T27
AF24
VSS
VSS
6
T28
AF25
VSS
VSS
T30
AF30
T33
VSS
VSS
AF33
VSS
VSS
C156
0.1u
T35
VSS
VSS
AG4
U4
AG8
VSS
VSS
U18
VSS
VSS
AG14
V6
U19
U32V3V8V9V10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AG16
AG18
AG20
AG22
AG24
VSS
VSS
C260
0.1u
AG26
VSS
VSS
AG28
VSS
VSS
V17
AG32
VSS
VSS
V19
VSS
VSS
AG35
V26
AH3
V27
VSS
VSS
AH6
V28
V30W4W17
VSS
VSS
VSS
VSS
VSS
VSS
AH12
AH10
V33
AH14
VSS
VSS
VSS
VSS
AH16
5
Y3
W18
W32Y6Y8Y9Y26
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AH18
AH20
AH22
AH24
AH30
5
Y28
Y30
Y33
Y35
Y27
AA1
AA4
AA32
AB10
AB26
AB3
AB6
AB8
VSS
VSS
AH33
Y10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK3
AJ1
AJ4
AJ9
AJ32
AJ35
AK8
AK10
VSS
VSS
AK12
VSS
VSS
AK14
VSS
VSS
AK16
VSS
VSS
AK18
VSS
VSS
AK20
VSS
VSS
AK22
VSS
VSS
AB9
AK24
VSS
VSS
AK26
VSS
VSS
AK28
Springdale Decoupling Capacitors
4
AB27
AB28
VSS
VSS
VSS
VSS
AL1
AL32
VCC_DDR
4
AB30
VSS
VSS
AM9
AB33
VSS
VSS
AM11
AC1
VSS
VSS
AM13
C243 0.1u
AC4
AC32
AC35
AD3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AM15
AM17
AM19
AM21
C264
0.1u
C261
0.1u
VSS
VSS
AD6
AM23
VSS
VSS
AD8
AM25
VSS
VSS
AD9
AM27
VSS
VSS
AD10
AM29
VSS
VSS
AM35
VSS
AN10
3
C266 0.1u
VCC_AGP
L1L5Y1J1J2J3K2K3K4K5J4J5L4L2L3
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AN12
AN14
AN16
AN18
AN20
AN22
AN24
AN26
3
AN28
AN30
AN32
AR9
VCC_AGP
VCC_AGP
VCC_AGP
VSS
VSS
VSS
AR11
AR13
AR16
VTTVCC_AGP
AG1
Y11
HI0
HI1
HI2
VCCA_AGP
VCCA_AGP
HI3
HI4
HI5
HI6
HI7
HI8
HI9
HI10
HI_STRF
HI_STRS
HI_RCOMP
HI_SWING
HI_VREF
CI0
CI1
CI2
CI3
CI4
CI5
CI6
CI7
CI8
CI9
CI10
CISTRF
CISTRS
CI_RCOMP
CI_SWING
CI_VREF
DREFCLK
DDCA_CLK
DDCA_DATA
VSYNC
HSYNC
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
REFSET
VCC_DAC
VCC_DAC
VCCA_DAC
VSSA_DAC
EXTTS#
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SpringDale
AR23
AR20
CRITICAL
C195
1u
C201
0.1u
2
VCC_AGP
C228
0.1u
C222
0.1u
HL0
AF5
HL1GAD2
AG3
HL2
AK2
HL3
AG5
AK5
HL4
HL5
AL3
HL6
AL2
HL7
AL4
HL8
AJ2
AH2
HL9
HL10
AJ3
AH5
AH4
HL_COMP
AD4
HL_SWING
AE3
HL_VREF
AE2
CI0
AK7
CI1
AH7
CI2
AD11
CI3
AF7
AD7
CI4
CI5
AC10
CI6
AF8
CI7
AG7
CI8
AE9
AH9
CI9
CI10
AG6
AJ6
AJ5
CI_RCOMP
AG2
AF2
CI_SWING
CI_VREF
AF4
G4
F2
H3
E2
G3
H7
G6
H6
G5
F4
E4
GSET
D2
G1
G2
C2
D3
AP8
AG9
AG10
AN35
AP34
AR1
AR25
AR27
AR29
AR32
R220 137
C217
0.01u
C213
0.01u
Title
Size Document Number Rev
Date: Sheet of
HL[0..10] 13
HI_RCOMP Calculation
R=[(1.5V-08V)/0.8V]*60ohm=52.5ohm
HL_STRF 13
HL_STRS 13
R261 52.3
R270 52.3
VCC_AGP
MSI
0.01uC252
0.01uC282
CI_STRF 10
CI_STRS 10
DOT_48 14
3VDDCCL 19GREQ#17
3VDDCDA 19
CRT_VSYNC 19
CRT_HSYNC 19
CRT_B 19
CRT_G 19
CRT_R 19
VCC3
VCCA_DAC
VCC_AGP
CI[0..10] 10
VCC_AGP
0.01uC250
0.01uC276
L9 100n
+
EC27
470u
R262 226
R255 147
R281 113
MICRO-STAR INt'L CO., LTD.
Intel Springdale - AGP & HLink & LAN Signals
21, 2003
MS-6756
2
星期五, 二月
1
VCC_DAC
CI_SWING
CI_VREF
8 25
1
1.5V/60mA
800mV
350mV
100
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