MSI MS-6712 Schematics
5
4
3
2
1
Title Page
Cover Sheet 1
MS-6712F1
Version 2.0B
11/04/2002 Update
MS-6712F1 ver:2.0B
VIA (R) KT400 VT8377 Chipset
Palamino/Mogan 462pin cPGA Processor S c hem ati cs
D D
*AMD PGA 462 Processor
*VIA KT400 / VT8235 Chipset
(DDR 400 / AGP 8X / VLink 8X)
*Winbond 83697HF-VF LPC I/O
*VT6103 Fast Ethernet 10 / 100
*AC'97 Codec ALC202A/ALC650
*USB 2.0 support (integrated into VT8235)
*Jump Less support
C C
Option L BOM (with LAN)
SMT 5010 785
SMT 5020 19
DIP 60 72
Total 878
Standard BOM (without LAN)
SMT 5010 XXX
SMT 5020 XX
DIP 60 XX
Total
XXX
Block Diagram
Clock Synthesizer 6
KT400 7,8,9,10
System Memory
DDR Terminations
AGP SLOT 15
VT8235
PCI Connectors
AC'97 Codec & Audio connector
ATA 66/100 Connectors
Ethernet LAN
Front USB Port &
2
3GPIO SPEC
4,5AMD 462 PGA Socket
11,12,13
14
16,17,18
19,20
21CNR RISER / DLED
22
23
24
25Rear USB Port
LPC I/O
H/W monitor;Fan;
B B
I/O Connectors
Thermal Protection
HIP 6302
CPU Ratio / Vcore / LED Setting
MS-5 ACPI POWER
Front Panel;
PowerOK Circuit
6712F1-20B-L
ERP BOM
601-6712-060
Function DescriptionOrcad Config
MSI Option:L
MS-6712F1 20B
MSI Standard
With LAN.MS-6712F1 20B
MSI Standard
Without LAN.
MSI Standard
Without CNR.
BULK / Decoupling
HISTORY
A A
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
5
4
3
2
http://www.msi.com.tw
26
27
28
29
30
31
32
33
34
Cover Sheet
MS-6712
1
Last Revision Date:
Friday, November 08, 2002
Sheet
134
Rev
20A
of
5
Block Diagram
4
3
2
1
D D
AMD Socket 462
FSB200/266
A
C C
G
P
AGP 8X /Fast Write
KT400
DDR 400
VLINK 8X
PCI-33
Dual ATA
100/133
B B
Rear 10/100
Port x1
VT6103 PHY
6 PCI Slots
VT8235
LPC BUS
MII 10/100M
SUPER I/O ROM
C
N
R
AC-LINK
USB 2.0
X BUS
A A
5
AC'97 Codec
4
Dual USB 1.1 OHCI
/2.0 EHCI 6 Ports
Rear x2 Front x4
3
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
2
http://www.msi.com.tw
Block Diagram
MS-6712
1
Last Revision Date:
Sheet
Rev
20A
Friday, November 08, 2002
234
of
5
4
3
2
1
GPIO FUNCTION
VT8233 GPIO Function Define
PIN NAME
D D
GPO0 (VSUS33)
GPO1/SUSA#(VSUS33)
GPO2/SUSB#(VSUS33)
GPO3/SUSST1#(VSUS33)
GPO4/SUSCLK(VSUS33)
GPO5/CPUSTP#
GPO6/PCISTP#
GPO7/SLP#
GPO8/GPI8/IPBIN0
GPO9/GPI9/IPBIN1
C C
GPO10/GPI10/IPBRDFR
GPO0
SUSA#
SUSB#
SUSST1#
SUSCLK
CPUSTP#
PCISTP#
SLP#
Exteranl Pull up to VCC3
Exteranl Pull up to VCC3
GPI10(PRI_DOWN)
GPO11/GPI11/IPBRDCK
GPO12/GPI12/IPBOUT0
GPO13/GPI13/IPBOUT1
GPO14/GPI14/IPBTDFR
GPO15/GPI15/IPBTDCK
GPO16/SA16/STRAP
GPO17/SA17/STRAP
GPO18/SA18/STRAP
GPO19/SA19/STRAP
B B
GPO20/GPI20
/ACSDIN2/PCS0#/EI
GPO21/GPI21/ACSDIN3
/PCS1#/SLPBTN#
GPO22/GPI22/IOR#
GPO23/GPI23/IOW#
GPO12
GPO13
GPO14
GPO15
CPU FID0 Strapping
CPU FID1 Strapping
CPU FID2 Strapping
CPU FID3 Strapping
GPO20
GPO21
GPO22
GPO23
GPO24/GPI24/GPIOA
GPO25/GPI25/GPIOC
GPO26/GPI26/SMBDT2
(VSUS33)
GPO27/GPI27/SMBCK2
(VSUS33)
GPO28/GPI28/
APICD0/APICCS#
GPO29/GPI29/
A A
APICD1/APICACK#
SMBDATA2/Slave SMBUS
SMBCLK2/Slave SMBUS
GPO30/GPI30/GPIOD
GPO31/GPI31/GPIOE
5
PIN NAME Function defineFunction define
GPI0
GPI1
GPI2/EXTSMI#
GPI3/RING#
GPI4/LID#
GPI5/BATLOW#
GPI6/PME#
GPI7/SMBALRT#
GPI16/INTRUDER#
GPI17/CPUMISS
GPI18/AOLGP1/THRM#
GPI19/IORDY
DDR Voltage
2.5V
2.6V
2.7V
2.8V
4
SET1 SET2
11
1
0
1
0
00
GPI0
ATADET0=>Detect IDE1 ATA100/66
EXTSMI#
RING#
ATADET1=>Detect IDE2 ATA100/66
Exteranl Pull up to 3VDUAL
PME#
Exteranl Pull up to 3VDUAL
Exteranl Pull down
Exteranl Pull up to 3VDUAL
THRM#
Exteranl Pull up to VCC3
3
DEVICES
PCI SLOT 1
PCI SLOT 2
PCI SLOT 3
PCI SLOT 4
PCI SLOT 5
PCI SLOT 6
2
PCI
INT#
INT#A
INT#B
INT#C
INT#D
INT#B
INT#C
INT#D
INT#A
INT#C
INT#D
INT#A
INT#B
INT#D
INT#A
INT#B
INT#C
INT#B
INT#C
INT#D
INT#A
INT#C
INT#D
INT#A
INT#B
IDSEL
AD16
AD17
AD18
AD19
AD21
AD22
REQ#/GNT#
PREQ#1
PGNT#1
PREQ#2
PGNT#2
PREQ#3
PGNT#3
PREQ#4
PGNT#4
PREQ#5
PGNT#6
PREQ#0
PGNT#0
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
http://www.msi.com.tw
CLOCK
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
GPIO Spec.
MS-6712
Last Revision Date:
Friday, November 08, 2002
Sheet
334
1
Rev
20A
of
5
4
3
2
1
**All CPU interface are 2.5V tolerant**
SOCKET 462 Part 1
SDATA#[0..63]{7}
D D
C C
DICLK#[0..3]{7}
B B
DOCLK#[0..3]{7}
AIN#[2..14]{7}
A A
SDATA#[0..63]
DICLK#[0..3]
DIVAL#{7}
DOCLK#[0..3]
AIN#[2..14]
AICLK#{7}
CFWDRST{7}
CONNECT{7}
PROCDRY{7}
SDATA#0
SDATA#1
SDATA#2
SDATA#3
SDATA#4
SDATA#5
SDATA#6
SDATA#7
SDATA#8
SDATA#9
SDATA#10
SDATA#11
SDATA#12
SDATA#13
SDATA#14
SDATA#15
SDATA#16
SDATA#17
SDATA#18
SDATA#19
SDATA#20
SDATA#21
SDATA#22
SDATA#23
SDATA#24
SDATA#25
SDATA#26
SDATA#27
SDATA#28
SDATA#29
SDATA#30
SDATA#31
SDATA#32
SDATA#33
SDATA#34
SDATA#35
SDATA#36
SDATA#37
SDATA#38
SDATA#39
SDATA#40
SDATA#41
SDATA#42
SDATA#43
SDATA#44
SDATA#45
SDATA#46
SDATA#47
SDATA#48
SDATA#49
SDATA#50
SDATA#51
SDATA#52
SDATA#53
SDATA#54
SDATA#55
SDATA#56
SDATA#57
SDATA#58
SDATA#59
SDATA#60
SDATA#61
SDATA#62
SDATA#63
DICLK#0
DICLK#1
DICLK#2
DICLK#3
DIVAL#
DOCLK#0
DOCLK#1
DOCLK#2
DOCLK#3
DOVAL#
5
AIN#0
AIN#1
AIN#2
AIN#3
AIN#4
AIN#5
AIN#6
AIN#7
AIN#8
AIN#9
AIN#10
AIN#11
AIN#12
AIN#13
AIN#14
CFWDRST
CONNECT
PROCDRY
FILVAL#
AA35
W37
W35
AA33
AE37
AC33
AC37
AA37
AC35
W33
AN33
AE35
AL31
AJ29
AL29
AG33
AJ37
AL35
AE33
AJ35
AG37
AL33
AN37
AL37
AG35
AN29
AN35
AN31
AJ33
AJ21
AL23
AN23
AJ31
Y35
U35
U33
S37
S33
Y37
S35
Q37
Q35
N37
J33
G33
G37
E37
G35
Q33
N33
L33
N35
L37
J37
A37
E35
E31
E29
A27
A25
E21
C23
C27
A23
A35
C35
C33
C31
A29
C29
E23
C25
E17
E13
E11
C15
A13
C21
A21
E19
C19
C17
A11
A17
A15
J35
E27
E15
C37
A33
C11
E9
C9
A9
SDATA0
SDATA1
SDATA2
SDATA3
SDATA4
SDATA5
SDATA6
SDATA7
SDATA8
SDATA9
SDATA10
SDATA11
SDATA12
SDATA13
SDATA14
SDATA15
SDATA16
SDATA17
SDATA18
SDATA19
SDATA20
SDATA21
SDATA22
SDATA23
SDATA24
SDATA25
SDATA26
SDATA27
SDATA28
SDATA29
SDATA30
SDATA31
SDATA32
SDATA33
SDATA34
SDATA35
SDATA36
SDATA37
SDATA38
SDATA39
SDATA40
SDATA41
SDATA42
SDATA43
SDATA44
SDATA45
SDATA46
SDATA47
SDATA48
SDATA49
SDATA50
SDATA51
SDATA52
SDATA53
SDATA54
SDATA55
SDATA56
SDATA57
SDATA58
SDATA59
SDATA60
SDATA61
SDATA62
SDATA63
SDATAINCLK0
SDATAINCLK1
SDATAINCLK2
SDATAINCLK3
SDATAINVAL
SDATAOUTCLK0
SDATAOUTCLK1
SDATAOUTCLK2
SDATAOUTCLK3
SDTATOUTVAL
SADDIN0
SADDIN1
SADDIN2
SADDIN3
SADDIN4
SADDIN5
SADDIN6
SADDIN7
SADDIN8
SADDIN9
SADDIN10
SADDIN11
SADDIN12
SADDIN13
SADDIN14
SADDINCLK
CLKFWDRST
CONNECT
PROCRDY
SFILLVAL
4
CPU1A
A20M
FERR
INIT
INTR
IGNNE
NMI
RESET
SMI
STPCLK
PWROK
PICCLK
PICD0/BYPASSCLK
PICD1/BYPASSCLK
COREFB-
COREFB+
CLKIN
CLKIN
RSTCLK
RSTCLK
K7CLKOUT
K7CLKOUT
ANALOG
SYSVREFMODE
VREF_SYS
PLLBYPASS
PLLBYPASSCLK
PLLBYPASSCLK
PLLMON1
PLLMON2
PLLTEST
SCANCLK1
SCANCLK2
SCANINTEVAL
SCANSHIFTEN
DBRDY
DBREQ
FLUSH
TCK
TDO
TMS
TRST
VID0
VID1
VID2
VID3
VID4
FID0
FID1
FID2
FID3
SCHECK0
SCHECK1
SCHECK2
SCHECK3
SCHECK4
SCHECK5
SCHECK6
SCHECK7
SADDOUT0
SADDOUT1
SADDOUT2
SADDOUT3
SADDOUT4
SADDOUT5
SADDOUT6
SADDOUT7
SADDOUT8
SADDOUT9
SADDOUT10
SADDOUT11
SADDOUT12
SADDOUT13
SADDOUT14
SADDOUTCLK
ZN
ZP
TDI
AE1
AG1
AJ3
AL1
AJ1
AN3
AG3
AN5
AC1
AE3
APICCLK_CPU
N1
N3
N5
AG13
AG11
AN17
AL17
AN19
AL19
AL21
AN21
AJ13
AA5
W5
AC5
AE5
AJ25
AN15
AL15
AN13
AL13
AC3
S1
S5
S3
Q5
AA1
AA3
AL3
Q1
U1
U5
Q3
U3
L1
L3
L5
L7
J7
W1
W3
Y1
Y3
U37
Y33
L35
E33
E25
A31
C13
A19
J1
J3
AOUT#2
C7
AOUT#3
A7
AOUT#4
E5
AOUT#5
A5
AOUT#6
E7
AOUT#7
C1
AOUT#8
C5
AOUT#9
C3
AOUT#10
G1
AOUT#11
E1
AOUT#12
A3
AOUT#13
G5
AOUT#14
G3
E3
N12-4620011-F02
A20M#
FERR
CPUINIT#
INTR
IGNNE#
NMI
CPURST#
SMI#
STPCLK#
APICD0#
APICD1#
COREFB#
COREFB
CPUCLK_R
CPUCLK#_R
CLKOUT
CLKOUT#
VREFMODE
VREF_SYS
ZN
ZP
PLLBP#
PLLMON1
PLLMON2
PLLTEST#
SCANCLK1
SCANCLK2
SINTVAL
SSHIFTEN
DBREQ#
FLUSH#
CPU_TCK
CPU_TDI
CPU_TMS
CPU_TRST#
VID0
VID1
VID2
VID3
VID4
FID0
FID1
FID2
FID3
A20M# {16}
CPUINIT# {16}
INTR {16}
IGNNE# {16}
NMI {16}
CPURST# {30}
SMI# {16}
STPCLK# {16}
K7PWRGD {30}
APICCLK_CPU {6}
APICD0# {16}
APICD1# {16}
COREFB# {29}
COREFB {29}
VCORE
R78
100
R79
100
VID0 {29}
VID1 {29}
VID2 {29}
VID3 {29}
VID4 {29}
FID0 {5}
FID1 {5}
FID2 {5}
FID3 {5}
AOUT#[2..14]
AOCLK# {7}
R82
100
R83
100
AOUT#[2..14] {7}
3
CPURST#
C10
X_100P
FERR
APICD0#
APICD1#
COREFB
C34
X_106P/0805
COREFB#
IGNNE#
A20M#
STPCLK#
CPURST#
SMI#
NMI
CPUINIT#
INTR
FLUSH#
PLLBP#
PLLMON1
PLLMON2
DOVAL#
FILVAL#
AIN#1
AIN#0
SCANCLK2
SCANCLK1
SINTVAL
SSHIFTEN
VCORE
for test only
R12
680
B
Pull to 2.5V
R22 330
R17 330
R54 10K
R63 10K
RN8
1 2
3 4
5 6
7 8
8P4R-680
RN11
1 2
3 4
5 6
7 8
8P4R-680
R50 680
R103 680
R77 56
R76 56
RN29
1 2
3 4
5 6
7 8
8P4R-270
RN6
1
3
5
7
8P4R-270
VCC3
DBREQ#
R87 510
R7
E C
510
Q5
2N3904S
VCORE
VCORE
FERR#
VCC2_5
FERR# {16}
C35
X_39P
CPUCLK_R
CPUCLK#_R
CPUCLK#{6}
PLLTEST#
CPU_TCK
CPU_TMS
CPU_TRST#
CPU_TDI
VREF_SYS
CPUCLK{6}
C63
680P
C65
680P
VREFMODE
R98 510
7 8
5 6
3 4
1 2
VCORE
VREFMODE=Low=No voltage scaling
ZN
R97 40.2RST
ZP
R88 40.2RST
match the transmission line
Push-pull compensation circuit
2
4
6
8
CLKOUT
CLKOUT#
* Trace lengths of CLKOUT
and -CLKOUT are between
2" and 3"
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
2
http://www.msi.com.tw
SOCKET 462 Part 1
MS-6712
RN5
8P4R-510
0.6 * VCORE
C43
473P
R85 60.4RST
R90
301RST
R93 60.4RST
close Socket 462
R92
for internal
X_1K
VREFSYS
R91
270
RN25
1 2
3 4
5 6
7 8
8P4R-100
Last Revision Date:
Friday, November 08, 2002
Sheet
1
VCORE
VCORE
R74
60.4RST
C42
R73
473P
60.4RST
VCORE
VCORE
VCORE
Rev
20A
of
434
5
SOCKET 462 Part 2
Power supply from MS-5
D D
Used when
spec.
change
Max 150mA,
Design for
100mA
C C
B B
C30
104P
166_DET{6}
C76
102P
VCCA_PLL trace length from the VR1 to the
PGA must be 0.75".
C89
39P
Place al filters close to the PGA.
Keep all power and signal trce away from
the VR1.
Place a cut in the GND plane around the
VCCA_PLL regulator circuit.
3VDUAL3VDUAL
VCC2_5
C12
C4
104P
AD30
AD8
AF10
AF28
AF30
AF32
AF6
AF8
AH30
AH8
AJ9
AK8
AL9
AM8
F30
H10
H28
H30
H32
K30
AJ7
AL7
AN7
G25
G17
AG7
AG15
AG29
F8
H6
H8
K8
G9
N7
Y7
H12
VCC_CORE1
VCC_SRAM1
VCC_SRAM2
VCC_SRAM3
VCC_SRAM4
VCC_SRAM5
VCC_SRAM6
VCC_SRAM7
VCC_SRAM8
VCC_SRAM9
VCC_SRAM11
VCC_SRAM13
VCC_SRAM14
VCC_SRAM16
VCC_SRAM17
VCC_SRAM19
VCC_SRAM20
VCC_SRAM21
VCC_SRAM22
VCC_SRAM23
VCC_SRAM24
VCC_SRAM25
VCC_SRAM26
VCC_SRAM27
VCC_SRAM28
VCC_SRAM29
VCC_SRAM30
VCC_SRAM31
KEY4
KEY6
KEY8
KEY10
KEY12
KEY14
KEY16
KEY18
R411
X_1K
104P
FSB_S1
VCCA_PLL1VCCA_PLL
R96 10
C85
39P
H16
H20
H24M8P30R8T30V8X30Z8AB30
VCC_CORE2
VCC_CORE3
VCC_CORE4
VCC_CORE5
VCC_CORE6
VCC_CORE7
VCC_CORE8
C69
39P
AF14
VCC_CORE9
VCC_CORE10
VCC_CORE11
VCC_CORE12
AF18
AF22
AF26
AM34
VCC_CORE13
VCC_CORE14
VCC_CORE15
VCC_CORE16
VCC_CORE17
AK36
VCC2_5
AK34
AK30
AK26
AK22
VCC_CORE18
VCC_CORE19
VCC_CORE20
VCC_CORE21
VCC_CORE22
4
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
VCC3
SW2
1
2
3
YJ103
AK18
AK14
AK10
AL5
VCC_CORE23
VCC_CORE24
VCC_CORE25
VCC_CORE26
RN124
8P4R-4.7K
RN13
8P4R-680
R383
4.7K
166_DET
AH26
AM30
AH22
AH18
VCC_CORE27
VCC_CORE28
VCC_CORE29
VCC_CORE30
BASS3
BASS1
BASS0
BASS2
FID2
FID3
FID1
FID0
For 166MHz power
strapping
VCC3
SB and CLK Gen
166MHz
strapping
R71
X_10K
R59
4.7K
AH14
AH10
AH4
AH2
AF36
AF34
AD6
AM26
VCC_CORE31
VCC_CORE32
VCC_CORE33
VCC_CORE34
VCC_CORE35
VCC_CORE36
VCC_CORE37
VCC_CORE38
FID2 {4}
FID3 {4}
FID1 {4}
FID0 {4}
B
AD4
AD2
AB36
AB34
VCC_CORE39
VCC_CORE40
VCC_CORE41
VCC_CORE42
Q13
2N3904S
E C
AB32Z6Z4Z2X36
VCC_CORE43
VCC_CORE44
VCC_CORE45
VCC_CORE46
VCC3
C57
X_102P
VCORE
X34
AM22
X32V6V4V2T36
VCC_CORE47
VCC_CORE48
VCC_CORE49
VCC_CORE50
VCC_CORE51
3
RN15
8P4R-10K
166_DET_SB {17}
T34
T32R6R4R2AM18
VCC_CORE52
VCC_CORE53
VCC_CORE54
VCC_CORE55
VCC_CORE56
12
34
56
78
P36
VCC_CORE57
VCC_CORE58
VCC_CORE59
VCC_CORE60
VCC_CORE61
RN18
7 8
5 6
3 4
1 2
8P4R-10K
R_FID3
R_FID2
R_FID1
R_FID0
FID[3:0] FID[3:0]
Clock
Multiplier
0000 11.0
0001 11.5
0010 12.0
0011 12.5
0100 5.0
0101 5.5
0110 6.0
0111 6.5
P34
P32M4M6M2K36
K34
K32H4H2
AM14
F36
F34
F32
F28
F24
F20
F16
F12
VCC_CORE62
VCC_CORE63
VCC_CORE64
VCC_CORE65
VCC_CORE66
VCC_CORE67
VCC_CORE68
VCC_CORE69
VCC_CORE70
VCC_CORE71
VCC_CORE72
VCC_CORE73
VCC_CORE74
VCC_CORE75
VCC_CORE76
VCC_CORE77
VCC_CORE78
VCC_CORE79
VCC_CORE80
2
SA19 {17}
SA18 {17}
SA17 {17}
SA16 {17}
Power Up
strapping
Clock
Multiplier
1000 7.0
1001 7.5
1010 8.0
1011 8.5
1100 9.0
1101 9.5
1110 10.0
1111 10.5
D32
D28
AM10
D24
D20
D16
D12D8D4D2B36
VCC_CORE81
VCC_CORE82
VCC_CORE83
VCC_CORE84
VCC_CORE85
VCC_CORE86
VCC_CORE87
VCC_CORE88
VCC_CORE89
B32
AM2
B28
VCC_CORE90
VCC_CORE91
VCC_CORE92
VCC_CORE93
VCC_CORE94
B24
B20
B16
B12B8B4
VCC_CORE95
VCC_CORE96
VCC_CORE97
VCC_CORE98
AJ5
VCC_CORE99
VCC_CORE100
VCC_CORE101
BP0_CUT
BP1_CUT
BP2_CUT
BP3_CUT
BASS0
BASS1
FID1
BASS2
FID2
BASS3
VCCA_PLL
AC7
AJ23
VCC_Z
VCC_A
NC1
NC2
NC3
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
NC25
NC27
NC28
NC29
NC30
NC31
NC32
NC33
NC34
NC35
NC36
NC37
NC42
NC43
NC44
NC45
E C
E C
E C
E C
0~32 mA,
2.25~2.75V
CPU1B
N12-4620011-F02
AA31
AC31
AE31
AG23
AG25
AG31
AG5
AJ11
AJ15
AJ17
AJ19
AJ27
AL11
AN11
AN9
G11
G13
G27
G29
G31
J31
J5
L31
N31
Q31
S31
S7
U31
U7
W31
W7
Y31
Y5
AG19
G21
AG21
G19
AN27
AL27
AN25
AL25
1
B
R_FID0FID0
Q52
2N3904S
B
R_FID1
Q53
2N3904S
B
R_FID2
Q54
2N3904S
B
R_FID3FID3
Q55
2N3904S
VCC3
R410
FSB_S0
GND
X_10K
THERMDP {27}
THERMDN {27}
For AMD CPU Thermal
protection
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS_Z
H14
H18
H22
H26
A A
5
M30P8R30T8V30X8Z30
AB8
AF12
AF16
AF20
AF24
AM36
AK32
AK28
AK24
AK20
AK16
AK12
AK4
AK2
AH36
AM32
AH34
AH32
AH28
AH24
AH20
AH16
AH12
AF4
AF2
AD36
AD34
AD32
AB6
AB4
AB2
Z36
Z34
Z32X6AM28X4X2
V36
V34
V32T6T4T2R36
R34
AM24
R32P6P4P2M36
M34
M32K6K4K2AM20
H36
H34
F26
F22
F18
F14
F10F6F4F2AM16
D36
D34
D30
D26
D22
D18
D14
D10D6B34
AM12
B30
B26
B22
B18
B14
B10B6B2
AM4
AK6
AM6
AE7
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
4
3
2
http://www.msi.com.tw
SOCKET 462 Part 2
MS-6712
Last Revision Date:
Sheet
1
Friday, November 08, 2002
534
Rev
20A
of
5
4
3
2
1
Clock
Synthesizer
VCC3
C300
D D
104P
C C
B B
C237
104P
A A
RESVD
RESVD
L33
1 2
X_80S/0805
CP5
X_COPPER
L31
1 2
X_80S/0805
CP3
X_COPPER
5
C262
475P/0805
C236
475P/0805
C253
104P
AGPCLK{15}
AGPCLK_NB{9}
VCLK{16}
PCICLK1{19}
PCICLK2{19}
PCICLK3{19}
PCICLK4{20}
PCICLK5{20}
PCICLK6{20}
SB_PCLK{16}
SIOPCLK{26}
C235
104P
X_104P
104P
AGPCLK
AGPCLK_NB
VCLK
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
SB_PCLK
SIOPCLK
C234
X_104P
VCC2_5
C280
C277
CLKVCC3 VCC2_5CLKVCC2
C208
104P
C239
104P
3
X1
4
X2
26
AGP0
27
AGP1
28
AGP2
9
FS4/PCI_F
10
PCI0/SEL24_48#
11
PCI1
13
PCI2
14
PCI3
16
PCI4
17
PCI5
18
PCI6
20
PCI7
21
PCI8
22
PCI9_E
C274
104P
2
8
12
17
23
32
37
41
47
3
9
14
18
26
31
35
40
46
48
36
24
25
13
1
1
5
15
232425
VDDREF
VDD_PCI
VDD_PCI
VDD_48MHz
GND_REF
GND_48MHz
2
8
VDD3.3/2.5
VDD3.3/2.5
VDD3.3/2.5
VDD3.3/2.5
VDD3.3/2.5
VDD2.5
VDD2.5
VDD2.5
VDD2.5
GND
GND
GND
GND
GND
GND
GND
GND
GND
SEL_DDR/-SDR
PWR_DWN
SDATA
SCLK
BUF_IN
FBOUT
33
VDD_AGP
GND_PCI
12
19
C272
10P
C244
10P
1 2
3 4
5 6
7 8
R248 22
1 2
3 4
5 6
7 8
R233 22
R234 22
R235 22
C247
104P
C245
X_104P
DCLK2_5
DCLKO{8}
DCLKI{8}
C275
C268
104P
X__104P
Y2
14.318MHZ
RN77
8P4R-22
8P4R-22
RN79
DCLK2_5VCC2_5
C210
104P
C246
104P
R223 4.7K
R222 4.7K
R202 X_680
4
C276
104P
FS4
24_48SEL
C209
104P
C248
C215
104P
104P
SMBDATA1
SMBCLK1
R193 33
VDD_CORE
GND_PCI
GND_AGP
GND_CORE
GND_CPU
GND_CPU
29
32
37
43
DDR1T/SDRAM0
DDR1C/SDRAM1
DDR2T/SDRAM2
DDR2C/SDRAM3
DDR3T/SDRAM4
DDR3C/SDRAM5
DDR4T/SDRAM6
DDR4C/SDRAM7
DDR10T
DDR10C
DDR11T
DDR11C
40
CPUCLKT0
CPUCLKC0
VDD_CPU
CPUCLKT_CS
CPUCLKC_CS
FS3/24_48MHz
FS2/48MHz
CPU_STOP#
PCI_STOP#
AGP_STOP#
REF_STOP#
U11
DDR0T
DDR0C
DDR5T
DDR5C
DDR6T
DDR6C
DDR7T
DDR7C
DDR8T
DDR8C
DDR9T
DDR9C
ICS93738/W255
REF1/FS1
REF0/FS0
REF2
PD#
RST#
SCLK
SDATA
ICS94230/W312
4
5
6
7
10
11
15
16
19
20
21
22
28
27
30
29
34
33
39
38
43
42
45
44
3
C260
C238
104P
105P
U12
42
41
39
38
7
6
47
48
46
36
35
44
45
34
30
31
24_48SEL
RESVD
R213 10
R214 10
R215 10
R216 10
FS3 SIO48M
R247 33
FS2
R249 33
FS1
R218 22
R208 22
FS0
R210 33
R211 22
R212 4.7K
R217 10K
SMBCLK1
SMBDATA1
R246 10K
RN74 8P4R-10
7 8
5 6
3 4
1 2
RN73 8P4R-10
7 8
5 6
3 4
1 2
RN72 8P4R-10
7 8
5 6
3 4
1 2
RN78 8P4R-10
7 8
5 6
3 4
1 2
R221 10
R220 10
L32
1 2
X_80S/0805
CP4
X_COPPER
AUD_PCLK
APICCLK_CPU
APICCLK
DCLK3
DCLK#3
DCLK6
DCLK#6
DCLK0
DCLK#0
DCLK4
DCLK#4
DCLK7
DCLK#7
DCLK1
DCLK#1
DCLK#5
DCLK5
DCLK#8
DCLK8
DCLK2
DCLK#2
CPUCLK
CPUCLK#
HCLK
HCLK#
USBCLK_SB
SB_OSC14
VCC3
FP_RST# {30,31}
SMBCLK1 {11,12,13,17,21,30}
SMBDATA1 {11,12,13,17,21,30}
DCLK3 {12}
DCLK#3 {12}
DCLK6 {13}
DCLK#6 {13}
DCLK0 {11}
DCLK#0 {11}
DCLK4 {12}
DCLK#4 {12}
DCLK7 {13}
DCLK#7 {13}
DCLK1 {11}
DCLK#1 {11}
DCLK#5 {12}
DCLK5 {12}
DCLK#8 {13}
DCLK8 {13}
DCLK2 {11}
DCLK#2 {11}
CPUCLK {4}
CPUCLK# {4}
HCLK {7}
HCLK# {7}
SIO48M {26}
USBCLK_SB {18}
SB_OSC14 {17}
AUD_PCLK {22}
APICCLK_CPU {4}
APICCLK {16,17}
FS0
FS1
FS2
FS3
FS4
VCC3
R206
R207 10K
R219 10K
R230 10K
R231 10K
R232 10K
Frequency strapping
1 1 1 1 0 for 100MHz(default)
1 1 1 1 1 for 133MHz
1 1 1 0 1 for 166MHz
1K
VCC3
Adjust other Frequency by BIOS.
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
2
http://www.msi.com.tw
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
SB_PCLK
APICCLK_CPU
SIOPCLK
SB_OSC14
AGPCLK
AGPCLK_NB
VCLK
CPUCLK
CPUCLK#
HCLK
HCLK#
USBCLK_SB
SIO48M
APICCLK
APICCLK_CPU
AUD_PCLK
DCLK3
DCLK#3
DCLK6
DCLK#6
DCLK0
DCLK#0
DCLK4
DCLK#4
DCLK7
DCLK#7
DCLK1
DCLK#1
DCLK#5
DCLK5
DCLK#8
DCLK8
DCLK2
DCLK#2
Micro Star Restricted Secret
Clock Synthesizer
MS-6712
C294 X_10P
CN18
7 8
5 6
3 4
1 2
X_8P4C-10P
R209 X_680
C287 X_10P
C243 X_10P
C240 10P
C233 10P
C526 10P
C227 10P
C228 10P
C229 10P
C230 10P
C292 10P
C293 10P
CN16
7 8
5 6
3 4
1 2
X_8P4C-10P
C525 X_10P
100_133_DET {17}
166_DET {5}
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
C258 X_10P
C257 X_10P
Remove on 07/22
Last Revision Date:
Friday, November 08, 2002
Sheet
1
X_10PC285
21
X_10PC286
21
CN15
X_8P4C-10P
CN14
X_8P4C-10P
CN13
X_8P4C-10P
CN17
X_8P4C-10P
Rev
20A
634
of
5
D D
S2K_VREF
AIN#2
AIN#3
AIN#4
AIN#5
AIN#6
AIN#7
AIN#8
AIN#9
AIN#10
AIN#11
AIN#12
AIN#13
AIN#14
AICLK#
AOUT#2
AOUT#3
AOUT#4
AOUT#5
AOUT#6
AOUT#7
AOUT#8
AOUT#9
AOUT#10
AOUT#11
AOUT#12
AOUT#13
AOUT#14
AOCLK#
DICLK_N#0
DICLK_N#1
DICLK_N#2
DICLK_N#3
DOCLK#0
DOCLK#1
DOCLK#2
DOCLK#3
DIVAL#
CFWDRST
CONNECT
PROCDRY
HCLK
HCLK#
VID#
C455
X_104P/B
W34
W33
AA32
W32
AB32
AA34
AB34
AB31
AA31
W31
AB33
AA33
AA30
AA29
E26
A25
E24
A26
C25
D25
C24
C23
D23
D26
E23
A24
B23
B25
Y32
Y34
B28
F33
L32
T34
C28
F32
K32
T33
A23
A22
E22
C22
K29
L29
G30
E25
AIN#[14..2]
AICLK#{4}
AOUT#[2..14]{4}
C C
DOCLK#[0..3]{4}
B B
AOUT#[14..2]
AOCLK#{4}
DOCLK#[0..3]
DIVAL#{4}
CFWDRST{4}
CONNECT{4}
PROCDRY{4}
HCLK{6}
HCLK#{6}
R116 300RST
L18
M18
VTT
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AINCLK
AOUT2
AOUT3
AOUT4
AOUT5
AOUT6
AOUT7
AOUT8
AOUT9
AOUT10
AOUT11
AOUT12
AOUT13
AOUT14
AOUTCLK
DICLK0
DICLK1
DICLK2
DICLK3
DOCLK0
DOCLK1
DOCLK2
DOCLK3
DIVAL
CFWDRST
CONNECT
PROCRDY
HCLK+
HCLK-
S2KCOMP
S2KVREF0
S2KVREF1
VID
VTT
4
A20
A21
B20
B21
C20
C21
D20
D21
E20
E21
F20
F21
L20
L21
L22
L23
M20
M21
M22
M23
M24
A33
A34
B33
B34
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VSS
VTT
VSS
VSS
VSS
VSS
VSS
VSS
D30
E33
E31
F27
F26
D31
VTT
VTT
VTT
VTT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D24
D27
B31
B32
C31
C33
C34
VSS
VSS
VSS
A32
B30
B24
B27
N23
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H33
H31
H29
L33
L31
J29
M30
3
AVDD1 VCC2_5VCORE
G29
K30
P23
P24
R23
R24
T23
T24
U23
U24
V23
V24
W23
W24
AD29
AD30
AD31
AD32
AD33
AD34
AE29
AE30
W30
VTT
VSS
AE31
VTT
VTT
VTT
VTT
VTT
VTT
VSS
VSS
VSS
VSS
VSS
VSS
D22
AC34
AC33
AC32
AC31
AC30
N24
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VSS
VTT
VSS
VSS
VSS
VSS
VSS
VSS
U33
U31
B22
Y33
Y31
Y30
VTT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N30
P33
P31
P30
P29
R30
R29
T30
T29
AE32
VTT
VSS
AC29
AE33
VTT
AE34
VTT
H30
L19
M19
U7A
VTT
VTT
VTS2K
VDS2K
AVDD1
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
VSS2K
AGND1
VT8377
F30
L30
2
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
E29
A29
B29
A30
C29
C30
A31
C27
E27
C26
E28
A28
D28
B26
D29
D32
D34
E30
H32
J34
F31
G31
H34
C32
D33
G34
E34
E32
F34
G32
G33
J30
K31
M31
M32
N31
N34
M34
N33
J32
J31
J33
K34
L34
K33
N32
M33
R31
V32
V33
T32
V34
U34
V31
V30
P34
P32
R34
R33
R32
U30
T31
U32
SDATA#1
SDATA#2
SDATA#3
SDATA#4
SDATA#5
SDATA#6
SDATA#7
SDATA#8
SDATA#9
SDATA#10
SDATA#11
SDATA#12
SDATA#13
SDATA#14
SDATA#15
SDATA#16
SDATA#17
SDATA#18
SDATA#19
SDATA#20
SDATA#21
SDATA#22
SDATA#23
SDATA#24
SDATA#25
SDATA#26
SDATA#27
SDATA#28
SDATA#29
SDATA#30
SDATA#31
SDATA#32
SDATA#33
SDATA#34
SDATA#35
SDATA#36
SDATA#37
SDATA#38
SDATA#39
SDATA#40
SDATA#41
SDATA#42
SDATA#43
SDATA#44
SDATA#45
SDATA#46
SDATA#47
SDATA#48
SDATA#49
SDATA#50
SDATA#51
SDATA#52
SDATA#53
SDATA#54
SDATA#55
SDATA#56
SDATA#57
SDATA#58
SDATA#59
SDATA#60
SDATA#61
SDATA#62
SDATA#63
SDATA#0
A27
SDATA#[0..63]
SDATA#[0..63] {4}AIN#[2..14]{4}
C433
C451
103P/B
5020 5020
105P/B
AGND1
1
CP16
X_COPPER
L48
X_30S/0603
CP15
X_COPPER
L47
X_30S/0603
VCC2_5AVDD1
VCORE
R126
60.4RST
DICLK#0 DICLK_N#0S2K_VREF
R128
60.4RST
A A
C456
C454
104P/B
5020 5020 5020
SOLDER
SIDE
5
473P/B
C467
X_473P/B
5020
C461
X_103P/0805/B
DICLK#[0..3]{4}
DICLK#[0..3]
10nH
10nH
L20
L16
4
C134
5P/B
C133
5P
5020
L22
10nH
L21
DICLK_N#1DICLK#1
10nH
DICLK#2 DICLK_N#2
10nH
10nH
3
L17
L14
C129
5P/B
C116
5P/B
L19
10nH
5020
L15
10nH
5020
AGND1
VCORE
C458
104P/B
C444
104P/B
C457
104P/B
C453
104P/B
C465
104P/B
C469
104P/B
5020 5020 5020 5020 5020 5020
DICLK_N#3DICLK#3
2
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
http://www.msi.com.tw
VT8377 CPU
MS-6712
Last Revision Date:
Friday, November 08, 2002
Sheet
734
1
Rev
20A
of
5
4
3
2
1
VDDR VCC2_5
AG1
AG2
AG3
AG4
AG5
AG6
AH1
AH2
AH3
AH4
AH5
AH6
AJ1
AJ2
AJ3
AJ4
AJ5
AJ6
AF29
AF30
AF31
AF32
AF33
AF34
AG29
AG30
AG31
AG32
AG33
AG34
AH29
AH30
AH31
AH32
AH33
AH34
AJ10
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VSS
AK16
VSS
VSS
AK19
AN2
VSS
AN5
VSS
AN8
VSS
VCC3
VSS
AN11
AN14
D D
C C
B B
A A
MD[63..0]{14}
VDDR
MD[63..0]
5
R130 4.7K
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
QDRRD
MVREF_NB
AK31
AM33
AN32
AP33
AK32
AL34
AN34
AP34
AP32
AM31
AM29
AM28
AN31
AP31
AN29
AP29
AN28
AP27
AM26
AP25
AP28
AM27
AM25
AN25
AM24
AN23
AP22
AM21
AP24
AP23
AN22
AP21
AM14
AN13
AP12
AM11
AP14
AP13
AN12
AP11
AN10
AM9
AP8
AM8
AP10
AM10
AN7
AP7
AM7
AM6
AN4
AP3
AP6
AN6
AP4
AM4
AP1
AN3
AL1
AK1
AP2
AN1
AM2
AK2
AK11
AK27
AJ28
AJ19
AJ12
AJ7
AK29
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
QDRRD
QDRWR
MVREF0
MVREF1
MVREF2
MVREF3
GCKE
VSS
AJ8
AK18
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AL18
AL19
AL21
AL24
AL27
VSS
AL30
AL33
VSS
AJ9
AJ15
AJ16
AJ20
AJ26
AJ27
AJ29
AJ30
AJ31
AJ32
AL2
AL5
AL8
AL11
AL14
AL16
AJ23
4
AL17
VCC3
VSS
AN17
VCC3
VSS
AN18
VCC3
VSS
AN21
VCC3
VSS
AN24
VCC3
VSS
AN27
VSS
VDD
VSS
AN30
AJ11
VDD
VSS
AN33
AJ13
VDD
3
AJ14
AJ21
VDD
AGND2
AJ33
AJ18
AGND2
AVDD2 AVDD3
AJ22
AJ24
AJ25
VDD
VDD
VDD
AGND3
AJ34
AJ17
VDD
AVDD2
MPD0/CKE0
MPD1/CKE1
MPD2/CKE2
MPD3/CKE3
MPD4/CKE4
MPD5/CKE5
MPD6/CKE6
MPD7/CKE7
AVDD3
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
MAB15
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS7
DQM0
DQM1
DQM2
DQM3
DQM4
DQM5
DQM6
DQM7
DQM8
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
DCLKO
DCLKI
SRASA
SRASB
SCASA
SCASB
SWEA
SWEB
VT8377
U7B
AM15
AM16
AM18
AM20
AK20
AL23
AK22
AL25
AK24
AK26
AK15
AL12
AL13
AL28
AK30
AL31
AL15
AK17
AP17
AM19
AL20
AL22
AK21
AK25
AK23
AL26
AK14
AK12
AK13
AK28
AL29
AL32
AN19
AP19
AN15
AP15
AP20
AN20
AP16
AN16
AL7
AK5
AK6
AM5
AL4
AK4
AL3
AK3
AM32
AP30
AP26
AM22
AM12
AN9
AL6
AM3
AM17
AM34
AM30
AN26
AM23
AM13
AP9
AP5
AM1
AP18
AK33
AK34
AL9
AL10
AK7
AK9
AK10
AK8
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
MAB15
MCKE0
MCKE1
MCKE2
MCKE3
MCKE4
MCKE5
MCS#0
MCS#1
MCS#2
MCS#3
MCS#4
MCS#5
MDQM#0
MDQM#1
MDQM#2
MDQM#3
MDQM#4
MDQM#5
MDQM#6
MDQM#7
MDQS#0
MDQS#1
MDQS#2
MDQS#3
MDQS#4
MDQS#5
MDQS#6
MDQS#7
R117 10
MSRASA#
MSRASB#
MSCASA#
MSCASB#
MSWEA#
MSWEB#
DCLKO
DCLKI
MAA[15..0]
MAB[15..0]
MCKE[5..0]
MCS#0 {11,14}
MCS#1 {11,14}
MCS#2 {12,14}
MCS#3 {12,14}
MCS#4 {13,14}
MCS#5 {13,14}
MDQM#0 {14}
MDQM#1 {14}
MDQM#2 {14}
MDQM#3 {14}
MDQM#4 {14}
MDQM#5 {14}
MDQM#6 {14}
MDQM#7 {14}
MDQS#0 {11,12,13,14}
MDQS#1 {11,12,13,14}
MDQS#2 {11,12,13,14}
MDQS#3 {11,12,13,14}
MDQS#4 {11,12,13,14}
MDQS#5 {11,12,13,14}
MDQS#6 {11,12,13,14}
MDQS#7 {11,12,13,14}
DCLKO {6}
DCLKI {6}
MSRASA# {11,14}
MSRASB# {12,13,14}
MSCASA# {11,14}
MSCASB# {12,13,14}
MSWEA# {11,14}
MSWEB# {12,13,14}
C140
X_5P
Place as close
as to VT8366
2
MAA[15..0] {11,14}
MAB[15..0] {12,13,14}
MCKE[5..0] {11,12,13}
C483
X_105P/B
5020 5020 5020
DCLKIDCLKO
C448
X_20P
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
MAB15
MSRASB#
MSCASB#
MSWEB#
For VIA KT400
AVDD3
C450
105P/B
AVDD2
C446
103P/B
Place resistors as close as to
NB;Length is 2.5"~3".
Solder side
MVREF_NB
C487
C445
105P/B
X_105P/B
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
http://www.msi.com.tw
VT8377 Memory
C441
105P/B
AGND2
C470
105P/B
5020
MS-6712
L23
X_30S/0603
CP2
X_COPPER
CP17
X_COPPER
L49
X_30S/0603
L50
X_30S/0603
CP18
X_COPPER
C127
104P
Last Revision Date:
Sheet
1
C438
X_33P/B
C437
X_33P/B
C436
X_33P/B
C435
X_33P/B
C434
X_33P/B
C429
X_33P/B
C431
X_33P/B
C427
X_33P/B
C428
X_33P/B
C426
X_33P/B
C439
X_33P/B
C460
X_33P/B
C440
X_33P/B
C425
X_33P/B
C423
X_33P/B
C488
X_33P/B
C462
X_33P/B
C472
X_33P/B
C468
X_33P/B
VCC2_5
VCC2_5
VDDR
C135
X_105P
C126
105P
Friday, November 08, 2002
of
834
R115
1KST
R113
1KST
Rev
20A
5
4
VDDQ
3
VSUS2_5
CLOSED TO NB
C500
X_103P/B
2
1
AE1
R6
VCC1
VSS
AE2
VCC1
VSS
AE3
VSS
AE4
VSS
AE5
VSS
AE6
Y4
VSS
AF1
VSUS25
VSS
VSS
AF2
AF3
GD10
GD11
GD12
GD13
GD14
GD15
GD16
GD17
GD18
GD19
GD20
GD21
GD22
GD23
GD24
GD25
GD26
GD27
GD28
GD29
GD30
GD31
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
C/BE0
C/BE1
C/BE2
C/BE3
AD_STBF0
AD_STBS0
AD_STBF1
AD_STBS1
SB_STBF
SB_STBS
DBIH
GFRAME
GIRDY
GTRDY
GDEVSEL
GSTOP
GPAR
GREQ
GGNT
GSERR
AGP8XDET
AGPVREF0
AGPVREF1
AGPCOMP
GCLK
VSS
VSS
VSS
VSS
VT8377
AF4
AF5
AF6
GD0
GD1
GD2
GD3
GD4
GD5
GD6
GD7
GD8
GD9
DBIL
PIPE
RBF
WBF
ST0
ST1
ST2
U7C
GAD0
M1
GAD1
L1
K2
GAD3
K1
GAD4
K3
GAD5
J1
GAD6
J2
GAD7
J3
GAD8
F1
GAD9
G3
GAD10
F2
GAD11
F3
GAD12
E1
GAD13
D1
GAD14
D2
GAD15
D3
GAD16
C5
GAD17
D6
GAD18
A4
GAD19
B5
GAD20
A5
GAD21
E7
GAD22
B6
GAD23
A6
GAD24
B8
GAD25
A8
GAD26
D8
GAD27
C8
GAD28
A9
GAD29
C9
GAD30
B9
GAD31
A10
SBA0
B14
SBA1
A14
SBA2
A13
SBA3
C14
SBA4
A11
SBA5
C11
SBA6
C10
SBA7
B11
GC/BE#0
H1
GC/BE#1
B1
GC/BE#2
A3
GC/BE#3
A7
AD_STBF0
G2
AD_STBS0
G1
AD_STBF1
C6
AD_STBS1
C7
SB_STBF
B12
SB_STBS
A12
DBIH
E8
DBIL
E9
GFRAME
E3
GIRDY
F4
GTRDY
G4
GDEVSEL
E10
GSTOP
H3
GPAR
L3
PIPE
D9
RBF
D11
WBF
E11
GREQ
E14
GGNT
D14
GSERR
J4
AGP8XDET#
E12
ST0
C13
ST1
D12
ST2
C12
F10
VREF_GC
J5
AGPCOMP
K5
AGPCLK_NB
M2
AD_STBF0 {15}
AD_STBS0 {15}
AD_STBF1 {15}
AD_STBS1 {15}
SB_STBF {15}
SB_STBS {15}
DBIH {15}
DBIL {15}
GFRAME {15}
GIRDY {15}
GTRDY {15}
GDEVSEL {15}
GSTOP {15}
GPAR {15}
PIPE {15}
RBF {15}
WBF {15}
GREQ {15}
GGNT {15}
GSERR {15}
AGP8XDET# {15}
ST0 {15}
ST1 {15}
ST2 {15}
VREF_GC {15}
R149 60.4RST
AGPCLK_NB {6}
GAD[0..31] {15}
SBA[7..0] {15}
GC/BE#[3..0] {15}
VREF_GC=20mils
AGPCOMP=10mils
VDDQ
VREF_GC
C202
105P/0805
VREF_GC
C192
104P
C491
104P
C484
105P
C191
105P
A1A2B2B3C2C3C4D4D5E5E6F5F6F7F8N4N5N6P1P2P3P4P5P6R1R2R3R4R5
VSSQQ
K6
T1
VSS
VSS
B4B7B10
VSS
J6
VSS
B13C1D7
VCCQQ
VSS
VSS
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D10
D13E2E4
E13F9G5H2H4H5K4L2L5M3T2T3T4T5T6U4U5U6V2V4V5W5AA2
D D
20mils WideVLREF_NB=
VCC2_5
10mils Wide
Remove on 07/22
R155
X_47
VCC2_5
VPAR
VLCOMPP_NB=
C C
B B
VLAD0{16}
VLAD1{16}
VLAD2{16}
VLAD3{16}
VLAD4{16}
VLAD5{16}
VLAD6{16}
VLAD7{16}
VBE0#{16}
VPAR{16}
R147 360RST
UPCMD{16}
DNCMD{16}
DNSTB{16}
DNSTB#{16}
UPSTB{16}
UPSTB#{16}
PWROK_NB#{17}
PCIRST1#{26,30}
NMI_NB{16}
R114 4.7K
SUSST#{17}
VLREF_NB=20mils
VCC2_5
R162
3KST
R160
1KST
A A
VLREF_NB is 0.65V
C179
104P
VLREF_NB
C178
104P
VLAD0
VLAD1
VLAD2 GAD2
VLAD3
VLAD4
VLAD5
VLAD6
VLAD7
VBE0#
VPAR
VLREF_NB
VCOMPP_NB
UPCMD
DNCMD
DNSTB
DNSTB#
UPSTB
UPSTB#
PWROK_NB#
PCIRST1#
NMI_NB
TESTIN#
VCC2_5
VCC2_5
AB30
AB29
AA3
AA1
AB2
AB1
AB3
AB4
AA5
AB5
AA6
AD6
AD5
AD4
AD3
AD2
AD1
AC6
AC5
AC4
AC3
AC2
AC1
V3
VD0
V1
VD1
VD2
VD3
U1
VD4
U3
VD5
VD6
VD7
W2
VBE
U2
VPAR
W4
LVREF
Y5
LCOMPP
UPCMD
Y3
DNCMD
W1
DNSTB
W3
DNSTB
Y1
UPSTB
Y2
UPSTB
PWROK
RESET
NMI
TESTIN
SUS_ST
VDD
Y6
VDD
W6
VDD
V6
VDD
M6
VDD
L6
VDD
H6
VDD
G6
VDD
F14
VDD
F13
VDD
F12
VDD
F11
VDD
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC1
VSS
VCC1
VSS
L4
VCC1
VSS
VCC1
VSS
VCC1
VSS
M4
N1N2N3
VCC1
VSS
M5
VCC1
VSS
VCC1
VSS
VCC1
VSS
VCC1
VSS
VCC1
VSS
VCC1
VSS
VCC1
VSS
VCC1
VSS
VCC1
VSS
VCC1
VSS
VCC1
VSS
VCC1
VSS
VCC1
VSS
VCC1
VSS
AA4
VCC1
VSS
AB6
VCC1
VSS
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
5
4
3
2
http://www.msi.com.tw
VT8377 AGP
MS-6712
Last Revision Date:
Friday, November 08, 2002
Sheet
934
1
Rev
20A
of
5
4
3
2
1
VCC2_5
Y29
VDD
W29
VDD
V29
VDD
VDDQ
VDDR
M29
M13
M14
M16
M15
M12
M11
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AC24
AC23
AC22
AC21
AC20
AC19
AC18
AC17
AC16
AC15
AC14
AC13
AC12
AC11
AB24
AB23
AB12
AB11
AA24
AA23
AA12
AA11
U29
VDD
N29
F29
F28
F25
F24
F23
F22
F16
F15
E16
E15
D16
D15
C16
C15
B16
B15
A16
A15
A17
B17
C17
D17
E17
F17
L13
L14
L16
L15
T12
T11
R12
R11
P12
P11
N12
N11
L12
Y23
Y24
Y12
Y11
VDD: NB Core Power
VDD
X50
VDD
VCC1: AGP Power
VDD
X56
VDD
VCC2: VLink Power
VDD
X20
VDD
VCC3: DDR Power
VDD
X68
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
D D
C C
B B
A A
U7D
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VT8377
U11
U12
V11
V12
W11
W12
B19
B18
L17
M17
AA21
AA20
AA19
AA18
AA17
AA16
AA15
AA14
Y21
Y20
Y19
Y18
Y17
Y16
Y15
Y14
W21
W20
W19
W18
W17
W16
W15
W14
V21
V20
V19
V18
V17
V16
V15
V14
U21
U20
U19
U18
U17
U16
U15
U14
T21
T20
T19
T18
T17
T16
T15
T14
R21
R20
R19
R18
R17
R16
R15
R14
P21
P20
P19
P18
P17
P16
P15
P14
F19
F18
E19
E18
D19
D18
C19
C18
A19
A18
VCC2_5
VDDQ
C473
C477
104P/B
104P/B
C506
C497
104P/B
104P/B
VDDR
C459
C464
104P/B
104P/B
105P/B
VDDR
C485
C474
105P/B
105P/B
C496
105P/B
close to KT400 power pin
VCC2_5
C489
C486
104P/B
C476
104P/B
104P/B
C481
104P/B
C471
C490
104P/B
C492
105P/B
C475
104P/B
5020
C480
105P/B
C493
X_104P
C495
104P/B
C499
X_105P/B
C501
104P/B
C449
X_105P/B
C452
104P/B
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
5
4
3
2
http://www.msi.com.tw
VT8377 POWER
MS-6712
Last Revision Date:
Sheet
1
Friday, November 08, 2002
10 34
Rev
20A
of
5
SYSTEM MEMORY
4
3
2
1
VDDR
D D
738467085
108
120
148
168223054627796
C131
103P
2 1
C505
X_105P
2 1
VDDR
R45
1KST
R39
1KST
C144
105P
2 1
2 1
C443
X_475P/0805
DR_MD[63..0]
C156
104P
2 1
2 1
C503
X_105P
50205020
R158 4.7K
MSWEA#{8,14}
DDR_VREF
C18
X_104P
C20
104P
DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
C174
105P
Place 104p Cap. near the DIMM
C17
104P
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63
MSWEA#
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
2
DQ0
4
DQ1
6
DQ2
8
DQ3
94
DQ4
95
DQ5
98
DQ6
99
DQ7
12
DQ8
13
DQ9
19
DQ10
20
DQ11
105
DQ12
106
DQ13
109
DQ14
110
DQ15
23
DQ16
24
DQ17
28
DQ18
31
DQ19
114
DQ20
117
DQ21
121
DQ22
123
DQ23
33
DQ24
35
DQ25
39
DQ26
40
DQ27
126
DQ28
127
DQ29
131
DQ30
133
DQ31
53
DQ32
55
DQ33
57
DQ34
60
DQ35
146
DQ36
147
DQ37
150
DQ38
151
DQ39
61
DQ40
64
DQ41
68
DQ42
69
DQ43
153
DQ44
155
DQ45
161
DQ46
162
DQ47
72
DQ48
73
DQ49
79
DQ50
80
DQ51
165
DQ52
166
DQ53
170
DQ54
171
DQ55
83
DQ56
84
DQ57
87
DQ58
88
DQ59
174
DQ60
175
DQ61
178
DQ62
179
DQ63
90
WP(NC)
63
WE#
1
VREF
9
NC2
101
NC3
102
4
SLAVE ADDRESS = 1010000B
NC4
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
3111826344250586674818993
DR_MD[63..0]{12,13,14}
VDDR
2 1
2 1
C79
105P
C132
105P
2 1
C447
X_105P
5020
5
2 1
VDDR
VDDR
C109
104P
2 1
2 1
C83
105P
C479
X_105P
2 1
VDDR
C23
103P
2 1
C C
B B
A A
104
112
128
136
143
156
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
184
DDR DIMM
SOCKET
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
100
116
124
132
139
VDDQ11
VSS17
164
172
1801582
VDDQ12
VDDQ13
VDDQ14
PIN
NC(RESET#)
VSS18
VSS19
VSS20
145
152
160
176
3
VCC3
VDDID
VDDQ15
CS0#
CS1#
CS2#
CS3#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
NC/FETEN
A10_AP
SDA
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
NC5
CKE0
CKE1
CAS#
RAS#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
VSS21
184
VDDSPD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A11
A12
A13
BA0
BA1
BA2
SCL
SA0
SA1
SA2
R145 10K
157
158
71
163
5
14
25
36
56
67
78
86
47
103
48
43
41
130
37
32
125
29
122
27
141
118
115
167
59
52
113
92
91
181
182
183
44
45
49
51
134
135
142
144
16
17
137
138
76
75
173
10
21
111
65
154
97
107
119
129
149
159
169
177
140
DDR1
DDRDIMM_184
MCS#0
MCS#1
DR_MDQS#0
DR_MDQS#1
DR_MDQS#2
DR_MDQS#3
DR_MDQS#4
DR_MDQS#5
DR_MDQS#6
DR_MDQS#7
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA13
MAA14
MAA15
MAA11
MAA12
SMBCLK1
SMBDATA1
DCLK0
DCLK#0
DCLK1
DCLK#1
DCLK2
DCLK#2
DDR_RESET#
MCKE0
MCKE1
MSCASA#
MSRASA#
DR_MDQM#0
DR_MDQM#1
DR_MDQM#2
DR_MDQM#3
DR_MDQM#4
DR_MDQM#5
DR_MDQM#6
DR_MDQM#7
DR_MDQM#8
MCS#0 {8,14}
MCS#1 {8,14}
DR_MDQS#0 {8,12,13,14}
DR_MDQS#1 {8,12,13,14}
DR_MDQS#2 {8,12,13,14}
DR_MDQS#3 {8,12,13,14}
DR_MDQS#4 {8,12,13,14}
DR_MDQS#5 {8,12,13,14}
DR_MDQS#6 {8,12,13,14}
DR_MDQS#7 {8,12,13,14}
MAA[15..0]
SMBCLK1 {6,12,13,17,21,30}
SMBDATA1 {6,12,13,17,21,30}
DCLK0 {6}
DCLK#0 {6}
DCLK1 {6}
DCLK#1 {6}
DCLK2 {6}
DCLK#2 {6}
MCKE0 {8}
MCKE1 {8}
MSCASA# {8,14}
MSRASA# {8,14}
DR_MDQM#0 {12,13,14}
DR_MDQM#1 {12,13,14}
DR_MDQM#2 {12,13,14}
DR_MDQM#3 {12,13,14}
DR_MDQM#4 {12,13,14}
DR_MDQM#5 {12,13,14}
DR_MDQM#6 {12,13,14}
DR_MDQM#7 {12,13,14}
MAA[15..0] {8,14}
2
R20
DDR_RESET#
1K
R25
4.7K
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
http://www.msi.com.tw
DDR_RESET# {12,13}PCIRST2#{19,20,30}
Micro Star Restricted Secret
System Memory : DDR DIMM 1
MS-6712
Last Revision Date:
Friday, November 08, 2002
Sheet
11 34
1
Rev
20A
of
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