MOTOROLA SN74LS259D, SN74LS259DR2, SN74LS259M, SN74LS259MEL, SN74LS259ML1 Datasheet
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Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6
1 Publication Order Number:
SN74LS259/D
SN74LS259
8-Bit Addressable Latch
The SN74LS259 is a high-speed 8-Bit Addressable Latch designed
for general purpose storage applications in digital systems. It is a
multifunctional device capable of storing single line data in eight
addressable latches, and also a 1-of-8 decoder and demultiplexer with
active HIGH outputs. The device also incorporates an active LOW
common Clear for resetting all latches, as well as, an active LOW
Enable.
• Serial-to-Parallel Conversion
• Eight Bits of Storage With Output of Each Bit Available
• Random (Addressable) Data Entry
• Active High Demultiplexing or Decoding Capability
• Easily Expandable
• Common Clear
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
Supply Voltage 4.75 5.0 5.25 V
T
A
Operating Ambient
T emperature Range
0 25 70 °C
I
OH
Output Current – High –0.4 mA
I
OL
Output Current – Low 8.0 mA
LOW
POWER
SCHOTTKY
Device Package Shipping
ORDERING INFORMATION
SN74LS259N 16 Pin DIP 2000 Units/Box
SN74LS259D 16 Pin
SOIC
D SUFFIX
CASE 751B
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2500/Tape & Reel
PLASTIC
N SUFFIX
CASE 648
16
1
16
1
SN74LS259
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2
CONNECTION DIAGRAM DIP (TOP VIEW)
Address Inputs
Data Input
Enable (Active LOW) Input
Clear (Active LOW) Input
Parallel Latch Outputs
A
0
, A1, A
2
D
E
C
Q0 – Q
7
0.5 U.L.
0.5 U.L.
1.0 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.5 U.L.
0.25 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
HIGH LOW
(Note a)LOADING
PIN NAMES
14 13 12 11 10 9
123456
7
16 15
8
V
CC
A
o
C E DQ
7
Q
5
Q
6
Q
4
A1A2Q0Q1Q2Q3GND
E
C MODE
L
H
L
H
H
H
L
L
Addressable Latch
Memory
Active HIGH Eight-Channel
Demultiplexer
Clear
MODE SELECTION
X = Don’t Care Condition
L = LOW Voltage Level
H = HIGH Voltage Level
Q
N–1
= Previous Output State
SN74LS259
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3
LOGIC DIAGRAM
E DA
0
A1A
2
C
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
14 12
67
3
4 5 9 11 1210
13 15
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
FUNCTIONAL DESCRIPTION
The SN74LS259 has four modes of operation as shown in
the mode selection table. In the addressable latch mode, data
on the Data line (D) is written into the addressed latch.The
addressed latch will follow the data input with all
non-addressed latches remaining in their previous states. In
the memory mode, all latches remain in their previous state
and are unaffected by the Data or Address inputs.
In the one-of-eight decoding or demultiplexing mode, the
addressed output will follow the state of the D input with all
other inputs in the LOW state. In the clear mode all outputs
are LOW and unaffected by the address and data inputs.
When operating the SN74LS259 as an addressable latch,
changing more then one bit of the address could impose a
transient wrong address. Therefore, this should only be done
while in the memory mode.
The truth table below summarizes the operations.
TRUTH TABLE
PRESENT OUTPUT STATES
C E D A0A1A2Q
0
Q
1
Q
2
Q
3
Q4Q
5
Q
6
Q
7
MODE
L H X X X X L L L L L L L L Clear
L LL L L L L L L L L L L L Demultiplex
L LH L L L H LLLLLLL
L LL H L L L LLLLLLL
L LH H L L L HLLLLLL
• •• • •
• •• • •
• •• • •
• •• • •
• •• • •
L LH H H H L LLLLLLH
H H X X X X Q
N–1
Memory
H I I L L L L Q
N–1QN–1QN–1
Addressable
H LH L L L H Q
N–1QN–1
Latch
H LL H L L Q
N–1
LQ
N–1
H LH H L L Q
N–1
HQ
N–1
• •• • •
• •• • •
• •• • •
• •• • •
• •• • •
H LL H H H Q
N–1
Q
N–1
L
H L H H H H Q
N–1
Q
N–1
H
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