Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 1
1 Publication Order Number:
MC74HC164A/D
MC74HC164A
8-Bit Serial-Input/
Parallel-Output Shift
Register
High–Performance Silicon–Gate CMOS
The MC74HC164A is identical in pinout to the LS164. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
The MC74HC164A is an 8–bit, serial–input to parallel–output shift
register. Two serial data inputs, A1 and A2, are provided so that one
input may be used as a data enable. Data is entered on each rising edge
of the clock. The active–low asynchronous Reset overrides the Clock
and Serial Data inputs.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 244 FETs or 61 Equivalent Gates
LOGIC DIAGRAM
PIN 14 = V
CC
PIN 7 = GND
3
Q
A
4
5
6
10
11
12
13
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
PARALLEL
DATA
OUTPUTS
9
RESET
CLOCK
8
SERIAL
DATA
INPUTS
A1
A2
1
2
DATA
FUNCTION TABLE
Inputs Outputs
Reset Clock A1 A2 QAQB… Q
H
LXXXLL… L
H X X No Change
HHDDQ
An
… Q
Gn
HDHDQ
An
… Q
Gn
D = data input
QAn – QGn = data shifted from the preceding
stage on a rising edge at the clock input.
Device Package Shipping
ORDERING INFORMATION
MC74HC164AN PDIP–14 2000 / Box
MC74HC164AD SOIC–14
http://onsemi.com
55 / Rail
MC74HC164ADR2 SOIC–14 2500 / Reel
MARKING
DIAGRAMS
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
MC74HC164ADT TSSOP–14 96 / Rail
MC74HC164ADTR2 TSSOP–14
2500 / Reel
TSSOP–14
DT SUFFIX
CASE 948G
HC
164A
ALYW
1
14
1
14
PDIP–14
N SUFFIX
CASE 646
MC74HC164AN
AWLYYWW
SOIC–14
D SUFFIX
CASE 751A
1
14
HC164A
AWLYWW
PIN ASSIGNMENT
11
12
13
14
8
9
105
4
3
2
1
7
6
Q
E
Q
F
Q
G
Q
H
V
CC
CLOCK
RESET
Q
B
Q
A
A2
A1
GND
Q
D
Q
C
MC74HC164A
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2
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic DIP†
SOIC Package†
TSSOP Package†
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time VCC = 2.0 V
(Figure 1) VCC = 4.5 V
VCC = 6.0 V
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Minimum High–Level Input
Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
Maximum Low–Level Input
Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
Minimum High–Level Output
Voltage
Vin = VIH or V
IL
|I
out
| v 20 µA
Vin = VIH or VIL|I
out
| v 2.4 mA
|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74HC164A
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3
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Maximum Low–Level Output
Voltage
Vin = VIH or V
IL
|I
out
| v 20 µA
Vin = VIH or VIL|I
out
| v 2.4 mA
|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
Maximum Input Leakage
Current
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
I
out
= 0 µA
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input tr = tf = 6 ns)
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)
Maximum Propagation Delay, Reset to Q
(Figures 2 and 4)
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
Maximum Input Capacitance
pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
C
PD
Power Dissipation Capacitance (Per Package)*
180
pF
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).