SEMICONDUCTOR TECHNICAL DATA
3–1
REV 0
Motorola, Inc. 1996
3/96
! "!
"!"! ! !
High–Performance Silicon–Gate CMOS
The MC54/74HC164A is identical in pinout to the LS164. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The MC54/74HC164A is an 8–bit, serial–input to p arallel–output s hift
register. Two serial data inputs, A1 and A2, are provided so that one input
may be used as a data enable. Data is entered on each rising edge of the
clock. The active–low asynchronous Reset overrides the Clock and Serial
Data inputs.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1
µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 244 FETs or 61 Equivalent Gates
LOGIC DIAGRAM
PIN 14 = V
CC
PIN 7 = GND
3
Q
A
4
5
6
10
11
12
13
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
PARALLEL
DATA
OUTPUTS
9
RESET
CLOCK
8
SERIAL
DATA
INPUTS
A1
A2
1
2
DATA
FUNCTION TABLE
Inputs Outputs
Reset Clock A1 A2 QAQB… Q
H
L X X X L L … L
H X X No Change
H H D D QAn… Q
Gn
H D H D QAn… Q
Gn
D = data input
QAn – QGn = data shifted from the preceding
stage on a rising edge at the clock input.
D SUFFIX
SOIC PACKAGE
CASE 751A–03
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
Ceramic
Plastic
SOIC
TSSOP
1
14
1
14
1
14
DT SUFFIX
TSSOP PACKAGE
CASE 948G–01
J SUFFIX
CERAMIC PACKAGE
CASE 632–08
1
14
PIN ASSIGNMENT
11
12
13
14
8
9
105
4
3
2
1
7
6
Q
E
Q
F
Q
G
Q
H
V
CC
CLOCK
RESET
Q
B
Q
A
A2
A1
GND
Q
D
Q
C
MC54/74HC164A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
3–2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
V
out
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
I
in
DC Input Current, per Pin
± 20
mA
I
out
DC Output Current, per Pin
± 25
mA
I
CC
DC Supply Current, VCC and GND Pins
± 50
mA
P
D
Power Dissipation in Still Air,Plastic or Ceramic DIP†
SOIC Package†
TSSOP Package†
750
500
450
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
(Ceramic DIP)
260
300
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
– 55
+ 125
_
C
tr, t
f
Input Rise and Fall Time VCC = 2.0 V
(Figure 1) VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC
V
–55_C to
25_C
v
85_Cv 125_C
Unit
V
IH
Minimum High–Level Input
Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
V
IL
Maximum Low–Level Input
Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
OH
Minimum High–Level Output
Voltage
Vin = VIH or V
IL
|I
out
| v 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or VIL|I
out
| v 2.4 mA
|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC54/74HC164A
High–Speed CMOS Logic Data
DL129 — Rev 6
3–3 MOTOROLA
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Unit
Guaranteed Limit
V
CC
V
Test Conditions
Parameter
Symbol
Unit
v
125_C
v
85_C
–55_C to
25_C
V
CC
V
Test Conditions
Parameter
Symbol
V
OL
Maximum Low–Level Output
Voltage
Vin = VIH or V
IL
|I
out
| v 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL|I
out
| v 2.4 mA
|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
I
in
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
I
CC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
I
out
= 0 µA
6.0
4
40
160
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
V
CC
V
–55_C to
25_C
v
85_Cv 125_C
Unit
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
3.0
4.5
6.0
10
20
40
50
10
20
35
45
10
20
30
40
MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)
2.0
3.0
4.5
6.0
160
100
32
27
200
150
40
34
250
200
48
42
ns
t
PHL
Maximum Propagation Delay, Reset to Q
(Figures 2 and 4)
2.0
3.0
4.5
6.0
175
100
35
30
220
150
44
37
260
200
53
45
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
C
in
Maximum Input Capacitance
—
10
10
10
pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
C
PD
Power Dissipation Capacitance (Per Package)*
180
pF
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
MC54/74HC164A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
3–4
TIMING REQUIREMENTS (Input t
r
= tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
V
CC
V
–55_C to
25_C
v
85_Cv 125_C
Unit
t
su
Minimum Setup Time, A1 or A2 to Clock
(Figure 3)
2.0
3.0
4.5
6.0
25
15
7
5
35
20
8
6
40
25
9
6
ns
t
h
Minimum Hold Time, Clock to A1 or A2
(Figure 3)
2.0
3.0
4.5
6.0
3
3
3
3
3
3
3
3
3
3
3
3
ns
t
rec
Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
2.0
3.0
4.5
6.0
3
3
3
3
3
3
3
3
3
3
3
3
ns
t
w
Minimum Pulse Width, Clock
(Figure 1)
2.0
3.0
4.5
6.0
50
26
12
10
60
35
15
12
75
45
20
15
ns
t
w
Minimum Pulse Width, Reset
(Figure 2)
2.0
3.0
4.5
6.0
50
26
12
10
60
35
15
12
75
45
20
15
ns
tr, t
f
Maximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MC54/74HC164A
High–Speed CMOS Logic Data
DL129 — Rev 6
3–5 MOTOROLA
PIN DESCRIPTIONS
INPUTS
A1, A2 (Pins 1, 2)
Serial Data Inputs. Data at these inputs determine the data
to be entered into the first stage of the shift register. For a
high level to be entered into the shift register, both A1 and A2
inputs must be high, thereby allowing one input to be used as
a data–enable input. When only one serial input is used, the
other must be connected to VCC.
Clock (Pin 8)
Shift Register Clock. A positive–going transition on this pin
shifts the data at each stage to the next stage. The shift
register is completely static, allowing clock rates down to DC
in a continuous or intermittent mode.
OUTPUTS
QA – QH (Pins 3, 4, 5, 6, 10, 11, 12, 13)
Parallel Shift Register Outputs. The shifted data is pres-
ented at these outputs in true, or noninverted, form.
CONTROL INPUT
Reset (Pin 9)
Active–Low, Asynchronous Reset Input. A low voltage applied to this input resets all internal flip–flops and sets Outputs QA – QH to the low level state.
SWITCHING WAVEFORMS
t
f
V
CC
GND
90%
50%
10%
t
w
t
PLH
t
PHL
CLOCK
Q
t
TLH
t
THL
Figure 1.
RESET
t
rec
Figure 2.
t
r
1/f
max
90%
50%
10%
V
CC
GND
V
CC
GND
Q
CLOCK 50%
50%
50%
t
PHL
t
w
A1 OR A2
Figure 3.
V
CC
GND
V
CC
GND
50%
50%
CLOCK
t
su
t
h
VALID
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 4. Test Circuit
MC54/74HC164A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
3–6
TIMING DIAGRAM
A1
A2
CLOCK
RESET
8
1
2
9
DRQ
3 4 5 6 10 11 12 13
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
EXPANDED LOGIC DIAGRAM
DRQ DRQ DRQ DRQ DRQ DRQ DRQ
CLOCK
RESET
A1
A2
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
MC54/74HC164A
High–Speed CMOS Logic Data
DL129 — Rev 6
3–7 MOTOROLA
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC DIP PACKAGE
CASE 632–08
ISSUE Y
MIN MINMAX MAX
INCHES MILLIMETERS
DIM
A
B
C
D
F
G
J
K
L
M
N
0.785
0.280
0.200
0.020
0.065
0.015
0.170
15
°
0.040
0.750
0.245
0.155
0.015
0.055
0.008
0.125
0
°
0.020
19.94
7.11
5.08
0.50
1.65
0.38
4.31
15
°
1.01
19.05
6.23
3.94
0.39
1.40
0.21
3.18
0
°
0.51
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMESNION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
14 8
1 7
-A-
-B-
-T-
SEATING
PLANE
F G
N
K
C
L
M
0.25 (0.010) T A
M
S
0.25 (0.010) T B
M
S
J 14 PL
D 14 PL
N SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
1 7
14 8
B
A
F
H G D
K
C
N
L
J
M
SEATING
PLANE
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L 0.300 BSC 7.62 BSC
M 0 10 0 10
N 0.015 0.039 0.39 1.01
_ _ _ _
MC54/74HC164A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
3–8
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
0.19
0.10
0
°
5.80
0.25
8.75
4.00
1.75
0.49
1.25
0.25
0.25
7
°
6.20
0.50
0.337
0.150
0.054
0.014
0.016
0.008
0.004
0°
0.228
0.010
0.344
0.157
0.068
0.019
0.049
0.009
0.009
7°
0.244
0.019
1.27 BSC 0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
–B–
P 7 PL
G
C
K
SEATING
PLANE
D 14 PL
M
J
R
X 45°
1
7
814
0.25 (0.010) T B A
M
S S
B0.25 (0.010)
M M
F
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G–01
ISSUE O
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
_ _ _ _
S
U0.15 (0.006) T
2X L/2
S
U
M
0.10 (0.004) V
S
T
L
–U–
SEATING
PLANE
0.10 (0.004)
–T–
SECTION N–N
DETAIL E
J
J1
K
K1
DETAIL E
F
M
–W–
0.25 (0.010)
8
14
7
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U0.15 (0.006) T
–V–
14X REFK
N
N
MC54/74HC164A
High–Speed CMOS Logic Data
DL129 — Rev 6
3–9 MOTOROLA
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MC54/74HC164A/D
*MC54/74HC164A/D*
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