MOTOROLA MC68HC908AP64, MC68HC908AP32, MC68HC908AP16, MC68HC908AP8 Technical data
查询MC68HC908AP16供应商
Freescale Semiconductor, Inc.
MC68HC908AP64
MC68HC908AP32
MC68HC908AP16
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M68HC08
Microcontrollers
MC68HC908AP8
Data Sheet
MC68HC908AP64/D
Rev. 2.5
10/2003
MOTOROLA.COM/SEMICONDUCTORS
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MC68HC908AP64
MC68HC908AP32
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MC68HC908AP16
MC68HC908AP8
Data Sheet
To provide the most up-to-date information, the revision of our
documents on the World Wide Web will be the most current. Your printed
copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://motorola.com/semiconductors/
The following revision history table summarizes changes contained in
this document. For your convenience, the page number designators
have been linked to the appropriate location.
Motorola and the Stylized M Logo are registered trademarks of Motorola, Inc.
DigitalDNA is a trademark of Motorola, Inc.
This product incorporates SuperFlash® technology licensed from SST. © Motorola, Inc., 2003
MC68HC908AP Family — Rev. 2.5 Data Sheet
MOTOROLA 3
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Revision History
Freescale Semiconductor, Inc.
Revision History
Date
October 2003 2.5
August 2003 2.4
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July 2003 2.3
May 2003 2.2
cale Semiconductor,
Revision
Level
Description
Added MC68HC908AP16/AP8 information throughout. —
Section 10. Monitor ROM (MON) — Corrected RAM address to
$60.
Section 24. Electrical Specifications — Added run and wait
data for 8MHz at 3V.
I
DD
Section 24. Electrical Specifications — Updated stop I
Removed MC68HC908AP16 references throughout. —
Table 1-2 . Pin Functions — Added footnote for V
5.3 Configuration Register 1 (CONFIG1) — Clarified LVIPWRD
and LVIREGD bits.
Section 8. Clock Generator Module (CGM), 8.7.2 Stop Mode
— Updated BSC bit behavior.
10.5 ROM-Resident Routines — Corrected data size limits and
control byte size for EE_READ and EE_WRITE.
Figure 12-2 . Timebase Control Register (TBCR) — Corrected
register address.
Section 24. Electrical Specifications — Updated. 415
Updated for f
in CGM section.
Updated electricals. 415
= 125kHz and filter components
NOM
REG
data.
DD
.
Page
Number(s)
167
421
417, 421
30
67
125
168–193
207
101
Frees
Data Sheet MC68HC908AP Family — Rev. 2.5
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Data Sheet – MC68HC908AP Family
Section 1. General Description. . . . . . . . . . . . . . . . . . . . . . . . . . 23
Section 2. Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Section 3. Random-Access Memory (RAM) . . . . . . . . . . . . . . . 53
Section 4. FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
List of Sections
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Section 5. Configuration & Mask Option Registers
(CONFIG & MOR) . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Section 6. Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . 73
Section 7. Oscillator (OSC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Section 8. Clock Generator Module (CGM) . . . . . . . . . . . . . . . 101
Section 9. System Integration Module (SIM) . . . . . . . . . . . . . . 129
Section 10. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . . 153
Section 11. Timer Interface Module (TIM) . . . . . . . . . . . . . . . . 181
Section 12. Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . 205
Section 13. Serial Communications Interface Module
(SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Section 14. Infrared Serial Communications Interface
Module (IRSCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Section 15. Serial Peripheral Interface Module (SPI) . . . . . . . 289
Section 16. Multi-Master IIC Interface (MMIIC) . . . . . . . . . . . . 319
Section 17. Analog-to-Digital Converter (ADC). . . . . . . . . . . . 345
Section 18. Input/Output (I/O) Ports. . . . . . . . . . . . . . . . . . . . . 363
Section 19. External Interrupt (IRQ). . . . . . . . . . . . . . . . . . . . . 379
Section 20. Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . 387
Section 21. Computer Operating Properly (COP). . . . . . . . . . 395
Section 22. Low-Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . 401
Section 23. Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . 407
Section 24. Electrical Specifications . . . . . . . . . . . . . . . . . . . . 415
Section 25. Mechanical Specifications . . . . . . . . . . . . . . . . . . 433
Section 26. Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 437
MC68HC908AP Family — Rev. 2.5 Data Sheet
MOTOROLA 5
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List of Sections
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Data Sheet MC68HC908AP Family — Rev. 2.5
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Data Sheet – MC68HC908AP Family
Section 1. General Description
1.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table of Contents
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1.3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.4 Pin Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.5 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.6 Power Supply Bypassing (VDD, VDDA, VSS, VSSA) . . . . . . . 32
1.7 Regulator Power Supply Configuration (VREG) . . . . . . . . . . . .33
Section 2. Memory Map
2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.2 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 35
2.3 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.4 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Section 3. Random-Access Memory (RAM)
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Section 4. FLASH Memory
4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
4.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.3 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
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4.4 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .58
4.5 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .59
4.6 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .60
4.7 FLASH Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.7.1 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . .62
Section 5. Configuration & Mask Option Registers (CON-
FIG & MOR)
5.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
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5.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.3 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . . 67
5.4 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . . . 69
5.5 Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . .71
6.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
6.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
6.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
6.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
6.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
6.3.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
6.3.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.4 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Section 6. Central Processor Unit (CPU)
6.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
6.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
6.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
6.6 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .80
6.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
6.8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Data Sheet MC68HC908AP Family — Rev. 2.5
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Table of Contents
Section 7. Oscillator (OSC)
7.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
7.2 Clock Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
7.2.1 CGM Reference Clock Selection . . . . . . . . . . . . . . . . . . . . . 93
7.2.2 TBM Reference Clock Selection . . . . . . . . . . . . . . . . . . . . .94
7.3 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
7.4 RC Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
7.5 X-tal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
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7.6 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.6.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . 97
7.6.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . .98
7.6.3 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . . 98
7.6.4 CGM Oscillator Clock (CGMXCLK) . . . . . . . . . . . . . . . . . . . 98
7.6.5 CGM Reference Clock (CGMRCLK) . . . . . . . . . . . . . . . . . .98
7.6.6 Oscillator Clock to Time Base Module (OSCCLK) . . . . . . . .98
7.7 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
7.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.8 Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . .99
Section 8. Clock Generator Module (CGM)
8.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
8.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
8.3.1 Oscillator Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
8.3.2 Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . .105
8.3.3 PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
8.3.4 Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . .107
8.3.5 Manual and Automatic PLL Bandwidth Modes. . . . . . . . . . 107
8.3.6 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
8.3.7 Special Programming Exceptions . . . . . . . . . . . . . . . . . . .113
8.3.8 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . 113
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8.3.9 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . .114
8.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
8.4.1 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . 115
8.4.2 PLL Analog Power Pin (V
8.4.3 PLL Analog Ground Pin (V
8.4.4 Oscillator Output Frequency Signal (CGMXCLK) . . . . . . .115
8.4.5 CGM Reference Clock (CGMRCLK) . . . . . . . . . . . . . . . . .115
8.4.6 CGM VCO Clock Output (CGMVCLK) . . . . . . . . . . . . . . . .116
8.4.7 CGM Base Clock Output (CGMOUT). . . . . . . . . . . . . . . . . 116
8.4.8 CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . .116
) . . . . . . . . . . . . . . . . . . . . . .115
DDA
) . . . . . . . . . . . . . . . . . . . . . 115
SSA
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8.5 CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
8.5.1 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
8.5.2 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . .119
8.5.3 PLL Multiplier Select Registers . . . . . . . . . . . . . . . . . . . . .121
8.5.4 PLL VCO Range Select Register . . . . . . . . . . . . . . . . . . . .122
8.5.5 PLL Reference Divider Select Register . . . . . . . . . . . . . . . 123
8.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
8.7 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
8.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
8.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
8.7.3 CGM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . 125
8.8 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .126
8.8.1 Acquisition/Lock Time Definitions. . . . . . . . . . . . . . . . . . . . 126
8.8.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . .126
8.8.3 Choosing a Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Section 9. System Integration Module (SIM)
9.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
9.2 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . .131
9.2.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
9.2.2 Clock Start-up from POR or LVI Reset. . . . . . . . . . . . . . . . 132
9.2.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . .133
9.3 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . .133
9.3.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
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9.3.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . 134
9.3.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
9.3.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . . 136
9.3.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .137
9.3.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
9.3.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . .137
9.3.2.6 Monitor Mode Entry Module Reset. . . . . . . . . . . . . . . . .137
9.4 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
9.4.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . 138
9.4.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . .138
9.4.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . .138
Table of Contents
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9.5 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
9.5.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
9.5.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
9.5.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
9.5.1.3 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . .142
9.5.1.4 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . 142
9.5.1.5 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . 144
9.5.1.6 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . 144
9.5.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
9.5.3 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
9.5.4 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . 145
9.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
9.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
9.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
9.7 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
9.7.1 SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . .149
9.7.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . .150
9.7.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . .151
Section 10. Monitor ROM (MON)
10.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
10.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
10.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
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10.3.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
10.3.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
10.3.3 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
10.3.4 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
10.3.5 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
10.4 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
10.5 ROM-Resident Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
10.5.1 PRGRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
10.5.2 ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
10.5.3 LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
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10.5.4 MON_PRGRNGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
10.5.5 MON_ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
10.5.6 EE_WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
10.5.7 EE_READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
cale Semiconductor,
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Section 11. Timer Interface Module (TIM)
11.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
11.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
11.3 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
11.4.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
11.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
11.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
11.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . .187
11.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . 188
11.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . .188
11.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . .189
11.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 190
11.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
11.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
11.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
11.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
11.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
Data Sheet MC68HC908AP Family — Rev. 2.5
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11.7 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .193
11.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
11.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
11.9.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . .195
11.9.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
11.9.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . .198
11.9.4 TIM Channel Status and Control Registers . . . . . . . . . . . .199
11.9.5 TIM Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table of Contents
Section 12. Timebase Module (TBM)
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cale Semiconductor,
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12.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
12.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
12.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
12.4 Timebase Register Description. . . . . . . . . . . . . . . . . . . . . . . .207
12.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
12.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
12.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
12.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
Section 13. Serial Communications Interface Module
(SCI)
13.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
13.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
13.3 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
13.4.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
13.4.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
13.4.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
13.4.2.2 Character Transmission. . . . . . . . . . . . . . . . . . . . . . . . . 218
13.4.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
13.4.2.4 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
13.4.2.5 Inversion of Transmitted Output. . . . . . . . . . . . . . . . . . . 220
MC68HC908AP Family — Rev. 2.5 Data Sheet
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13.4.2.6 Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .220
13.4.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
13.4.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
13.4.3.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
13.4.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
13.4.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
13.4.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
13.4.3.6 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
13.4.3.7 Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
13.4.3.8 Error Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
13.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
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13.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
13.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
cale Semiconductor,
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13.6 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . .230
13.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
13.7.1 TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
13.7.2 RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
13.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
13.8.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
13.8.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
13.8.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . .238
13.8.4 SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
13.8.5 SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
13.8.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
13.8.7 SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . .246
Section 14. Infrared Serial Communications
Interface Module (IRSCI)
14.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
14.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
14.3 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
14.4 IRSCI Module Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
14.5 Infrared Functional Description. . . . . . . . . . . . . . . . . . . . . . . .253
Data Sheet MC68HC908AP Family — Rev. 2.5
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14.5.1 Infrared Transmit Encoder . . . . . . . . . . . . . . . . . . . . . . . . . 254
14.5.2 Infrared Receive Decoder . . . . . . . . . . . . . . . . . . . . . . . . .254
14.6 SCI Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
14.6.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256
14.6.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
14.6.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
14.6.2.2 Character Transmission. . . . . . . . . . . . . . . . . . . . . . . . . 258
14.6.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
14.6.2.4 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
14.6.2.5 Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .260
14.6.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260
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cale Semiconductor,
14.6.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
14.6.3.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
14.6.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262
14.6.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
14.6.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
14.6.3.6 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
14.6.3.7 Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
14.6.3.8 Error Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
14.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
14.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
14.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
14.8 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . .269
14.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
14.9.1 PTC6/SCTxD (Transmit Data) . . . . . . . . . . . . . . . . . . . . . . 270
14.9.2 PTC7/SCRxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . .270
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14.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
14.10.1 IRSCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . .272
14.10.2 IRSCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . .274
14.10.3 IRSCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . .277
14.10.4 IRSCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .279
14.10.5 IRSCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .283
14.10.6 IRSCI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
14.10.7 IRSCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . .285
14.10.8 IRSCI Infrared Control Register . . . . . . . . . . . . . . . . . . . . .288
MC68HC908AP Family — Rev. 2.5 Data Sheet
MOTOROLA 15
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Table of Contents
Section 15. Serial Peripheral Interface Module (SPI)
15.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
15.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
15.3 Pin Name Conventions and I/O Register Addresses . . . . . . .290
15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
15.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292
15.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
15.5 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
15.5.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . .294
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15.5.2 Transmission Format When CPHA = 0 . . . . . . . . . . . . . . .295
15.5.3 Transmission Format When CPHA = 1 . . . . . . . . . . . . . . .297
15.5.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . .298
cale Semiconductor,
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15.6 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . 300
15.7 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301
15.7.1 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301
15.7.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303
15.8 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
15.9 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
15.10 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
15.10.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
15.10.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
15.11 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .309
15.12 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
15.12.1 MISO (Master In/Slave Out) . . . . . . . . . . . . . . . . . . . . . . . .310
15.12.2 MOSI (Master Out/Slave In) . . . . . . . . . . . . . . . . . . . . . . . .310
15.12.3 SPSCK (Serial Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
15.12.4 SS
15.12.5 CGND (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
(Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
15.13 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
15.13.1 SPI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
15.13.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . .315
15.13.3 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Data Sheet MC68HC908AP Family — Rev. 2.5
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Table of Contents
Section 16. Multi-Master IIC Interface (MMIIC)
16.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319
16.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320
16.3 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
16.4 Multi-Master IIC System Configuration . . . . . . . . . . . . . . . . . .322
16.5 Multi-Master IIC Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . .322
16.5.1 START Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
16.5.2 Slave Address Transmission . . . . . . . . . . . . . . . . . . . . . . .323
16.5.3 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323
16.5.4 Repeated START Signal . . . . . . . . . . . . . . . . . . . . . . . . . . 324
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16.5.5 STOP Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
16.5.6 Arbitration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324
16.5.7 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . .325
16.5.8 Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325
16.5.9 Packet Error Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326
cale Semiconductor,
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16.6 MMIIC I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
16.6.1 MMIIC Address Register (MMADR) . . . . . . . . . . . . . . . . . .326
16.6.2 MMIIC Control Register 1 (MMCR1) . . . . . . . . . . . . . . . . .328
16.6.3 MMIIC Control Register 2 (MMCR2) . . . . . . . . . . . . . . . . .330
16.6.4 MMIIC Status Register (MMSR). . . . . . . . . . . . . . . . . . . . . 332
16.6.5 MMIIC Data Transmit Register (MMDTR) . . . . . . . . . . . . . 334
16.6.6 MMIIC Data Receive Register (MMDRR). . . . . . . . . . . . . . 335
16.6.7 MMIIC CRC Data Register (MMCRCDR). . . . . . . . . . . . . . 336
16.6.8 MMIIC Frequency Divider Register (MMFDR) . . . . . . . . . .337
16.7 Program Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338
16.7.1 Data Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
16.8 SMBus Protocols with PEC and without PEC. . . . . . . . . . . . .340
16.8.1 Quick Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
16.8.2 Send Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340
16.8.3 Receive Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340
16.8.4 Write Byte/Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .341
16.8.5 Read Byte/Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .341
16.8.6 Process Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342
16.8.7 Block Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
16.9 SMBus Protocol Implementation . . . . . . . . . . . . . . . . . . . . . .343
MC68HC908AP Family — Rev. 2.5 Data Sheet
MOTOROLA 17
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Table of Contents
Section 17. Analog-to-Digital Converter (ADC)
17.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
17.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
17.3.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347
17.3.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347
17.3.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
17.3.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . .349
17.3.5 Auto-Scan Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
17.3.6 Result Justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350
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17.3.7 Data Register Interlocking . . . . . . . . . . . . . . . . . . . . . . . . .351
17.3.8 Monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351
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17.4 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
17.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
17.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
17.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
17.6 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
17.6.1 ADC Voltage In (V
17.6.2 ADC Analog Power Pin (V
17.6.3 ADC Analog Ground Pin (V
17.6.4 ADC Voltage Reference High Pin (V
17.6.5 ADC Voltage Reference Low Pin (V
17.7 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354
17.7.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . . 354
17.7.2 ADC Clock Control Register. . . . . . . . . . . . . . . . . . . . . . . . 356
17.7.3 ADC Data Register 0 (ADRH0 and ADRL0). . . . . . . . . . . . 358
17.7.4 ADC Auto-Scan Mode Data Registers (ADRL1–ADRL3). . 360
17.7.5 ADC Auto-Scan Control Register (ADASCR). . . . . . . . . . . 360
) . . . . . . . . . . . . . . . . . . . . . . . . . . .353
ADIN
) . . . . . . . . . . . . . . . . . . . . .353
DDA
). . . . . . . . . . . . . . . . . . . . . 353
SSA
). . . . . . . . . . . . .353
REFH
) . . . . . . . . . . . . . 353
REFL
Section 18. Input/Output (I/O) Ports
18.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363
18.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366
18.2.1 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . .366
Data Sheet MC68HC908AP Family — Rev. 2.5
18 MOTOROLA
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18.2.2 Data Direction Register (DDRA). . . . . . . . . . . . . . . . . . . . . 367
18.2.3 Port-A LED Control Register (LEDA) . . . . . . . . . . . . . . . . .369
18.3 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .370
18.3.1 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . .370
18.3.2 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . .371
18.4 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
18.4.1 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . 373
18.4.2 Data Direction Register C (DDRC). . . . . . . . . . . . . . . . . . . 374
18.5 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376
18.5.1 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . 376
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18.5.2 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . 377
Table of Contents
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Section 19. External Interrupt (IRQ)
19.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379
19.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379
19.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
19.4 IRQ1 and IRQ2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382
19.5 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .383
19.6 IRQ Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
19.6.1 IRQ1 Status and Control Register . . . . . . . . . . . . . . . . . . . 384
19.6.2 IRQ2 Status and Control Register . . . . . . . . . . . . . . . . . . . 385
Section 20. Keyboard Interrupt Module (KBI)
20.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387
20.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387
20.3 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
20.4.1 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . .390
20.5 Keyboard Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . .391
20.5.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . .391
20.5.2 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . .392
MC68HC908AP Family — Rev. 2.5 Data Sheet
MOTOROLA 19
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Table of Contents
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20.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
20.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
20.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
20.7 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .393
Section 21. Computer Operating Properly (COP)
21.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395
21.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
21.3 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
21.3.1 ICLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396
21.3.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396
21.3.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397
21.3.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397
21.3.5 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397
21.3.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397
21.3.7 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
21.3.8 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . 398
21.4 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
21.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399
21.6 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399
21.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399
21.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399
21.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399
21.8 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . 400
Section 22. Low-Voltage Inhibit (LVI)
22.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401
22.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401
22.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
22.3.1 Low V
22.3.2 Low V
22.3.3 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .404
Data Sheet MC68HC908AP Family — Rev. 2.5
20 MOTOROLA
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Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
DD
Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
REG
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22.3.4 Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .404
22.3.5 Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . .404
22.4 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .404
22.5 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
22.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405
22.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405
22.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405
Table of Contents
Section 23. Break Module (BRK)
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23.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407
23.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407
23.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
23.3.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . .409
23.3.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 409
23.3.3 TIMI and TIM2 During Break Interrupts . . . . . . . . . . . . . . . 410
23.3.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .410
23.4 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .410
23.4.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .410
23.4.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .410
23.5 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .410
23.5.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . .411
23.5.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 412
23.5.3 SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . .412
23.5.4 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . 414
Section 24. Electrical Specifications
24.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415
24.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .415
24.3 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .416
24.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .416
24.5 5V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . .417
MC68HC908AP Family — Rev. 2.5 Data Sheet
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24.6 5V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .419
24.7 5V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .419
24.8 5V ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 420
24.9 3V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . .421
24.10 3V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422
24.11 3V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 423
24.12 3V ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 424
24.13 MMIIC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . .425
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24.14 CGM Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . .427
24.15 5V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .428
24.16 3V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .429
24.17 FLASH Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . .432
Section 25. Mechanical Specifications
25.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .433
25.2 48-Pin Low-Profile Quad Flat Pack (LQFP) . . . . . . . . . . . . . .434
25.3 44-Pin Quad Flat Pack (QFP). . . . . . . . . . . . . . . . . . . . . . . . .435
25.4 42-Pin Shrink Dual In-Line Package (SDIP) . . . . . . . . . . . . . .436
Section 26. Ordering Information
26.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .437
26.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .437
Data Sheet MC68HC908AP Family — Rev. 2.5
22 MOTOROLA
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Data Sheet – MC68HC908AP Family
Section 1. General Description
1.1 Introduction
The MC68HC908AP64 is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08
Family is based on the customer-specified integrated circuit (CSIC)
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design strategy. All MCUs in the family use the enhanced M68HC08
central processor unit (CPU08) and are available with a variety of
modules, memory sizes and types, and package types.
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1.2 Features
Table 1-1. Summary of Device Variations
Device
MC68HC908AP64 2,048 62,368
MC68HC908AP32 2,048 32,768
MC68HC908AP16 1,024 16,384
MC68HC908AP8 1,024 8,192
Features of the MC68HC908AP64 include the following:
• High-performance M68HC08 architecture
• Fully upward-compatible object code with M6805, M146805, and
M68HC05 Families
• Maximum internal bus frequency:
– 8-MHz at 5V or 3V operating voltage
RAM Size
(bytes)
FLASH Memory Size
(bytes)
• Clock input options:
– RC-oscillator
– 32-kHz crystal-oscillator with 32MHz internal phase-lock-loop
MC68HC908AP Family — Rev. 2.5 Data Sheet
MOTOROLA 23
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General Description
Freescale Semiconductor, Inc.
• User program FLASH memory with security1 feature
• On-chip RAM
– 62,368 bytes for MC68HC908AP64
– 32,768 bytes for MC68HC908AP32
– 16,384 bytes for MC68HC908AP16
– 8,192 bytes for MC68HC908AP8
– 2,048 bytes for MC68HC908AP64 and MC68HC908AP32
– 1,024 bytes for MC68HC908AP16 and MC68HC908AP8
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• Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2)
with selectable input capture, output compare, and PWM
capability on each channel
• Timebase module
• Serial communications interface module 1 (SCI)
• Serial communications interface module 2 (SCI) with
infrared (IR) encoder/decoder
• Serial peripheral interface module (SPI)
• System management bus (SMBus), version 1.0/1.1
(multi-master IIC bus)
• 8-channel, 10-bit analog-to-digital converter (ADC)
•IRQ1
•IRQ2 external interrupt pin with programmable pullup
• 8-bit keyboard wakeup port with integrated pullup
• 32 general-purpose input/output (I/O) pins:
external interrupt pin with integrated pullup
– 31 shared-function I/O pins
– 8 LED drivers (sink)
–6 × 25mA open-drain I/O with pullup
• Low-power design (fully static with stop and wait modes)
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
Data Sheet MC68HC908AP Family — Rev. 2.5
24 MOTOROLA
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• Master reset pin (with integrated pullup) and power-on reset
• System protection features
• 48-pin low quad flat pack (LQFP), 44-pin quad flat pack (QFP),
General Description
MCU Block Diagram
– Optional computer operating properly (COP) reset, driven by
internal RC oscillator
– Low-voltage detection with optional reset or interrupt
– Illegal opcode detection with reset
– Illegal address detection with reset
and 42-pin shrink dual-in-line package (SDIP)
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• Specific features of the MC68HC908AP64 in 42-pin SDIP are:
– 30 general-purpose l/Os only
– External interrupt on IRQ1
Features of the CPU08 include the following:
• Enhanced HC05 programming model
• Extensive loop control functions
• 16 addressing modes (eight more than the HC05)
• 16-bit Index register and stack pointer
• Memory-to-memory data transfers
• Fast 8 × 8 multiply instruction
• Fast 16/8 divide instruction
• Binary-coded decimal (BCD) instructions
• Optimization for controller applications
only
• Efficient C language support
1.3 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC908AP64.
MC68HC908AP Family — Rev. 2.5 Data Sheet
MOTOROLA 25
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General Description
M68HC08 CPU
CPU
REGISTERS
CONTROL AND STATUS REGISTERS — 96 BYTES
USER FLASH — (SEE TABLE)
ARITHMETIC/LOGIC
UNIT (ALU)
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INTERNAL BUS
10-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
TIMEBASE
MODULE
DDRA
PTA7/ADC7
PTA6/ADC6
PTA5/ADC5
PTA4/ADC4
PORTA
PTA3/ADC3
PTA2/ADC2
PTA1/ADC1
PTA0/ADC0
‡
‡
‡
‡
‡
‡
‡
‡
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USER RAM — (SEE TABLE)
MONITOR ROM — 959 BYTES
USER FLASH VECTOR SPACE — 48 BYTES
OSCILLATORS AND
CLOCK GENERATOR MODULE
INTERNAL OSCILLATOR
OSC1
OSC2
CGMXFC
* RST
* IRQ1
** IRQ2
VDD
VDDA
VSS
VSSA
VREG
VREFH
VREFL
RC OSCILLATOR
X-TAL OSCILLATOR
PHASE-LOCKED LOOP
SYSTEM INTEGRATION
MODULE
EXTERNAL INTERRUPT
MODULE
COMPUTER OPERATING
PROPERLY MODULE
POWER-ON RESET
MODULE
POWER
ADC REFERENCE
2-CHANNEL TIMER INTERFACE
2-CHANNEL TIMER INTERFACE
MODULATOR/DEMODULATOR)
* Pin contains integrated pullup device.
** Pin contains configurable pullup device.
*** Pin contains integrated pullup device when configured as KBI.
†
Pin is open-drain when configured as output.
‡
LED direct sink pin.
#
Pin not bonded on 42-pin SDIP.
MC68HC908AP64 2,048 62,368
MC68HC908AP32 2,048 32,768
MC68HC908AP16 1,024 16,384
MC68HC908AP8 1,024 8,192
MODULE 1
MODULE 2
SERIAL COMMUNICATIONS
INTERFACE MODULE 1
MULTI-MASTER IIC (SMBUS)
INTERFACE MODULE
SERIAL COMMUNICATIONS
INTERFACE MODULE 2
(WITH INFRARED
SERIAL PERIPHERAL
INTERFACE MODULE
KEYBOARD INTERRUPT
MODULE
LOW-VOLTAGE INHIBIT
MODULE
DEVICE
.
USER RAM
(bytes)
DDRB
DDRC
DDRD
USER FLASH
PORTB
PORTC
PORTD
(bytes)
PTB7/T2CH1
PTB6/T2CH0
PTB5/T1CH1
PTB4/T1CH0
PTB3/RxD
PTB2/TxD
PTB1/SCL
PTB0/SDA
PTC7/SCRxD
PTC6/SCTxD
PTC5/SPSCK
PTC4/SS
PTC3/MOSI
PTC2/MISO
PTC1
PTC0/IRQ2 **
PTD7/KBI7 ***
PTD6/KBI6 ***
PTD5/KBI5 ***
PTD4/KBI4 ***
PTD3/KBI3 ***
PTD2/KBI2 ***
PTD1/KBI1 ***
PTD0/KBI0 ***
†
†
†
†
#
†
†
#
Figure 1-1. MC68HC908AP64 Block Diagram
Data Sheet MC68HC908AP Family — Rev. 2.5
26 MOTOROLA
For More Information On This Product,
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1.4 Pin Assignment
Freescale Semiconductor, Inc.
PTB6/T2CH0
1
PTB7/T2CH1
CGMXFC
48
47
PTD0/KBI0
46
PTD1/KBI1
45
PTD2/KBI2
44
VDDA
43
VSSA
42
PTD3/KBI3
41
PTD4/KBI4
40
PTD5/KBI5
39
General Description
Pin Assignment
PTD7/KBI7
PTD6/KBI6
37
38
36
VREFH
12
2
3
4
5
6
7
8
9
10
11
13
PTB1/SCL
14
15
PTB0/SDA
PTC6/SCTxD
PTC7/SCRxD
16
17
PTC5/SPSCK
18
19
PTC4/SS
PTC3/MOSI
20
21
22
PTC1
PTC2/MISO
PTC0/IRQ2
23
PTA7/ADC7
VREG
PTB5/T1CH1
nc...
I
PTB4/T1CH0
VDD
OSC1
OSC2
VSS
IRQ1
PTB3/RxD
RST
PTB2/TxD
cale Semiconductor,
35
34
33
32
31
30
29
28
27
26
24
NC
VREFL
NC
NC
PTA0/ADC0
NC
PTA1/ADC1
PTA2/ADC2
PTA3/ADC3
PTA4/ADC4
PTA5/ADC5
25
PTA6/ADC6
Frees
NC: No connection
Figure 1-2. 48-Pin LQFP Pin Assignments
MC68HC908AP Family — Rev. 2.5 Data Sheet
MOTOROLA 27
For More Information On This Product,
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General Description
Freescale Semiconductor, Inc.
PTB6/T2CH0
PTB7/T2CH1
CGMXFC
44
43
42
41
1
40
39
VSSA
38
PTD3/KBI3
37
VDDA
PTD2/KBI2
PTD1/KBI1
PTD0/KBI0
PTD5/KBI5
PTD4/KBI4
36
35
PTD6/KBI6
34
33
PTD7/KBI7
VREG
PTB5/T1CH1
VDD
OSC1
nc...
I
OSC2
VSS
PTB4/T1CH0
IRQ1
PTB3/RxD
RST
cale Semiconductor,
11
2
3
4
5
6
7
8
9
10
12
PTB2/TxD
13
14
PTB1/SCL
PTB0/SDA
15
16
17
PTC6/SCTxD
PTC7/SCRxD
PTC5/SPSCK
18
19
PTC4/SS
PTC3/MOSI
20
PTC2/MISO
32
31
30
29
28
27
26
25
24
21
22
PTC1
PTC0/IRQ2
Figure 1-3. 44-Pin QFP Pin Assignments
VREFH
VREFL
PTA0/ADC0
PTA1/ADC1
PTA2/ADC2
PTA3/ADC3
PTA4/ADC4
PTA5/ADC5
PTA6/ADC6
PTA7/ADC7
23
Frees
Data Sheet MC68HC908AP Family — Rev. 2.5
28 MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
General Description
Pin Assignment
nc...
I
cale Semiconductor,
Frees
PTD2/KBI2
PTD1/KBI1
PTD0/KBI0
PTB7/T2CH1
CGMXFC
PTB6/T2CH0
VREG
PTB5/T1CH1
VDD
OSC1
OSC2
VSS
PTB4/T1CH0
IRQ1
PTB3/RxD
RST
PTB2/TxD
PTB1/SCL
PTB0/SDA
PTC7/SCRxD
PTC6/SCTxD
Pins not available on 42-pin package Internal connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 22
PTC0/IRQ2
PTC1 Unconnected
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Unconnected
VDDA
VSSA
PTD3/KBI3
PTD4/KBI4
PTD5/KBI5
PTD6/KBI6
PTD7/KBI7
VREFH
VREFL
PTA0/ADC0
PTA1/ADC1
PTA2/ADC2
PTA3/ADC3
PTA4/ADC4
PTA5/ADC5
PTA6/ADC6
PTA7/ADC7
PTC2/MISO
PTC3/MOSI
PTC4/SS
PTC5/SPSCK
Figure 1-4. 42-Pin SDIP Pin Assignment
MC68HC908AP Family — Rev. 2.5 Data Sheet
MOTOROLA 29
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General Description
1.5 Pin Functions
Description of the pin functions are provided in Table 1-2.
Freescale Semiconductor, Inc.
Table 1-2. Pin Functions
nc...
I
cale Semiconductor,
Frees
PIN NAME PIN DESCRIPTION IN/OUT
V
V
V
V
V
V
V
DD
SS
DDA
SSA
REFH
REFL
REG
Power supply. In
Power supply ground. Out 0 V
Power supply for analog circuits. In
Power supply ground for analog circuits. Out
ADC input reference high. In
ADC input reference low. Out
Internal (2.5 V) regulator output.
Require external capacitors for decoupling.
Out
RST
IRQ1
OSC1 Crystal or RC oscillator input. In
OSC2
Reset input, active low; with internal pullup and schmitt
trigger input.
External IRQ1 pin; with internal pullup and schmitt trigger
input.
Used for mode entry selection. In
Crystal OSC option: crystal oscillator output; inverted
OSC1.
RC OSC option: bus clock output. Out
Internal OSC option: bus clock output. Out
In
In
Out
VOLTAGE
LEVEL
4.5 to 5.5
or
2.7 to 3.3
V
DD
V
SS
V
DDA
V
SSA
(1)
2.5V
V
DD
V
DD
V
to V
DD
V
V
V
V
TST
REG
REG
REG
REG
CGMXFC CGM external filter capacitor connection. In/Out Analog
PTA0/ADC0
:
PTA7/ADC7
Data Sheet MC68HC908AP Family — Rev. 2.5
30 MOTOROLA
8-bit general purpose I/O port. In/Out
Pins as ADC inputs, ADC0–ADC7. In
Each pin has high current sink for LED. Out
For More Information On This Product,
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V
V
V
DD
REFH
DD
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