MOTOROLA MC10H642FNR2, MC100H642FNR2 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

68030/040 PECL-TTL Clock Driver

The MC10H/100H642 generates the necessary clocks for the 68030,
68040 and similar microprocessors. It is guaranteed to meet the clock
specifications required by the 68030 and 68040 in terms of part–to–part
skew, within–part skew and also duty cycle skew.

The user has a choice of using either TTL or PECL (ECL referenced to
+5.0V) for the input clock. TTL clocks are typically used in present MPU
systems. However, as clock speeds increase to 50MHz and beyond, the
inherent superiority of ECL (particularly differential ECL) as a means of
clock signal distribution becomes increasingly evident. The H642 also
uses differential PECL internally to achieve its superior skew
characteristic.

The H642 includes divide–by–two and divide–by–four stages, both to
achieve the necessary duty cycle skew and to generate MPU clocks as
required. A typical 50MHz processor application would use an input clock
running at 100MHz, thus obtaining output clocks at 50MHz and 25MHz
(see Logic Diagram).

The 10H version is compatible with MECL 10H ECL logic levels,
while the 100H version is compatible with 100K levels (referenced to
+5.0V).

• Generates Clocks for 68030/040

• Meets 030/040 Skew Requirements

• TTL or PECL Input Clock

• Extra TTL and PECL Power/Ground Pins

• Asynchronous Reset

• Single +5.0V Supply

MC10H642

MC100H642

68030/040

PECL–TTL CLOCK

DRIVER

26

45

FN SUFFIX

PLASTIC PACKAGE

CASE 776–02

11

Function

Reset(R):

Select(SEL):

LOW on RESET forces all Q outputs LOW.
LOW selects the ECL input source (DE/DE).

HIGH selects the TTL input source (DT).

The H642 also contains circuitry to force a stable input state of the ECL differential input pair , should both sides be left open. In
this Case, the DE side of the input is pulled LOW, and DE

Power Up:

The device is designed to have positive edges of the ÷2 and ÷4 outputs synchronized at Power Up.

VT VT Q1 GT GT Q0 VT

25 24 23 22 21 20 19

Q2

26

GT

27

GT

28

Pinout: 28–Lead PLCC

567891011

Q5

GT GT Q6 Q7 VT SEL

VT

VT

Q3

1

2

3

4

goes HIGH.

(Top View)

18

V

BB

17

DE

16

DE

VE

15

R

14

GE

13

12

DTQ4

9/96

 Motorola, Inc. 1996

2–1

REV 4

MC10H642 MC100H642

LOGIC DIAGRAM

TTL Outputs

Q7

TTL/ECL Clock Inputs

V

BB

DE
DE

DT

SEL

TTL Control Inputs

R

MUX

÷4

÷2

Q6

Q5

Q4

Q3

Q2

Q1

Q0

PIN NAMES

Pin Symbol Description Pin Symbol Description

81
82
83
84
85
86
87
88
89

10
11
12
13
14

**Divide by 2

**Divide by 4

Q3
VT
VT
Q4
Q5
GT
GT
Q6
Q7
VT

SEL

DT
GE

R

Signal Output (TTL)**
TTL VCC (+5.0V)
TTL VCC (+5.0V)
Signal Output (TTL)**
Signal Output (TTL)**
TTL Ground (0V)
TTL Ground (0V)
Signal Output (TTL)**
Signal Output (TTL)**
TTL VCC (+5.0V)
Input Select (TTL)
TTL Signal Input
ECL Ground (0V)
Reset (TTL)

15
16
17
18
19
20
21
22
23
24
25
26
27
28

V

VE
DE
DE

BB

VT
Q0
GT
GT
Q1
VT
VT
Q2
GT
GT

ECL VCC (+5.0V)
ECL Signal Input (Non–Inverting)
ECL Signal Input (Inverting)
VBB Reference Output
TTL VCC (+5.0V)
Signal Output (TTL)*
TTL Ground (0V)
TTL Ground (0V)
Signal Output (TTL)*
TTL VCC (+5.0V)
TTL VCC (+5.0V)
Signal Output (TTL)**
TTL Ground (0V)
TTL Ground (0V)

MOTOROLA MECL Data

2–2

DL122 — Rev 6

MC10H642 MC100H642

AC CHARACTERISTICS (VT = VE = 5.0V ±5%)

TA = 0°C TA = 25°C TA = 85°C

Symbol Characteristic Min Max Min Max Min Max Unit Condition

t

PLH

tskpp Part–to–Part Skew 1.0 1.0 1.0 ns
tskwd* Within–Device Skew 0.5 0.5 0.5 ns
t

PLH

tskpp Part–to–Part Skew All

tskwd Within–Device Skew 1.0 1.0 1.0 ns CL = 25pF
t

PD

t

R

t

F

f

MAX

RPW Reset Pulse Width 1.5 1.5 1.5 ns
RRT Reset Recovery Time 1.25 1.25 1.25 ns

* Within–Device Skew defined as identical transactions on similar paths through a device.
** NOTE: MAX Frequency is 135MHz.

Propagation Delay
D to Output

Propagation Delay
D to Output

Propagation Delay
R to Output

Output Rise/Fall Time

0.8 V to 2.0 V

** Maximum Input Frequency 100 100 100 MHz CL = 25pF

Q2–Q7
C ECL
C TTL

Q0, Q1
C ECL
C TTL

Outputs

All
Outputs

All
Outputs

4.70

4.70

4.30

4.30

4.3 6.3 4.0 6.0 4.5 6.5 ns CL = 25pF

5.70

5.70

5.30

5.30

2.0 2.0 2.0 ns CL = 25pF

2.5

2.5

4.75

4.75

4.50

4.50

5.75

5.75

5.50

5.50

2.5

2.5

4.60

4.50

4.25

4.25

5.60

5.50

5.25

5.25

2.5

2.5

ns CL = 25pF

ns CL = 25pF

ns CL = 25pF

10H PECL CHARACTERISTICS (VT = VE = 5.0V ±5%)

TA = 0°C TA = 25°C TA = 85°C

Symbol Characteristic Min Max Min Max Min Max Unit Condition

I

IH

I

IL

V

IH

V

IL

V

BB

Input HIGH Current
Input LOW Current

* NOTE
Input HIGH Voltage

Input LOW Voltage
* NOTE
Output Reference Voltage 3.62 3.73 3.65 3.75 3.69 3.81 V

0.5

3.83

3.05

225

4.16

3.52

0.5

3.87

3.05

175

4.19

3.52

0.5

3.94

3.05

175 µA

4.28

3.555

V VEE = 5.0V

100H PECL CHARACTERISTICS (VT = VE = 5.0V ±5%)

TA = 0°C TA = 25°C TA = 85°C

Symbol Characteristic Min Max Min Max Min Max Unit Condition

I

IH

I

IL

V

IH

V

IL

V

BB

*NOTE: PECL LEVELS are referenced to VCC and will vary 1:1 with the power supply. The VALUES shown are for VCC = 5.0V.

Input HIGH Current
Input LOW Current

* NOTE
Input HIGH Voltage

Input LOW Voltage
* NOTE
Output Reference Voltage 3.620 3.740 3.620 3.740 3.620 3.740 V

0.5

3.835

3.190

225

4.120

3.525

0.5

3.835

3.190

175

4.120

3.525

0.5

3.835

3.190

175 µA

4.120

3.525

V VEE = 5.0V

DL122 — Rev 6

2–3 MOTOROLAMECL Data