The MC10EP31 is a D flip flop with set and reset. The device is pin
and functionally equivalent to the EL31 and LVEL31 devices. With
AC performance much faster than the EL31 and LVEL31 devices, the
EP31 is ideal for applications requiring the fastest AC performance
available. Both set and reset inputs are asynchronous, level triggered
signals. Data enters the master portion of the flip–flop when CLK is
low and is transferred to the slave, and thus the outputs, upon a
positive transition of the CLK.
• 275ps T ypical Propagation Delay
• High Bandwidth to 3 Ghz T ypical
• PECL mode: 3.0V to 5.5V V
• ECL mode: 0V V
• 75k
W
Internal Input Pulldown Resistors
with VEE = –3.0V to –5.5V
CC
• Q Output will default LOW with inputs open or at V
• ESD Protection: >4KV HBM, >200V MM
• Moisture Sensitivity Level 1, Indefinite Time Out of Drypack.
For Additional Information, See Application Note AND8003/D
• Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
• Transistor Count = 75 devices
SET
1
2
D
with VEE = 0V
CC
S
D
Flip Flop
EE
78Q
V
CC
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8
1
SO–8
D SUFFIX
CASE 751
MARKING DIAGRAM
8
HEP31
ALYW
1
*For additional information, see Application Note
AND8002/D
PIN DESCRIPTION
PIN
CLK
ResetECL Asynchronous Reset
Set
DECL Data Input
Q, QECL Data Outputs
VCCPositive Supply
VEENegative, 0 Supply
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
FUNCTION
ECL Clock Inputs
ECL Asynchronous Set
3
R
RESET
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram
Semiconductor Components Industries, LLC, 1999
January , 2000 – Rev. 3
45
6
QCLK
D
V
EE
1Publication Order Number:
L
H
X
X
X
Z = LOW to HIGH Transition
DevicePackageShipping
MC10EP31DSOIC98 Units/Rail
MC10EP31DR2SOIC2500 Tape & Reel
TRUTH TABLE
SET
ORDERING INFORMATION
RESET
L
L
H
L
H
L
L
L
H
H
CLK
Z
Z
X
X
X
MC10EP31/D
Q
L
H
H
L
UNDEF
MC10EP31
MAXIMUM RATINGS*
SymbolParameterValueUnit
V
EE
V
CC
V
I
V
I
I
out
T
A
T
stg
θ
JA
θ
JC
T
sol
* Maximum Ratings are those values beyond which damage to the device may occur.
DC CHARACTERISTICS, ECL/LVECL (VCC = 0V; VEE = –5.5V to –3.0V) (Note 3.)
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
1. VCC = 0V, VEE = V
2. All loading with 50 ohms to VCC–2.0 volts.
3. Input and output parameters vary 1:1 with VCC.
Power Supply Current
(Note 1.)
Output HIGH Voltage
(Note 2.)
Output LOW Voltage
(Note 2.)
Input HIGH Voltage
Single Ended
Input LOW Voltage
Single Ended
Input HIGH Current150150150µA
Input LOW Current0.50.50.5µA
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
Power Supply (VCC = 0V)–6.0 to 0VDC
Power Supply (VEE = 0V)6.0 to 0VDC
Input Voltage (VCC = 0V, VI not more negative than VEE)–6.0 to 0VDC
Input Voltage (VEE = 0V, VI not more positive than VCC)6.0 to 0VDC
Output CurrentContinuous
Operating Temperature Range–40 to +85°C
Storage Temperature–65 to +150°C
Thermal Resistance (Junction–to–Ambient)Still Air
Thermal Resistance (Junction–to–Case)41 to 44 ± 5%°C/W
Solder Temperature (<2 to 3 Seconds: 245°C desired)265°C
11.Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
Maximum Toggle
Frequency (Note 10.)
,
Propagation Delay to
Output Differential
Set/Reset Recovery225150200140185130ps
Setup Time
Hold Time
Duty Cycle Skew (Note 11.)
Skew Part–to–Part
Minimum Pulse Width
Cycle–to–Cycle JitterTBDTBDTBDps
Output Rise/Fall Times
(20% – 80%) Q, Q
guaranteed for functionality only. VOL and VOH levels are guaranteed at DC only.
max
CLK–>Q, Q
S, R–>Q, Q
CLK, SET, RESET
175
200
150
150
550450550450550450
501201806013020070150220
3.03.03.0GHz
250
280
50
50
TBD
TBD
325
360
200
250
150
150
275
330
50
50
TBD
TBD
350
420
0V)
250
325
150
150
320
400
50
50
TBD
TBD
ps
400
475
ps
ps
ps
ps
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MC10EP31
P ACKAGE DIMENSIONS
SO–8
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751–06
ISSUE T
A
C
E
B
A1
D
58
0.25MB
1
H
4
e
M
h
X 45
_
q
C
A
SEATING
PLANE
0.10
L
B
SS
A0.25MCB
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETER.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
MILLIMETERS
DIM MINMAX
A1.351.75
A10.100.25
B0.350.49
C0.190.25
D4.805.00
E
3.804.00
1.27 BSCe
H5.806.20
h
0.250.50
L0.401.25
0 7
q
__
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Notes
MC10EP31
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6
Notes
MC10EP31
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MC10EP31
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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MC10EP31/D
8
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