Motorola MC10105P, MC10105FN, MC10105FNR2, MC10105L Datasheet
SEMICONDUCTOR TECHNICAL DATA
The MC10105 is a triple 2–3–2 input OR/NOR gate.
PD= 30 mW typ/gate (No Load)
tpd= 2.0 ns typ
tr, tf= 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
43
5
9
10
11
13 14
12
V
= PIN 1
CC1
V
= PIN 16
CC2
VEE= PIN 8
2
6
7
15
CERAMIC PACKAGE
PLASTIC PACKAGE
DIP
PIN ASSIGNMENT
V
A
OUT
A
OUT
B
OUT
B
OUT
CC1
A
IN
A
IN
V
EE
1
2
3
4
5
6
7
8
L SUFFIX
CASE 620–10
P SUFFIX
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
16
15
14
13
12
11
10
V
C
C
C
C
B
B
B
9
CC2
OUT
OUT
IN
IN
IN
IN
IN
3/93
Motorola, Inc. 1996
3–21
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
T ables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
REV 5
MC10105
Under
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Characteristic Symbol
Power Supply Drain Current I
Input Current I
Output Voltage Logic 1 V
Output Voltage Logic 0 V
Threshold Voltage Logic 1 V
Threshold Voltage Logic 0 V
Switching Times (50Ω Load) ns
Propagation Delay t
Rise Time (20 to 80%) t
Fall Time (20 to 80%) t
inH
I
inL
OH
OL
OHA
OLA
4+3–
t
4–3+
t
4+2+
t
4–2–
3+
t
2+
3–
t
2–
E
Under
Test
8 23 17 21 23 mAdc
4 425 265 265 µAdc
4 0.5 0.5 0.3 µAdc
3
2
3
2
3
2
3
2
3
3
2
2
3
2
3
2
–30°C +25°C +85°C
Min Max Min Typ Max Min Max
–1.060
–1.060
–1.890
–1.890
–1.080
–1.080
1.0
1.0
1.0
1.0
1.1
1.1
1.1
1.1
–0.890
–0.890
–1.675
–1.675
–1.655
–1.655
3.1
3.1
3.1
3.1
3.6
3.6
3.6
3.6
–0.960
–0.960
–1.850
–1.850
–0.980
–0.980
1.0
1.0
1.0
1.0
1.1
1.1
1.1
1.1
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
–0.810
–0.810
–1.650
–1.650
–1.630
–1.630
2.9
2.9
2.9
2.9
3.3
3.3
3.3
3.3
–0.890
–0.890
–1.825
–1.825
–0.910
–0.910
1.0
1.0
1.0
1.0
1.1
1.1
1.1
1.1
–0.700
–0.700
–1.615
–1.615
–1.595
–1.595
3.3
3.3
3.3
3.3
3.7
3.7
3.7
3.7
Unit
Vdc
Vdc
Vdc
Vdc
MOTOROLA MECL Data
3–22
DL122 — Rev 6
Loading...