Motorola DigitalDNA ColdFire MCF5272 User Manual

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MCF5272 ColdFire

Integrated Microprocessor

User’s Manual

MCF5272UM/D Rev. 0, 02/2001

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ColdFire is a registered trademark and DigitalDNA is a trademark of Motorola, Inc.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

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Overview

ColdFire Core

Hardware Multiply/Accumulate (MAC) Unit

Local Memory

Debug Support

System Integration Module (

SIM)

Interrupt Controller

Chip-Select Module

SDRAM Controller

DMA Controller Module

Ethernet Module

Universal Serial Bus (USB)

Physical Layer Interface Controller (PLIC)

Queued Serial Peripheral Interface (QSPI) Module

Timer Module

UART Modules

2 3 4 5 6 7 8

9 10 11 12 13 14

General-Purpose I/O Module

Pulse-Width Modulation (PWM) Module

Signal Descriptions

Bus Operation

IEEE 1149.1 Test Access Port (JTAG)

Mechanical Data

Electrical Characteristics

Appendix A: List of Memory Maps

Appendix B: Buffering and Impedence Matching

Index

17 18 19 20 21 22 23

A B

IND

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Overview

2 3 4 5 6 7 8

9 10 11 12 13 14

ColdFire Core Hardware Multiply/Accumulate (MAC) Unit Local Memory Debug Support System Integration Module (

SIM) Interrupt Controller Chip-Select Module SDRAM Controller DMA Controller Module Ethernet Module Universal Serial Bus (USB) Physical Layer Interface Controller (PLIC) Queued Serial Peripheral Interface (QSPI) Module Timer Module UART Modules

17 18 19 20 21 22 23

A B

IND

General-Purpose I/O Module Pulse-Width Modulation (PWM) Module Signal Descriptions Bus Operation IEEE 1149.1 Test Access Port (JTAG) Mechanical Data Electrical Characteristics Appendix A: List of Memory Maps Appendix B: Buffering and Impedence Matching Index

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About This Book

Chapter 1

Overview

1.1 MCF5272 Key Features...................................................................................... 1-1

1.2 MCF5272 Architecture....................................................................................... 1-4

1.2.1 Version 2 ColdFire Core................................................................................. 1-4

1.2.2 System Integration Module (SIM).................................................................. 1-5

1.2.2.1 External Bus Interface ................................................................................ 1-5

1.2.2.2 Chip Select and Wait State Generation ...................................................... 1-5

1.2.2.3 System Configuration and Protection......................................................... 1-5

1.2.2.4 Power Management .................................................................................... 1-6

1.2.2.5 Parallel Input/Output Ports ......................................................................... 1-6

1.2.2.6 Interrupt Inputs ........................................................................................... 1-6

1.2.3 UART Module................................................................................................ 1-6

1.2.4 Timer Module................................................................................................. 1-7

1.2.5 Test Access Port.............................................................................................. 1-7

1.3 System Design ................................................................................................... 1-7

1.3.1 System Bus Configuration.............................................................................. 1-7

1.4 MCF5272-Specific Features............................................................................... 1-8

1.4.1 Physical Layer Interface Controller (PLIC).................................................... 1-8

1.4.2 Pulse-Width Modulation (PWM) Unit ........................................................... 1-8

1.4.3 Queued Serial Peripheral Interface (QSPI)..................................................... 1-8

1.4.4 Universal Serial Bus (USB) Module .............................................................. 1-9

Chapter 2

ColdFire Core

2.1 Features and Enhancements.............................................................................. 2-11

2.1.1 Decoupled Pipelines ...................................................................................... 2-11

2.1.1.1 Instruction Fetch Pipeline (IFP)................................................................ 2-12

2.1.1.2 Operand Execution Pipeline (OEP).......................................................... 2-13

2.1.1.2.1 Illegal Opcode Handling....................................................................... 2-13

2.1.1.2.2 Hardware Multiply/Accumulate (MAC) Unit...................................... 2-13

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2.1.1.2.3 Hardware Divide Unit .......................................................................... 2-14

2.1.2 Debug Module Enhancements...................................................................... 2-14

2.2 Programming Model......................................................................................... 2-15

2.2.1 User Programming Model ............................................................................ 2-16

2.2.1.1 Data Registers (D0–D7) ........................................................................... 2-16

2.2.1.2 Address Registers (A0–A6)...................................................................... 2-16

2.2.1.3 Stack Pointer (A7, SP).............................................................................. 2-17

2.2.1.4 Program Counter (PC).............................................................................. 2-17

2.2.1.5 Condition Code Register (CCR)............................................................... 2-17

2.2.1.6 MAC Programming Model....................................................................... 2-18

2.2.2 Supervisor Programming Model................................................................... 2-18

2.2.2.1 Status Register (SR).................................................................................. 2-18

2.2.2.2 Vector Base Register (VBR) .................................................................... 2-19

2.2.2.3 Cache Control Register (CACR) .............................................................. 2-19

2.2.2.4 Access Control Registers (ACR0–ACR1)................................................ 2-20

2.2.2.5 ROM Base Address Register (ROMBAR)............................................... 2-20

2.2.2.6 RAM Base Address Register (RAMBAR)............................................... 2-20

2.2.2.7 Module Base Address Register (MBAR) ................................................. 2-20

2.3 Integer Data Formats......................................................................................... 2-20

2.4 Organization of Data in Registers..................................................................... 2-20

2.4.1 Organization of Integer Data Formats in Registers...................................... 2-21

2.4.2 Organization of Integer Data Formats in Memory ....................................... 2-22

2.5 Addressing Mode Summary ............................................................................. 2-22

2.6 Instruction Set Summary................................................................................... 2-23

2.6.1 Instruction Set Summary .............................................................................. 2-26

2.7 Instruction Timing ............................................................................................ 2-29

2.7.1 MOVE Instruction Execution Times............................................................ 2-30

2.7.2 Execution Timings—One-Operand Instructions.......................................... 2-32

2.7.3 Execution Timings—Two-Operand Instructions.......................................... 2-33

2.7.4 Miscellaneous Instruction Execution Times................................................. 2-34

2.7.5 Branch Instruction Execution Times ............................................................ 2-35

2.8 Exception Processing Overview....................................................................... 2-36

2.8.1 Exception Stack Frame Definition................................................................ 2-38

2.8.2 Processor Exceptions.................................................................................... 2-39

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Chapter 3

Hardware Multiply/Accumulate (MAC) Unit

3.1 Overview............................................................................................................. 3-1

3.1.1 MAC Programming Model............................................................................. 3-2

3.1.2 General Operation........................................................................................... 3-3

3.1.3 MAC Instruction Set Summary ...................................................................... 3-4

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3.1.4 Data Representation........................................................................................ 3-5

3.2 MAC Instruction Execution Timings.................................................................. 3-5

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Chapter 4

Local Memory

4.1 Interactions between Local Memory Modules ................................................... 4-1

4.2 Local Memory Registers..................................................................................... 4-2

4.3 SRAM Overview ................................................................................................ 4-2

4.3.1 SRAM Operation............................................................................................ 4-2

4.3.2 SRAM Programming Model........................................................................... 4-2

4.3.2.1 SRAM Base Address Register (RAMBAR)............................................... 4-3

4.3.2.2 SRAM Initialization.................................................................................... 4-4

4.3.2.3 Programming RAMBAR for Power Management ..................................... 4-5

4.4 ROM Overview................................................................................................... 4-5

4.4.1 ROM Operation .............................................................................................. 4-5

4.4.2 ROM Programming Model............................................................................. 4-6

4.4.2.1 ROM Base Address Register (ROMBAR)................................................. 4-6

4.4.2.2 Programming ROMBAR for Power Management ..................................... 4-7

4.5 Instruction Cache Overview ............................................................................... 4-7

4.5.1 Instruction Cache Physical Organization........................................................ 4-7

4.5.2 Instruction Cache Operation........................................................................... 4-9

4.5.2.1 Interaction with Other Modules.................................................................. 4-9

4.5.2.2 Cache Coherency and Invalidation............................................................. 4-9

4.5.2.3 Caching Modes........................................................................................... 4-9

4.5.2.3.1 Cacheable Accesses.............................................................................. 4-10

4.5.2.3.2 Cache-Inhibited Accesses..................................................................... 4-10

4.5.2.4 Reset ......................................................................................................... 4-11

4.5.2.5 Cache Miss Fetch Algorithm/Line Fills ................................................... 4-11

4.5.3 Instruction Cache Programming Model........................................................ 4-12

4.5.3.1 Cache Control Register (CACR) .............................................................. 4-13

4.5.3.2 Access Control Registers (ACR0 and ACR1).......................................... 4-15

Chapter 5

Debug Support

5.1 Overview............................................................................................................. 5-1

5.2 Signal Description............................................................................................... 5-2

5.3 Real-Time Trace Support.................................................................................... 5-2

5.3.1 Begin Execution of Taken Branch (PST = 0x5)............................................. 5-4

5.4 Programming Model........................................................................................... 5-5

5.4.1 Revision A Shared Debug Resources............................................................. 5-7

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5.4.2 Address Attribute Trigger Register (AATR).................................................. 5-7

5.4.3 Address Breakpoint Registers (ABLR, ABHR)............................................. 5-9

5.4.4 Configuration/Status Register (CSR).............................................................. 5-9

5.4.5 Data Breakpoint/Mask Registers (DBR, DBMR)......................................... 5-11

5.4.6 Program Counter Breakpoint/Mask Registers (PBR, PBMR)...................... 5-12

5.4.7 Trigger Definition Register (TDR)............................................................... 5-13

5.5 Background Debug Mode (BDM).................................................................... 5-15

5.5.1 CPU Halt....................................................................................................... 5-16

5.5.2 BDM Serial Interface.................................................................................... 5-17

5.5.2.1 Receive Packet Format ............................................................................. 5-18

5.5.2.2 Transmit Packet Format............................................................................ 5-18

5.5.3 BDM Command Set...................................................................................... 5-19

5.5.3.1 ColdFire BDM Command Format............................................................ 5-20

5.5.3.1.1 Extension Words as Required............................................................... 5-20

5.5.3.2 Command Sequence Diagrams................................................................. 5-21

5.5.3.3 Command Set Descriptions ...................................................................... 5-22

5.5.3.3.1 Read A/D Register (rareg/rdreg) .......................................................... 5-23

5.5.3.3.2 Write A/D Register (wareg/wdreg) ...................................................... 5-24

5.5.3.3.3 Read Memory Location (read).............................................................. 5-25

5.5.3.3.4 Write Memory Location (write) ........................................................... 5-26

5.5.3.3.5 Dump Memory Block (dump).............................................................. 5-28

5.5.3.3.6 Fill Memory Block (fill)....................................................................... 5-30

5.5.3.3.7 Resume Execution (go) ........................................................................ 5-32

5.5.3.3.8 No Operation (nop)............................................................................... 5-33

5.5.3.3.9 Read Control Register (rcreg)............................................................... 5-34

5.5.3.3.10 Write Control Register (wcreg) ............................................................ 5-35

5.5.3.3.11 Read Debug Module Register (rdmreg) ............................................... 5-36

5.5.3.3.12 Write Debug Module Register (wdmreg)............................................. 5-37

5.6 Real-Time Debug Support................................................................................ 5-37

5.6.1 Theory of Operation...................................................................................... 5-38

5.6.1.1 Emulator Mode......................................................................................... 5-39

5.6.2 Concurrent BDM and Processor Operation.................................................. 5-39

5.7 Processor Status, DDATA Definition............................................................... 5-40

5.7.1 User Instruction Set ...................................................................................... 5-40

5.7.2 Supervisor Instruction Set............................................................................. 5-44

5.8 Motorola-Recommended BDM Pinout............................................................. 5-45

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Chapter 6

System Integration Module (SIM)

6.1 Features............................................................................................................... 6-1

6.2 Programming Model........................................................................................... 6-3

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6.2.1 SIM Register Memory Map............................................................................ 6-3

6.2.2 Module Base Address Register (MBAR) ....................................................... 6-4

6.2.3 System Configuration Register (SCR)............................................................ 6-5

6.2.4 System Protection Register (SPR).................................................................. 6-6

6.2.5 Power Management Register (PMR).............................................................. 6-7

6.2.6 Activate Low-Power Register (ALPR)......................................................... 6-10

6.2.7 Device Identification Register (DIR)............................................................ 6-11

6.2.8 Software Watchdog Timer............................................................................ 6-12

6.2.8.1 Watchdog Reset Reference Register (WRRR)......................................... 6-13

6.2.8.2 Watchdog Interrupt Reference Register (WIRR) ..................................... 6-13

6.2.8.3 Watchdog Counter Register (WCR)......................................................... 6-14

6.2.8.4 Watchdog Event Register (WER)............................................................. 6-14

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Chapter 7

Interrupt Controller

7.1 Overview............................................................................................................. 7-1

7.2 Interrupt Controller Registers............................................................................. 7-2

7.2.1 Interrupt Controller Registers......................................................................... 7-3

7.2.2 Interrupt Control Registers (ICR1–ICR4) ...................................................... 7-4

7.2.2.1 Interrupt Control Register 1 (ICR1) ........................................................... 7-4

7.2.2.2 Interrupt Control Register 2 (ICR2) ........................................................... 7-5

7.2.2.3 Interrupt Control Register 3 (ICR3) ........................................................... 7-5

7.2.2.4 Interrupt Control Register 4 (ICR4) ........................................................... 7-6

7.2.3 Interrupt Source Register (ISR)...................................................................... 7-6

7.2.4 Programmable Interrupt Transition Register (PITR)...................................... 7-7

7.2.5 Programmable Interrupt Wakeup Register (PIWR)........................................ 7-8

7.2.6 Programmable Interrupt Vector Register (PIVR)........................................... 7-9

Chapter 8

Chip Select Module

8.1 Overview............................................................................................................. 8-1

8.1.1 Features........................................................................................................... 8-1

8.1.2 Chip Select Usage........................................................................................... 8-1

8.1.3 Boot CS0 Operation........................................................................................ 8-2

8.2 Chip Select Registers.......................................................................................... 8-2

8.2.1 Chip Select Base Registers (CSBR0–CSBR7)............................................... 8-3

8.2.2 Chip Select Option Registers (CSOR0–CSOR7) ........................................... 8-5

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Chapter 9

SDRAM Controller

9.1 Overview............................................................................................................. 9-1

9.2 SDRAM Controller Signals................................................................................ 9-1

9.3 Interface to SDRAM Devices............................................................................. 9-5

9.4 SDRAM Banks, Page Hits, and Page Misses..................................................... 9-6

9.5 SDRAM Registers .............................................................................................. 9-7

9.5.1 SDRAM Configuration Register (SDCR) ...................................................... 9-7

9.5.2 SDRAM Timing Register (SDTR)................................................................. 9-9

9.6 Auto Initialization............................................................................................. 9-10

9.7 Power-Down and Self-Refresh......................................................................... 9-10

9.8 Performance...................................................................................................... 9-11

9.9 Solving Timing Issues with SDCR[INV]......................................................... 9-13

9.10 SDRAM Interface............................................................................................. 9-16

9.10.1 SDRAM Read Accesses ............................................................................... 9-17

9.10.2 SDRAM Write Accesses .............................................................................. 9-19

9.10.3 SDRAM Refresh Timing.............................................................................. 9-21

Chapter 10

DMA Controller

10.1 DMA Data Transfer Types ............................................................................... 10-1

10.2 DMA Address Modes....................................................................................... 10-2

10.3 DMA Controller Registers................................................................................ 10-2

10.3.1 DMA Mode Register (DMR)........................................................................ 10-2

10.3.2 DMA Interrupt Register (DIR)..................................................................... 10-4

10.3.3 DMA Source Address Register (DSAR)...................................................... 10-5

10.3.4 DMA Destination Address Register (DDAR).............................................. 10-6

10.3.5 DMA Byte Count Register (DBCR)............................................................. 10-6

Chapter 11

Ethernet Module

11.1 Overview........................................................................................................... 11-1

11.1.1 Features......................................................................................................... 11-1

11.2 Module Operation............................................................................................. 11-2

11.3 Transceiver Connection.................................................................................... 11-3

11.4 FEC Frame Transmission ................................................................................. 11-4

11.4.1 FEC Frame Reception................................................................................... 11-5

11.4.2 CAM Interface.............................................................................................. 11-6

11.4.3 Ethernet Address Recognition...................................................................... 11-7

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11.4.4 Hash Table Algorithm .................................................................................. 11-8

11.4.5 Interpacket Gap Time ................................................................................... 11-9

11.4.6 Collision Handling........................................................................................ 11-9

11.4.7 Internal and External Loopback.................................................................... 11-9

11.4.8 Ethernet Error-Handling Procedure............................................................ 11-10

11.4.8.1 Transmission Errors................................................................................ 11-10

11.4.8.2 Reception Errors ..................................................................................... 11-10

11.5 Programming Model....................................................................................... 11-11

11.5.1 Ethernet Control Register (ECNTRL)........................................................ 11-12

11.5.2 Interrupt Event Register (I_EVENT).......................................................... 11-13

11.5.3 Interrupt Mask Register (I_MASK)............................................................ 11-14

11.5.4 Interrupt Vector Status Register (IVEC) .................................................... 11-14

11.5.5 Receive Descriptor Active Register (R_DES_ACTIVE)........................... 11-15

11.5.6 Transmit Descriptor Active Register (X_DES_ACTIVE) ......................... 11-16

11.5.7 MII Management Frame Register (MII_DATA)........................................ 11-17

11.5.8 MII Speed Control Register (MII_SPEED)................................................ 11-19

11.5.9 FIFO Receive Bound Register (R_BOUND) ............................................. 11-20

11.5.10 FIFO Receive Start Register (R_FSTART)................................................ 11-20

11.5.11 Transmit FIFO Watermark (X_WMRK).................................................... 11-21

11.5.12 FIFO Transmit Start Register (X_FSTART).............................................. 11-22

11.5.13 Receive Control Register (R_CNTRL)....................................................... 11-23

11.5.14 Maximum Frame Length Register (MAX_FRM_LEN)............................. 11-24

11.5.15 Transmit Control Register (X_CNTRL)..................................................... 11-25

11.5.16 RAM Perfect Match Address Low (ADDR_LOW)................................... 11-26

11.5.16.1 RAM Perfect Match Address High (ADDR_HIGH).............................. 11-26

11.5.17 Hash Table High (HASH_TABLE_HIGH)................................................ 11-27

11.5.18 Hash Table Low (HASH_TABLE_LOW)................................................. 11-28

11.5.19 Pointer-to-Receive Descriptor Ring (R_DES_START)............................. 11-28

11.5.20 Pointer-to-Transmit Descriptor Ring (X_DES_START)........................... 11-29

11.5.21 Receive Buffer Size Register (R_BUFF_SIZE)......................................... 11-30

11.5.22 Initialization Sequence................................................................................ 11-30

11.5.22.1 Hardware Initialization ........................................................................... 11-31

11.5.23 User Initialization (Prior to Asserting ETHER_EN).................................. 11-31

11.5.24 FEC Initialization........................................................................................ 11-32

11.5.24.1 User Initialization (after setting ETHER_EN) ....................................... 11-32

11.6 Buffer Descriptors........................................................................................... 11-33

11.6.1 FEC Buffer Descriptor Tables.................................................................... 11-33

11.6.1.1 Ethernet Receive Buffer Descriptor (RxBD).......................................... 11-34

11.6.1.2 Ethernet Transmit Buffer Descriptor...................................................... 11-36

11.7 Differences between MCF5272 FEC and MPC860T FEC............................. 11-38

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Chapter 12

Universal Serial Bus (USB)

12.1 Introduction....................................................................................................... 12-1

12.2 Module Operation............................................................................................. 12-3

12.2.1 USB Module Architecture............................................................................ 12-3

12.2.1.1 USB Transceiver Interface ....................................................................... 12-4

12.2.1.2 Clock Generator........................................................................................ 12-4

12.2.1.3 USB Control Logic................................................................................... 12-4

12.2.1.4 Endpoint Controllers................................................................................. 12-5

12.2.1.5 USB Request Processor ............................................................................ 12-5

12.3 Register Description and Programming Model ................................................ 12-7

12.3.1 USB Memory Map........................................................................................ 12-7

12.3.2 Register Descriptions.................................................................................... 12-9

12.3.2.1 USB Frame Number Register (FNR) ....................................................... 12-9

12.3.2.2 USB Frame Number Match Register (FNMR)......................................... 12-9

12.3.2.3 USB Real-Time Frame Monitor Register (RFMR)................................ 12-10

12.3.2.4 USB Real-Time Frame Monitor Match Register (RFMMR) ................. 12-10

12.3.2.5 USB Function Address Register (FAR) ................................................. 12-11

12.3.2.6 USB Alternate Settings Register (ASR)................................................. 12-11

12.3.2.7 USB Device Request Data 1 and 2 Registers (DRR1/ 2) ....................... 12-12

12.3.2.8 USB Specification Number Register (SPECR) ...................................... 12-13

12.3.2.9 USB Endpoint 0 Status Register (EP0SR).............................................. 12-13

12.3.2.10 USB Endpoint 0 IN Configuration Register (IEP0CFG) ....................... 12-14

12.3.2.11 USB Endpoint 0 OUT Configuration Register (OEP0CFG).................. 12-15

12.3.2.12 USB Endpoint 1–7 Configuration Register (EPnCFG).......................... 12-16

12.3.2.13 USB Endpoint 0 Control Register (EP0CTL) ........................................ 12-16

12.3.2.14 USB Endpoint 1–7 Control Register (EPnCFG) .................................... 12-19

12.3.2.15 USB Endpoint 0 Interrupt Mask (E0PIMR) and General/Endpoint 0

Interrupt Registers (EP0ISR) ..............................................................12-21

12.3.2.16 USB Endpoints 1–7 Status / Interrupt Registers (EPnISR).................... 12-24

12.3.2.17 USB Endpoint 1–7 Interrupt Mask Registers (EPnIMR) ....................... 12-25

12.3.2.18 USB Endpoint 0–7 Data Registers (EPnDAT)....................................... 12-26

12.3.2.19 USB Endpoint 0–7 Data Present Registers (EPnDPR)........................... 12-27

12.3.3 Configuration RAM.................................................................................... 12-27

12.3.3.1 Configuration RAM Content .................................................................. 12-27

12.3.3.2 USB Device Configuration Example...................................................... 12-28

12.3.4 USB Module Access Times........................................................................ 12-29

12.3.4.1 Registers ................................................................................................. 12-29

12.3.4.2 Endpoint FIFOs ...................................................................................... 12-29

12.3.4.3 Configuration RAM................................................................................ 12-29

12.4 Software Architecture and Application Notes................................................ 12-30

12.4.1 USB Module Initialization.......................................................................... 12-30

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12.4.2 USB Configuration and Interface Changes ................................................ 12-30

12.4.3 FIFO Configuration .................................................................................... 12-30

12.4.4 Data Flow.................................................................................................... 12-31

12.4.4.1 Control, Bulk, and Interrupt Endpoints .................................................. 12-32

12.4.4.1.1 IN Endpoints....................................................................................... 12-32

12.4.4.1.2 OUT Endpoints................................................................................... 12-32

12.4.4.2 Isochronous Endpoints............................................................................ 12-33

12.4.4.2.1 IN Endpoints....................................................................................... 12-33

12.4.4.2.2 OUT Endpoints................................................................................... 12-33

12.4.5 Class- and Vendor-Specific Request Operation ......................................... 12-34

12.4.6 remote wakeup and resume Operation........................................................ 12-34

12.4.7 Endpoint Halt Feature................................................................................. 12-35

12.5 Line Interface.................................................................................................. 12-35

12.5.1 Attachment Detection................................................................................. 12-35

12.5.2 PCB Layout Recommendations.................................................................. 12-36

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Chapter 13

Physical Layer Interface Controller (PLIC)

13.1 Introduction....................................................................................................... 13-1

13.2 GCI/IDL Block ................................................................................................. 13-3

13.2.1 GCI/IDL B- and D-Channel Receive Data Registers................................... 13-4

13.2.2 GCI/IDL B- and D-Channel Transmit Data Registers.................................. 13-5

13.2.3 GCI/IDL B- and D-Channel Bit Alignment ................................................. 13-6

13.2.3.1 B-Channel Unencoded Data ..................................................................... 13-6

13.2.3.2 B-Channel HDLC Encoded Data.............................................................. 13-7

13.2.3.3 D-Channel HDLC Encoded Data ............................................................. 13-7

13.2.3.4 D-Channel Unencoded Data..................................................................... 13-8

13.2.3.5 GCI/IDL D-Channel Contention ............................................................. 13-9

13.2.4 GCI/IDL Looping Modes ............................................................................. 13-9

13.2.4.1 Automatic Echo Mode............................................................................ 13-10

13.2.4.2 Local Loopback Mode............................................................................ 13-10

13.2.4.3 Remote Loopback Mode......................................................................... 13-10

13.2.5 GCI/IDL Interrupts..................................................................................... 13-11

13.2.5.1 GCI/IDL Periodic Frame Interrupt ......................................................... 13-11

13.2.5.2 GCI Aperiodic Status Interrupt.............................................................. 13-11

13.2.5.3 Interrupt Control ..................................................................................... 13-12

13.3 PLIC Timing Generator.................................................................................. 13-12

13.3.1 Clock Synthesis........................................................................................... 13-12

13.3.2 Super Frame Sync Generation.................................................................... 13-13

13.3.3 Frame Sync Synthesis................................................................................. 13-14

13.4 PLIC Register Memory Map .......................................................................... 13-15

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13.5 PLIC Registers................................................................................................ 13-16

13.5.1 B1 Data Receive Registers (P0B1RR–P3B1RR) ....................................... 13-16

13.5.2 B2 Data Receive Registers (P0B2RR–P3B2RR) ....................................... 13-17

13.5.3 D Data Receive Registers (P3DRR–P0DRR)............................................. 13-17

13.5.4 B1 Data Transmit Registers (P3B1TR–P0B1TR)...................................... 13-18

13.5.5 B2 Data Transmit Registers (P3B2TR–P0B2TR)...................................... 13-19

13.5.6 D Data Transmit Registers (P3DTR–P0DTR)............................................ 13-19

13.5.7 Port Configuration Registers (P0CR–P3CR).............................................. 13-20

13.5.8 Loopback Control Register (PLCR)........................................................... 13-21

13.5.9 Interrupt Configuration Registers (P0ICR–P3ICR).................................... 13-22

13.5.10 Periodic Status Registers (P0PSR–P3PSR)................................................ 13-24

13.5.11 Aperiodic Status Register (PASR).............................................................. 13-25

13.5.12 GCI Monitor Channel Receive Registers (P3GMR–P0GMR)................... 13-26

13.5.13 GCI Monitor Channel Transmit Registers (P0GMT–P3GMT).................. 13-27

13.5.14 GCI Monitor Channel Transmit Abort Register (PGMTA) ....................... 13-28

13.5.15 GCI Monitor Channel Transmit Status Register (PGMTS)........................ 13-28

13.5.16 GCI C/I Channel Receive Registers (P0GCIR–P3GCIR).......................... 13-29

13.5.17 GCI C/I Channel Transmit Registers (P3GCIT–P0GCIT)......................... 13-31

13.5.18 GCI C/I Channel Transmit Status Register (PGCITSR) ............................ 13-31

13.5.19 D-Channel Status Register (PDCSR) ......................................................... 13-32

13.5.20 D-Channel Request Register (PDRQR)...................................................... 13-33

13.5.21 Sync Delay Registers (P0SDR–P3SDR) .................................................... 13-34

13.5.22 Clock Select Register (PCSR) .................................................................... 13-34

13.6 Application Examples..................................................................................... 13-35

13.6.1 Introduction................................................................................................. 13-35

13.6.2 PLIC Initialization ...................................................................................... 13-36

13.6.2.1 Port Configuration Example................................................................... 13-36

13.6.2.2 Interrupt Configuration Example............................................................ 13-37

13.6.3 Example 1: ISDN SOHO PBX with Ports 0, 1, 2, and 3............................ 13-38

13.6.4 Example 2: ISDN SOHO PBX with Ports 1, 2, and 3................................ 13-41

13.6.5 Example 3: Two-Line Remote Access with Ports 0 and 1......................... 13-42

Title

Page

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Chapter 14

Queued Serial Peripheral Interface (QSPI) Module

14.1 Overview........................................................................................................... 14-1

14.2 Features............................................................................................................. 14-1

14.3 Module Description .......................................................................................... 14-1

14.3.1 Interface and Pins.......................................................................................... 14-2

14.3.2 Internal Bus Interface.................................................................................... 14-3

14.4 Operation........................................................................................................... 14-3

14.4.1 QSPI RAM.................................................................................................... 14-4

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14.4.1.1 Receive RAM ........................................................................................... 14-5

14.4.1.2 Transmit RAM.......................................................................................... 14-6

14.4.1.3 Command RAM........................................................................................ 14-6

14.4.2 Baud Rate Selection...................................................................................... 14-6

14.4.3 Transfer Delays............................................................................................. 14-7

14.4.4 Transfer Length............................................................................................. 14-8

14.4.5 Data Transfer ................................................................................................ 14-8

14.5 Programming Model......................................................................................... 14-9

14.5.1 QSPI Mode Register (QMR) ........................................................................ 14-9

14.5.2 QSPI Delay Register (QDLYR) ................................................................. 14-11

14.5.3 QSPI Wrap Register (QWR)....................................................................... 14-12

14.5.4 QSPI Interrupt Register (QIR).................................................................... 14-12

14.5.5 QSPI Address Register (QAR)................................................................... 14-14

14.5.6 QSPI Data Register (QDR)......................................................................... 14-14

14.5.7 Command RAM Registers (QCR0–QCR15).............................................. 14-14

14.5.8 Programming Example............................................................................... 14-15

Title

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Chapter 15

Timer Module

15.1 Overview........................................................................................................... 15-1

15.2 Timer Operation................................................................................................ 15-2

15.3 General-Purpose Timer Registers..................................................................... 15-3

15.3.1 Timer Mode Registers (TMR0–TMR3) ....................................................... 15-3

15.3.2 Timer Reference Registers (TRR0–TRR3) .................................................. 15-4

15.3.3 Timer Capture Registers (TCR0–TCR3)...................................................... 15-5

15.3.4 Timer Counters (TCN0–TCN3).................................................................... 15-5

15.3.5 Timer Event Registers (TER0–TER3).......................................................... 15-5

Chapter 16

UART Modules

16.1 Overview........................................................................................................... 16-1

16.2 Serial Module Overview................................................................................... 16-2

16.3 Register Descriptions........................................................................................ 16-3

16.3.1 UART Mode Registers 1 (UMR1n).............................................................. 16-5

16.3.2 UART Mode Register 2 (UMR2n)............................................................... 16-6

16.3.3 UART Status Registers (USRn) ................................................................... 16-7

16.3.4 UART Clock-Select Registers (UCSRn)...................................................... 16-8

16.3.5 UART Command Registers (UCRn)............................................................ 16-9

16.3.6 UART Receiver Buffers (URBn) ............................................................... 16-11

16.3.7 UART Transmitter Buffers (UTBn)........................................................... 16-11

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16.3.8 UART Input Port Change Registers (UIPCRn).......................................... 16-12

16.3.9 UART Auxiliary Control Registers (UACRn) ........................................... 16-12

16.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn).......................... 16-13

16.3.11 UART Divider Upper/Lower Registers (UDUn/UDLn)............................ 16-14

16.3.12 UART Autobaud Registers (UABUn/UABLn).......................................... 16-15

16.3.13 UART Transmitter FIFO Registers (UTFn)............................................... 16-15

16.3.14 UART Receiver FIFO Registers (URFn) ................................................... 16-16

16.3.15 UART Fractional Precision Divider Control Registers (UFPDn).............. 16-17

16.3.16 UART Input Port Registers (UIPn) ............................................................ 16-18

16.3.17 UART Output Port Command Registers (UOP1n/UOP0n) ....................... 16-18

16.4 UART Module Signal Definitions.................................................................. 16-19

16.5 Operation......................................................................................................... 16-20

16.5.1 Transmitter/Receiver Clock Source............................................................ 16-20

16.5.1.1 Programmable Divider............................................................................ 16-20

16.5.1.2 Calculating Baud Rates........................................................................... 16-21

16.5.1.2.1 CLKIN Baud Rates............................................................................. 16-21

16.5.1.2.2 External Clock .................................................................................... 16-22

16.5.1.2.3 Autobaud Detection............................................................................ 16-22

16.5.2 Transmitter and Receiver Operating Modes............................................... 16-23

16.5.2.1 Transmitting ........................................................................................... 16-23

16.5.2.2 Receiver .................................................................................................. 16-25

16.5.2.3 Transmitter FIFO.................................................................................... 16-26

16.5.2.4 Receiver FIFO ....................................................................................... 16-26

16.5.3 Looping Modes........................................................................................... 16-28

16.5.3.1 Automatic Echo Mode............................................................................ 16-28

16.5.3.2 Local Loop-Back Mode.......................................................................... 16-28

16.5.3.3 Remote Loop-Back Mode....................................................................... 16-29

16.5.4 Multidrop Mode.......................................................................................... 16-29

16.5.5 Bus Operation............................................................................................. 16-31

16.5.5.1 Read Cycles ............................................................................................ 16-31

16.5.5.2 Write Cycles ........................................................................................... 16-31

16.5.5.3 Interrupt Acknowledge Cycles ............................................................... 16-31

16.5.6 Programming .............................................................................................. 16-31

16.5.6.1 UART Module Initialization Sequence .................................................. 16-32

Title

Page

Number

Chapter 17

General Purpose I/O Module

17.1 Overview........................................................................................................... 17-1

17.2 Port Control Registers....................................................................................... 17-2

17.2.1 Port A Control Register (PACNT)................................................................ 17-2

17.2.2 Port B Control Register (PBCNT)................................................................ 17-5

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17.2.3 Port C Control Register................................................................................. 17-8

17.2.4 Port D Control Register (PDCNT)................................................................ 17-8

17.3 Data Direction Registers................................................................................... 17-9

17.3.1 Port A Data Direction Register (PADDR).................................................. 17-10

17.3.2 Port B Data Direction Register (PBDDR).................................................. 17-10

17.3.3 Port C Data Direction Register (PCDDR).................................................. 17-11

17.4 Port Data Registers ......................................................................................... 17-11

17.4.1 Port Data Register (PxDAT)....................................................................... 17-12

Title

Page

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Chapter 18

Pulse Width Modulation (PWM) Module

18.1 Overview........................................................................................................... 18-1

18.2 PWM Operation................................................................................................ 18-2

18.3 PWM Programming Model............................................................................... 18-2

18.3.1 PWM Control Register (PWCRn) ................................................................ 18-3

18.3.2 PWM Width Register (PWWDn)................................................................. 18-4

Chapter 19

Signal Descriptions

19.1 Signal List......................................................................................................... 19-1

19.2 Address Bus (A[22:0]/SDRAM_ADR[13:0]) ................................................ 19-16

19.3 Data Bus (D[31:0]) ......................................................................................... 19-16

19.3.1 Dynamic Data Bus Sizing........................................................................... 19-17

19.4 Chip Selects (CS7/SDCS, CS6/AEN, CS[5:1], CS0)..................................... 19-17

19.5 Bus Control Signals ........................................................................................ 19-17

19.5.1 Output Enable/Read (OE/RD).................................................................... 19-17

19.5.2 Byte Strobes (BS[3:0])................................................................................ 19-17

19.5.3 Read/Write (R/W)....................................................................................... 19-19

19.5.4 Transfer Acknowledge (TA/PB5)............................................................... 19-19

19.5.5 Hi-Z............................................................................................................. 19-19

19.5.6 Bypass......................................................................................................... 19-20

19.5.7 SDRAM Row Address Strobe (RAS0)....................................................... 19-20

19.5.8 SDRAM Column Address Strobe (CAS0) ................................................. 19-20

19.5.9 SDRAM Clock (SDCLK)........................................................................... 19-20

19.5.10 SDRAM Write Enable (SDWE)................................................................. 19-20

19.5.11 SDRAM Clock Enable (SDCLKE) ............................................................ 19-20

19.5.12 SDRAM Bank Selects (SDBA[1:0]) .......................................................... 19-20

19.5.13 SDRAM Row Address 10 (A10)/A10 Precharge (A10_PRECHG)........... 19-20

19.6 CPU Clock and Reset Signals......................................................................... 19-20

19.6.1 RSTI

............................................................................................................ 19-20

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19.6.2 DRESETEN................................................................................................ 19-21

19.6.3 CPU External Clock (CLKIN).................................................................... 19-21

19.6.4 Reset Output (RSTO).................................................................................. 19-21

19.7 Interrupt Request Inputs (INT[6:1])................................................................ 19-21

19.8 General-Purpose I/O (GPIO) Ports................................................................. 19-21

19.9 UART0 Module Signals and PB[4:0]............................................................. 19-22

19.9.1 Transmit Serial Data Output (URT0_TxD/PB0)........................................ 19-22

19.9.2 Receive Serial Data Input (URT0_RxD/PB1)............................................ 19-22

19.9.3 Clear-to-Send (URT0_CTS/PB2)............................................................... 19-22

19.9.4 Request to Send (UR

19.9.5 Clock (URT0_CLK/PB4)........................................................................... 19-23

19.10 USB Module Signals and PA[6:0].................................................................. 19-23

19.10.1 USB Transmit Serial Data Output (USB_TP/PA0).................................... 19-23

19.10.2 USB Receive Serial Data Input (USB_RP/PA1)........................................ 19-23

19.10.3 USB Receive Data Negative (USB_RN/PA2)............................................ 19-23

19.10.4 USB Transmit Data Negative (USB_TN/PA3).......................................... 19-23

19.10.5 USB Suspend Driver (USB_SUSP/PA4) ................................................... 19-23

19.10.6 USB Transmitter Output Enable (USB_TxEN/PA5) ................................. 19-24

19.10.7 USB Rx Data Output (USB_RxD/PA6)..................................................... 19-24

19.10.8 USB_D+ and USB_D-................................................................................ 19-24

19.10.9 USB_CLK................................................................................................... 19-24

19.10.10 INT1/USB Wake-on-Ring (USB_WOR) ................................................... 19-24

19.11 Timer Module Signals..................................................................................... 19-25

19.11.1 Timer Input 0 (TIN0).................................................................................. 19-25

19.11.2 Timer Output (TOUT0)/PB7...................................................................... 19-25

19.11.3 Timer Input 1 (TIN1)/PWM Mode Output 2 (PWM_OUT2) .................... 19-25

19.11.4 Timer Output 1 (TOUT1)/PWM Mode Output 1 (PWM_OUT1).............. 19-25

19.12 Ethernet Module Signals................................................................................. 19-25

19.12.1 Transmit Clock (E_TxCLK)....................................................................... 19-25

19.12.2 Transmit Data (E_TxD0)............................................................................ 19-25

19.12.3 Collision (E_COL)...................................................................................... 19-26

19.12.4 Receive Data Valid (E_RxDV)................................................................... 19-26

19.12.5 Receive Clock (E_RxCLK)........................................................................ 19-26

19.12.6 Receive Data (E_RxD0) ............................................................................. 19-26

19.12.7 Transmit Enable (E_TxEN)........................................................................ 19-26

19.12.8 Transmit Data (E_TxD[3:1]/PB[10:8]) ...................................................... 19-26

19.12.9 Receive Data (E_RxD[3:1]/PB[13:11])...................................................... 19-26

19.12.10 Receive Error (E_RxER/PB14).................................................................. 19-27

19.12.11 Management Data Clock (E_MDC/PB15)................................................. 19-27

19.12.12 Management Data (E_MDIO).................................................................... 19-27

19.12.13 Transmit Error (E_TxER)........................................................................... 19-27

19.12.14 Carrier Receive Sense (E_CRS)................................................................. 19-27

19.13 PWM Module Signals (PWM_OUT0–PWM_OUT2]).................................. 19-27

Title

T0_RTS/PB3)............................................................ 19-23

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19.14 Queued Serial Peripheral Interface (QSPI) Signals........................................ 19-28

19.14.1 QSPI Synchronous Serial Data Output (QSPI_Dout)................................. 19-28

19.14.2 QSPI Synchronous Serial Data Input (QSPI_Din)..................................... 19-28

19.14.3 QSPI Serial Clock (QSPI_CLK/BUSW1).................................................. 19-28

19.14.4 Synchronous Peripheral Chip Select 0 (QSPI_CS0/BUSW0).................... 19-28

19.14.5 Synchronous Peripheral Chip Select 1 (QSPI_CS1/PA11)........................ 19-28

19.14.6 Synchronous Peripheral Chip Select 2 (QSPI_CS2/UR

19.14.7 Synchronous Peripheral Chip Select 3 (PA7/DOUT3/QSPI_CS3)............ 19-29

19.15 Physical Layer Interface Controller TDM Ports............................................. 19-29

19.15.1 GCI/IDL TDM Port 0................................................................................. 19-29

19.15.1.1 Frame Sync (FSR0/FSC0/PA8).............................................................. 19-29

19.15.1.2 D-Channel Grant (DGNT0/PA9)............................................................ 19-29

19.15.1.3 Data Clock (DCL0/URT1_CLK) ........................................................... 19-30

19.15.1.4 Serial Data Input (DIN0/URT1_RxD).................................................... 19-30

19.15.1.5 UART1 CTS (URT1_CTS/QSPI_CS2) ................................................. 19-30

19.15.1.6 UART1 RTS (UR

19.15.1.7 Serial Data Output (DOUT0/URT1_TxD) ............................................. 19-30

19.15.1.8 D-Channel Request(DREQ0/PA10) ....................................................... 19-31

19.15.1.9 QSPI Chip Select 1 (QSPI_CS1/PA11).................................................. 19-31

19.15.2 GCI/IDL TDM Port 1................................................................................. 19-31

19.15.2.1 GCI/IDL Data Clock (DCL1/GDCL1_OUT)......................................... 19-31

19.15.2.2 GCI/IDL Data Out (DOUT1) ................................................................. 19-31

19.15.2.3 GCI/IDL Data In (DIN1)........................................................................ 19-31

19.15.2.4 GCI/IDL Frame Sync (FSC1/FSR1/DFSC1) ......................................... 19-32

19.15.2.5 D-Channel Request (DREQ1/PA14) ...................................................... 19-32

19.15.2.6 D-Channel Grant (DGNT1_INT6/PA15_INT6) .................................... 19-32

19.15.3 GCI/IDL TDM Ports 2 and 3...................................................................... 19-32

19.15.3.1 GCI/IDL Delayed Frame Sync 2 (DFSC2/PA12) .................................. 19-33

19.15.3.2 GCI/IDL Delayed Frame Sync 3 (DFSC3/PA13) .................................. 19-33

19.15.3.3 QSPI_CS3, Port 3 GCI/IDL Data Out 3, PA7

(PA7/DOUT3/QSPI_CS3) ..................................................................19-33

19.15.3.4 INT4 and Port 3 GCI/IDL Data In (INT4/DIN3) ................................... 19-33

19.16 JTAG Test Access Port and BDM Debug Port............................................... 19-34

19.16.1 Test Clock (TCK/PSTCLK) ....................................................................... 19-34

19.16.2 Test Mode Select and Force Breakpoint (TMS/BKPT).............................. 19-34

19.16.3 Test and Debug Data Out (TDO/DSO)....................................................... 19-34

19.16.4 Test and Debug Data In (TDI/DSI) ............................................................ 19-35

19.16.5 JTAG TRST and BDM Data Clock (TRST/DSCLK)................................ 19-35

19.16.6 Motorola Test Mode Select (MTMOD)...................................................... 19-35

19.16.7 Debug Transfer Error Acknowledge (TEA)............................................... 19-35

19.16.8 Processor Status Outputs (PST[3:0]).......................................................... 19-35

19.16.9 Debug Data (DDATA[3:0])........................................................................ 19-36

19.16.10 Device Test Enable (TEST)........................................................................ 19-36

T1_RTS/INT5)........................................................... 19-30

Title

T1_CTS).............. 19-29

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Number

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19.17 Operating Mode Configuration Pins............................................................... 19-36

19.18 Power Supply Pins.......................................................................................... 19-37

Title

Page

Number

Chapter 20

Bus Operation

20.1 Features............................................................................................................. 20-1

20.2 Bus And Control Signals .................................................................................. 20-1

20.2.1 Address Bus (A[22:0]).................................................................................. 20-2

20.2.2 Data Bus (D[31:0]) ....................................................................................... 20-2

20.2.3 Read/Write (R/W)......................................................................................... 20-2

20.2.4 Transfer Acknowledge (TA)......................................................................... 20-3

20.2.5 Transfer Error Acknowledge (TEA)............................................................. 20-4

20.3 Bus Exception: Double Bus Fault..................................................................... 20-4

20.4 Bus Characteristics............................................................................................ 20-5

20.5 Data Transfer Mechanism................................................................................. 20-5

20.5.1 Bus Sizing..................................................................................................... 20-6

20.6 External Bus Interface Types.......................................................................... 20-10

20.6.1 Interface for FLASH/SRAM Devices with Byte Strobes........................... 20-10

20.6.2 Interface for FLASH/SRAM Devices without Byte Strobes...................... 20-15

20.7 Burst Data Transfers....................................................................................... 20-20

20.8 Misaligned Operands...................................................................................... 20-20

20.9 Interrupt Cycles............................................................................................... 20-21

20.10 Bus Errors ....................................................................................................... 20-22

20.11 Bus Arbitration................................................................................................ 20-24

20.12 Reset Operation............................................................................................... 20-24

20.12.1 Master Reset ............................................................................................... 20-25

20.12.2 Normal Reset .............................................................................................. 20-26

20.12.3 Software Watchdog Timer Reset Operation............................................... 20-27

20.12.4 Soft Reset Operation................................................................................... 20-28

Chapter 21

IEEE 1149.1 Test Access Port (JTAG)

21.1 Overview........................................................................................................... 21-1

21.2 JTAG Test Access Port and BDM Debug Port................................................. 21-2

21.3 TAP Controller.................................................................................................. 21-3

21.4 Boundary Scan Register.................................................................................... 21-4

21.5 Instruction Register........................................................................................... 21-7

21.6 Restrictions ....................................................................................................... 21-8

21.7 Non-IEEE 1149.1 Operation............................................................................. 21-9

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Title

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Chapter 22

Mechanical Data

22.1 Pinout................................................................................................................ 22-1

22.2 Package Dimensions......................................................................................... 22-2

Chapter 23

Electrical Characteristics

23.1 Maximum Ratings............................................................................................. 23-1

23.1.1 Supply, Input Voltage, and Storage Temperature......................................... 23-1

23.1.2 Operating Temperature................................................................................. 23-1

23.1.3 Resistance ..................................................................................................... 23-2

23.2 DC Electrical Specifications............................................................................. 23-2

23.2.1 Output Driver Capability and Loading......................................................... 23-3

23.3 AC Electrical Specifications............................................................................. 23-4

23.3.1 Clock Input and Output Timing Specifications............................................ 23-5

23.3.2 Processor Bus Input Timing Specifications.................................................. 23-5

23.3.3 Processor Bus Output Timing Specifications............................................... 23-7

23.4 Debug AC Timing Specifications................................................................... 23-12

23.4.1 SDRAM Interface Timing Specifications................................................... 23-13

23.4.2 Fast Ethernet AC Timing Specifications.................................................... 23-15

23.4.2.1 MII Receive Signal Timing (E_RxD[3:0], E_RxDV, E_RxER,

and E_RxCLK) ................................................................................... 23-15

23.4.2.2 MII Transmit Signal Timing (E_TxD[3:0], E_TxEN, E_TxER,

E_TxCLK).......................................................................................... 23-16

23.4.2.3 MII Async Inputs Signal Timing (CRS and COL)................................. 23-17

23.4.2.4 MII Serial Management Channel Timing (MDIO and MDC)................ 23-17

23.4.3 Timer Module AC Timing Specifications.................................................. 23-18

23.4.4 UART Modules AC Timing Specifications................................................ 23-19

23.4.5 PLIC Module: IDL and GCI Interface Timing Specifications................... 23-21

23.4.6 General-Purpose I/O Port AC Timing Specifications................................. 23-25

23.4.7 USB Interface AC Timing Specifications .................................................. 23-26

23.4.8 IEEE 1149.1 (JTAG) AC Timing Specifications ....................................... 23-27

23.4.9 QSPI Electrical Specifications.................................................................... 23-28

23.4.10 PWM Electrical Specifications................................................................... 23-29

Appendix A

List of Memory Maps

A.1 Overview............................................................................................................ A-1

A.2 List of Memory Map Tables.............................................................................. A-1

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Title

Appendix B

Buffering and Impedance Matching

Page

Number

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ILLUSTRATIONS

Figure Number

1-1 MCF5272 Block Diagram.............................................................................................1-2

2-1 ColdFire Pipeline........................................................................................................2-12

2-2 ColdFire Multiply-Accumulate Functionality Diagram ............................................. 2-14

2-3 ColdFire Programming Model....................................................................................2-16

2-4 Condition Code Register (CCR)................................................................................. 2-17

2-5 Status Register (SR)....................................................................................................2-19

2-6 Vector Base Register (VBR)....................................................................................... 2-19

2-7 Organization of Integer Data Formats in Data Registers............................................ 2-21

2-8 Organization of Integer Data Formats in Address Registers......................................2-21

2-9 Memory Operand Addressing..................................................................................... 2-22

2-10 Exception Stack Frame Form......................................................................................2-38

3-1 ColdFire MAC Multiplication and Accumulation........................................................3-2

3-2 MAC Programming Model........................................................................................... 3-2

4-1 SRAM Base Address Register (RAMBAR)................................................................. 4-3

4-2 ROM Base Address Register (ROMBAR)...................................................................4-6

4-3 Instruction Cache Block Diagram................................................................................. 4-8

4-4 Cache Control Register (CACR) ................................................................................ 4-13

4-5 Access Control Register Format (ACRn)...................................................................4-15

5-1 Processor/Debug Module Interface...............................................................................5-1

5-2 PSTCLK Timing...........................................................................................................5-2

5-3 Example JMP Instruction Output on PST/DDATA......................................................5-5

5-4 Debug Programming Model ......................................................................................... 5-6

5-5 Address Attribute Trigger Register (AATR)................................................................ 5-8

5-6 Address Breakpoint Registers (ABLR, ABHR) ........................................................... 5-9

5-7 Configuration/Status Register (CSR).......................................................................... 5-10

5-8 Data Breakpoint/Mask Registers (DBR and DBMR).................................................5-12

5-9 Program Counter Breakpoint Register (PBR).............................................................5-13

5-10 Program Counter Breakpoint Mask Register (PBMR)............................................... 5-13

5-11 Trigger Definition Register (TDR)............................................................................. 5-14

5-12 BDM Serial Interface Timing..................................................................................... 5-17

5-13 Receive BDM Packet..................................................................................................5-18

5-14 Transmit BDM Packet ................................................................................................ 5-18

5-15 BDM Command Format.............................................................................................5-20

5-16 Command Sequence Diagram.....................................................................................5-21

5-18 rareg/rdreg Command Sequence................................................................................. 5-23

5-17 rareg/rdreg Command Format.....................................................................................5-23

Title

Page

Number

Illustrations

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ILLUSTRATIONS

Figure Number

5-20 wareg/wdreg Command Sequence.............................................................................. 5-24

5-19 wareg/wdreg Command Format ................................................................................. 5-24

5-22 read Command Sequence............................................................................................ 5-25

5-21 read Command/Result Formats...................................................................................5-25

5-23 write Command Format.............................................................................................. 5-26

5-24 write Command Sequence .......................................................................................... 5-27

5-25 dump Command/Result Formats ................................................................................ 5-28

5-26 dump Command Sequence ......................................................................................... 5-29

5-27 fill Command Format.................................................................................................. 5-30

5-28 fill Command Sequence..............................................................................................5-31

5-30 go Command Sequence...............................................................................................5-32

5-29 go Command Format .................................................................................................. 5-32

5-32 nop Command Sequence.............................................................................................5-33

5-31 nop Command Format ................................................................................................ 5-33

5-34 rcreg Command Sequence .......................................................................................... 5-34

5-33 rcreg Command/Result Formats.................................................................................5-34

5-36 wcreg Command Sequence......................................................................................... 5-35

5-35 wcreg Command/Result Formats................................................................................ 5-35

5-38 rdmreg Command Sequence....................................................................................... 5-36

5-37 rdmreg bdm Command/Result Formats...................................................................... 5-36

5-40 wdmreg Command Sequence ..................................................................................... 5-37

5-39 wdmreg BDM Command Format............................................................................... 5-37

5-41 Recommended BDM Connector................................................................................. 5-45

6-1 SIM Block Diagram......................................................................................................6-1

6-2 Module Base Address Register (MBAR) ..................................................................... 6-4

6-3 System Configuration Register (SCR).......................................................................... 6-5

6-4 System Protection Register (SPR)................................................................................6-7

6-5 Power Management Register (PMR)............................................................................ 6-8

6-6 Activate Low-Power Register (ALPR).......................................................................6-10

6-7 Device Identification Register (DIR).......................................................................... 6-12

6-8 Watchdog Reset Reference Register (WRRR)...........................................................6-13

6-9 Watchdog Interrupt Reference Register (WIRR) ....................................................... 6-13

6-10 Watchdog Counter Register (WCR)........................................................................... 6-14

6-11 Watchdog Event Register (WER)...............................................................................6-14

7-1 Interrupt Controller Block Diagram..............................................................................7-2

7-2 Interrupt Control Register 1 (ICR1).............................................................................. 7-4

7-3 Interrupt Control Register 2 (ICR2).............................................................................. 7-5

7-4 Interrupt Control Register 3 (ICR3).............................................................................. 7-6

7-5 Interrupt Control Register 4(ICR4)............................................................................... 7-6

7-6 Interrupt Source Register (ISR)....................................................................................7-7

7-7 Programmable Interrupt Transition Register (PITR)....................................................7-8

7-8 Programmable Interrupt Wakeup Register (PIWR)...................................................... 7-9

7-9 Programmable Interrupt Vector Register (PIVR)....................................................... 7-10

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8-1 Chip Select Base Registers (CSBRn) ........................................................................... 8-3

8-2 Chip Select Option Registers (CSORn).......................................................................8-5

9-1 SDRAM Controller Signals.......................................................................................... 9-2

9-2 54-Pin TSOP SDRAM Pin Definition.......................................................................... 9-4

9-3 SDRAM Configuration Register (SDCR) .................................................................... 9-7

9-4 SDRAM Timing Register (SDTR) ............................................................................... 9-9

9-5 Example Setup Time Violation on SDRAM Data Input during Write.......................9-14

9-6 Timing Refinement with Inverted SDCLK.................................................................9-14

9-7 Timing Refinement with True CAS Latency and Inverted SDCLK...........................9-15

9-8 Timing Refinement with Effective CAS Latency....................................................... 9-15

9-9 SDRAM Burst Read, 32-Bit Port, Page Miss, Access = 9-1-1-1 ............................... 9-18

9-10 SDRAM Burst Read, 32-Bit Port, Page Hit, Access = 5-1-1-1.................................. 9-19

9-11 SDRAM Burst Write, 32-Bit Port, Page Miss, Access = 7-1-1-1 ..............................9-20

9-12 SDRAM Burst Write, 32-Bit Port, Page Hit, Access = 3-1-1-1.................................9-21

9-13 SDRAM Refresh Cycle...............................................................................................9-22

9-14 Enter SDRAM Self-Refresh Mode............................................................................. 9-23

9-15 Exit SDRAM Self-Refresh Mode............................................................................... 9-24

10-1 DMA Mode Register (DMR)...................................................................................... 10-2

10-2 DMA Interrupt Register (DIR) ................................................................................... 10-4

10-3 DMA Source Address Register (DSAR) .................................................................... 10-6

10-4 DMA Destination Address Register (DDAR) ............................................................ 10-6

10-5 DMA Byte Count Register (DBCR)........................................................................... 10-6

11-1 Ethernet Block Diagram ............................................................................................. 11-2

11-2 Fast Ethernet Module Block Diagram ........................................................................ 11-2

11-3 Ethernet Frame Format...............................................................................................11-4

11-4 Ethernet Address Recognition Flowchart................................................................... 11-8

11-5 Ethernet Control Register (ECNTRL)......................................................................11-12

11-6 I_MASK Register ..................................................................................................... 11-14

11-7 Interrupt Vector Status Register (IVEC)...................................................................11-15

11-8 R_DES_ACTIVE Register ....................................................................................... 11-16

11-9 X_DES_ACTIVE Register....................................................................................... 11-17

11-10 MII Management Frame Register (MII_DATA)......................................................11-17

11-11 MII Speed Control Register (MII_SPEED)..............................................................11-19

11-12 FIFO Receive Bound Register (R_BOUND) ........................................................... 11-20

11-13 FIFO Receive Start Register (R_FSTART)..............................................................11-21

11-14 Transmit FIFO Watermark (X_WMRK).................................................................. 11-22

11-15 FIFO Transmit Start Register (X_FSTART)............................................................ 11-23

11-16 Receive Control Register (R_CNTRL)..................................................................... 11-23

11-17 Maximum Frame Length Register (MAX_FRM_LEN)........................................... 11-24

11-18 Transmit Control Register (X_CNTRL)...................................................................11-25

11-19 RAM Perfect Match Address Low (ADDR_LOW) ................................................. 11-26

11-20 RAM Perfect Match Address High (ADDR_HIGH)................................................ 11-27

11-21 Hash Table High (HASH_TABLE_HIGH).............................................................. 11-27

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11-22 Hash Table Low (HASH_TABLE_LOW) .............................................................. 11-28

11-23 Pointer to Receive Descriptor Ring (R_DES_START)............................................ 11-29

11-24 Pointer to Transmit Descriptor Ring (X_DES_START).......................................... 11-29

11-25 Receive Buffer Size (R_BUFF_SIZE)......................................................................11-30

11-26 Receive Buffer Descriptor (RxBD) .......................................................................... 11-34

11-27 Transmit Buffer Descriptor (TxBD)......................................................................... 11-36

12-1 The USB “tiered star” topology..................................................................................12-2

12-2 USB Module Block Diagram...................................................................................... 12-3

12-3 USB Frame Number Register (FNR).......................................................................... 12-9

12-4 USB Frame Number Match Register (FNMR)...........................................................12-9

12-5 USB Real-Time Frame Monitor Register (RFMR)..................................................12-10

12-6 USB Real-Time Frame Monitor Match Register (RFMMR) ................................... 12-11

12-7 USB Function Address Register (FAR).................................................................... 12-11

12-8 USB Alternate Settings Register (ASR)...................................................................12-12

12-9 USB Device Request Data 1 Register (DRR1)......................................................... 12-12

12-10 USB Device Request Data 2 Register (DRR2)......................................................... 12-13

12-11 USB Specification Number Register (SPECR) ........................................................ 12-13

12-12 USB Endpoint 0 Status Register (EP0SR)................................................................ 12-14

12-13 USB Endpoint 0 IN Configuration Register (IEP0CFG).......................................... 12-15

12-14 USB Endpoint 0 OUT Configuration Register......................................................... 12-16

12-15 USB Endpoint 1–7 Configuration Register .............................................................. 12-16

12-16 USB Endpoint 0 Control Register (EP0CTL)........................................................... 12-17

12-17 USB Endpoint 1-7 Control Register (EPnCR)..........................................................12-20

12-18 USB Endpoint 0 Interrupt Mask (EP0IMR) and General/Endpoint 0

Interrupt Registers (EP0ISR).................................................................................... 12-22

12-19 USB Endpoints 1–7 Interrupt Status Registers (EPnISR) ........................................ 12-24

12-20 USB Endpoint 1-7 Interrupt Mask Registers (EPnIMR).......................................... 12-26

12-21 USB Endpoint 0-7 Data Registers (EPnDAT).......................................................... 12-26

12-22 USB Endpoint 0-7 Data Present Registers (EPnDPR) ............................................. 12-27

12-23 Example USB Configuration Descriptor Structure...................................................12-28

12-24 Recommended USB Line Interface..........................................................................12-35

13-1 PLIC System Diagram................................................................................................ 13-2

13-2 GCI/IDL Receive Data Flow......................................................................................13-4

13-3 GCI/IDL B-Channel Receive Data Register Demultiplexing..................................... 13-5

13-4 GCI/IDL Transmit Data Flow..................................................................................... 13-5

13-5 GCI/IDL B Data Transmit Register Multiplexing...................................................... 13-6

13-6 B-Channel Unencoded and HDLC Encoded Data...................................................... 13-7

13-7 D-Channel HDLC Encoded and Unencoded Data......................................................13-8

13-8 D-Channel Contention................................................................................................13-9

13-9 GCI/IDL Loopback Mode.........................................................................................13-10

13-10 Periodic Frame Interrupt........................................................................................... 13-11

13-11 PLIC Internal Timing Signal Routing.......................................................................13-14

13-12 PLIC Clock Generator .............................................................................................. 13-14

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13-13 B1 Receive Data Registers P0B1RR–P3B1RR........................................................ 13-17

13-14 B2 Receive Data Registers P3B2RR – P0B2RR...................................................... 13-17

13-15 D Receive Data Registers P3DRR–P0DRR ............................................................. 13-18

13-16 B1 Transmit Data Registers P3B1TR–P0B1TR....................................................... 13-18

13-17 B2 Transmit Data Registers P3B2TR–P0B2TR....................................................... 13-19

13-18 D Transmit Data Registers P3DTR–P0DTR ............................................................ 13-20

13-19 Port Configuration Registers (P0CR–P3CR)............................................................ 13-20

13-20 Loopback Control Register (PLCR) ......................................................................... 13-22

13-21 Interrupt Configuration Registers (P0ICR–P3ICR).................................................. 13-22

13-22 Periodic Status Registers (P0PSR–P3PSR)..............................................................13-24

13-23 Aperiodic Status Register (PASR)............................................................................ 13-25

13-24 GCI Monitor Channel Receive Registers (P0GMR–P3GMR)................................. 13-26

13-25 GCI Monitor Channel Transmit Registers (P0GMT–P3GMT)................................ 13-27

13-26 GCI Monitor Channel Transmit Abort Register (PGMTA) ..................................... 13-28

13-27 GCI Monitor Channel Transmit Status Register (PGMTS)...................................... 13-28

13-28 GCI C/I Channel Receive Registers (P0GCIR–P3GCIR)........................................13-29

13-29 GCI C/I Channel Transmit Registers (P0GCIT–P3GCIT)....................................... 13-31

13-30 GCI C/I Channel Transmit Status Register (PGCITSR)...........................................13-32

13-31 D-Channel Status Register (PDCSR)........................................................................13-32

13-32 D-Channel Request Registers (PDRQR)..................................................................13-33

13-33 Sync Delay Registers (P0SDR–P3SDR) .................................................................. 13-34

13-34 Clock Select Register (PCSR) .................................................................................. 13-35

13-35 Port 1 PLCR Configuration ...................................................................................... 13-37

13-36 Port 1 PLICR Configuration..................................................................................... 13-38

13-37 ISDN SOHO PABX Example .................................................................................. 13-39

13-38 Standard IDL2 10-Bit Mode..................................................................................... 13-40

13-39 ISDN SOHO PABX Example .................................................................................. 13-41

13-40 Standard IDL2 10-bit mode......................................................................................13-42

13-41 Two-Line Remote Access......................................................................................... 13-43

13-42 Standard IDL2 8-Bit mode........................................................................................13-43

14-1 QSPI Block Diagram .................................................................................................. 14-2

14-2 QSPI RAM Model ...................................................................................................... 14-5

14-3 QSPI Mode Register (QMR) ...................................................................................... 14-9

14-4 QSPI Clocking and Data Transfer Example............................................................. 14-11

14-5 QSPI Delay Register (QDLYR)................................................................................14-11

14-6 QSPI Wrap Register (QWR)..................................................................................... 14-12

14-7 QSPI Interrupt Register (QIR).................................................................................. 14-12

14-8 QSPI Address Register ............................................................................................. 14-14

14-9 QSPI Data Register................................................................................................... 14-14

14-10 Command RAM Registers (QCR0–QCR15)............................................................ 14-15

15-1 Timer Block Diagram.................................................................................................15-2

15-2 Timer Mode Registers (TMR0–TMR3)......................................................................15-3

15-3 Timer Reference Registers (TRR0–TRR3) ................................................................ 15-4

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15-4 Timer Capture Registers (TCR0–TCR3).................................................................... 15-5

15-5 Timer Counter (TCN0–TCN3)...................................................................................15-5

15-6 Timer Event Registers (TER0–TER3)........................................................................ 15-5

16-1 Simplified Block Diagram.......................................................................................... 16-1

16-2 UART Mode Registers 1 (UMR1n)............................................................................ 16-5

16-3 UART Mode Register 2 (UMR2n).............................................................................16-6

16-4 UART Status Registers (USRn)..................................................................................16-7

16-5 UART Clock-Select Registers (UCSRn).................................................................... 16-9

16-6 UART Command Registers (UCRn)..........................................................................16-9

16-7 UART Receiver Buffer (URBn)............................................................................... 16-11

16-8 UART Transmitter Buffers (UTBn) ......................................................................... 16-12

16-9 UART Input Port Change Registers (UIPCRn)........................................................ 16-12

16-10 UART Auxiliary Control Registers (UACRn) ......................................................... 16-13

16-11 UART Interrupt Status/Mask Registers (UISRn/UIMRn)........................................ 16-13

16-12 UART Divider Upper Registers (UDUn).................................................................16-14

16-13 UART Divider Lower Registers (UDLn).................................................................16-15

16-14 UART Autobaud Upper Registers (UABUn)........................................................... 16-15

16-15 UART Autobaud Lower Registers (UABLn)........................................................... 16-15

16-16 UART Transmitter FIFO Registers (UTFn).............................................................16-16

16-17 UART Receiver FIFO Registers (URFn) ................................................................. 16-16

16-18 UART Fractional Precision Divider Control Registers (UFPDn) ............................ 16-17

16-19 UART Input Port Registers (UIPn)...........................................................................16-18

16-20 UART Output Port Command Registers (UOP1/UOP0)..........................................16-18

16-21 UART Block Diagram Showing External and Internal Interface Signals................ 16-19

16-22 UART/RS-232 Interface........................................................................................... 16-20

16-23 Clocking Source Diagram......................................................................................... 16-21

16-24 Transmitter and Receiver Functional Diagram......................................................... 16-23

16-25 Transmitter Timing................................................................................................... 16-24

16-26 Receiver Timing........................................................................................................16-25

16-27 Automatic Echo ........................................................................................................ 16-28

16-28 Local Loop-Back ...................................................................................................... 16-28

16-29 Remote Loop-Back................................................................................................... 16-29

16-30 Multidrop Mode Timing Diagram............................................................................16-30

16-31 UART Mode Programming Flowchart..................................................................... 16-32

17-1 Port A Control Register (PACNT).............................................................................. 17-3

17-2 Port B Control Register (PBCNT).............................................................................. 17-5

17-3 Port D Control Register (PDCNT).............................................................................. 17-8

17-4 Port A Data Direction Register (PADDR)................................................................ 17-10

17-5 Port B Data Direction Register (PBDDR)................................................................17-10

17-6 Port C Data Direction Register (PCDDR)................................................................17-11

17-7 Port x Data Register (PADAT, PBDAT, and PCDAT)............................................ 17-12

18-1 PWM Block Diagram (3 Identical Modules).............................................................. 18-1

18-2 PWM Control Registers (PWCRn).............................................................................18-3

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18-3 PWM Width Register (PWWDn) ............................................................................... 18-4

18-4 PWM Waveform Examples (PWCRn[EN] = 1).........................................................18-5

20-1 Internal Operand Representation ................................................................................ 20-6

20-2 MCF5272 Interface to Various Port Sizes.................................................................. 20-7

20-3 Longword Read; EBI = 00; 32-Bit Port; Internal Termination ................................20-11

20-4 Word Write; EBI = 00; 16-/32-Bit Port; Internal Termination................................. 20-12

20-5 Longword Read with Address Setup; EBI = 00; 32-Bit Port; Internal Termination 20-12 20-6 Longword Write with Address Setup; EBI = 00; 32-Bit Port; Internal Termination20-13 20-7 Longword Read with Address Hold; EBI = 00; 32-Bit Port; Internal Termination . 20-13 20-8 Longword Write with Address Hold; EBI = 00; 32-Bit Port; Internal Termination 20-14 20-9 Longword Read; EBI = 00; 32-Bit Port; Terminated by TA with One Wait State .. 20-14

20-10 Longword Read; EBI=11; 32-Bit Port; Internal Termination ..................................20-15

20-11 Word Write; EBI=11; 16/32-Bit Port; Internal Termination.................................... 20-16

20-12 Read with Address Setup; EBI=11; 32-Bit Port; Internal Termination....................20-17

20-13 Longword Write with Address Setup; EBI=11; 32-Bit Port; Internal Termination . 20-17

20-14 Read with Address Hold; EBI=11; 32-Bit Port; Internal Termination..................... 20-18

20-15 Longword Write with Address Hold; EBI=11; 32-Bit Port; Internal Termination .. 20-18 20-16 Longword Read with Address Setup and Address Hold; EBI = 11;

32-Bit Port, Internal Termination ............................................................................. 20-19

20-17 Longword Write with Address Setup and Address Hold; EBI = 11;

32-Bit Port, Internal Termination ............................................................................. 20-19

20-18 Example of a Misaligned Longword Transfer.......................................................... 20-21

20-19 Example of a Misaligned Word Transfer..................................................................20-21

20-20 Longword Write Access To 32-Bit Port Terminated with TEA Timing.................. 20-23

20-21 Master Reset Timing................................................................................................. 20-25

20-22 Normal Reset Timing................................................................................................ 20-26

20-23 Software Watchdog Timer Reset Timing.................................................................20-27

20-24 Soft Reset Timing.....................................................................................................20-28

21-1 Test Access Port Block Diagram................................................................................ 21-2

21-2 TAP Controller State Machine....................................................................................21-4

21-3 Output Cell (O.Cell) (BC–1).......................................................................................21-5

21-4 Input Cell (I.Cell). Observe only (BC–4) ................................................................... 21-5

21-5 Output Control Cell (En.Cell) (BC–4)........................................................................ 21-6

21-6 Bidirectional Cell (IO.Cell) (BC–6) ........................................................................... 21-6

21-7 General Arrangement for Bidirectional Pins .............................................................. 21-7

21-8 Bypass Register........................................................................................................... 21-8

22-1 MCF5272 Pinout (196 MAPBGA).............................................................................22-1

22-2 196 MAPBGA Package Dimensions (Case No. 1128A-01) ...................................... 22-2

23-1 Clock Input Timing Diagram...................................................................................... 23-5

23-2 General Input Timing Requirements .......................................................................... 23-7

23-3 Read/Write SRAM Bus Timing.................................................................................. 23-9

23-4 SRAM Bus Cycle Terminated by TA.......................................................................23-10

23-5 SRAM Bus Cycle Terminated by TEA .................................................................... 23-11

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23-6 Reset and Mode Select/HIZ Configuration Timing.................................................. 23-11

23-7 Real-Time Trace AC Timing.................................................................................... 23-12

23-8 BDM Serial Port AC Timing.................................................................................... 23-12

23-9 SDRAM Signal Timing ............................................................................................ 23-14

23-10 SDRAM Self-Refresh Cycle Timing........................................................................ 23-15

23-11 MII Receive Signal Timing Diagram ....................................................................... 23-16

23-12 MII Transmit Signal Timing Diagram......................................................................23-17

23-13 MII Async Inputs Timing Diagram .......................................................................... 23-17

23-14 MII Serial Management Channel Timing Diagram.................................................. 23-18

23-15 Timer Timing............................................................................................................ 23-19

23-16 UART Timing...........................................................................................................23-20

23-17 IDL Master Timing................................................................................................... 23-21

23-18 IDL Slave Timing.....................................................................................................23-23

23-19 GCI Slave Mode Timing........................................................................................... 23-24

23-20 GCI Master Mode Timing ........................................................................................ 23-25

23-21 General-Purpose I/O Port Timing.............................................................................23-26

23-22 USB Interface Timing............................................................................................... 23-27

23-23 IEEE 1149.1 (JTAG) Timing.................................................................................... 23-28

23-24 QSPI Timing............................................................................................................. 23-29

23-25 PWM Timing............................................................................................................23-30

B-1 Buffering and Termination ...........................................................................................B-2

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2-1 CCR Field Descriptions ............................................................................................. 2-17

2-2 MOVEC Register Map ............................................................................................... 2-18

2-3 Status Field Descriptions ............................................................................................ 2-19

2-4 Integer Data Formats...................................................................................................2-20

2-5 ColdFire Effective Addressing Modes........................................................................2-23

2-6 Notational Conventions .............................................................................................. 2-24

2-7 User-Mode Instruction Set Summary ......................................................................... 2-26

2-8 Supervisor-Mode Instruction Set Summary................................................................2-29

2-9 Misaligned Operand References................................................................................. 2-30

2-10 Move Byte and Word Execution Times......................................................................2-31

2-11 Move Long Execution Times......................................................................................2-31

2-12 Move Execution Times............................................................................................... 2-32

2-13 One-Operand Instruction Execution Times................................................................2-32

2-14 Two-Operand Instruction Execution Times................................................................2-33

2-15 Miscellaneous Instruction Execution Times...............................................................2-34

2-16 General Branch Instruction Execution Times............................................................. 2-35

2-17 Bcc Instruction Execution Times................................................................................ 2-36

2-18 Exception Vector Assignments................................................................................... 2-37

2-19 Format Field Encoding ............................................................................................... 2-38

2-20 Fault Status Encodings................................................................................................ 2-38

2-21 MCF5272

3-1 MAC Instruction Summary...........................................................................................3-4

4-1 Memory Map of Instruction Cache Registers...............................................................4-2

4-2 RAMBAR Field Description ........................................................................................ 4-3

4-3 Examples of Typical RAMBAR Settings..................................................................... 4-5

4-4 ROMBAR Field Description ........................................................................................ 4-6

4-5 Examples of Typical ROMBAR Settings..................................................................... 4-7

4-6 Instruction Cache Operation as Defined by CACR[CENB,CEIB]............................. 4-12

4-7 Memory Map of Instruction Cache Registers.............................................................4-13

4-8 CACR Field Descriptions...........................................................................................4-13

4-9 ACRn Field Descriptions............................................................................................4-15

5-1 Debug Module Signals.................................................................................................. 5-2

5-2 Processor Status Encoding............................................................................................5-4

5-3 BDM/Breakpoint Registers........................................................................................... 5-6

5-4 Rev. A Shared BDM/Breakpoint Hardware ................................................................. 5-7

5-5 AATR Field Descriptions.............................................................................................5-8

Exceptions ................................................................................................. 2-39

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5-6 ABLR Field Description............................................................................................... 5-9

5-7 ABHR Field Description...............................................................................................5-9

5-8 CSR Field Descriptions ..............................................................................................5-10

5-9 DBR Field Descriptions..............................................................................................5-12

5-10 DBMR Field Descriptions .......................................................................................... 5-12

5-11 Access Size and Operand Data Location.................................................................... 5-12

5-12 PBR Field Descriptions ..............................................................................................5-13

5-13 PBMR Field Descriptions........................................................................................... 5-13

5-14 TDR Field Descriptions.............................................................................................. 5-14

5-15 Receive BDM Packet Field Description..................................................................... 5-18

5-16 Transmit BDM Packet Field Description ................................................................... 5-18

5-17 BDM Command Summary.........................................................................................5-19

5-18 BDM Field Descriptions............................................................................................. 5-20

5-19 Control Register Map.................................................................................................. 5-34

5-20 Definition of DRc Encoding—Read...........................................................................5-36

5-21 DDATA[3:0]/CSR[BSTAT] Breakpoint Response.................................................... 5-38

5-22 PST/DDATA Specification for User-Mode Instructions............................................ 5-41

5-23 PST/DDATA Specification for Supervisor-Mode Instructions..................................5-44

6-1 SIM Registers................................................................................................................6-3

6-2 MBAR Field Descriptions ............................................................................................ 6-5

6-3 SCR Field Descriptions ................................................................................................6-5

6-4 SPR Field Descriptions................................................................................................. 6-7

6-5 PMR Field Descriptions................................................................................................ 6-8

6-6 USB and USART Power Down Modes...................................................................... 6-10

6-7 Exiting Sleep and Stop Modes....................................................................................6-11

6-8 DIR Field Descriptions...............................................................................................6-12

6-9 WRRR Field Descriptions .......................................................................................... 6-13

6-10 WIRR Field Descriptions............................................................................................ 6-13

6-11 WER Field Descriptions.............................................................................................6-14

7-1 Interrupt Controller Registers.......................................................................................7-2

7-2 Interrupt and Power Management Register Mnemonics .............................................. 7-3

7-3 ICR Field Descriptions ................................................................................................. 7-5

7-4 ISR Field Descriptions..................................................................................................7-7

7-5 PITR Field Descriptions ............................................................................................... 7-8

7-6 PIWR Field Descriptions.............................................................................................. 7-9

7-7 PIVR Field Descriptions............................................................................................. 7-10

7-8 MCF5272 Interrupt Vector Table............................................................................... 7-10

8-1 CSCR and CSOR Values after Reset............................................................................ 8-2

8-2 CSBRn Field Descriptions............................................................................................8-3

8-3 Output Read/Write Strobe Levels versus Chip Select EBI Code.................................8-4

8-4 Chip Select Memory Address Decoding Priority ......................................................... 8-5

8-5 CSORn Field Descriptions............................................................................................ 8-5

9-1 SDRAM Controller Signal Descriptions ...................................................................... 9-2

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9-2 Connecting BS[3:0] to DQMx...................................................................................... 9-4

9-3 Configurations for 16-Bit Data Bus..............................................................................9-5

9-4 Configurations for 32-Bit Data Bus..............................................................................9-5

9-5 Internal Address Multiplexing (16-Bit Data Bus) ........................................................ 9-5

9-6 Internal Address Multiplexing (32-Bit Data Bus) ........................................................ 9-6

9-7 SDCR Field Descriptions.............................................................................................. 9-8

9-8 SDTR Field Descriptions..............................................................................................9-9

9-9 SDRAM Controller Performance, 32-Bit Port, (RCD = 0, RP = 1)

or (RCD = 1, RP = 0)..................................................................................................9-11

9-10 SDRAM Controller Performance, 32–Bit Port, (RCD = 0, RP = 0)...........................9-11

9-11 SDRAM Controller Performance (RCD = 1, RP = 1), 16-Bit Port............................9-12

9-12 SDRAM Controller Performance, 16-Bit Port, (RCD=0, RP=1)

or (RCD=1, RP = 0)....................................................................................................9-12

9-13 SDRAM Controller Performance, 16-Bit Port, (RCD=0, RP=0)...............................9-13

10-1 DMA Data Transfer Matrix........................................................................................10-1

10-2 DMR Field Descriptions............................................................................................. 10-3

10-3 DIR Field Descriptions...............................................................................................10-4

11-1 MII Mode.................................................................................................................... 11-3

11-2 Seven-Wire Mode Configuration................................................................................ 11-3

11-3 Ethernet Address Recognition .................................................................................... 11-7

11-4 Transmission Errors.................................................................................................. 11-10

11-5 Reception Errors ....................................................................................................... 11-10

11-6 FEC Register Memory Map...................................................................................... 11-11

11-7 ECNTRL Field Descriptions.....................................................................................11-12

11-8 I_EVENT Field Descriptions.................................................................................... 11-13

11-9 I_MASK Register Field Descriptions.......................................................................11-14

11-10 IVEC Field Descriptions........................................................................................... 11-15

11-11 R_DES_ACTIVE Register Field Descriptions.........................................................11-16

11-12 X_DES_ACTIVE Field Descriptions....................................................................... 11-17

11-13 MII_DATA Field Descriptions................................................................................. 11-18

11-14 MII_SPEED Field Descriptions................................................................................ 11-19

11-15 Programming Examples for MII_SPEED Register .................................................. 11-20

11-16 R_BOUND Field Descriptions.................................................................................11-20

11-17 R_FSTART Field Descriptions ................................................................................11-21

11-18 X_WMRK Field Descriptions .................................................................................. 11-22

11-19 X_FSTART Field Descriptions ................................................................................ 11-23

11-20 R_CNTRL Field Descriptions .................................................................................. 11-24

11-21 MAX_FRM_LEN Field Descriptions.......................................................................11-25

11-22 X_CNTRL Field Descriptions.................................................................................. 11-25

11-23 ADDR_LOW Field Descriptions.............................................................................. 11-26

11-24 ADDR_HIGH Field Descriptions............................................................................. 11-27

11-25 HASH_TABLE_HIGH Field Descriptions .............................................................. 11-28

11-26 HASH_TABLE_LOW Field Descriptions...............................................................11-28

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11-27 R_DES_START Field Descriptions.........................................................................11-29

11-28 X_DES_START Field Descriptions......................................................................... 11-30

11-29 R_BUFF_SIZE Field Descriptions........................................................................... 11-30

11-30 Hardware Initialization ............................................................................................. 11-31

11-31 I ETHER_EN = 0...................................................................................................... 11-31

11-32 User Initialization Process (before ETHER_EN).....................................................11-31

11-33 User Initialization (after ETHER_EN) ..................................................................... 11-32

11-34 RxBD Field Descriptions..........................................................................................11-35

11-35 TxBD Field Descriptions.......................................................................................... 11-37

12-1 USB Device Requests................................................................................................. 12-6

12-2 USB Memory Map...................................................................................................... 12-7

12-3 FNR Field Descriptions .............................................................................................. 12-9

12-4 FNMR Field Descriptions......................................................................................... 12-10

12-5 RFMR Field Descriptions......................................................................................... 12-10

12-6 RFMMR Field Descriptions ..................................................................................... 12-11

12-7 FAR Field Descriptions ............................................................................................ 12-11

12-8 ASR Field Descriptions ............................................................................................ 12-12

12-9 SPECR Field Descriptions........................................................................................12-13

12-10 EP0SR Field Descriptions ........................................................................................12-14

12-11 IEP0CFG Field Descriptions .................................................................................... 12-15

12-12 EP0CTL Field Descriptions......................................................................................12-17

12-13 EPnCR Field Descriptions........................................................................................ 12-20

12-14 EP0IMR and EP0ISR Field Descriptions.................................................................12-22

12-15 EPnISR Field Descriptions.......................................................................................12-25

12-17 EPnDAT Field Descriptions.....................................................................................12-26

12-16 EPnIMR Field Descriptions......................................................................................12-26

12-18 EPnDPR Field Descriptions...................................................................................... 12-27

12-19 USB FIFO Access Timing........................................................................................ 12-29

12-20 Example FIFO Setup.................................................................................................12-31

13-1 PLIC Module Memory Map ..................................................................................... 13-15

13-2 P0CR–P3CR Field Descriptions............................................................................... 13-20

13-3 PLCR Field Description............................................................................................ 13-22

13-4 P0ICR–P3ICR Field Descriptions ............................................................................ 13-23

13-5 P0PSR–P3PSR Field Descriptions ........................................................................... 13-24

13-6 PASR Field Descriptions.......................................................................................... 13-25

13-7 P0GMR–P3GMR Field Descriptions ....................................................................... 13-26

13-8 P0GMT–P3GMT Field Descriptions........................................................................13-27

13-9 PGMTA Field Descriptions...................................................................................... 13-28

13-10 PGMTS Field Descriptions....................................................................................... 13-29

13-11 P0GCIR–P3GCIR Field Descriptions ......................................................................13-30

13-12 P0GCIT–P3GCIT Field Descriptions....................................................................... 13-31

13-13 PGCITSR Field Descriptions.................................................................................... 13-32

13-14 PDCSR Field Descriptions ....................................................................................... 13-32

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13-15 PDRQR Field Descriptions....................................................................................... 13-33

13-16 P0SDR–P3SDR Field Descriptions.......................................................................... 13-34

13-17 PCSR Field Descriptions .......................................................................................... 13-35

14-1 QSPI Input and Output Signals and Functions...........................................................14-3

14-2 QSPI_CLK Frequency as Function of CPU Clock and Baud Rate............................14-7

14-3 QMR Field Descriptions........................................................................................... 14-10

14-4 QDLYR Field Descriptions ...................................................................................... 14-11

14-5 QWR Field Descriptions........................................................................................... 14-12

14-6 QIR Field Descriptions.............................................................................................14-13

14-7 QCR0–QCR15 Field Descriptions............................................................................ 14-15

15-1 TMRn Field Descriptions ........................................................................................... 15-4

15-2 TERn Field Descriptions.............................................................................................15-6

16-1 UART Module Programming Model.......................................................................... 16-3

16-2 UMR1n Field Descriptions......................................................................................... 16-5

16-3 UMR2n Field Descriptions......................................................................................... 16-7

16-4 USRn Field Descriptions ............................................................................................ 16-8

16-5 UCSRn Field Descriptions.......................................................................................... 16-9

16-6 UCRn Field Descriptions..........................................................................................16-10

16-7 UIPCRn Field Descriptions ...................................................................................... 16-12

16-8 UACRn Field Descriptions....................................................................................... 16-13

16-9 UISRn/UIMRn Field Descriptions ........................................................................... 16-14

16-10 UTFn Field Descriptions...........................................................................................16-16

16-11 URFn Field Descriptions .......................................................................................... 16-17

16-12 UFPDn Field Descriptions........................................................................................16-17

16-13 UIPn Field Descriptions............................................................................................ 16-18

16-14 UOP1/UOP0 Field Descriptions............................................................................... 16-18

16-15 UART Module Signals ............................................................................................. 16-19

16-16 Transmitter FIFO Status Bits.................................................................................... 16-26

16-17 Receiver FIFO Status Bits ........................................................................................ 16-27

17-1 GPIO Signal Multiplexing.......................................................................................... 17-1

17-2 GPIO Port Register Memory Map.............................................................................. 17-2

17-3 PACNT Field Descriptions......................................................................................... 17-3

17-4 Port A Control Register Function Bits........................................................................ 17-4

17-5 PBCNT Field Descriptions.........................................................................................17-6

17-6 Port B Control Register Function Bits........................................................................ 17-7

17-7 PDCNT Field Descriptions......................................................................................... 17-8

17-8 Port D Control Register Function Bits........................................................................ 17-9

17-9 PADDR Field Descriptions.......................................................................................17-10

18-1 PWM Module Memory Map ...................................................................................... 18-2

18-2 PWCRn Field Descriptions......................................................................................... 18-3

18-3 PWWDn Field Descriptions ....................................................................................... 18-4

19-1 Signal Descriptions Sorted by Function ..................................................................... 19-1

19-2 Signal Name and Description by Pin Number............................................................19-9

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19-3 Byte Strobe Operation for 32-Bit Data Bus..............................................................19-18

19-4 Byte Strobe Operation for 16-Bit Data Bus..............................................................19-18

19-5 Connecting BS[3:0] to DQMx.................................................................................. 19-19

19-6 Processor Status Encoding........................................................................................19-35

19-7 MCF5272 Bus Width Selection................................................................................ 19-36

19-8 MCF5272 CS0 Memory Bus Width Selection ......................................................... 19-36

19-9 MCF5272 High Impedance Mode Selection ............................................................ 19-37

20-1 ColdFire Bus Signal Summary ................................................................................... 20-1

20-2 Chip Select Memory Address Decoding Priority ....................................................... 20-5

20-3 Data Bus Byte Strobes................................................................................................20-7

20-4 Data Bus Requirement for Read Cycles ..................................................................... 20-9

20-5 Internal to External Data Bus Multiplexer–Write Cycle ............................................ 20-9

20-6 External Bus Interface Codes for CSBRs................................................................. 20-10

21-1 JTAG Signals.............................................................................................................. 21-3

21-2 Instructions.................................................................................................................. 21-7

23-1 Maximum Supply, Input Voltage and Storage Temperature...................................... 23-1

23-2 Operating Temperature............................................................................................... 23-2

23-3 Thermal Resistance.....................................................................................................23-2

23-4 DC Electrical Specifications....................................................................................... 23-2

23-5 I/O Driver Capability.................................................................................................. 23-3

23-6 Clock Input and Output Timing Specifications..........................................................23-5

23-7 Processor Bus Input Timing Specifications................................................................23-6

23-8 Processor Bus Output Timing Specifications.............................................................23-8

23-9 Debug AC Timing Specification .............................................................................. 23-12

23-10 SDRAM Interface Timing Specifications................................................................. 23-13

23-11 MII Receive Signal Timing ...................................................................................... 23-15

23-12 MII Transmit Signal Timing.....................................................................................23-16

23-13 MII Async Inputs Signal Timing.............................................................................. 23-17

23-14 MII Serial Management Channel Timing................................................................. 23-17

23-15 Timer Module AC Timing Specifications ................................................................ 23-18

23-16 UART Modules AC Timing Specifications.............................................................. 23-19

23-17 IDL Master Mode Timing, PLIC Ports 1, 2, and 3................................................... 23-21

23-18 IDL Slave Mode Timing, PLIC Ports 0–3................................................................ 23-22

23-19 GCI Slave Mode Timing, PLIC Ports 0–3................................................................ 23-23

23-20 GCI Master Mode Timing, PLIC PORTs 1, 2, 3...................................................... 23-24

23-21 General-Purpose I/O Port AC Timing Specifications............................................... 23-26

23-22 USB Interface AC Timing Specifications.................................................................23-26

23-23 IEEE 1149.1 (JTAG) AC Timing Specifications ..................................................... 23-27

23-24 QSPI Modules AC Timing Specifications................................................................23-28

23-25 PWM Modules AC Timing Specifications............................................................... 23-29

A-1 On-Chip Module Base Address Offsets from MBAR................................................. A-1

A-2 CPU Space Registers Memory Map............................................................................ A-2

A-3 On-Chip Peripherals and Configuration Registers Memory Map............................... A-2

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A-4 Interrupt Control Register Memory Map..................................................................... A-3

A-5 Chip Select Register Memory Map..............................................................................A-3

A-6 GPIO Port Register Memory Map............................................................................... A-3

A-7 QSPI Module Memory Map........................................................................................ A-4

A-8 PWM Module Memory Map....................................................................................... A-4

A-9 DMA Module Memory Map........................................................................................A-4

A-10 UART0 Module Memory Map.................................................................................... A-5

A-11 UART1 Module Memory Map.................................................................................... A-6

A-12 SDRAM Controller Memory Map............................................................................... A-7

A-13 Timer Module Memory Map....................................................................................... A-7

A-14 PLIC Module Memory Map ........................................................................................ A-8

A-15 Ethernet Module Memory Map ................................................................................... A-9

A-16 USB Module Memory Map....................................................................................... A-10

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About This Book

The primary objective of this user’s manual is to deﬁne the functionality of the MCF5272 processors for use by software and hardware developers.

The information in this book is subject to change without notice, as described in the disclaimers on the title page of this book. As with any technical documentation, it is the readers’ responsibility to be sure he is using the most recent v ersion of the documentation.

T o locate an y published errata or updates for this document, refer to the world-wide web at http://www.motorola.com/coldﬁre.

Audience

This manual is intended for system software and hardware developers and applications programmers who want to develop products with the MCF5272. It is assumed that the reader understands operating systems, microprocessor system design, basic principles of software and hardware, and basic details of the ColdFire

Organization

Following is a summary and brief description of the major sections of this manual:

• Chapter 1, “Overview,” includes general descriptions of the modules and features incorporated in the MCF5272, focussing in particular on new features.

• Chapter 2, “ColdFire Core,” provides an ov erview of the microprocessor core of the MCF5272. The chapter describes the organization of the Version 2 (V2) ColdFire 5200 processor core and an overview of the program-visible registers (the programming model) as they are implemented on the MCF5272. It also includes a full description of exception handling and a table of instruction timings.

• Chapter 3, “Hardware Multiply/Accumulate (MAC) Unit, ” describes the MCF5272 multiply/accumulate unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. The MAC is integrated into the operand execution pipeline (OEP).

• Chapter 4, “Local Memory.” This chapter describes the MCF5272 implementation of the ColdFire V2 local memory speciﬁcation. It consists of three major sections, as follows.

architecture.

About This Book xxxix

Page 40

Organization

— Section 4.3, “SRAM Overview,” describes the MCF5272 on-chip static RAM

(SRAM) implementation. It covers general operations, conﬁguration, and initialization. It also provides information and examples of how to minimize power consumption when using the SRAM.

— Section 4.4, “ROM Overview,” describes the MCF5272 on-chip static ROM.

The ROM module contains tabular data that the ColdFire core can access in a single cycle.

— Section 4.5, “Instruction Cache Overview,” describes the MCF5272 cache

implementation, including organization, conﬁguration, and coherency. It describes cache operations and how the cache interacts with other memory structures.

• Chapter 5, “Debug Support,” describes the Revision A hardware debug support in the MCF5272.

• Chapter 6, “System Integration Module (SIM),” describes the SIM programming model, bus arbitration, power management, and system-protection functions for the MCF5272.

• Chapter 7, “Interrupt Controller,” describes operation of the interrupt controller portion of the SIM. Includes descriptions of the registers in the interrupt controller memory map and the interrupt priority scheme.

• Chapter 8, “Chip Select Module,” describes the MCF5272 chip-select implementation, including the operation and programming model, which includes the chip-select address, mask, and control registers.

• Chapter 9, “SDRAM Controller,” describes conﬁguration and operation of the synchronous DRAM controller component of the SIM, including a general description of signals involved in SDRAM operations. It provides interface information for memory conﬁgurations using most common SDRAM devices for both 16- and 32-bit-wide data buses. The chapter concludes with signal timing diagrams.

• Chapter 10, “DMA Controller,” provides an overview of the MCF5272’s one-channel DMA controller intended for memory-to-memory block data transfers. This chapter describes in detail its signals, registers, and operating modes.

• Chapter 11, “Ethernet Module,” describes the MCF5272 fast Ethernet media access controller (MAC). This chapter begins with a feature-set overview, a functional block diagram, and transceiver connection information for both MII and se ven-wire serial interfaces. The chapter concludes with detailed descriptions of operation and the programming model.

• Chapter 12, “Universal Serial Bus (USB), ” provides an o verview of the USB module of the MCF5272, including detailed operation information and the USB programming model. Connection examples and circuit board layout considerations are also provided.

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Organization

The USB Speciﬁcation, Revision 1.1 is a recommended supplement to this chapter. It can be downloaded from http://www.usb.org. Chapter 2 of this speciﬁcation, Terms and Abbreviations, provides deﬁnitions of many of the words found here.

• Chapter 13, “Physical Layer Interface Controller (PLIC),” provides detailed information about the MCF5272’s physical layer interface controller, a module intended to support ISDN applications. The chapter begins with a description of operation and a series of related block diagrams starting with a high-level ov erview. Each successive diagram depicts progressively more internal detail. The chapter then describes timing generation and the programming model and concludes with three application examples.

• Chapter 14, “Queued Serial Peripheral Interface (QSPI) Module,” provides a feature-set overview and description of operation, including details of the QSPI’s internal RAM organization. The chapter concludes with the programming model and a timing diagram.

• Chapter 15, “Timer Module,” describes conﬁguration and operation of the four general-purpose timer modules, timer 0, 1, 2 and 3.

• Chapter 16, “UART Modules,” describes the use of the universal asynchronous/synchronous receiver/transmitters (UARTs) implemented on the MCF5272, including example register values for typical conﬁgurations.

• Chapter 17, “General Purpose I/O Module,” describes the operation and programming model of the three general purpose I/O (GPIO) ports on the MCF5272. The chapter details pin assignment, direction-control, and data registers.

• Chapter 18, “Pulse Width Modulation (PWM) Module, ” describes the conﬁguration and operation of the pulse width modulation (PWM) module. It includes a block diagram, programming model, and timing diagram.

• Chapter 19, “Signal Descriptions,” provides a listing and brief description of all the MCF5272 signals. Speciﬁcally, it shows which are inputs or outputs, how they are multiplexed, and the state of each signal at reset. The ﬁrst listing is organized by function, with signals appearing alphabetically within each functional group. This is followed by a second listing sorted by pin number.

• Chapter 20, “Bus Operation,” describes the functioning of the bus for data-transfer operations, error conditions, bus arbitration, and reset operations. It includes detailed timing diagrams showing signal interaction. Operation of the bus is deﬁned for transfers initiated by the MCF5272 as a bus master. The MCF5272 does not support external bus masters. Note that Chapter 9, “SDRAM Controller, ” describes DRAM cycles.

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Page 42

1.1 MCF5272 Key Features

A block diagram of the MCF5272 is shown in Figure 1-1. The main features are as follows:

• Static Version 2 ColdFire variable-length RISC processor — 32-bit address and data path on-chip — 66-MHz processor core and bus frequency — Sixteen general-purpose 32-bit data and address registers — Multiply-accumulate unit (MAC) for DSP and fast multiply operations

• On-chip memories — 4-Kbyte SRAM on CPU internal bus — 16-Kbyte ROM on CPU internal bus — 1-Kbyte instruction cache

• Power management — Fully-static operation with processor sleep and whole-chip stop modes — Very rapid response to interrupts from the low-power sleep mode (wake-up

feature) — Clock enable/disable for each peripheral when not used — Software-controlled disable of external clock input for virtually zero power

consumption (low-power stop mode)

• Two universal asynchronous/synchronous receiver transmitters (UARTs) — Full-duplex operation — Based on MC68681 dual-UART (DUART) programming model — Flexible baud rate generator — Modem control signals available (CTS — Processor interrupt and wake-up capability — Enhanced Tx, Rx FIFOs, 24 bytes each

and RTS)

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MCF5272 Key Features

JTAG

V2 ColdFire Processor Complex

Instruction Unit

IFP

Instruction Address Generation

Instruction Fetch

FIFO Instruction Buffer (3 X 32)

OEP

Decode, Select, Operand Fetch

Address Generation, Execute

RAMBAR

Local

Memory

Instruction

Bus

ROMBAR

Instruction Cache

ACR0 ACR1

SYSTEM INTEGRATION MODULE (SIM)

System Control Base Address

SCR WCR SPR

SDRAM Controller External

WIRRALPR

WER

Chip Select Module

WRRR

PMR

SDRAM Control

SDCR

CSORs CSBRs

MBAR

Identification

Bus Interface

SDRAM Timer

SDTR

DRAM Controller Outputs

CS[7:0]

Control Signals

Figure 1-1. MCF5272 Block Diagram

Local Memory

SRAM Controller

4-Kbyte

SRAM

ROM Controller

16-Kbyte

ROM

Controller

CACR

1-Kbyte

Cache

DIR

32-Bit Address Bus

PACNT–

PDCNT

32-Bit Data Bus

Local Memory Data Bus

4-Entry Store Buffer

Parallel Port

PADDR–

PCDDR

PADR–

PCDR

Interrupt Controller

4 ICRs

ISR PITR PIWR PIVR

[6:1]

INT

D[31:0]

PLIC

QSPI

DMA

USB

PWM

Ethernet

Two UARTs

Four GeneralPurpose

Timers

1-2 MCF5272 User’s Manual

Page 51

MCF5272 Key Features

• Ethernet Module — 10 baseT capability, half- or full-duplex — 100 baseT capability , half duplex and limited throughput full-duplex (MCF5272) — On-chip transmit and receive FIFOs — Off-chip ﬂexible buffer descriptor rings — Media-independent interface (MII)

• Universal serial bus (USB) module — 12 Mbps (full-speed) — Fully compatible with USB 1.1 speciﬁcations — Eight endpoints (control, bulk, interrupt Rx, isochronous) — Endpoint FIFOs — Selectable on-chip analog interface

• External memory interface — External glueless 8, 16, and 32-bit SRAM and ROM interface bus — SDRAM controller supports 16–256 Mbit devices — External bus conﬁgurable for 16 or 32 bits width for SDRAM — Glueless interface to SRAM devices with or without byte strobe inputs — Programmable wait state generator

• Queued serial peripheral interface (QSPI) — Full-duplex, three-wire synchronous transfer — Up to four chip selects available — Master operation — Programmable master bit rates — Up to 16 preprogrammed transfers

• Timer module — 4x16-bit general-purpose multi-mode timer

– Input capture and output compare pins for timers 1 and 2

– Programmable prescaler — 15-nS resolution at 66-MHz clock frequency — Software watchdog timer — Software watchdog can generate interrupt before reset — Processor interrupt for each timer

• Pulse width modulation (PWM) unit — Three identical channels — Independent prescaler TAP point — Period/duty range variable

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MCF5272 Architecture

• System integration module (SIM) — System conﬁguration including internal and external address mapping — System protection by hardware watchdog — Versatile programmable chip select signals with wait state generation logic — Up to three 16-bit parallel input/output ports — Latchable interrupt inputs with programmable priority and edge triggering — Programmable interrupt vectors for on-chip peripherals

• Physical layer interface controller (PLIC) — Allows connection using general circuit interface (GCI) or interchip digital link

(IDL) physical layer protocols for 2B + D data — Three physical interfaces — Four time-division multiplex (TDM) ports

• IEEE 1149.1 boundary-scan test access port (JTAG) for board-level testing

• Operating voltage: 3.3 V ±0.3 V

• Operating temperature: 0

–70

• Operating frequency: DC to 66 MHz, from external CMOS oscillator

• Compact ultra low-proﬁle 196 ball-molded plastic ball-grid array package (PGBA)

1.2 MCF5272 Architecture

This section brieﬂy describes the MCF5272 core, SIM, UART , and timer modules, and test access port.

1.2.1 Version 2 ColdFire Core

Based on the concept of variable-length RISC technology, ColdFire combines the simplicity of conventional 32-bit RISC architectures with a memory-saving, variable-length instruction set. The main features of the MCF5272 core are as follows:

• 32-bit address bus directly addresses up to 4 Gbytes of address space

• 32-bit data bus

• Variable-length RISC

• Optimized instruction set for high-level language constructs

• Sixteen general-purpose 32-bit data and address registers

• MAC unit for DSP applications

• Supervisor/user modes for system protection

• Vector base register to relocate exception-vector table

• Special core interfacing signals for integrated memories

• Full debug support

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MCF5272 Architecture

The Version 2 ColdFire core has a 32-bit address bus and a 32-bit data bus. The address bus allows direct addressing of up to 4 Gbytes. It supports misaligned data accesses and a bus arbitration unit for multiple bus masters.

The Version 2 ColdFire supports an enhanced subset of the 68000 instruction set. The MAC provides new instructions for DSP applications; otherwise, Version 2 ColdFire user code runs unchanged on 68020, 68030, 68040, and 68060 processors. The removed instructions include BCD, bit ﬁeld, logical rotate, decrement and branch, integer division, and integer multiply with a 64-bit result. Also, four indirect addressing modes have been eliminated.

The ColdFire 2 core incorporates a complete debug module that provides real-time trace, background debug mode, and real-time debug support.

1.2.2 System Integration Module (SIM)

The MCF5272 SIM provides the external bus interface for the ColdFire 2 architecture. It also eliminates most or all of the glue logic that typically supports the microprocessor and its interface with the peripheral and memory system. The SIM provides programmable circuits to perform address-decoding and chip selects, wait-state insertion, interrupt handling, clock generation, discrete I/O, and power management features.

1.2.2.1 External Bus Interface

The external bus interface (EBI) handles the transfer of information between the internal core and memory , peripherals, or other processing elements in the external address space.

1.2.2.2 Chip Select and Wait State Generation

Programmable chip select outputs provide signals to enable external memory and peripheral circuits, providing all handshaking and timing signals for automatic wait-state insertion and data bus sizing.

Base memory address and block size are programmable, with some restrictions. For example, the starting address must be on a boundary that is a multiple of the block size. Each chip select is general purpose; however, any one of the chip selects can be programmed to provide read and write enable signals suitable for use with most popular static RAMs and peripherals. Data bus width (8-bit, 16-bit, or 32-bit) is programmable on all chip selects, and further decoding is available for protection from user mode access or read-only access.

1.2.2.3 System Conﬁguration and Protection

The SIM provides conﬁguration registers that allow general system functions to be controlled and monitored. For example, all on-chip registers can be relocated as a block by programming a module base address, power management modes can be selected, and the source of the most recent RESET or BERR can be checked. The hardware watchdog features can be enabled or disabled, and the bus time-out period can be programmed.

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MCF5272 Architecture

A software watchdog timer is also provided for system protection. If programmed, the timer causes a reset to the MCF5272 if it is not refreshed periodically by software.

1.2.2.4 Power Management

The sleep and stop power management modes reduce power consumption by allowing software to shut down the core, peripherals, or the whole device during inacti v e periods. To reduce power consumption further , software can individually disable internal clocks to the on-chip peripheral modules. The power-saving modes are described as follows:

• Sleep mode uses interrupt control logic to allow any interrupt condition to wake the processor. As the MCF5272 is fully static, sleep mode is simply the disabling of the core’s clock after the current instruction completes. An interrupt from any internal or external source causes on-chip power management logic to reenable the core’s clock; execution resumes with the next instruction. This allows rapid return from power-down state as compared to a dynamic implementation that must perform power-on reset processing before software can handle the interrupt request. If interrupts are enabled at the appropriate priority level, program control passes to the relevant interrupt service routine.

• Stop mode is entered by the disabling of the external clock input and is achieved by software setting a bit in a control register . Program e xecution stops after the current instruction. In stop mode, neither the core nor peripherals are active. The MCF5272 consumes very little power in this mode. To resume normal operation, the external interrupts cause the power management logic to re-enable the external clock input. The MCF5272 resumes program execution from where it entered stop mode (if no interrupt are pending), or starts interrupt exception processing if interrupts are pending.

1.2.2.5 Parallel Input/Output Ports

The MCF5272 has up to three 16-bit general-purpose parallel ports, each line of which can be programmed as either an input or output. Some port lines have dedicated pins and others are shared with other MCF5272 functions. Some outputs have high driv e current capability .

1.2.2.6 Interrupt Inputs

The MCF5272 has ﬂexible latched interrupt inputs each of which can generate a separate, maskable interrupt with programmable interrupt priority level and triggering edge (falling or rising). Each interrupt has its own interrupt vector.

1.2.3 UART Module

The MCF5272 has two full-duplex UART modules with an on-chip baud rate generator providing both standard and non-standard baud rates up to 5 Mbps. The module is functionally equivalent to the MC68681 DU ART with enhanced features including 24-byte Tx and Rx FIFOs. Data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity and up

1-6

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System Design

to 2 stop bits in 1/16-bit increments. Receive and transmit FIFOs minimize CPU service calls. A wide variety of error detection and maskable interrupt capability is provided.

Using a programmable prescaler or an external source, the MCF5272 system clock supports various baud rates. Modem support is provided with request-to-send (R clear-to-send (CTS loopback, and remote loopback modes can be selected.

The UART can be programmed to interrupt or wake-up the CPU on various normal or abnormal events. To reduce power consumption, the UART can be disabled by software if not in use.

) lines available externally. Full-duplex autoecho loopback, local

TS) and

1.2.4 Timer Module

The timer module contains ﬁve timers arranged in two submodules. One submodule contains a programmable software watchdog timer. The other contains four independent, identical general-purpose timer units, each containing a free-running 16-bit timer for use in various modes, including capturing the timer value with an external event, counting external events, or triggering an external signal or interrupting the CPU when the timer reaches a set value. Each unit has an 8-bit prescaler for deriving the clock input frequency from the system clock or external clock input. The output pin associated with each timer has programmable modes.

To reduce power consumption, the timer module can be disabled by software.

1.2.5 Test Access Port

For system diagnostics and manufacturing testing, the MCF5272 includes user-accessible test logic that complies with the IEEE 1149.1 standard for boundary scan testing, often referred to as JTAG (Joint Test Action Group). The IEEE 1149.1 Standard provides more information.

1.3 System Design

This section presents issues to consider when designing with the MCF5272. It describes differences between the MCF5272 (core and peripherals) and various other standard components that are replaced by moving to an integrated device like the MCF5272.

1.3.1 System Bus Conﬁguration

The MCF5272 has ﬂexibility in its system bus interfacing due to the dynamic bus sizing feature in which 32-,16-, and 8-bit data bus sizes are programmable on a per-chip select basis. The programmable nature of the strobe signals (including OE CS

) should ensure that external decode logic is minimal or nonexistent. Conﬁguration

software is required upon power-on reset before chip-selected devices can be used, except

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/RD, R/W , BS[3:0], and

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MCF5272-Speciﬁc Features

for chip select 0 (CS0 BUSW1 and BUSW0 select the initial data bus width for CS0 mode or a restart from stop mode does not require reconﬁguration of the chip select registers or other system conﬁguration registers.

), which is active after power-on reset until programmed otherwise.

only . A wake-up from sleep

1.4 MCF5272-Speciﬁc Features

This section describes features peculiar to the MCF5272.

1.4.1 Physical Layer Interface Controller (PLIC)

The physical layer interface controller (PLIC) allows the MCF5272 to connect at a physical level with external CODECs and other peripheral de vices that use either the general circuit interface (GCI), or interchip digital link (IDL), physical layer protocols. This module is primarily intended to facilitate designs that include ISDN interfaces.

1.4.2 Pulse-Width Modulation (PWM) Unit

The PWM unit is intended for use in control applications. W ith a suitable low-pass ﬁlter, it can be used as a digital-to-analog converter. This module generates a synchronous series of pulses. The duty cycle of the pulses is under software control.

Its main features include the following:

• Double-buffered width register

• Variable-divide prescale

• Three identical, independent PWM modules

• Byte-wide width register provides programmable control of duty cycle.

The PWM implements a simple free-running counter with a width register and comparator such that the output is cleared when the counter exceeds the value of the width register. When the counter wraps around, its value is not greater than the width register value, and the output is set high. With a suitable low-pass ﬁlter, the PWM can be used as a digital-to-analog converter.

1.4.3 Queued Serial Peripheral Interface (QSPI)

The QSPI module provides a serial peripheral interface with queued transfer capability. It supports up to 16 stacked transfers at a time, making CPU intervention between transfers unnecessary. Transfer RAMs in the QSPI are indirectly accessible using address and data registers. Functionality is similar to the QSPI portion of the QSM (queued serial module) implemented in the MC68332.

The QSPI has the following features:

• Programmable queue to support up to 16 transfers without user intervention

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MCF5272-Speciﬁc Features

• Supports transfer sizes of 8 to 16 bits in 1-bit increments

• Four peripheral chip-select lines for control of up to 15 devices

• Baud rates from 129.4 Kbps to 33 Mbps at 66 MHz.

• Programmable delays before and after transfers

• Programmable clock phase and polarity

• Supports wrap-around mode for continuous transfers

1.4.4 Universal Serial Bus (USB) Module

The USB controller on the MCF5272 supports device mode data communications with a USB host (typically a PC). One host and up to 127 attached peripherals share USB bandwidth through a host-scheduled, token-based protocol. The USB uses a tiered star topology with a hub at the center of each star. Each wire segment is a point-to-point connection between the host connector and a peripheral connector.

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Chapter 2 ColdFire Core

This chapter provides an overview of the microprocessor core of the MCF5272. The chapter describes the V2 programming model as it is implemented on the MCF5272. It also includes a full description of exception handling, data formats, an instruction set summary , and a table of instruction timings.

2.1 Features and Enhancements

The MCF5272 is the most highly-integrated V2 standard product, containing a variety of communications and general-purpose peripherals. The V2 core was designed to maximize code density and performance while minimizing die area.

The following list summarizes MCF5272 features:

• Variable-length RISC Version 2 microprocessor core

• Two independent, decoupled pipelines—two-stage instruction fetch pipeline (IFP) and two-stage operand execution pipeline (OEP)

• Three longword FIFO buffer provides decoupling between the pipelines

• 32-bit internal address bus supporting 4 Gbytes of linear address space

• 32-bit data bus

• 16 user-accessible, 32-bit-wide, general-purpose registers

• Supervisor/user modes for system protection

• Vector base register to relocate exception-vector table

• Optimized for high-level language constructs

2.1.1 Decoupled Pipelines

The IFP prefetches instructions. The OEP decodes instructions, fetches required operands, then executes the speciﬁed function. The two independent, decoupled pipeline structures maximize performance while minimizing core size. Pipeline stages are shown in Figure 2-1 and are summarized as follows:

• Two-stage IFP (plus optional instruction buffer stage) — Instruction address generation (IAG) calculates the next prefetch address.

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Features and Enhancements

— Instruction fetch cycle (IC) initiates prefetch on the processor’ s local instruction

bus.

— Instruction buffer (IB) optional stage uses FIFO queue to minimize effects of

fetch latency.

• Two-stage OEP — Decode, select/operand fetch (DSOC) decodes the instruction and selects the

required components for the effective address calculation, or the operand fetch cycle.

— Address generation/execute (A GEX) calculates the operand address, or performs

the execution of the instruction.

Instruction

IAG

Address

Generation

Instruction

Fetch Cycle

Address [31:0]

Instruction Fetch Pipeline

FIFO

Instruction Buffer

Decode & Select,

Operand Fetch

Data[31:0]

Operand

DSOC

Execution Pipeline

AGEX

Address

Generation,

Execute

Figure 2-1. ColdFire Pipeline

2.1.1.1 Instruction Fetch Pipeline (IFP)

The IFP generates instruction addresses and fetches. Because the fetch and execution pipelines are decoupled by a 3 longword FIFO buffer, the IFP can prefetch instructions before the OEP needs them, minimizing stalls.

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2.1.1.2 Operand Execution Pipeline (OEP)

The OEP is a two-stage pipeline featuring a traditional RISC datapath with a register ﬁle feeding an arithmetic/logic unit (ALU). For simple register-to-re gister instructions, the ﬁrst stage of the OEP performs the instruction decode and fetching of the required register operands (OC), while the actual instruction execution is performed in the second stage (EX).

For memory-to-register instructions, the instruction is effectively staged through the OEP twice in the following way:

• The instruction is decoded and the components of the operand address are selected (DS).

• The operand address is generated using the execute engine (AG).

• The memory operand is fetched while any register operand is simultaneously fetched (OC).

• The instruction is executed (EX).

For register-to-memory operations, the stage functions (DS/OC, AG/EX) are effectively performed simultaneously allowing single-cycle execution. For read-modify-write instructions, the pipeline effectiv ely combines a memory-to-register operation with a store operation.

2.1.1.2.1 Illegal Opcode Handling

2.1.1.2.2 Hardware Multiply/Accumulate (MAC) Unit

The MAC is an optional unit in Version 2 that provides hardware support for a limited set of digital signal processing (DSP) operations used in embedded code, while supporting the integer multiply instructions in the ColdFire microprocessor family. The MAC features a three-stage execution pipeline, optimized for 16 x 16 multiplies. It is tightly coupled to the OEP, which can issue a 16 x 16 multiply with a 32-bit accumulation plus fetch a 32-bit operand in a single cycle. A 32 x 32 multiply with a 32-bit accumulation requires three cycles before the next instruction can be issued.

Figure 2-2 shows basic functionality of the MAC. A full set of instructions are pro vided for signed and unsigned integers plus signed, ﬁxed-point fractional input operands.

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Features and Enhancements

Operand Y Operand X

Shift 0,1,-1

+/-

Accumulator

Figure 2-2. ColdFire Multiply-Accumulate Functionality Diagram

The MAC provides functionality in the following three related areas, which are described in detail in Chapter 3, “Hardware Multiply/Accumulate (MAC) Unit.”

• Signed and unsigned integer multiplies

• Multiply-accumulate operations with signed and unsigned fractional operands

• Miscellaneous register operations

2.1.1.2.3 Hardware Divide Unit

The hardware divide unit performs the following integer division operations:

• 32-bit operand/16-bit operand producing a 16-bit quotient and a 16-bit remainder

• 32-bit operand/32-bit operand producing a 32-bit quotient

• 32-bit operand/32-bit operand producing a 32-bit remainder

2.1.2 Debug Module Enhancements

The ColdFire processor core debug interface supports system integration in conjunction with low-cost development tools. Real-time trace and debug information can be accessed through a standard interface, which allows the processor and system to be debugged at full speed without costly in-circuit emulators. On-chip breakpoint resources include the following:

• Conﬁguration/status register (CSR)

• Bus attributes and mask register (AATR)

• Breakpoint registers. These can be used to deﬁne triggers combining address, data, and PC conditions in single- or dual-level deﬁnitions. They include the following:

— PC breakpoint register (PBR) — PC breakpoint mask register (PBMR)

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— Data operand address breakpoint registers (ABHR/ABLR) — Data breakpoint register (DBR)

• Data breakpoint mask register (DBMR)

• Trigger deﬁnition register (TDR) can be programmed to generate a processor halt or initiate a debug interrupt exception.

These registers can be accessed through the dedicated debug serial communication channel, or from the processor’s supervisor programming model, using the WDEBUG instruction.

2.2 Programming Model

The MCF5272 programming model consists of three instruction and register groups—user, MAC (also user-mode), and supervisor, shown in Figure 2-2. User mode programs are restricted to user and MAC instructions and programming models. Supervisor-mode system software can reference all user-mode and MAC instructions and registers and additional supervisor instructions and control registers. The user or supervisor programming model is selected based on SR[S]. The following sections describe the registers in the user, MAC, and supervisor programming models.

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Programming Model

User Registers

Supervisor

Registers

31 0

31 19

(CCR) SR Status register

Must be zeros VBR Vector base register

D0 Data registers D1 D2 D3 D4 D5 D6 D7

A0 Address registers A1 A2 A3 A4 A5 A6 A7 Stack pointer PC Program counter CCR Condition code register

MACSR MAC status register ACC MAC accumulator MASK MAC mask register

CACR Cache control register ACR0 Access control register 0 ACR1 Access control register 1 ROMBAR ROM base address register RAMBAR RAM base address register MBAR Module base address register

Figure 2-3. ColdFire Programming Model

2.2.1 User Programming Model

As Figure 2-3 shows, the user programming model consists of the following registers:

• 16 general-purpose 32-bit registers, D0–D7 and A0–A7

• 32-bit program counter

• 8-bit condition code register

2.2.1.1 Data Registers (D0–D7)

Registers D0–D7 are used as data registers for bit, byte (8-bit), word (16-bit), and longword (32-bit) operations. They may also be used as index registers.

2.2.1.2 Address Registers (A0–A6)

The address registers (A0–A6) can be used as software stack pointers, index registers, or base address registers and may be used for word and longword operations.

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2.2.1.3 Stack Pointer (A7, SP)

The processor core supports a single hardware stack pointer (A7) used during stacking for subroutine calls, returns, and exception handling. The stack pointer is implicitly referenced by certain operations and can be explicitly referenced by any instruction specifying an address register. The initial value of A7 is loaded from the reset exception vector, address 0x0000. The same register is used for user and supervisor modes, and may be used for word and longword operations.

A subroutine call saves the program counter (PC) on the stack and the return restores the PC from the stack. The PC and the status register (SR) are saved on the stack during exception and interrupt processing. The return from exception instruction restores SR and PC values from the stack.

2.2.1.4 Program Counter (PC)

The PC holds the address of the executing instruction. For sequential instructions, the processor automatically increments PC. When program ﬂow changes, the PC is updated with the target instruction. For some instructions, the PC speciﬁes the base address for PC-relative operand addressing modes.

2.2.1.5 Condition Code Register (CCR)

The CCR, Figure 2-4, occupies SR[7–0], as shown in Figure 2-3. CCR[4–0] are indicator ﬂags based on results generated by arithmetic operations.

76543210

Field — X N Z V C

Reset 000 Undeﬁned

R/W R R/W R/W R/W R/W R/W

Figure 2-4. Condition Code Register (CCR)

CCR ﬁelds are described in Table 2-1.

Table 2-1. CCR Field Descriptions

Bits Name Description

7–5 — Reserved, should be cleared.

4 X Extend condition code bit. Assigned the value of the carry bit for arithmetic operations; otherwise not

3 N Negative condition code bit. Set if the msb of the result is set; otherwise cleared. 2 Z Zero condition code bit. Set if the result equals zero; otherwise cleared. 1 V Overﬂow condition code bit. Set if an arithmetic overﬂow occurs, implying that the result cannot be

0 C Carry condition code bit. Set if a carry-out of the data operand msb occurs for an addition or if a

affected or set to a speciﬁed result. Also used as an input operand for multiple-precision arithmetic.

represented in the operand size; otherwise cleared.

borrow occurs in a subtraction; otherwise cleared.

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Programming Model

2.2.1.6 MAC Programming Model

Figure 2-3 shows the registers in the MAC portion of the user programming model. These registers are described as follows:

• Accumulator (ACC)—This 32-bit, read/write, general-purpose register is used to accumulate the results of MAC operations.

• Mask register (MASK)—This 16-bit general-purpose register provides an optional address mask for MAC instructions that fetch operands from memory. It is useful in the implementation of circular queues in operand memory.

• MAC status register (MACSR)—This 8-bit register deﬁnes conﬁguration of the MAC unit and contains indicator ﬂags af fected by MAC instructions. Unless noted otherwise, MACSR indicator ﬂag settings are based on the ﬁnal result, that is, the result of the ﬁnal operation involving the product and accumulator.

2.2.2 Supervisor Programming Model

The MCF5272 supervisor programming model is shown in Figure 2-3. Typically, system programmers use the supervisor programming model to implement operating system functions and provide memory and I/O control. The supervisor programming model provides access to the user registers and additional supervisor registers, which include the upper byte of the status register (SR), the vector base register (VBR), and registers for conﬁguring attributes of the address space connected to the Version 2 processor core. Most supervisor-mode registers are accessed by using the MOVEC instruction with the control register deﬁnitions in Table 2-2.

Table 2-2. MOVEC Register Map

Rc[11–0] Register Deﬁnition

0x002 Cache control register (CACR) 0x004 Access control register 0 (ACR0) 0x005 Access control register 1 (ACR1) 0x801 Vector base register (VBR) 0xC00 ROM base address register 0xC04 RAM base address register (RAMBAR) 0xC0F Module base address register (MBAR)

2.2.2.1 Status Register (SR)

The SR stores the processor status, the interrupt priority mask, and other control bits. Supervisor software can read or write the entire SR; user software can read or write only SR[7–0], described in Section 2.2.1.5, “Condition Code Register (CCR).” The control bits indicate processor states—trace mode (T), supervisor or user mode (S), and master or interrupt state (M). SR is set to 0x27xx after reset.

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15 8 7 0

System byte Condition code register (CCR)

Field T — S M — I — X N Z V C

Reset 00100 111 000 —————

R/W R/W R R/W R/W R R/W R R/W R/W R/W R/W R/W

Figure 2-5. Status Register (SR)

Table 2-3 describes SR ﬁelds.

Table 2-3. Status Field Descriptions

Bits Name Description

15 T Trace enable. When T is set, the processor performs a trace exception after every instruction. 13 S Supervisor/user state. Indicates whether the processor is in supervisor or user mode

12 M Master/interrupt state. Cleared by an interrupt exception. It can be set by software during execution

10–8 I Interrupt priority mask. Deﬁnes the current interrupt priority. Interrupt requests are inhibited for all

7–0 CCR Condition code register. See Table 2-4.

0 User mode 1 Supervisor mode

of the RTE or move to SR instructions so the OS can emulate an interrupt stack pointer.

priority levels less than or equal to the current priority, except the edge-sensitive level-7 request, which cannot be masked.

2.2.2.2 Vector Base Register (VBR)

The VBR holds the base address of the exception vector table in memory . The displacement of an exception vector is added to the value in this register to access the vector table. VBR[19–0] are not implemented and are assumed to be zero, forcing the vector table to be aligned on a 0-modulo-1-Mbyte boundary.

31 20 19 0

Field Exception vector table base address —

Reset 0000_0000_0000_0000_0000_0000_0000_0000

R/W Written from a BDM serial command or from the CPU using the MOVEC instruction. VBR can be read from

Rc[11–0] 0x801

the debug module only. The upper 12 bits are returned, the low-order 20 bits are undeﬁned.

Figure 2-6. Vector Base Register (VBR)

2.2.2.3 Cache Control Register (CACR)

The CACR controls operation of both the instruction and data cache memory. It includes bits for enabling, freezing, and inv alidating cache contents. It also includes bits for deﬁning the default cache mode and write-protect ﬁelds. See Section 4.5.3.1, “Cache Control Register (CACR).”

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Integer Data Formats

2.2.2.4 Access Control Registers (ACR0–ACR1)

The access control registers (ACR0–ACR1) deﬁne attributes for two user-deﬁned memory regions. Attributes include deﬁnition of cache mode, write protect and buf fer write enables. See Section 4.5.3.2, “Access Control Registers (ACR0 and ACR1).”

2.2.2.5 ROM Base Address Register (ROMBAR)

The ROMBAR base address register determines the base address of the internal ROM module and indicates the types of references mapped to it. The ROMBAR includes a base address, write-protect bit, address space mask bits, and an enable. Note that the MCF5272 ROM contains data for the HDLC module and is not user programmable. See Section 4.4.2.1, “ROM Base Address Register (ROMBAR).”

2.2.2.6 RAM Base Address Register (RAMBAR)

The RAMBAR register determines the base address location of the internal SRAM module and indicates the types of references mapped to it. The RAMBAR includes a base address, write-protect bit, address space mask bits, and an enable. The RAM base address must be aligned on a 0-modulo-4-Kbyte boundary. See Section 4.3.2.1, “SRAM Base Address Register (RAMBAR).”

2.2.2.7 Module Base Address Register (MBAR)

The module base address register (MBAR) deﬁnes the logical base address for the memory-mapped space containing the control registers for the on-chip peripherals. See Section 6.2.2, “Module Base Address Register (MBAR).”

2.3 Integer Data Formats

Table 2-4 lists the integer operand data formats. Integer operands can reside in registers, memory, or instructions. The operand size for each instruction is either explicitly encoded in the instruction or implicitly deﬁned by the instruction operation.

Table 2-4. Integer Data Formats

Operand Data Format Size

Bit 1 bit Byte integer 8 bits Word integer 16 bits Longword integer 32 bits

2.4 Organization of Data in Registers

The following sections describe data organization within the data, address, and control registers.

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Organization of Data in Registers

2.4.1 Organization of Integer Data Formats in Registers

Figure 2-7 shows the integer format for data registers. Each integer data register is 32 bits wide. Byte and word operands occupy the lower 8- and 16-bit portions of integer data registers, respectively. Longword operands occupy the entire 32 bits of integer data registers. A data re gister that is either a source or destination operand only uses or changes the appropriate lower 8 or 16 bits in byte or word operations, respectively. The remaining high-order portion does not change. The least signiﬁcant bit (lsb) of all integer sizes is zero, the most-signiﬁcant bit (msb) of a longword integer is 31, the msb of a word integer is 15, and the msb of a byte integer is 7.

31 30 1 0

msb lsb Bit (0 ≤ bit number ≤ 31)

31 8 7 6 1 0

Not used msb Low order byte lsb Byte (8 bits)

31 16 15 14 1 0

Not used msb Lower order word lsb Word (16 bits)

31 30 1 0

msb Longword lsb Longword (32 bits)

Figure 2-7. Organization of Integer Data Formats in Data Registers

The instruction set encodings do not allow the use of address registers for byte-sized operands. When an address register is a source operand, either the low-order word or the entire longword operand is used, depending on the operation size. Word-length source operands are sign-extended to 32 bits and then used in the operation with an address register destination. When an address register is a destination, the entire register is affected, regardless of the operation size. Figure 2-8 shows integer formats for address registers.

31 16 15 0

Sign-Extended 16-Bit Address Operand

31 0

Full 32-Bit Address Operand

Figure 2-8. Organization of Integer Data Formats in Address Registers

The size of control registers varies according to function. Some have undeﬁned bits reserved for future deﬁnition by Motorola. Those particular bits read as zeros and must be written as zeros for future compatibility.

All operations to the SR and CCR are word-size operations. For all CCR operations, the upper byte is read as all zeros and is ignored when written, regardless of privilege mode.

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Addressing Mode Summary

2.4.2 Organization of Integer Data Formats in Memory

All ColdFire processors use a big-endian addressing scheme. The byte-addressable organization of memory allows lower addresses to correspond to higher order bytes. The address N of a longword data item corresponds to the address of the high-order word. The lower order word is located at address N + 2. The address N of a word data item corresponds to the address of the high-order byte. The lower order byte is located at address N + 1. This organization is shown in Figure 2-9.

31 24 23 16 15 8 7 0

Longword 0x0000_0000

Word 0x0000_0000 Word 0x0000_0002

Byte 0x0000_0000 Byte 0x0000_0001 Byte 0x0000_0002 Byte 0x0000_0003

Longword 0x0000_0004

Word 0x0000_0004 Word 0x0000_0006

Byte 0x0000_0004 Byte 0x0000_0005 Byte 0x0000_0006 Byte 0x0000_0007

. . .

Longword 0xFFFF_FFFC

Word 0xFFFF_FFFC Word 0xFFFF_FFFE

Byte 0xFFFF_FFFC Byte 0xFFFF_FFFD Byte 0xFFFF_FFFE Byte 0xFFFF_FFFF

Figure 2-9. Memory Operand Addressing

2.5 Addressing Mode Summary

Addressing modes are categorized by how they are used. Data addressing modes refer to data operands. Memory addressing modes refer to memory operands. Alterable addressing modes refer to alterable (writable) data operands. Control addressing modes refer to memory operands without an associated size.

These categories sometimes combine to form more restrictive categories. Two combined classiﬁcations are alterable memory (both alterable and memory) and data alterable (both alterable and data). Twelve of the most commonly used effective addressing modes from the M68000 Family are available on ColdFire microprocessors. Table 2-5 summarizes these modes and their categories.

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Table 2-5. ColdFire Effective Addressing Modes

— —

X X X X

X X

2.6 Instruction Set Summary

X X

X X X X

— —

The ColdFire instruction set is a simpliﬁed version of the M68000 instruction set. The removed instructions include BCD, bit ﬁeld, logical rotate, decrement and branch, and integer multiply with a 64-bit result. Nine new MAC instructions have been added.

Table 2-6 lists notational conventions used throughout this manual.

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Instruction Set Summary

Table 2-6. Notational Conventions

Instruction Operand Syntax

Opcode Wildcard

cc Logical condition (example: NE for not equal)

An Any address register n (example: A3 is address register 3)

Ay,Ax Source and destination address registers, respectively

Dn Any data register n (example: D5 is data register 5)

Dy,Dx Source and destination data registers, respectively

Rc Any control register (example VBR is the vector base register)

Rm MAC registers (ACC, MAC, MASK)

Rn Any address or data register Rw Destination register w (used for MAC instructions only)

Ry,Rx Any source and destination registers, respectively

Xi index register i (can be an address or data register: Ai, Di)

ACC MAC accumulator register

CCR Condition code register (lower byte of SR)

MACSR MAC status register

MASK MAC mask register

PC Program counter SR Status register

Port Names

DDATA Debug data port

PST Processor status port

Miscellaneous Operands

#<data> Immediate data following the 16-bit operation word of the instruction

<ea> Effective address

<ea>y,<ea>x Source and destination effective addresses, respectively

<label> Assembly language program label

<list> List of registers for MOVEM instruction (example: D3–D0) <shift> Shift operation: shift left (<<), shift right (>>) <size> Operand data size: byte (B), word (W), longword (L)

bc Instruction cache

# <vector> Identiﬁes the 4-bit vector number for trap instructions

<> identiﬁes an indirect data address referencing memory

<xxx> identiﬁes an absolute address referencing memory

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Table 2-6. Notational Conventions (Continued)

Instruction Operand Syntax

dn Signal displacement value, n bits wide (example: d16 is a 16-bit displacement)

SF Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations)

Operations

+ Arithmetic addition or postincrement indicator – Arithmetic subtraction or predecrement indicator x Arithmetic multiplication

/ Arithmetic division

~ Invert; operand is logically complemented

& Logical AND

| Logical OR

^ Logical exclusive OR << Shift left (example: D0 << 3 is shift D0 left 3 bits) >> Shift right (example: D0 >> 3 is shift D0 right 3 bits)

→ Source operand is moved to destination operand

←→ Two operands are exchanged

sign-extended All bits of the upper portion are made equal to the high-order bit of the lower portion

If <condition>

then

else

{} Optional operation () Identiﬁes an indirect address

Address Calculated effective address (pointer)

Bit Bit selection (example: Bit 3 of D0)

lsb Least signiﬁcant bit (example: lsb of D0)

LSB Least signiﬁcant byte

LSW Least signiﬁcant word

msb Most signiﬁcant bit MSB Most signiﬁcant byte MSW Most signiﬁcant word

Test the condition. If the condition is true, the operations in the then clause are performed. If the condition is false and the optional else clause is present, the operations in the else clause are performed. If the condition is false and the else clause is omitted, the instruction performs no operation. Refer to the Bcc instruction description as an example.

Subﬁelds and Qualiﬁers

Displacement value, n-bits wide (example: d16 is a 16-bit displacement)

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Instruction Set Summary

Table 2-6. Notational Conventions (Continued)

Instruction Operand Syntax

Condition Code Register Bit Names

C Carry N Negative V Overﬂow X Extend

Z Zero

2.6.1 Instruction Set Summary

Table 2-7 lists implemented user-mode instructions by opcode.

Table 2-7. User-Mode Instruction Set Summary

Instruction Operand Syntax Operand Size Operation

ADD Dy,<ea>x

<ea>y,Dx ADDA <ea>y,Ax .L Source + destination → destination ADDI #<data>,Dx .L Immediate data + destination → destination ADDQ #<data>,<ea>x .L Immediate data + destination → destination ADDX Dy,Dx .L Source + destination + X → destination AND Dy,<ea>x

<ea>y,Dx ANDI #<data>,Dx .L Immediate data & destination → destination ASL Dy,Dx

#<data>,Dx ASR Dy,Dx

#<data>,Dx Bcc <label> .B,.W If condition true, then PC + 2 + dn → PC BCHG Dy,<ea>x

#<data>,<ea-1>x BCLR Dy,<ea>x

#<data>,<ea-1>x BRA <label> .B,.W PC + 2 + d BSET Dy,<ea>x

#<data>,<ea-1>x BSR <label> .B,.W SP – 4 → SP; next sequential PC→ (SP); PC + 2 + dn → PC BTST Dy,<ea>x

#<data>,<ea-1>x CLR <ea>y,Dx .B,.W,.L 0 → destination CMP <ea>y,Ax .L Destination – source

.L .L

.B,.L .B,.L

Source + destination → destination

Source & destination → destination

X/C ← (Dx << Dy) ← 0 X/C ← (Dx << #<data>) ← 0

MSB → (Dx >> Dy) → X/C MSB → (Dx >> #<data>) → X/C

~(<bit number> of destination) → Z, Bit of destination

~(<bit number> of destination) → Z; 0 → bit of destination

→ PC

~(<bit number> of destination) → Z; 1→ bit of destination

~(<bit number> of destination) → Z

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Instruction Set Summary

Table 2-7. User-Mode Instruction Set Summary (Continued)

Instruction Operand Syntax Operand Size Operation

CMPA <ea>y,Dx .L Destination – source CMPI <ea>y,Dx .L Destination – immediate data DIVS <ea-1>y,Dx

DIVU <ea-1>y,Dx

EOR Dy,<ea>x .L Source ^ destination → destination EORI #<data>,Dx .L Immediate data ^ destination → destination EXT #<data>,Dx .B →.W

EXTB Dx .B →.L Sign-extended destination → destination HALT JMP <ea-3>y Unsized Address of <ea> → PC JSR <ea-3>y Unsized SP – 4 → SP; next sequential PC → (SP); <ea> → PC LEA <ea-3>y,Ax .L <ea> → Ax LINK Ax,#<d16> .W SP – 4 → SP; Ax → (SP); SP → Ax; SP + d16 → SP LSL Dy,Dx

LSR Dy,Dx

MAC Ry,RxSF .L + (.W × .W) → .L

MACL Ry,RxSF,<ea-1>y,Rw .L + (.W × .W) → .L, .L

MOVE <ea>y,<ea>x .B,.W,.L <ea>y → <ea>x MOVE from

MAC

MOVE to MAC

MOVE from CCR

MOVE to CCR

<ea>y,Dx

Dy,<ea>x

None Unsized Enter halted state

#<data>,Dx

MASK,Rx

ACC,Rx

MACSR,Rx

MACSR,CCR .L MACSR → CCR

Ry,ACC

Ry,MACSR

Ry,MASK

#<data>,ACC

#<data>,MACSR

#<data>,MASK

CCR,Dx .W CCR → Dx

Dy,CCR

#<data>,CCR

.W .L

.W →.L

.L .L

.L + (.L × .L) → .L

.L + (.L × .L) → .L, .L

.L Rm → Rx

.L Ry → Rm

.L #<data> → Rm

.B Dy → CCR

Dx /<ea>y → Dx {16-bit remainder; 16-bit quotient} Dx /<ea>y → Dx {32-bit quotient} Signed operation

Dx /<ea>y → Dx {16-bit remainder; 16-bit quotient} Dx /<ea>y → Dx {32-bit quotient} Unsigned operation

Sign-extended destination → destination

X/C ← (Dx << Dy) ← 0 X/C ← (Dx << #<data>) ← 0

0 → (Dx >> Dy) → X/C 0 → (Dx >> #<data>) → X/C

ACC + (Ry × Rx){<< 1 | >> 1} → ACC ACC + (Ry × Rx){<< 1 | >> 1} → ACC; (<ea>y{&MASK}) → Rw

ACC + (Ry × Rx){<< 1 | >> 1} → ACC ACC + (Ry × Rx){<< 1 | >> 1} → ACC; (<ea-1>y{&MASK}) → Rw

#<data> → CCR

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Instruction Set Summary

Table 2-7. User-Mode Instruction Set Summary (Continued)

Instruction Operand Syntax Operand Size Operation

MOVEA <ea>y,Ax .W,.L → .L Source → destination MOVEM #<list>,<ea-2>x

<ea-2>y,#<list> MOVEQ #<data>,Dx .B → .L Sign-extended immediate data → destination MSAC Ry,RxSF .L - (.W × .W) → .L

MSACL Ry,RxSF,<ea-1>y,Rw .L - (.W × .W) → .L, .L

MULS <ea>y,Dx .W X .W → .L

MULU <ea>y,Dx .W X .W → .L

NEG Dx .L 0 – destination → destination NEGX Dx .L 0 – destination – X → destination NOP none Unsized Synchronize pipelines; PC + 2 → PC NOT Dx .L ~ Destination → destination OR <ea>y,Dx

Dy,<ea>x ORI #<data>,Dx .L Immediate data | destination → destination PEA <ea-3>y .L SP – 4 → SP; Address of <ea> → (SP) PULSE none Unsized Set PST= 0x4 REMS <ea-1>,Dx .L Dx/<ea>y → Dw {32-bit remainder}

REMU <ea-1>,Dx .L Dx/<ea>y → Dw {32-bit remainder}

RTS none Unsized (SP) → PC; SP + 4 → SP Scc Dx .B If condition true, then 1s  destination;

SUB <ea>y,Dx

Dy,<ea>x SUBA <ea>y,Ax .L Destination – source → destination SUBI #<data>,Dx .L Destination – immediate data → destination SUBQ #<data>,<ea>x .L Destination – immediate data → destination SUBX Dy,Dx .L Destination – source – X → destination SWAP Dx .W MSW of Dx ←→ LSW of Dx TRAP #<vector> Unsized SP – 4 → SP;PC → (SP);

.L .L

.L - (.L × .L) → .L

.L - (.L × .L) → .L, .L

.L X .L → .L

.L Source | destination → destination

.L .L

Listed registers → destination Source → listed registers

ACC – (Ry × Rx){<< 1 | >> 1} → ACC

ACC – (Ry × Rx){<< 1 | >> 1} → ACC; (<ea-1>y{&MASK}) → Rw

Source × destination → destination Signed operation

Source × destination → destination Unsigned operation

Signed operation

Unsigned operation

Else 0s → destination Destination – source → destination

SP – 2 → SP;SR → (SP); SP – 2 → SP; format → (SP); Vector address → PC

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Table 2-7. User-Mode Instruction Set Summary (Continued)

Instruction Operand Syntax Operand Size Operation

TRAPF None

TST <ea>y .B,.W,.L Set condition codes UNLK Ax Unsized Ax →SP; (SP) → Ax; SP + 4 → SP WDDATA <ea>y .B,.W,.L <ea>y →DDATA port

By default the HALT instruction is a supervisor-mode instruction; however, it can be conﬁgured to allow user-mode

execution by setting CSR[UHE].

#<data>

Unsized .W .L

PC + 2 → PC PC + 4 → PC PC + 6 → PC

Table 2-8 describes supervisor-mode instructions.

Table 2-8. Supervisor-Mode Instruction Set Summary

Instruction Operand Syntax Operand Size Operation

CPUSHL (bc),(Ax) Unsized Invalidate instruction cache line

HALT MOVE from SR SR, Dx .W SR → Dx MOVE to SR Dy,SR

MOVEC Ry,Rc .L Ry → Rc

RTE None Unsized (SP+2) → SR; SP+4 → SP; (SP) → PC; SP + formatﬁeld  SP STOP #<data> .W Immediate data → SR; enter stopped state WDEBUG <ea-2>y .L <ea-2>y → debug module

The HALT instruction can be conﬁgured to allow user-mode execution by setting CSR[UHE].

none Unsized Enter halted state

.W Source → SR

#<data>,SR

Rc Register Deﬁnition

0x002 Cache control register (CACR) 0x004 Access control register 0 (ACR0) 0x005 Access control register 1 (ACR1) 0x801 Vector base register (VBR) 0xC00 ROM base address register (ROMBAR) 0xC04 RAM base address register (RAMBAR) 0xC0F Module base address register (MBAR)

2.7 Instruction Timing

The timing data presented in this section assumes the following:

• The OEP is loaded with the opword and all required extension words at the beginning of each instruction execution. This implies that the OEP spends no time waiting for the IFP to supply opwords and/or extension words.

• The OEP experiences no sequence-related pipeline stalls. For the MCF5272,the most common example of this type of stall involves consecutive store operations, excluding the MOVEM instruction. For all store operations (except MOVEM),

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Instruction Timing

certain hardware resources within the processor are marked as busy for two clock cycles after the ﬁnal DSOC cycle of the store instruction. If a subsequent store instruction is encountered within this two-cycle window, it is stalled until the resource again becomes available. Thus, the maximum pipeline stall involving consecutive store operations is two cycles.

• The OEP can complete all memory accesses without memory causing any stall conditions. Thus, timing details in this section assume an inﬁnite zero-wait state memory attached to the core.

• All operand data accesses are assumed to be aligned on the same byte boundary as the operand size:

— 16-bit operands aligned on 0-modulo-2 addresses — 32-bit operands aligned on 0-modulo-4 addresses Operands that do not meet these guidelines are misaligned. T able 2-9 shows how the

core decomposes a misaligned operand reference into a series of aligned accesses.

Table 2-9. Misaligned Operand References

A[1:0] Size Bus Operations Additional C(R/W)

x1 Word Byte, Byte 2(1/0) if read

x1 Long Byte, Word, Byte 3(2/0) if read

10 Long Word, Word 2(1/0) if read

Each timing entry is presented as C(r/w), described as follows: C is the number of processor clock cycles, including all applicable operand f etches and writes, as

well as all internal core cycles required to complete the instruction execution. r/w is the number of operand reads (r) and writes (w) required by the instruction. An operation

performing a read-modify write function is denoted as (1/1).

1(0/1) if write

2(0/2) if write

1(0/1) if write

2.7.1 MOVE Instruction Execution Times

The execution times for the MOVE.{B,W,L} instructions are shown in the next tables. Table 2-12 shows the timing for the other generic move operations.

NOTE:

For all tables in this section, the execution time of any instruction using the PC-relative effective addressing modes is equivalent to the time using comparable An-relative mode.

ET with {<ea> = (d16,PC)} equals ET with {<ea> = (d16,An)} ET with {<ea> = (d8,PC,Xi*SF)} equals ET with {<ea> = (d8,An,Xi*SF)}

The nomenclature “(xxx).wl” refers to both forms of absolute addressing, (xxx).w and (xxx).l.

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Table 2-10 lists execution times for MOVE.{B,W} instructions.

Table 2-10. Move Byte and Word Execution Times

Instruction Timing

Source

Rx (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) (xxx).wl

Dy 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)

Ay 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)

(Ay) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1)

(Ay)+ 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1)

-(Ay) 3(1/0) 31/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1)

(d16,Ay) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) — —

(d8,Ay,Xi*SF) 4(1/0) 4(1/1) 4(1/1) 4(1/1) — — —

(xxx).w 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —

(xxx).l 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —

(d16,PC) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) — —

(d8,PC,Xi*SF) 4(1/0) 4(1/1) 4(1/1) 4(1/1) — — —

#<xxx> 1(0/0) 3(0/1) 3(0/1) 3(0/1) — — —

Destination

Table 2-11 lists timings for MOVE.L.

Table 2-11. Move Long Execution Times

Source

Rx (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) (xxx).wl

Dy 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) Ay 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)

(Ay) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1)

(Ay)+ 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1)

-(Ay) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1)

(d16,Ay) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) — —

(d8,Ay,Xi*SF) 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —

(xxx).w 2(1/0) 2(1/1) 2(1/1) 2(1/1) — — —

(xxx).l 2(1/0) 2(1/1) 2(1/1) 2(1/1) — — —

(d16,PC) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) — —

(d8,PC,Xi*SF) 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —

#<xxx> 1(0/0) 2(0/1) 2(0/1) 2(0/1) — — —

Destination

Table 2-12 gives execution times for MOVE.L instructions accessing program-visible registers of the MAC unit, along with other MOVE.L timings. Execution times for moving contents of the ACC or MACSR into a destination location represent the best-case scenario when the store instruction is executed and no load, MAC, or MSAC instructions are in the

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MAC execution pipeline. In general, these store operations require only one cycle for execution, but if the y are preceded immediately by a load, MAC, or MSAC instruction, the MAC pipeline depth is exposed and execution time is three cycles.

Table 2-12. Move Execution Times

Opcode <ea>

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx>

move.l <ea>,ACC 1(0/0) — — — — — — 1(0/0) move.l <ea>,MACSR 2(0/0) — — — — — — 2(0/0) move.l <ea>,MASK 1(0/0) — — — — — — 1(0/0) move.l ACC,Rx 1(0/0) — — — — — — — move.l MACSR,CCR 1(0/0) — — — — — — — move.l MACSR,Rx 1(0/0) — — — — — — — move.l MASK,Rx 1(0/0) — — — — — — —

Effective Address

2.7.2 Execution Timings—One-Operand Instructions

Table 2-13 shows standard timings for single-operand instructions.

Table 2-13. One-Operand Instruction Execution Times

Opcode <ea>

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #xxx

clr.b <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) —

clr.w <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) —

clr.l <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) —

ext.w Dx 1(0/0) — — — — — — —

ext.l Dx 1(0/0) — — — — — — — extb.l Dx 1(0/0) — — — — — — — neg.l Dx 1(0/0) — — — — — — —

negx.l Dx 1(0/0) — — — — — — —

not.l Dx 1(0/0) — — — — — — —

scc Dx 1(0/0) — — — — — — —

swap Dx 1(0/0) — — — — — — —

tst.b <ea> 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) tst.w <ea> 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)

tst.l <ea> 1(0/0) 2(1/0) 2(1/0) 2(1/0) 2(1/0) 3(1/0) 2(1/0) 1(0/0)

Effective Address

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2.7.3 Execution Timings—Two-Operand Instructions

Table 2-14 shows standard timings for two-operand instructions.

Table 2-14. Two-Operand Instruction Execution Times

Opcode <ea>

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx>

add.l <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) add.l Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

addi.l #imm,Dx 1(0/0) — — — — — — —

addq.l #imm,<ea> 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) — addx.l Dy,Dx 1(0/0) — — — — — — —

and.l <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) and.l Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

andi.l #imm,Dx 1(0/0) — — — — — — —

asl.l <ea>,Dx 1(0/0) — — — — — — 1(0/0)

asr.l <ea>,Dx 1(0/0) — — — — — — 1(0/0)

bchg Dy,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) — bchg #imm,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — —

bclr Dy,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) —

bclr #imm,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — — bset Dy,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) — bset #imm,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — —

btst Dy,<ea> 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) —

btst #imm,<ea> 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) — — —

cmp.l <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) cmpi.l #imm,Dx 1(0/0) — — — — — — — divs.w <ea>,Dx 20(0/0) 23(1/0) 23(1/0) 23(1/0) 23(1/0) 24(1/0) 23(1/0) 20(0/0) divu.w <ea>,Dx 20(0/0) 23(1/0) 23(1/0) 23(1/0) 23(1/0) 24(1/0) 23(1/0) 20(0/0)

divs.l <ea>,Dx 35(0/0) 35(1/0) 35(1/0) 35(1/0) 35(1/0) — — —

divu.l <ea>,Dx 35(0/0) 35(1/0) 35(1/0) 35(1/0) 35(1/0) — — —

eor.l Dy,<ea> 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

eori.l #imm,Dx 1(0/0) — — — — — — —

lea <ea>,Ax — 1(0/0) — — 1(0/0) 2(0/0) 1(0/0) — lsl.l <ea>,Dx 1(0/0) — — — — — — 1(0/0) lsr.l <ea>,Dx 1(0/0) — — — — — — 1(0/0)

mac.w Ry,Rx 1(0/0) — — — — — — —

mac.l Ry,Rx 3(0/0) — — — — — — —

msac.w Ry,Rx 1(0/0) — — — — — — —

Effective Address

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Table 2-14. Two-Operand Instruction Execution Times (Continued)

Opcode <ea>

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx>

msac.l Ry,Rx 3(0/0) — — — — — — — mac.w Ry,Rx,ea,Rw — 3(1/0) 3(1/0) 3(1/0) 3(1/0) — — —

mac.l Ry,Rx,ea,Rw — 5(1/0) 5(1/0) 5(1/0) 5(1/0) — — —

moveq #imm,Dx — — — — — — — 1(0/0)

msac.w Ry,Rx,ea,Rw — 3(1/0) 3(1/0) 3(1/0) 3(1/0) — — —

msac.l Ry,Rx,ea,Rw — 5(1/0) 5(1/0) 5(1/0) 5(1/0) — — —

muls.w <ea>,Dx 4(0/0) 6(1/0) 6(1/0) 6(1/0) 6(1/0) 7(1/0) 6(1/0) 4(0/0)

mulu.w <ea>,Dx 4(0/0) 6(1/0) 6(1/0) 6(1/0) 6(1/0) 8(1/0) 6(1/0) 4(0/0)

muls.l <ea>,Dx 6(0/0) 8(1/0) 8(1/0) 8(1/0) 8(1/0) — — — mulu.l <ea>,Dx 6(0/0) 8(1/0) 8(1/0) 8(1/0) 8(1/0) — — —

or.l <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) or.l Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

or.l #imm,Dx 1(0/0) — — — — — — — rems.l <ea>,Dx 35(0/0) 35(1/0) 35(1/0) 35(1/0) 35(1/0) — — — remu.l <ea>,Dx 35(0/0) 35(1/0) 35(1/0) 35(1/0) 35(1/0) — — —

sub.l <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) sub.l Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

subi.l #imm,Dx 1(0/0) — — — — — — — subq.l #imm,<ea> 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) — subx.l Dy,Dx 1(0/0) — — — — — — —

Effective Address

2.7.4 Miscellaneous Instruction Execution Times

Table 2-15 lists timings for miscellaneous instructions.

Table 2-15. Miscellaneous Instruction Execution Times

Opcode <ea>

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx>

cpushl (Ax) — 11(0/1) — — — — — —

link.w Ay,#imm 2(0/1) — — — — — — — move.w CCR,Dx 1(0/0) — — — — — — — move.w <ea>,CCR 1(0/0) — — — — — — 1(0/0) move.w SR,Dx 1(0/0) — — — — — — — move.w <ea>,SR 7(0/0) — — — — — — 7(0/0)

movec Ry,Rc 9(0/1) — — — — — — —

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Table 2-15. Miscellaneous Instruction Execution Times (Continued)

Opcode <ea>

movem.l 1<ea>,&list — 1+n(n/0) — — 1+n(n/0) — — —

movem.l &list,<ea> — 1+n(0/n) — — 1+n(0/n) — — —

nop 3(0/0) — — — — — — — pea <ea> — 2(0/1) — — 2(0/1)

pulse 1(0/0) — — — — — — —

stop #imm — — — — — — — 3(0/0) trap #imm — — — — — — — 15(1/2) trapf 1(0/0) — — — — — — —

trapf.w 1(0/0) — — — — — — —

trapf.l 1(0/0) — — — — — — —

unlk Ax 2(1/0) — — — — — — — wddata.l <ea> — 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) — wdebug.l <ea> — 5(2/0) — — 5(2/0) — — —

n is the number of registers moved by the MOVEM opcode.

PEA execution times are the same for (d16,PC).

PEA execution times are the same for (d8,PC,Xi*SF).

The execution time for STOP is the time required until the processor begins sampling continuously for interrupts.

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx>

Effective Address

3(0/1)

2(0/1) —

2.7.5 Branch Instruction Execution Times

Table 2-16 shows general branch instruction timing.

Table 2-16. General Branch Instruction Execution Times

Opcode <ea>

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx>

bra — — — — 2(0/1) — — — bsr ————3(0/1) — — —

jmp <ea> — 3(0/0) — — 3(0/0) 4(0/0) 3(0/0) —

jsr <ea> — 3(0/1) — — 3(0/1) 4(0/1) 3(0/1) — rte — — 10(2/0) — — — — — rts — — 5(1/0) — — — — —

Effective Address

Table 2-17 shows timing for Bcc instructions.

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Table 2-17. Bcc Instruction Execution Times

Opcode Forward T aken

bcc 3(0/0) 1(0/0) 2(0/0) 3(0/0)

Forward Not

Taken

Backward T aken

Backward Not

Taken

2.8 Exception Processing Overview

Exception processing for ColdFire processors is streamlined for performance. Differences from previous M68000 Family processors include the following:

• A simpliﬁed exception vector table

• Reduced relocation capabilities using the vector base register

• A single exception stack frame format

• Use of a single, self-aligning system stack pointer

ColdFire processors use an instruction restart exception model but require more software support to recover from certain access errors. See Table 2-18 for details.

Exception processing can be deﬁned as the time from the detection of the fault condition until the fetch of the ﬁrst handler instruction has been initiated. It is comprised of the following four major steps:

1. The processor makes an internal copy of the SR and then enters supervisor mode by setting SR[S] and disabling trace mode by clearing SR[T]. The occurrence of an interrupt exception also forces SR[M] to be cleared and the interrupt priority mask to be set to the level of the current interrupt request.

2. The processor determines the exception vector number. For all faults except interrupts, the processor performs this calculation based on the exception type. For interrupts, the processor performs an interrupt-acknowledge (IACK) bus cycle to obtain the vector number from a peripheral device. The IACK cycle is mapped to a special acknowledge address space with the interrupt level encoded in the address.

3. The processor saves the current context by creating an exception stack frame on the system stack. ColdFire processors support a single stack pointer in the A7 address register; therefore, there is no notion of separate supervisor and user stack pointers. As a result, the exception stack frame is created at a 0-modulo-4 address on the top of the current system stack. Additionally, the processor uses a simpliﬁed ﬁxed-length stack frame for all exceptions. The exception type determines whether the program counter in the exception stack frame deﬁnes the address of the faulting instruction (fault) or of the next instruction to be executed (next).

4. The processor acquires the address of the ﬁrst instruction of the exception handler. The exception vector table is aligned on a 1-Mbyte boundary. This instruction address is obtained by fetching a value from the table at the address deﬁned in the vector base register. The index into the exception table is calculated as

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4 x vector_number. When the index value is generated, the vector table contents determine the address of the ﬁrst instruction of the desired handler. After the fetch of the ﬁrst opcode of the handler is initiated, exception processing terminates and normal instruction processing continues in the handler.

ColdFire processors support a 1024-byte vector table aligned on any 1-Mbyte address boundary; see Table 2-18. The table contains 256 exception vectors where the ﬁrst 64 are deﬁned by Motorola; the remaining 192 are user-deﬁned interrupt vectors.

Table 2-18. Exception Vector Assignments

Vector Numbers Vector Offset (Hex) Stacked Program Counter

0 000 — Initial stack pointer 1 004 — Initial program counter 2 008 Fault Access error 3 00C Fault Address error 4 010 Fault Illegal instruction 5 014 Fault Divide by zero

6–7 018–01C — Reserved

8 020 Fault Privilege violation

9 024 Next Trace 10 028 Fault Unimplemented line-a opcode 11 02C Fault Unimplemented line-f opcode 12 030 Next Debug interrupt 13 034 — Reserved 14 038 Fault Format error 15 03C Next Uninitialized interrupt

16–23 040–05C — Reserved

24 060 Next Spurious interrupt

25–31 064–07C Next Level 1–7 autovectored interrupts 32–47 080–0BC Next Trap #0–15 instructions 48–60 0C0–0F0 — Reserved

61 0F4 Fault Unsupported instruction

62–63 0F8–0FC — Reserved

64–255 100–3FC Next User-deﬁned interrupts

The term ‘fault’ refers to the PC of the instruction that caused the exception. The term ‘next’ refers to the PC of the instruction that immediately follows the instruction that caused the fault.

Assignment

ColdFire processors inhibit sampling for interrupts during the ﬁrst instruction of all exception handlers. This allows any handler to effectively disable interrupts, if necessary, by raising the interrupt mask level contained in the status register.

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2.8.1 Exception Stack Frame Deﬁnition

The exception stack frame is shown in Figure 2-10. The ﬁrst longword of the exception stack frame contains the 16-bit format/vector word (F/V) and the 16-bit status register. The second longword contains the 32-bit program counter address.

31 28 27 26 25 18 17 16 15 0

A7→ Format FS[3–2] Vector[7–0] FS[1–0] Status Register

+ 0x04 Program Counter [31–0]

Figure 2-10. Exception Stack Frame Form

The 16-bit format/vector word contains three unique ﬁelds:

• Format ﬁeld—This 4-bit ﬁeld at the top of the system stack is always written with a value of {4,5,6,7} by the processor indicating a 2-longword frame format. See Table 2-19. This ﬁeld records any longword misalignment of the stack pointer that may have existed when the exception occurred.

Table 2-19. Format Field Encoding

Original A7 at Time of

Exception, Bits 1–0

00 Original A[7–8] 0100 01 Original A[7–9] 0101 10 Original A[7–10] 0110 11 Original A[7–11] 0111

A7 at First Instruction of

Handler

Format Field Bits

31–28

• Fault status ﬁeld—The 4-bit ﬁeld, FS[3–0], at the top of the system stack is deﬁned for access and address errors along with interrupted debug service routines. See Table 2-20.

Table 2-20. Fault Status Encodings

FS[3–0] Deﬁnition

0000-001x Reserved

0100 Error on instruction fetch

0101–011x Reserved

1000 Error on operand write 1001 Attempted write to write-protected space 101x Reserved 1100 Error on operand read

1101–111x Reserved

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• Vector number—This 8-bit ﬁeld, vector[7–0], deﬁnes the exception type. It is calculated by the processor for internal faults and is supplied by the peripheral for interrupts. See Table 2-18.

2.8.2 Processor Exceptions

Table 2-21 describes MCF5272 exceptions.

Table 2-21. MCF5272 Exceptions

Exception Description

Access Error Caused by an error when accessing memory. For an access error on an instruction fetch, the

Address

Error

Illegal

Instruction

Divide by

Zero

Privilege Violation

processor postpones the error reporting until the instruction at the faulted reference is executed. Thus, faults that occur during instruction prefetches that are followed by a change of instruction ﬂow do not generate an exception. When the processor attempts to execute an instruction with a faulted opword or extension word, the access error is signaled, and the instruction is aborted. For this type of exception, the programming model is not altered by the faulted instruction. If an access error occurs on an operand read, the processor immediately aborts the current instruction execution and initiates exception processing. In this case, any address register changes caused by the auto-addressing modes, (An)+ and -(An), have already occurred. In addition, if an access error occurs during the execution of a MOVEM instruction loading from memory, registers updated before the fault occurs contain the memory operand. Due to the processor pipeline implementation, a write cycle may be decoupled from the execution of the instruction causing the write. Thus, if an access error occurs on an operand write, the signaling of the error is imprecise. Accordingly, the PC contained in the exception stack frame represents the location in the program when the access error is signaled, not necessarily the instruction causing the fault. All programming model updates associated with the write instruction are complete. The NOP instruction can be used to help identify write access errors. A NOP is not executed until all previous operations, including any pending writes are complete. Thus if any previous write terminates with an access error, it is guaranteed to be reported on the NOP.

Caused by an attempted execution transf erring control to an odd instruction address (that is, if bit 0 of the target address is set), an attempted use of a word-sized index register (Xi.w) or a scale factor of 8 on an indexed effectiv e addressing mode , or attempted ex ecution of an instruction with a full-f ormat indexed addressing mode.

On Version 2 ColdFire implementations, only some illegal opcodes (0x0000 and 0x4AFC) are decoded and generate an illegal instruction exception. Additionally, attempting to execute an illegal line A or line F opcode generates unique exception types: vectors 10 and 11, respectively. If any other nonsupported opcode is executed, the resulting operation is undeﬁned. ColdFire processors do not provide illegal instruction detection on extension words of any instruction, including MOVEC. Attempting to execute an instruction with an illegal extension word causes undeﬁned results.

Attempted division by zero causes an exception (vector 5, offset = 0x014) e xcept when the PC points to the faulting instruction (DIVU, DIVS, REMU, REMS).

Caused by attempted execution of a supervisor mode instruction while in user mode. The ColdFire Programmer’s Reference Manual lists supervisor- and user-mode instructions.

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Table 2-21. MCF5272 Exceptions (Continued)

Exception Description

Trace

Exception

Debug

Interrupt

RTE and

Format Error

Exceptions

TRAP Executing TRAP always forces an exception and is useful for implementing system calls. The trap

ColdFire processors provide instruction-by-instruction tracing. While the processor is in trace mode (SR[T] = 1), instruction completion signals a trace exception. This allows a debugger to monitor program execution. The only exception to this deﬁnition is the STOP instruction. If the processor is in trace mode, the instruction before the STOP executes and then generates a trace exception. In the exception stack frame, the PC points to the STOP opcode. When the trace handler is exited, the STOP instruction is executed, loading the SR with the immediate operand from the instruction. The processor then generates a trace exception. The PC in the exception stack frame points to the instruction after STOP, and the SR reﬂects the just-loaded value. If the processor is not in trace mode and executes a STOP instruction where the immediate operand sets the trace bit in the SR, hardware loads the SR and generates a trace exception. The PC in the exception stack frame points to the instruction after STOP, and the SR reﬂects the just-loaded value. Because ColdFire processors do not support hardware stacking of multiple exceptions, it is the responsibility of the operating system to check for trace mode after processing other e xception types. As an example, consider a TRAP instruction executing in trace mode. The processor initiates the TRAP exception and passes control to the corresponding handler. If the system requires that a trace exception be processed, the TRAP exception handler must check for this condition (SR[15] in the exception stack frame asserted) and pass control to the trace handler before returning from the original exception.

Caused by a hardware breakpoint register trigger. Rather than generating an IACK cycle, the processor internally calculates the vector number (12). Additionally, the M bit and the interrupt priority mask ﬁelds of the SR are unaffected by the interrupt. See Section 2.2.2.1, “Status Register (SR).”

When an RTE instruction executes, the processor ﬁrst examines the 4-bit format ﬁeld to validate the frame type. For a ColdFire processor, any attempted execution of an RTE where the format is not equal to {4,5,6,7} generates a format error. The exception stack frame for the format error is created without disturbing the original exception frame and the stacked PC points to R TE.The selection of the format value provides limited debug support for porting code from M68000 applications. On M68000 Family processors, the SR was at the top of the stack. Bit 30 of the longword addressed by the system stack pointer is typically zero; so, attempting an RTE using this old format generates a format error on a ColdFire processor. If the format ﬁeld deﬁnes a valid type, the processor does the following: 1 Reloads the SR operand. 2 Fetches the second longword operand. 3 Adjusts the stack pointer by adding the format value to the auto-incremented address after the ﬁrst

longword fetch.

4 Transfers control to the instruction address deﬁned by the second longword operand in the stack

frame.

instruction may be used to change from user to supervisor mode.

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Table 2-21. MCF5272 Exceptions (Continued)

Exception Description

Interrupt

Exception

Reset

Exception

Interrupt exception processing, with interrupt recognition and vector fetching, includes uninitialized and spurious interrupts as well as those where the requesting device supplies the 8-bit interrupt vector.

Asserting the reset input signal (RSTI priority; it provides for system initialization and recovery from catastrophic failure. When assertion of RSTI

is recognized, current processing is aborted and cannot be recovered. The reset exception places the processor in supervisor mode by setting SR[S] and disables tracing by clearing SR[T]. This exception also clears SR[M] and sets the processor’s interrupt priority mask in the SR to the highest level (lev el 7). Next, the VBR is initializ ed to 0x0000_0000. Conﬁguration registers controlling the operation of all processor-local memories (cache and RAM modules on the MCF5272) are invalidated, disabling the memories. Note: Other implementation-speciﬁc supervisor registers are also affected. Refer to each of the modules in this manual for details on these registers. If the processor is not halted and it has ownership of the bus, it initiates the reset exception by performing two longword read bus cycles. The longword at address 0 is loaded into the stack pointer and the longword at address 4 is loaded into the PC. After the initial instruction is fetched from memory, program execution begins at the address in the PC. If an access error or address error occurs before the ﬁrst instruction executes, the processor enters the fault-on-fault halted state.

) causes a reset exception. Reset has the highest exception

If a ColdFire processor encounters any type of fault during the exception processing of another fault, the processor immediately halts execution with the catastrophic fault-on-fault condition. A reset is required to force the processor to exit this halted state.

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Chapter 3 Hardware Multiply/Accumulate (MAC) Unit

This chapter describes the MCF5272 multiply/accumulate (MAC) unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. The MAC is integrated into the operand execution pipeline (OEP).

3.1 Overview

The MAC unit provides hardware support for a limited set of digital signal processing (DSP) operations used in embedded code, while supporting the integer multiply instructions in the ColdFire microprocessor family.

The MAC unit provides signal processing capabilities for the MCF5272 in a variety of applications including digital audio and servo control. Integrated as an ex ecution unit in the processor’s OEP, the MAC unit implements a three-stage arithmetic pipeline optimized for 16 x 16 multiplies. Both 16- and 32-bit input operands are supported by this design in addition to a full set of extensions for signed and unsigned integers plus signed, ﬁxed-point fractional input operands.

The MAC unit provides functionality in three related areas:

• Signed and unsigned integer multiplies

• Multiply-accumulate operations supporting signed, unsigned, and signed fractional operands

• Miscellaneous register operations

Each of the three areas of support is addressed in detail in the succeeding sections. Logic that supports this functionality is contained in a MAC module, as shown in Figure 3-1.

The MAC unit is tightly coupled to the OEP and features a three-stage execution pipeline. To minimize silicon costs, the ColdFire MAC is optimized for 16 x 16 multiply instructions. The OEP can issue a 16 x 16 multiply with a 32-bit accumulation and fetch a 32-bit operand in the same cycle. A 32 x 32 multiply with a 32-bit accumulation takes three cycles before the next instruction can be issued. Figure 3-1 shows the basic functionality of the ColdFire MAC. A full set of instructions is provided for signed and unsigned integers plus signed, ﬁxed-point, fractional input operands.

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Operand Y Operand X

Shift 0,1,-1

+/-

Accumulator

Figure 3-1. ColdFire MAC Multiplication and Accumulation

The MAC unit is an extension of the basic multiplier found on most microprocessors. It can perform operations native to signal processing algorithms in an acceptable number of cycles, given the application constraints. F or example, small digital ﬁlters can tolerate some variance in the execution time of the algorithm; larger, more complicated algorithms such as orthogonal transforms may have more demanding speed requirements exceeding the scope of any processor architecture and requiring a fully developed DSP implementation.

The M68000 architecture was not designed for high-speed signal processing, and a large DSP engine would be excessive in an embedded environment. In striking a middle ground between speed, size, and functionality , the ColdFire MAC unit is optimized for a small set of operations that involve multiplication and cumulative additions. Speciﬁcally, the multiplier array is optimized for single-cycle, 16 x 16 multiplies producing a 32-bit result, with a possible accumulation cycle following. This is common in a large portion of signal processing applications. In addition, the ColdFire core architecture has been modiﬁed to allow for an operand fetch in parallel with a multiply, increasing overall performance for certain DSP operations.

3.1.1 MAC Programming Model

Figure 3-2 shows the registers in the MAC portion of the user programming model.

31 0

Figure 3-2. MAC Programming Model

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MACSR MAC status register ACC MAC accumulator MASK MAC mask register

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Overview

These registers are described as follows:

• Accumulator (ACC)—This 32-bit, read/write, general-purpose register is used to accumulate the results of MAC operations.

• MAC status register (MACSR)—This 8-bit register deﬁnes conﬁguration of the MAC unit and contains indicator ﬂags af fected by MAC instructions. Unless noted otherwise, the setting of MACSR indicator ﬂags is based on the ﬁnal result, that is, the result of the ﬁnal operation involving the product and accumulator.

3.1.2 General Operation

The MAC unit supports the ColdFire integer multiply instructions (MULS and MULU) and provides additional functionality for multiply-accumulate operations. The added MAC instructions to the ColdFire ISA provide for the multiplication of two numbers, followed by the addition or subtraction of this number to or from the value contained in the accumulator. The product may be optionally shifted left or right one bit before the addition or subtraction takes place. Hardware support for saturation arithmetic may be enabled to minimize software overhead when dealing with potential ov erﬂo w conditions using signed or unsigned operands.

These MAC operations treat the operands as one of the following formats:

• Signed integers

• Unsigned integers

• Signed, ﬁxed-point, fractional numbers

To maintain compactness, the MAC module is optimized for 16-bit multiplications. Two 16-bit operands produce a 32-bit product. Longword operations are performed by reusing the 16-bit multiplier array at the expense of a small amount of extra control logic. Again, the product of two 32-bit operands is a 32-bit result. For longword integer operations, only the least signiﬁcant 32 bits of the product are calculated. For fractional operations, the entire 63-bit product is calculated and then either truncated or rounded to a 32-bit result using the round-to-nearest (even) method.

Because the multiplier array is implemented in a 3-stage pipeline, MAC instructions can have an effective issue rate of one clock for word operations, three for longword integer operations, and four for 32-bit fractional operations. Arithmetic operations use register-based input operands, and summed values are stored internally in the accumulator. Thus, an additional MOVE instruction is necessary to store data in a general-purpose register. MAC instructions can choose the upper or lower word of a register as the input, which helps ﬁltering operations in which one data register is loaded with input data and another is loaded with coefﬁcient data. Two 16-bit MAC operations can be performed without fetching additional operands between instructions by alternating the word choice during the calculations.

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The need to move large amounts of data quickly can limit throughput in DSP engines. However, data can be moved efﬁciently by using the MOVEM instruction, which automatically generates line-sized burst references and is ideal for ﬁlling registers quickly with input data, ﬁlter coefﬁcients, and output data. Loading an operand from memory into a register during a MAC operation makes some DSP operations, especially ﬁltering and convolution, more manageable.

The MACSR has a 4-bit operational mode ﬁeld and three condition ﬂags. The operational mode bits control the overﬂow/saturation mode, whether operands are signed or unsigned, whether operands are treated as integers or fractions, and how rounding is performed. Negative, zero and overﬂow ﬂags are also provided.

The three program-visible MAC registers, a 32-bit accumulator (ACC), the MAC mask register (MASK), and MACSR, are described in Section 3.1.1, “MAC Programming Model.”

3.1.3 MAC Instruction Set Summary

The MAC unit supports the integer multiply operations deﬁned by the baseline ColdFire architecture, as well as the new multiply-accumulate instructions. Table 3-1 summarizes the MAC unit instruction set.

Table 3-1. MAC Instruction Summary

Instruction Mnemonic Description

Multiply Signed MULS <ea>y,Dx Multiplies two signed operands yielding a signed result Multiply Unsigned MULU <ea>y,Dx Multiplies two unsigned operands yielding an unsigned result Multiply Accumulate MAC Ry,RxSF

Multiply Accumulate with Load

Load Accumulator MOV.L {Ry,#imm},ACC Loads the accumulator with a 32-bit operand Store Accumulator MOV.L ACC,Rx Writes the contents of the accumulator to a register Load MACSR MOV.L {Ry,#imm},MACSR Writes a value to the MACSR Store MACSR MOV.L MACSR,Rx Writes the contents of MACSR to a register Store MACSR to CCR MOV.L MACSR,CCR Writes the contents of MACSR to the processor’s CCR register Load MASK MOV.L {Ry,#imm},MASK Writes a value to MASK Store MASK MOV.L MASK,Rx Writes the contents of MASK to a register

MSAC Ry,RxSF MAC Ry,RxSF,Rw

MSAC Ry,RxSF,Rw

Multiplies two operands, then adds or subtracts the product to/from the accumulator

Multiplies two operands, then adds or subtracts the product to/from the accumulator while loading a register with the memory operand

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3.1.4 Data Representation

The MAC unit supports three basic operand types:

• Two’s complement signed integer: In this format, an N-bit operand represents a number within the range -2

(N-1)

< operand < 2

of the least signiﬁcant bit.

• Two’s complement unsigned integer: In this format, an N-bit operand represents a number within the range 0 <

operand < 2N - 1. The binary point is to the right of the

least signiﬁcant bit.

• T wo’ s complement, signed fractional: In an N-bit number , the ﬁrst bit is the sign bit. The remaining bits signify the ﬁrst N-1 bits after the binary point. Given an N-bit number, a

N-1aN-2aN-3

... a2a1a0, its value is given by the following formula:

(N-1)

- 1. The binary point is to the right

N2–

i0=

This format can represent numbers in the range -1 <

i1N–+()

∑

ai⋅

operand < 1 - 2

(N-1)

For words and longwords, the greatest negati ve number that can be represented is -1, whose internal representation is 0x8000 and 0x0x8000_0000, respectively. The

most positive word is 0x7FFF or (1 - 2 0x7FFF_FFFF or (1 - 2

-31

-15

); the most positive longword is

3.2 MAC Instruction Ex ecution Timings

For information on MAC instruction execution timings, refer to Section 2.7, “Instruction Timing.”

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Chapter 4 Local Memory

This chapter describes the MCF5272 implementation of the ColdFire Version 2 core local memory speciﬁcation. It consists of the following sections.

• Section 4.3, “SRAM Overview,” and Section 4.4, “ROM Overview,” describe the on-chip static RAM (SRAM) and ROM implementations. These chapters cover general operations, conﬁguration, and initialization. They also provide information and examples showing ho w to minimize power consumption when using the ROM and SRAM.

• Section 4.5, “Instruction Cache Overview,” describes the cache implementation, including organization, conﬁguration, and coherency. It describes cache operations and how the cache interfaces with other memory structures.

4.1 Interactions between Local Memory Modules

Depending on conﬁguration information, instruction fetches and data read accesses may be sent simultaneously to the SRAM, ROM, and cache controllers. This approach is required because the controllers are memory-mapped devices and the hit/miss determination is made concurrently with the read data access. Power dissipation can be minimized by conﬁguring the ROM and SRAM base address registers (ROMBAR and RAMBAR) to mask unused address spaces whenever possible.

If the access address is mapped into the region deﬁned by the SRAM (and this region is not masked), it provides the data back to the processor and any cache or R OM data is discarded. If the access address does not hit the SRAM, but is mapped into the region deﬁned by the ROM (and this region is not mask ed), the R OM provides the data back to the processor and any cache data is discarded. Accesses from the SRAM and ROM modules are ne ver cached. The complete deﬁnition of the processor’s local bus priority scheme for read references is as follows:

if (SRAM “hits”)

SRAM supplies data to the processor if (ROM “hits”) ROM supplies data to the processor else if (cache “hits”)

cache supplies data to the processor

else system memory reference to access data

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4.2 Local Memory Registers

Table 4-1 lists the local memory registers. Note the following:

• Addresses not assigned to the register and undeﬁned register bits are reserved. Write accesses to these bits have no effect; read accesses return zeros.

• The reset value column indicates the register initial value at reset. Uninitialized ﬁelds may contain random values after reset.

Table 4-1. Memory Map of Instruction Cache Registers

Address (using MOVEC) Name Width Description Reset Value

0x002 CACR 32 Cache control register 0x0000 0x004 ACR0 32 Access control register 0 0x0000 0x005 ACR1 32 Access control register 1 0x0000

0xC00 ROMBAR 32 ROM base address register Uninitialized (except V = 0)

0xC04 RAMBAR 32 SRAM base address register Uninitialized (except V = 0)

4.3 SRAM Overview

The SRAM module has the following features:

• 4-Kbyte SRAM, organized as 1K x 32 bits

• Single-cycle access

• Physically located on the ColdFire core's high-speed local bus

• Byte, word, longword address capabilities

• Programmable memory mapping

4.3.1 SRAM Operation

The SRAM module provides a general-purpose memory block the ColdFire core can access in a single cycle. The location of the memory block can be set to any 4-Kbyte address boundary within the 4-Gbyte address space. The memory is ideal for storing critical code or data structures or for use as the system stack. Because the SRAM module is physically connected to the processor's high-speed local bus, it can quickly service core-initiated accesses or memory-referencing commands from the debug module.

Section 4.1, “Interactions between Local Memory Modules,” describes priorities when an access address hits multiple local memory resources.

4.3.2 SRAM Programming Model

The MCF5272 implements the SRAM base address register (RAMBAR), shown in Figure 4-1 and described in the following section.

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4.3.2.1 SRAM Base Address Register (RAMBAR)

RAMBAR determines the base address location of the internal SRAM module, as well as the deﬁnition of the types of accesses allowed for it.

• RAMBAR is a 32-bit write-only supervisor control register. It is accessed in the CPU address space via the MOVEC instruction with an Rc encoding of 0xC04. RAMBAR can be read or written in background debug mode (BDM). At system reset, the V bit is cleared and the remaining bits are uninitialized. To access the SRAM module, RAMBAR must be written with the appropriate base address after system reset.

• The SRAM base address register (RAMBAR) can be accessed only in supervisor mode using the MOVEC instruction with an Rc value of 0xC04.

31 12 11 9 8 7 6 5 4 3 2 1 0

Field BA — WP — C/I SC SD UC UD V

Reset — 0

R/W W for CPU; R/W for debug

Address CPU space + 0xC04

Figure 4-1. SRAM Base Address Register (RAMBAR)

RAMBAR ﬁelds are described in Table 4-2.

Table 4-2. RAMBAR Field Description

Bits Name Description

31–12 BA Base address. SRAM module base address. The SRAM module occupies a 4-Kbyte space

11–9 — Reserved, should be cleared.

8 WP Write protect. Controls read/write properties of the SRAM.

7–6 — Reserved, should be cleared.

deﬁned by BA. SRAM can reside on any 4-Kbyte boundary in the 4-Gbyte address space.

0 Allows read and write accesses to the SRAM module. 1 Allows only read accesses to the SRAM module. Any attempted write reference generates an

access error exception to the ColdFire processor core.

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Table 4-2. RAMBAR Field Description (Continued)

Bits Name Description

5–1 C/I,

0 V Valid. Enables/disables the SRAM module. V is cleared at reset.

Address space masks (ASn). These ﬁelds allow certain types of accesses to be masked, or inhibited from accessing the SRAM module. These bits are useful for power management as

SC,

described in Section 4.3.2.3, “Programming RAMBAR for P ow er Management.” In particular, C/I is

SD,

typically set.

UC,

The address space mask bits are follows:

C/I = CPU space/interrupt acknowledge cycle mask. Note that C/I must be set if BA = 0. SC = Supervisor code address space mask SD = Supervisor data address space mask UC = User code address space mask UD = User data address space mask For each ASn bit: 0 An access to the SRAM module can occur for this address space 1 Disable this address space from the SRAM module. References to this address space cannot

access the SRAM module and are processed like other non-SRAM references.

0 RAMBAR contents are not valid. 1 RAMBAR contents are valid.

The mapping of a given access into the SRAM uses the following algorithm to determine if the access hits in the memory:

if (RAMBAR[0] = 1)

if (requested address[31:12] = RAMBAR[31:12])

if (address space mask of the requested type = 0)

Access is mapped to the SRAM module if (access = read)

Read the SRAM and return the data

if (access = write)

if (RAMBAR[8] = 0)

Write the data into the SRAM

else Signal a write-protect access error

4.3.2.2 SRAM Initialization

After a hardware reset, the contents of the SRAM module are undeﬁned. The valid bit of RAMBAR is cleared, disabling the module. If the SRAM needs to be initialized with instructions or data, the following steps should be performed:

1. Load RAMBAR, mapping the SRAM module to the desired location.

2. Read the source data and write it to the SRAM. Various instructions support this function, including memory-to-memory MOVE instructions and the MOVEM opcode. The MOVEM instruction is optimized to generate line-sized burst fetches on 0-modulo-16 addresses, so this opcode generally provides the best performance.

3. After data is loaded into the SRAM, it may be appropriate to load a revised value into RAMBAR with new write-protect and address space mask attributes. These attributes consist of the write-protect and address-space mask ﬁelds.

The ColdFire processor or an external BDM emulator using the debug module can perform this initialization.

4-4 MCF5272 User’s Manual

Motorola DigitalDNA ColdFire MCF5272 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1.1 MCF5272 Key Features

1.2 MCF5272 Architecture

1.2.1 Version 2 ColdFire Core

1.2.2 System Integration Module (SIM)

1.2.2.1 External Bus Interface

1.2.2.2 Chip Select and Wait State Generation

1.2.2.4 Power Management

1.2.2.5 Parallel Input/Output Ports

1.2.2.6 Interrupt Inputs

1.2.3 UART Module

1.2.4 Timer Module

1.2.5 Test Access Port

1.3 System Design

1.4.1 Physical Layer Interface Controller (PLIC)

1.4.2 Pulse-Width Modulation (PWM) Unit

1.4.3 Queued Serial Peripheral Interface (QSPI)

1.4.4 Universal Serial Bus (USB) Module

2.1 Features and Enhancements

2.1.1 Decoupled Pipelines

2.1.1.1 Instruction Fetch Pipeline (IFP)

2.1.1.2 Operand Execution Pipeline (OEP)

2.1.1.2.1 Illegal Opcode Handling

2.1.1.2.2 Hardware Multiply/Accumulate (MAC) Unit

2.1.1.2.3 Hardware Divide Unit

2.1.2 Debug Module Enhancements

2.2 Programming Model

2.2.1 User Programming Model

2.2.1.1 Data Registers (D0–D7)

2.2.1.2 Address Registers (A0–A6)

2.2.1.3 Stack Pointer (A7, SP)

2.2.1.4 Program Counter (PC)

2.2.1.5 Condition Code Register (CCR)

2.2.1.6 MAC Programming Model

2.2.2 Supervisor Programming Model

2.2.2.1 Status Register (SR)

2.2.2.2 Vector Base Register (VBR)

2.2.2.3 Cache Control Register (CACR)

2.2.2.4 Access Control Registers (ACR0–ACR1)

2.2.2.5 ROM Base Address Register (ROMBAR)

2.2.2.6 RAM Base Address Register (RAMBAR)

2.2.2.7 Module Base Address Register (MBAR)

2.3 Integer Data Formats

2.4 Organization of Data in Registers

2.4.1 Organization of Integer Data Formats in Registers

2.4.2 Organization of Integer Data Formats in Memory

2.5 Addressing Mode Summary

2.6 Instruction Set Summary

2.6.1 Instruction Set Summary

2.7 Instruction Timing

2.7.1 MOVE Instruction Execution Times

2.7.2 Execution Timings—One-Operand Instructions

2.7.3 Execution Timings—Two-Operand Instructions

2.7.4 Miscellaneous Instruction Execution Times

2.7.5 Branch Instruction Execution Times

2.8 Exception Processing Overview

2.8.2 Processor Exceptions

3.1 Overview

3.1.1 MAC Programming Model

3.1.2 General Operation

3.1.3 MAC Instruction Set Summary

3.1.4 Data Representation

3.2 MAC Instruction Ex ecution Timings

4.1 Interactions between Local Memory Modules

4.2 Local Memory Registers

4.3 SRAM Overview

4.3.1 SRAM Operation

4.3.2 SRAM Programming Model

4.3.2.1 SRAM Base Address Register (RAMBAR)

4.3.2.2 SRAM Initialization