Motorola® and the Motorola symbol are registered trademarks of Motorola, Inc.
PowerPC® and the PowerPC logo are registered trade mark s of International Business
Machines Corporation (IBM) and are used by Motorola, Inc. under license from IBM.
CompactPCI® is a registered trademark o f the PC I In dustrial Computer Manufacturer’s
Group (PICMG).
All other product or service names mentioned in this doc ument are trademarks or registered
trademarks of their respective holders.
Safety Summary
Warning
The followi ng gen eral safety precaut io ns mus t be observed during all ph ases of oper ation, service, an d repa ir of
this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual
could result in personal injury or damage to the equipment.
The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as
the user of the product, should follow these warnings and all other safety precautions necessary for the safe
operation of the equipment in your operating environment.
Ground the Instrument.
T o minimi ze shock haz ard, the equi pment chassis and enclosure must be connec ted to an electr ical ground . If the
equipment is supp lied with a three-co nduct or AC power cable, th e powe r cabl e mus t be plu gged int o an approv ed
three-con tact e lectrical outlet, with the groundin g wir e (green/yellow) r eliab ly co nnected to an electrical ground
(safety ground) at the power outlet. The power jack and mating plug of the power cable meet International
Electrotechnical Commission (IEC) safety standards and local electrical regulatory codes.
Do Not Operate in an Explosive Atmosphere.
Do not operate the equipm ent in a ny explosive atm osp here such as in the presence of flam mabl e g ases or fumes.
Operation of any electrical equipment in such an environment could result in an explosion and cause injury or
damage.
Keep Away From Live Circuits Inside the Equipment.
Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or other
qualified service personnel may remove equipment covers for internal subassembly or component replacement
or any inte rnal adjus tment. Se rvice pe rsonnel s houl d not repl ace comp onents w ith power cab le co nnected . Under
certain conditions, dangerous voltages may exist even with the power cable removed. To avoid injuries, such
personnel should always disconnect power and discharge circuits before touching components.
Use Caution When Exposing or Handling a CRT.
Breakage of a Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion). To
prevent CRT implo sion , do not ha ndl e the CRT and avo id roug h handling or jarrin g of t he equ ipm ent . Ha ndling
of a CRT should be done only by qualified service personnel using approved safety mask and gloves.
Do Not Substitute Parts or Modify Equipment.
Do not install substitute parts or perform any unauthorized modification of the equipment. Contact your local
Motorola representative for service and repair to ensure that all safety features are maintained.
Observe Warnings in Manual.
Warnings, such as the example below, precede potentially dangerous procedures throughout this manual.
Instructions contained in the warnings must be followed. You should also employ all other safety precautions
which you deem necessary for the operation of the equipment in your operating environment.
Warnin g
To prevent serious injury or death from dangerous voltages, use extreme
caution when handling, testing, and adjusting this equipment and its
components.
Flammability
!
Warning
All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating
of 94V-0 by UL-recognized manufac turers.
CE Notice (European Community)
Warnin g
Motorola Computer Group p roducts with t he CE marking comply wi th the EMC Dir ective
(89/336/EEC). Compliance with this dir ective implies conformity to the following
European Norms:
EN55022 “Limits and Methods of Measurement of Radio Interference Characteristics
of Information Technology Equipment”; this product tested to Equipment Class A
EN55024 “Information technol ogy equipment—Immunity characteristics—Limits and
methods of measurement”
This product also fulfill s EN60950 (pr oduct safety) which is essentially the requir ement fo r
the Low Voltage Directive (73/23/EEC).
AC configurations of this system also mee t the req uirements of the following European
standards:
EN61000-3-2 “Limits of Harmonic Current Emissions (equipment input current ≤ 16
A per phase)”
This is a Class A product. In a domestic environment, this product may
cause radio interference, in which case the user may be required to take
adequate measures.
EN61000-3-3 “Limits of Voltage Fluctuations and Flicker in Low-Voltage Supply
Systems for Equipment with Rated Current ≤ 16 A”
In accordance with European Community directives, a “Declaration of Conformit y” has
been made and is available on request. Please contac t your sales representative.
This product is not a workstation per the Europe an Ergonomic Standard.
Kein Bildschirmarbeitsplatz nach dem Europäischen Ergonomie Standard.
FCC Class A
!
Caution
This equipment ha s been tested and found to comply with the limits for a Class A digital
device, pursuant to Part 15 of the FCC Rules. These lim its are designed to provide
reasonable protec tion against harmful interferen ce when the equipment is operated in a
commercial environm ent. Thi s equipment g enerates , uses, and can rad iate radio f requency
energy and, if not ins talle d and used in accordance with the instr uction manual, may cause
harmful interference to radio communications. Operati on of this equipment in a residential
area is likely to cause ha rmful interference in which case the use r will be required to c orrect
the interference at his own expense.
Changes or modifications no t expre ssly approve d by Motor ola Computer Group could voi d
the user’s author ity to operate the equipment.
Use only shielded cables when connecting peripherals to assure that appropriate radio
frequency emissions co mpli ance is maintained.
EMI Caution
Caution
This equipment generates, uses and can radiate electromagnetic energy. It
may cause or be susceptible to electromagnetic interference (EMI) if not
installed and used with adequ at e EMI protection.
Notice
While reasonable ef forts have been made to assure the accuracy of this document,
Motorola, Inc. assumes no liabil ity re sult ing from any o missions i n thi s document, or f rom
the use of the information obtained therein. Motorola reserves the right to revise this
document and to make ch ang es from time to time in the content hereof without obligation
of Motorola to notify any person of such revision or changes.
Electronic versi ons of this material may be read online, downloaded for personal use, or
referenced in another document as a UR L to the Motorola Compute r Group Web site. The
text itself may not be published commercially in prin t or electr onic form, e dited, transla ted,
or otherwise altered without the permission of Motorola, Inc.
It is possible that this publication may con tain reference to or information about Motorola
products (mach ines and pro grams), p rogramming, or s ervi ces tha t ar e not avail able in your
country. Such references or inform at ion must not be construed to mean that Motorola
intends to announce such Motorola produc ts, programming, or services in your country.
Limited and Restricted Rights Legend
If the documentation containe d here in is supplied, directly or indirectly, to the U.S.
Government, the following notice shall apply unless otherwise agreed to in writing by
Motoro la , Inc.
Use, duplication, or disclosure by the Government is subject to restrictions as set forth in
subparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013 (Nov.
1995) and of the Rights in Nonc ommercial Compute r Software a nd Documenta tion clause
at DF ARS 252.227-7014 (Jun. 1995).
Motoro la , Inc.
Computer Group
2900 South Diablo Way
T empe, Arizona 85282
About t his Manual
Summary of Changes ................................................................................................xix
Systems Supported ........................... .................... ............................... .................... ..xxi
Overvie w ............ .............. ............... ...................... ...................... ..................... ........xxi i
Comments and Suggestions ................................................................................ .....xxii
Conventions Used in This Manual ......................................................................... xxiii
T able 6-44. DC Analog Voltages for H.110 Bus ................................................... 6-57
T able A-1. Total Regulation (per Output) ...............................................................A-3
T able B-1. Related Specifications ...........................................................................B-2
xvii
About this Manual
This manual is directed at the per son who needs de tailed configur ation a nd
specification information for CompactPCI modules and system
subassemblies of the CPX8000 series computer system. Included is an
overview of the system archite cture for the CPX8216 and CPX81216T
systems. It also presents the corr ect strapping and pin-out information for
the modules and subassemblie s covered.
This manual does not provide installation, removal, or use procedures.
People requiri ng this type of information should refer to the CompactPCI CPX8216 and CPX8216T System Installa tion and Use man ual as listed in
Appendix B, Related Documentation.
Summary of Changes
This manual has been revised and replaced any previous editions. Below
is a history of the changes affecting this manual.
DateChange
July 2002Updated PMC Module chapter, see Chapter 4, PMC
Modules.
Load sharing information a dded, see The Act ive/A ctiv e or
Load-Sharing Configuration on page 1-9
Domain ownership further def ined, see Chapt er 1, System
Architecture
Dual breaker DC power distribution panel information
added (with Smart cabl e), see D u a l Breake r DC Power
Distribution Panel (CPX8216) on page 6-55.
April 2002Section describing system domains and domai n
ownership information added, see System Domains on
page 1-1.
Section describing hot swap controllers added, see Hot
Swap Controller on page 1-6.
xix
DateChange
Power distribution information added, see Power
Distribution Panel on page 6-54.
August 2001Details about assi gning chassis IDs on the CPX8216T
system added. See Chassis ID for CPX8216T on page
1-13.
Updated model numbers , see Systems Supported in this
section.
April 2001Added cautions regarding hot swap software and hot
swappable drives.
July 2000Updated pin assignment table s for connector P2
(HSC and CPU slots.)
March 2000DC Input vol tage change d to - 36Vdc to -72Vd c. Change d
URLs to reflect new Web sites.
November 1999Added System Architecture chapter.
Added TNV branch circuit safety standards information.
Added the Index.
August 1999Added information for the CPV5350 Intel CPU
Added information for the H.110 Backplane and Power
Distribution Pane l for the CPX8216T system
xx
May 1999Replaced Figure 2-1 with corrected board illustration
January 1999Original Document
Systems Supported
This information in this manual applie s to the modules and subassemblie s
supported by the following systems:
This manual is divided into the followi ng topic s:
❏Chapter 1, System Architecture
❏Chapter 2, CPU Modules
❏Chapter 3, CPX8540 Carrier Card
❏Chapter 4, PMC Modules
❏Chapter 5, Tr ansition/Bridge Modules
❏Chapter 6, Subassembly Reference
❏Appendix A, Specifications
❏Appendix B, Related Documentation
Comments and Suggestions
Motorola welcomes and appreciates your comments on its documentati on.
W e want to know what yo u think about our manuals and how we can make
them better. Mail comments to:
Motorola Computer Group
Reader Comments DW164
2900 S. Diablo Way
T empe, Arizona 85282
xxii
You can also submit comments to the following e-mail address:
reader-comments@mcg.mot.com
In all your c orrespondence, please list your name, position, and company .
Be sure to include the title and part number of the manua l and tell how you
used it. Then tell us your feelings about its str engths and weaknesses and
any recommendations for improvements.
Conventions Used in This Manual
The following typographi cal c onventions are used in this document:
bold
is used for user input that you typ e ju st as it appe ars; it is als o used for
commands, options and arguments to commands, and names of
programs, directories and files.
italic
is used for names of varia bles to which you assign value s. Italic is also
used for comments in sc ree n displays and examples, and to introduce
new terms.
courier
is used for system output (for example, sc reen displays, reports),
examples, and system prompts.
<Enter>, <Return> or <CR>
represents the carriage return or Enter key.
Ctrl
represents the Contr ol key. Execute control characters by pr essing the
Ctrl key and the letter simultaneously, for example, Ctrl-d.
xxiii
1System Architecture
PICMG Compliance
The CPX8216 system is designed to be fully complia nt with the
CompactPCI Hot Swap Specification developed by the PCI Industrial
Computers Manufacturi ng Group (PICMG). With the proper software
support and testing, it should be possible to integrate all propri etary and
third-party I/O modul es which are compatible with this specificat ion.
Further , the system allows the use of I/O modules which are not hot
swappable, but the system must be powered off when such modules are
inserted and extract ed .
The CPX8216 also fe atures the ability to hot swap system and nonsystem
processor boards, a feature which is beyond the scope of the PICMG
specification. As part of its c ommitment to open standards, Motorola will
propose that th e proce ssor ho t swap c apabilit ie s of th e CPX8216 be added
to the Hot Swap Specification. At this point, however, there are no thirdparty CPU modules which are compatible with the CPX8216 syst em.
1
System Domains
The high availa bility a nd high slot coun t of th e CPX8216 sys tems i s made
possible by implementing two host CPU slots a nd multi ple CompactPCI
bus segments in a single chassis. These bus segments, along with other
system resources are grouped into two logical domains, A and B, which
can be controlle d by either host-HSC pair r egardless of the bus se gment the
host sits on. Domain A includes C ompactPCI bus segment A (sl ots 1 to 8),
the power supply/fan tray modul es and alarm controls. In the CPX8216,
domain B consists of the CompactPCI bus segment B (slots 9 to 16). For
further information on domain c ontrol or ownership, see the section, Hot
Swap Contr oller on page 1-6.
1-1
1
System A rchitecture
Al arm Controls
Domai n ADomain BD om a in A/B
Figure 1-1. CPX8216 Domains
System Layout
The CPX8216 is a 16-slot, high-avail abilit y CompactPCI system with two
separate 6-slot CompactPCI I/ O domains and the capa bility to contain
redundant CPU modules and redundant Hot-Swap Controller (HSC)
modules. It is also possible to configure the sy stem as a simplex, h igh I/O
system containing a single CPU-HSC pair. Eve n as a simplex system, the
CPX8216 still provides improved availability through redundant powe r
supplies and the control/moni toring capabilities of the HSC, as described
in The Hot Swap Controll er/Bridge (HSC) Module on page 1-5.
Bus ABus B
Power Supply/Fan Trays
Drive
Bays
CPX8216
The CPX8216 standard system consists of two 8-slot subsystems, or
domains, each with two slots for the host proces sor and six slots for
nonhost CompactPCI boards. The HSC board mounts in the rear of the
chassis, behind the s econdar y CPU slot. Figur e 1-2 on pa ge 1-3 pr ovides a
diagram of this configuration.
1-2Computer Group Literature Center Web Site
CPX8216
Rear Card Locations
Segment A
CPU Transition Module
Segment B
Transition Slots
12345679111213141516
Segment A
I/O Slots
Compact PCI
Segment A
Segment B
CPU Transition Module
Segment B
Front Card Locations
HSC
Segment A
HSC
Segment B
Transition Slots
Segment B
I/O Slots
Compact PCI Bus
Segment B
2450 9812
Figure 1-2. CPX8216 Standard System Layout
Each of the two independent I/O domains has its own system processor
slot. Each system processor has direct access to its local bus through an
onboard PCI-to-PCI (P2P) bridge. Each domain is also capable of
supporting a Hot Swap Con troller ( HSC) module that cont ains its own P2P
bridge. Thus, in a f ul ly redunda nt configurati on, there are two bridge s tha t
have access to ea ch of the I/O buses—one assoc iated with the CPU and one
with the HSC. Only one of the bridges may be active at a time, however.
1
http://www.motorola.com/computer/literature1-3
1
System A rchitecture
CPX8216T (H.110)
The CPX8216T H.110 system consists of two 8- slot subsystems, or
domains, each with one slot for the host processor, one slot for the frontloaded HSC, and six slots for nonhost CompactPCI boards. F igure 1-3 on
page 1-4 provides a diagram of this configuration.
Rear Card Locations
Segment A
CPU Transition Module
Segment B
CPU Transition Module
Segment B
Transition Slots
12345679111213141516
Segment A
I/O Slots
Compact PCI
Segment A
CPU
A
Segment B
HSC
Front Card Locations
Figure 1-3. CPX8216T H.110 System Layout
Bus Access and Control
In the fully redundant configur ation, the CPU in the left system slot, CPU
A, is associated with the HSC in t he right HSC slot, HSC A (note th at HSC
A actually sits on the Domain B bus). The re is a l ocal connec tion betwe en
each CPU-HSC pair that allows the CPU in one domain to control the other
domain through its HSC. This architecture is illustrated in the following
figure.
810
CPU
B
Segment A
HSC
Segment B
Transition Slots
Segment B
I/O Slots
Compact PCI Bus
Segment B
1-4Computer Group Literature Center Web Site
The Hot Swap Controller/B ridge (HSC) Module
S p e c ia l B a c k p la n e
P C I Inte r co n n e c ts
C
H
H
C
P
U
A
S
P
S
C
U
C
A
B
B
1
I/O D o main A
I/O
I/O
S
S
L
L
O
O
T
T
I/O
I/O
I/O
I/O
S
S
S
L
L
O
O
T
T
S
L
L
O
O
T
Primary CompactPCI
T
Buses
I/O D o m a in B
I/O
I/O
S
S
L
L
O
O
T
T
I/O
I/O
I/O
I/O
S
S
S
L
L
O
O
T
T
S
L
L
O
O
T
T
Figure 1-4. CPX8216 I/O Bus Connectivity
In addition to provi ding bridges t o the remote I/O bus es, the HSC provides
the services necessar y to hot swap CPU boards and nonhost proces sor
boards and also contro ls the system ala rm panel, fans, and power suppli es.
The Hot Swap Controller/Bridge (HSC) Module
The HSC module connect s to the CPU module through a loc al P CI bus, as
illustrated in Figure 1-2 and Figure 1-3. The HSC module contains a PCI-
to-PCI bridge and also contains a Hot Swap Controller .
The functionalit y provided by the HSC is at the heart of the High
Ava ilability CPX8216 System. Its primary functions include:
❏Providing a bridge between the two ei ght-slot CompactPCI buses
so that they can be managed by a single CPU module
❏Maintaining a Control Status Register whi ch contains in formation
on the status of each system module
http://www.motorola.com/computer/literature1-5
1
System A rchitecture
❏Controlling power and resets to each system module through
radial connections
❏Monitoring and controlling CPU boards, nonhost boar ds, a nd
peripherals, including power and fan sleds, board and system
LEDs, and alarms
Hot Swap Controller
Each of the nonhost slots in the syste m can be controlled from either HSC.
When an HSC has control over a domain it has control over the nonhost
boards in that domain. Each host processor /br idge pair is controlled as a
single item by the other processor/bridge pair. The bridge and the host
processor are linked together so tha t both must be present for power to be
applied. A host processor cannot be operate d without its HSC.
With the CPX8216 a rchitectur e it is importa nt that the syste m initializes t o
a state that allows the host processor s and HSCs to be in control of the
system. The default conditions are:
❏System processors an d bridges are powered up (if present)
❏System processors an d bridges are disconne cted from their busses
❏HSCs are not in control of either domain
❏Nonhost boards are powered off
❏Peripheral bay s are pow e red u p (if pres en t)
❏Fans and power supplies are powere d on
NoteSystem components such as fans and power supplies may be
controlled by e ither HSC but not both. Def ault cont rol belongs to
Domain A and whichever HSC has control of Domain A has
control of the system functions .
If Domain A is not controlled, nonhost boards are powere d- off
and all LED updates to the display panel and power supplies are
suspended. Also, monitoring of alarm inputs from the display
panel and power supplies are inhibited.
1-6Computer Group Literature Center Web Site
System Process o r Config urati o n s
Subsequent to the default, the system software must determine the
configuration of the system and then proceed to change it.
System Processor Configurations
The CPX8216 is a flexib le system that allows for multiple configurations
of processor control, I/O redundancy, and peripheral configur ations. The
following sections br iefly touch on possible configurati ons.
As noted above, there are three possible processor/control configurations:
❏A simplex system conta ining a single CPU-HSC pair controlling
both I/O domains
❏An active/pa ssive configuration simila r to the simpl ex
configuration , but providing a warm backup for bot h the CPU and
the HSC
❏An active/active or load-sharing configuration in which each CPU
runs a single domain while also serving a s a backup to the othe r
CPU.
NoteH.110 traffic and HA Linux do not support a load-
sharing configura tion.
1
The following sections give a general de scription of these configurations.
The Simplex Configuration
Because of the flexible nature of the CPX8216, it is possible to configure
it with different lev el s of redundancy and availability. For applications
which do not require the benefits of full high availability, it is possible to
configure the CPX8216 as a simplex, 16-slot system. This configuration
provides the benefits of redundant power supplies and the system
monitoring capabilities of the fully redundant configuration.
http://www.motorola.com/computer/literature1-7
1
System A rchitecture
The simplex configuration is illustrated in the following figure.
I/O D o main A
I/O
I/O
I/O
I/O
I/O
I/O
S
S
S
S
S
L
L
L
O
T
L
O
O
O
T
T
T
S
L
L
O
O
T
T
The Activ e/Pa ssive Configu r ati on
In the active/passi ve configuration , one CPU manages all twelve I/ O slots,
much like in the simplex confi guration. In addition, th e second CPU serves
as a warm standby, ready to run the system in the event of a failure on the
active system.
The active/passive confi gur ation is illustrated in the following figure.
Active CPU
C
P
U
A
H
S
C
A
I/O D o main B
I/O
I/O
I/O
I/O
I/O
I/O
S
S
S
S
S
L
L
L
O
O
T
T
C
H
H
C
P
U
A
S
P
S
C
U
C
A
B
B
Activ e HS C
L
O
O
T
T
S
L
L
O
O
T
T
I/O Domain A
Passive
I/O Domain B
CPU/HS C
I/O
I/O
I/O
I/O
I/O
I/O
S
S
S
S
S
L
L
O
T
L
O
O
O
T
T
S
L
L
L
O
O
T
T
T
I/O
I/O
I/O
I/O
I/O
I/O
S
S
S
S
S
L
L
L
O
O
T
T
L
O
O
T
T
S
L
L
O
O
T
T
1-8Computer Group Literature Center Web Site
The Active/Active or Load-Sharing Configuration
The Active/Ac tive or Load-Sharing Confi guration
In the load sharing configu ration, each CPU manages si x of the twelve I/O
slots, much like a dual 8-slot system with the added benefit of one CPU
being able to control all twelve I/O slots if the other CPU fails. It is
important in a load-shar ing configuration to note that the total cri tical
activity does not exceed the capabilities of a single CPU, because either
one of the C PUs must be ready to take over the loa d carried by the other.
The active/activ e confi guration is illustrated in the following figure.
H
C
H
C
P
S
S
P
U
A
C
U
C
AB
B
1
I/O D o main A
I/O
I/O
S
S
L
L
O
O
T
T
I/O
I/O
I/O
I/O
S
S
S
L
L
O
O
T
T
S
L
L
O
O
T
T
I/O D o m a in B
I/O
I/O
S
S
L
L
O
O
T
T
I/O
I/O
I/O
S
S
L
O
T
S
L
L
O
O
T
T
NoteH.110 traffic and HA Linux do not support a load-sharing
configuration .
I/O
S
L
O
T
http://www.motorola.com/computer/literature1-9
1
System A rchitecture
I/O Configurations
The CPX8216 contains two independent 8-slot Co mpactPCI buses. One
slot in each bus is dedicated to a system processor, and another is needed
for the HSC. This leaves six slots on each bus to support I/O devic es or
nonsystem processors.
One possible configuration is to use the CPX8216 as a high I/O
CompactPCI system with redundant CPUs. With this configuration, it is
possible to run twelve independent I /O modul es within a CPX8216
system. Applications requiring dense processing power could use all
twelve I/O slots to support nonsystem processors.
Such a system would be protecte d against a CPU or HSC fault, but it would
be vulnerable to data losses if any of the I/O modules or nonsystem
processor modules were to fail. In syste ms handling critical data, it is
possible to implement a 2N or an N+1 I/O redundancy str ategy that allows
the level of service to be continued in the event that a module fails.
In the case of a 2N-redundant system, each I/O module or nonsystem
processor module is matched with an identical module on the other bus.
The paired modules can be configur ed in an active/passi ve arrangement or
a load-sharing arrangement in wh ic h each carri es h al f of the load of a
single module. In an N+1 ar rangement, multi ple modules a re backed up by
a single spare. For example, a single passive nonsystem processor module
can be used to back up five others.
Peripherals
Power/Fan Modules
The CPX8216 system requires a minimum of two power/fan sled modules
and a fan-only sled module to provide adequate power and cooling for a
fully loaded, nonredundant system. The system can c onta in a third power
supply/fan sled a s part of an N+1 strategy, meaning that the system can
continue providing se rvice if one of the mod ules fails. These modules are
hot swappable and available for DC and AC environments.
1-10Computer Group Liter ature Center Web Site
The fans run at e ither high speed (def ault) or temperatu re controlled, which
!
Caution
can be changed using the operatin g syste m software via the API.
Drive Modules
The CPX8216 contains four hot-swappa ble peripheral bays, all of which
support both S CSI and EIDE protocols.
Drive Modules
1
Caution
The hot swapping of hard drive s is supported when your system is
configured with the appropriate software support for hot swap and when
the drives a re in a hot-swap drive carrier.
SCSI devices can be conf igured to be fully hot -swappable, and data can be
hot switched between two inde pendent SCSI controllers. EIDE devices are
assigned to a single EI DE contr oller . They can be wa rm swapped, m eaning
that a failed device can be replaced once the controller has been powered
off.
The rear of the CPX8216 chassis may be configured with either single or
double, fixed, floppy dr ives. Floppy drives are not hot-swappable.
For more information on instal ling both hot-swappable and non-hotswappable drives, refer to the Drive Removal and Installation chapter of
the CPX8216 and CPX8216T CompactPCI System Installation and Use
manual.
http://www.motorola.com/computer/literature1-11
1
System A rchitecture
CPU Complex Architecture
The CPU complex in the CPX8216 contains two CPU modules and their
corresponding Hot Swap Controller (HSC) modules. The figure below
illustrates the architecture, including elements on the boards as well as
local connections between the CPU modules and the PCI-to-PCI (P2P)
connections to the local CompactPCI buses.
Local Conne ct i ons between CPU Modules
Enet
Serial
Link
ISA
IDE
The CPU Module
In addition to the processor, RAM, etc., each CPU module contains one:
❏Up to two Ethernet controllers
❏Up to two serial communications links
❏P2P bridge to the local CompactPCI bus
❏Local PCI Bus connection to the HSC
Proc
P2P
RAM
HSC
P2P
HSC
P2P
RAM
P2P
CompactPCI BusCompactPCI Bus
Proc
Enet
ISA
IDE
Serial
Link
1-12Computer Group Liter ature Center Web Site
Switching Service to the Passive CPU
The switchover from one CPU to another is initia te d by the passive CPU
when there is an indication tha t there is something wrong with the active
CPU--such as a failed heartbe at protocol. The passive side notifies the
active side t hat it is about to begin a switchover process. I f the active side
agrees to the switc hover, then the two si des coordinat e the hand-of f and no
bus signals, clocks, or devices should be corrupted. If the active system
fails to cooperate with the takeover atte mpt, the n we mus t assume that b us
signals, clocks, and devices attached to the bus may be corrupted.
In a more e xtreme ta keove r , i t i s pos sibl e for the passi ve CPU to powe r -on
reset the active CPU and to take control that way.
Chassis ID for CPX8216T
A unique 5-bit chassis ID can be assigned for each CPX8216T system.
Hex values are on the r otary switches locate d on the HSC boards. A jumper
can be added to J14 to double the number of unique identifiers. This
feature should be used if more than 15 chassis a re deployed in one locatio n.
The HSC boards are shipped wi th no j umper as the def ault. For gui de lines
on setting the chassis ID on yo ur CPX8216T system, refer to the CPX8000 Series CPX8216 and C PX8216T CompactPCI System Install ation and Use
manual.
Switching Service to the Pa ssive CPU
1
Alarms and LEDs
In order to provide a uniform appear ance, without depending on individual
board manufa ct u rers, the CPX8216 con tai ns a se parat e al arm display
panel, which runs across the top of the chassis. In addition to In
Service/Out of Service LED indicators for all sixteen slots, the alarm
display panel contains LEDs for system status (System in
Service/Component out of Service/System out of S ervice) and for the thre e
standard Telco levels (Critical/Major/Minor ). The three Telco alarms are
also signalled through a dry contact relay.
http://www.motorola.com/computer/literature1-13
1
System A rchitecture
H.110 Telephony Bus
The CPX8216T supports an H.110 Computer Telephony Bus. The H.110
bus uses P4/J4 as defined in the PICMG specification for CompactPCI.
P5
P4
P3
P2
P1
H. 110 Bus
CompactPCI Bus
System Slot
HSC Slot
2557 9906
Figure 1-5. The CPX8216T H.110 Bus
Board Insertion and Extraction Features
The PICMG specificat ion detail s sof tware and hardwar e fea tures, i n orde r
to support hot swapping of I/O boards. Hardware features include:
❏Staged pins that contr ol voltages when inserting or extracting
boards
❏BD_SEL#, HEALTHY#, and ENUM# signals
❏Hot swap control status register
1-14Computer Group Liter ature Center Web Site
Staged Pins
Staged P i n s
1
The PICMG CompactPCI hot swap specification provides for three
separate pin lengths in order to control the insertion and extraction
voltages and to notify the syste m when boards are inserted or extracted.
The longest pins, which include VCC pins and GND pins, are the first to
mate during the insertion pr ocess a nd the last to break contact during
extraction. These pins are used to supply power to pre-charge the PCI
interface signals to a neutral state before they contact the bus. This precharging se rves to min imize the c apa citive effects of the board as it makes
or breaks contact with the bus.
The medium-length pins carry PCI and other signal traffic.
The shortest pins are used to asser t signals, including BD_SEL#. During
insertion, the BD_SEL# si gnal ena bles the board to at tach to the local P CI
bus. On extraction, it cause s the board to logically and electricall y
disconnect from the PCI bus before the bus pins physically break contact
with the bus.
BD_SEL#
BD_SEL# is asserted by one of the pins that mate last on insertion and
break first on extr actio n. On inser tion , the signal t ells t he boa rd to conne ct
to the PCI bus. On extraction this pin breaks first, causing the board to
logically and elect ri cally disconnect from the PCI bus before the PCI bus
pins physically break contact with the bus.
ENUM#
An ENUM interrupt is generated when a boar d is ho t inse rt ed into the
CPX8216 chassis, or when an operator trips the board microswitch by
raising its ejector handles. The signal informs the active CPU that the
status of a board ha s changed. The CPU then identifie s the board by polling
the INSert a nd EXTract bits in all of the boards’ Control Status Registers.
http://www.motorola.com/computer/litera ture1-15
1
System A rchitecture
Hot Swap Control Status Register (CSR)
The CPX8216 supports hot swap CompactPCI cards with the standar d
control status regis ter defined by the PICMG Hot Swap Specification . The
register is visibl e in PCI configuration space and pro vides hot swap control
and status bits: INS and EXT. The INS signal is set when ENUM# is
asserted by a board being inserted into the system. The EXT signal is
asserted when ENUM# is asserted by an operator triggering the
microswitch in the board handles. The host also uses these bits to
acknowledge and de-assert ENUM#.
The Hot Swap Process
PICMG divided the complete hot swap process into physical, hardware
and softw are connection processes. These processes are formally brok en
down further int o a group of transit iona l stat es, wh ich are i llust rated in t he
following figure.
PHYSICAL
CONNECTION
STATES
P0P1
H0H1
HARDW ARE
CONNECTION STATES
H1F
SOFTW ARE
CONNECTION
STATES
H2
S0S2S3
S1
S2QS3Q
When inserting a board, it goes through all states f rom P0 to S3.
Conversely, a board transitions from S3 to P0 before being extracted.
During normal operation, no states are skipped. Extracting a board in a
software connection st ate other than S0 is l ikely to disrupt software enoug h
to crash the system, b ut the C ompactPCI bus , from a purely ele ctrical poi nt
of view , will not be disrupted enough to cause logic levels to be viol ated.
Certain states are overlapping. For example, when the board is fully seated
(completed P1), but has not yet started the hardware connection process
1-16Computer Group Liter ature Center Web Site
(H0), it said to be in the P1/H0 state. Similarly , one can speak of a board
being in the H2/S0 state.
Physical Connection Process
The physical connect ion process is the basic proce ss of putting a board into
a live system, or physi cally remo ving th e board. The process i nclude s two
states:
❏P0 - The board is physically separate from the system
❏P1 - The board is fully seated, but not powered, and not active on
the PCI bus. All pins are connected.
Hardware Connection Process
The hardware connection pro cess involves the electrical connection or
disconnection of the board. This process includes three states:
❏H0 - The board is not active on the PCI bus. This state is equivale nt
to P1 above.
Physical Connection Process
1
❏H1 - The board has powered up and is suffic ie ntly initialized to
connect to the PCI bus.
❏H2 - The board is powered, and enabled for access by a PCI bus
transaction (nor mally by the host) in PCI conf iguration space onl y .
The board configuration spa ce is not yet initialized.
When a newly inserted board has completed H2, the board is ope rable
from a hardware perspective. It has run its power up diagnostics, initi alized
itself, loaded EEPROM data, etc. The blue LED is off in the H2 state,
indicating that the board should not be pulled out.
http://www.motorola.com/computer/literature1-17
1
System A rchitecture
Software Con n ect io n Proce ss
The software connection process inc ludes the tasks needed to configure
and load software. This process conta ins four states:
❏S0 - The Software Connection Process has not been initi ated. The
board’s configuration space registers are accessible but not yet
initialized.
❏S1 - The board is configured by the system. The system has
initialized the board ’s PCI configuration space registers with I/O
space, memory space, inte rrupts a nd PCI bus nu mbers. The board
is ready to be accessed by a devic e driver, but no drivers are loaded
at this time.
❏S2 - The necessary supporting sof tware (drivers, etc.) have been
loaded. The board is ready for use by the OS and/or the
application, but no operations involving the board are active or
pending.
❏S3 - The board is active. Software operations are either active or
pending.
Software Disconnection Process
The software disconnecti on proce ss defines two additional states which
are used when quiescing activity on a board in prepara tion for extraction:
❏S3Q - The software is completing current operations, but is not
allowed to start new ones . When current operations are c ompleted,
the board transitions to S2.
❏S2Q - The board is quiesced. This is the same state as S2, except
that no new operations are allowed to be initiated.
The Software Disconnection Process proceeds as S3, S3Q, S2Q, S1, and
finally S0.
1-18Computer Group Liter ature Center Web Site
Typical Inserti on and E xtraction Processes
Typical Insertion and Extraction Pro cesses
Many of the steps in the inser tion and extraction proc esses are automated
by software. After the operator installs a board, it automatical ly advances
to P1. The hardware connection process proceeds automatically a nd
asserts the ENUM# signal to initi ate the softwa re conne ction process. The
host responds to the bussed ENUM# signal by reading the Hot Swap
Control Status Regist er of each board to find out which one is signaling an
insertion or extraction (INS or EXT bit asserted). Upon detecting an
insertion, the Host responds by adding software drivers to support the
newly inserted board.
Extraction is initia ted when the operator opens the board ejector handl e,
which activates a mechanica l switc h to assert ENUM#. The hot plug
system driver senses ENUM# and notifies software that board activity
must be quiesc ed and that software device drivers should be unloaded. The
application tha t is using the board is informed that the reso urce is no longer
available. When the board is ready for extraction, software informs the
operator by illuminating the blue LED. After extraction, all system
resources previously assigned to that board are made available for other
uses.
1
Device Drivers
In order to take full advantage of the high availability functions of the
CPX8216, and to support hot swap, board device drivers need to be
enhanced. Driver s need to cease a ll ac tivity whe n the devic e is a bout to be
hot swapped, and they need to support initialization of the device without
support from the device firmware or BIOS.
Further , high availability device drivers need to be able to enter a sta ndby
mode while bus control is being passed from one CPU to another. They
also provide diagnost ic interfaces for run time fault detection and for preinitialization testing of newly inserted boards.
http://www.motorola.com/computer/literature1-19
Overview
2CPU Modules
2
This chapter provides reference information for the CompactPCI system
controller/ host CPU modules supported in the CPX8216 system.
The correct jumper setting and pin-out information is provided for each
module.
NoteThe CPX750HA is som etimes identified as an MCP750HA in
some chassis and firmware documentation, for packaging and
ordering purposes, but both numbers apply to the same board.
Your system may not contain all boards listed in this chapter, or
it may contain third-par ty boards that are not listed in this
chapter. For information about third-party boards, refer to the
board manufacturer’s documentation.
This chapter contains information for the following CompactPCI boards:
Part No.Des cr iption
CPX750HAPowerPC Hot Swappable CPU12-1
CPV5350Intel H ot Swappable CPU12-16
CPX750HA
The CPX750HA is a single-slot, single-board computer equipped with a
PowerPC™ 750 Series microprocesso r. The processor implements a
backside cache controller and the board comes with 1MB of cache
memory.
Table 2-1. CompactPCI Boards
Slots
OccupiedPage
2-1
CPU Modules
2
The CPX750HA offers many standard features desirable in a CompactPCI
computer system, suc h as:
❏PCI Bridge and Interrupt Con troller
❏ECC Memory Controller chipset
❏5MB to 9MB of linear FLASH memory
❏IDE CompactFlash memory
❏16MB to 256MB of ECC-protected DRAM
❏Interface to a CompactPCI bus
❏Several I/O periph erals
The I/O peripheral interfac es present on the onboard PCI bus include:
❏One 10/100-BASE-T Etherne t interface
❏One USB host controller
❏One SA master/slave interface
❏One Fast EIDE interface
❏One P MC Slot
Functions provided from the ISA bus are two asynchronous and two
synchronous/asynchronous serial ports, keyboard, mouse, a floppy disk
controller, printer port, a real time clock, and NVRAM.
The CPX750HA interfaces to a CompactPCI bus us ing a DEC 21 154 P CIto-PCI bridge device. This device pr ovides a 64-bit primary and a 64-bit
secondary interfa ce allo wing full 64-bit d ata ac cess between Compac tPCI
bus devices and the host/PCI bridge. This bus is capa ble of driving seven
CompactPCI slots.
Another key f eature of the CPX750HA is the P CI (Peripheral Component
Interconnect) bus. In additi on to the onboard local bus periphe rals, the PCI
bus supports an industry-standard mezzanine interface, IEEE P1386.1
PMC (PCI Mezzanine Car d). PMC m odules of fer a variety of pos sibil ities
for I/O expansion.
2-2Computer Group Literature Center Web Site
CPX750HA
The base board suppor ts PMC I/O for the fr ont panel or th rough backplane
connector J3 to a CPX750HATM transition module.
J6
1
3
PCI MEZZANINE CARD
10/100 BASE T
COM 1
RST
ABT
BFL
CPCI
USB 1
USB 0
CPU
CPI
J8
1
82
71
J15
69
15
J10
S2S1
189
1902
DS2
DS1 DS3
DS4
1
J17
4
1
J18
4
1
XU1
XU2
J19
2213 9804
1
2
1
2
J11
49
50
1
2
J13
49
50
J9
1902
189
J5J4J3J2J1
J12
49
50
1
2
J14
49
50
F1F2F3
2
http://www.motorola.com/computer/literature2-3
CPU Modules
2
Connectors and Ju mper Settings
The next sections provide pinout inform ation and jumper settings for the
CPX750HA board. Additiona l pinout assignments can be found in
Chapters 3 through 6.
Backplane Connectors (P5, P4, P3, P2, P1)
Refer to the backplane reference section for the backplane connector pin
assignments.
Front USB Connectors (J17 and J18)
Two USB Series A receptacl es are l oc ated at the fron t pan el of the
CPX750HA board. The pin assignments for these connec tors are as
follows:
Table 2-2. USB 0 Connector J18
1UVCC0
2UDATA0N
3UDATA0P
4GND
Table 2-3. USB 1 Connector J17
1UVCC1
2UDATA1N
3UDATA1P
4GND
10BaseT/100BaseTx Connector (J8)
The 10BaseT/100BaseTx Connector is an RJ45 connector located on the
front panel of the CPX750HA board. The pin assignments for this
connector are as follows:
2-4Computer Group Literature Center Web Site
Connectors and Jumper Settings
Table 2-4. 10BaseT/100BaseTx Connector J8
COM1 Connector (J15)
A standard DB9 receptac le is located on the fr ont panel of the CPX750HA
to provide the interfac e to the COM1 serial port. These COM1 signals are
also routed to J11 on the tra n sition module. A terminal may be connected
to J15 or J11 on the transition module but not both at the same time. The
pin assignments for this con nector is as follows:
A 190-pin connector (J19 on the CPX750HA base board) provid es access
to the processor bus (MPU bus) and some bridge/memory controller
signals. It can be used for debugging purposes. The pin assignments are
listed in the following table.
A 190-pin connector (J10 on the CPX750HA base board) supplies the
interface b etw een the mem o ry bus and the RAM300 DRAM mezzanine.
The pin assignments are listed in the following table.
A 50-pin Compact F LASH card header connector provides the EIDE
interface to the Compact FLASH Memory Card. The pin assignments for
this connector are as follows:
The CPX750HA base board has provision for 1MB of 16-bit flash
memory. The RAM300 memory mezzanine accommodates 4MB or 8MB
of additional 64-bit flash m emory.
The flash memory is organized in eithe r one or two banks, each bank either
16- or 64-bits wide. Bank B contains the onboard de bugger, PPCBug.
T o en able fla sh ban k A (4MB or 8MB of fir mware reside nt on soldere d-in
devices on the RAM300 mezza nine) , pla ce a j umper acros s he ader J 6 pi ns
1 and 2. To enable fla sh ban k B (1MB of firmware lo cated in soc k et s on
the base board), place a jumper across he ader J6 pins 2 and 3.
2
J6J6
3
3
2
1
Flash Bank A Enabled (4MB/8MB, Soldered)Flash Bank B Enabled (1MB, Sockets)
2
1
(Factory Configuration)
http://www.motorola.com/computer/literature2-15
CPU Modules
2
CPV5350
The CPV5350 Single Boar d Computer (SBC) is a hot swap, CompactPCI
(Compact Peripheral Communication Interface) compliant computer with
high availability pla tform support. It is powered by a PICMG (PCI
Industrial Computer Manufacturers Group) compatible Pentium® II
Deschutes Mobile Module. The CPV5350’s 6U CompactPCI standard
form factor (160mm x 233mm x 61mm), 4HP (.8 inch) is designed for
installation into PICMG CompactPCI-compliant backplanes.
The CPV5350 provides:
❏Standard PC I/O
❏USB
❏PCI EIDE
❏3D AGP graphics
❏Dual fast Ethernet controllers
❏Optional onboard CompactF lash™ connector
The CPV5350’s front panel has connectors for:
❏Keyboard/mouse
❏Video
❏Two serial ports (COM1 and COM2)
❏Two Ethernet ports
❏Two USB ports
❏LED Indicator lights for wat chdog alarm, speaker st atus, ha rd disk
drive activity, and power.
Refer to the following ill ustra tion for front panel c onnector s and LEDs on
the CPV5350.
2-16Computer Group Liter ature Center Web Site
Video
COM 1
Ethernet 1
Ethernet 2
USB
CPV5350
2
V
I
D
E
O
1
COM 2
2
1
E
T
H
E
R
N
E
T
2
Keyboard/Mous e
RESET
Indicator
Lights
RESET
SPKR
ALRM
PWR
HDD
CPV5350
http://www.motorola.com/computer/literature2-17
CPU Modules
2
Connectors
The next table lists the connectors available to support devices on the
CPV5350. Figure 2-1 on page 2-19 shows the location of the connectors
described in the table.
Table 2-9. CPV5350 Front Panel Connectors, Board
Headers and Componen ts
ConnectorDescription
J1Backplane connecto r
J2Backplane connecto r
J3Backplane connecto r
J4Backplane connecto r
J5Backplane connecto r
J6E therne t 2
J9E IDE
J10Reserved (in-circuit programming)
J12Reserved (in-circuit emulator)
J13Eth ernet 1
J14USB port 1
J16Reset (c onnected to push-butt on on the front panel)
J21Flash ROM
J23Video connector
J24CO M 1 (S erial P o r t 1)
J25CO M 2 (S erial P o r t 2)
J50Keyboard/Mouse
2-18Computer Group Liter ature Center Web Site
Transiti on Module
2
U34U35
U30U31
12
J12
J5
U11
J23
J4
J24J25
J3
2475 99012475 9901
J13J6
2
1
BT1
T1T2
J2
U38
J20
U55
U62
J14J50
J1
U50
U25U26
J51
CR2 CR4
21
CRI
8
J17
1
J21
CR3
Figure 2-1. CPV5350 Component Side View
Transitio n Mo du le
The CPV5350TM80 transi tion module provides backpl ane I/O through the
J3 and J5 connectors on the CPV5350 controll er modul e.
When the identical function is available through the CPV5350’s front
panel and the rear transition module, you can use either the front or the
rear , not both.
http://www.motorola.com/computer/literature2-19
CPU Modules
2
DRAM Memory Configuration
The CPV5350 has one 168-pin DIMM site for memory expansion. The
DIMM sites accept industry standar d PC100-com pliant DIMM modules
(8, 16, 32, 64, 128, or 256MB) with or without ECC. You can use either
registered or unbuffered memory modules.
Keyboard/Mouse PS2 Connector
The keyboard/mouse connector (J50) uses a 6-pin, female PS/2 c onnector.
Table 2-10. Keyboard/Mouse P/S2 Connector Pin
Assignments (J50)
Pin
Number
1KBDDATKeyboard Data
2AUXDATAuxiliary Data
3GNDGround
4KBDVCCKeyboard Power (c urrent limited to .75 Amp)
5KBDCLKKeyboard Clock
Signal
MnemonicSi gn al Des cription
6AUXC LKAuxiliary Clock
7CGNDCommon Ground
6
4
2
2489 9902
5
3
1
7
Figure 2-2. Keybo ar d/M ous e Conne cto r Diagra m
2-20Computer Group Liter ature Center Web Site
Ethernet Connectors
Ethernet Connec tors
Ethernet 1 (J13) and Ethernet 2 (J6) use standard RJ-45 connectors.
T able 2-11. Etherne t Connec tor P in Ass ignme nt s (J13 an d
J6)
Pin
Num berSigna l M n emon icSi gnal De s c r i p t io n
USB Port 1 and Port 2 (J14) use a 2 x 4 pin USB connector.
Table 2-12. USB Connector Pin Assignments (J14)
Pin
NumberSignal MnemonicSignal Description
1+5VCurrent limited USB power
2DATA+USB serial communication diffe rential
3DATA-USB serial communication differenti al
4GNDUSB port common
http://www.motorola.com/computer/literature2-21
CPU Modules
2
Serial Port Connectors
COM 1 (Serial Port 1) (J2 4) an d COM 2 (Seria l Port 2) (J25) use 2 x 9-pin
D-sub connectors.
Table 2-13. Serial Port Connector Pin Assignments (J24
and J25)
Pin
Number
1DCD-dat a set has detected the d ata carrier
2RXReceives serial data input from communication
3TXS ends serial output to communication link
4DTR-data s et is ready to establish a communication link
5GNDGround
6DSR-data set is ready to establish a comm unication link
7RTS-indicates to data set that UART is ready to
8CTS-data set is ready to exchan ge data
Signal
MnemonicSignal Description
link
exchange data
9RI-modem has received a telephone ring ing signal
Video Connector
The video connector (J23) uses a 15-pin high de nsity D-sub connector.
Table 2-14. Video Connector Pin Assignments (J23)
Pin
NumberSignal MnemonicSignal Descrip tion
1REDRed signal
2GREENGreen signal
3BLUEBlue signal
2-22Computer Group Liter ature Center Web Site
Video Connector
Table 2-14. Video Connector Pin Assignments (J23)
Pin
NumberSignal MnemonicSignal Description
4NCNot connected
5DACVSSVideo return
6DACVSSVideo return
7DACVSSVideo return
8DACVSSVideo return
9NCNot connected
10DACVSSVideo return
11NCNot connected
12DDCDATDisplay data channel data signal for
DDC2 support
13HSYNCHorizontal synchronization
14VSYNCVe rtical synchronization
15DDCCLKDisplay data channel clock signal for
DDC2 support
2
http://www.motorola.com/computer/literature2-23
3CPX8540 Carrier Card
Overview
This chapter provid es reference information for the CPX8540 carrier card.
The CPV8540 is a 64-bit, 6U, single-width ( 4HP) CompactPCI® card tha t
provides front access to PMC modules with both front and rear I/O
connectivity. Rear I/O co nne ct ions via J3 and J5 allow its use in both
standard CompactPCI backpl anes a nd CompactPCI backplanes with the
H.110 CT bus. The corr ect jum per settings and pin-out information is
provided for each connect or on the carrie r card.
This chapter does not include the system controller/host modules. For
information about the system controller/host, refer to Chapter 2, CPU
Modules.
CPX8540 Carrier Card
3
The CPX8540 carrier card provides connectivity to a wide variety of
video, ATM, analog, serial, and many other funct ions. The board suppor ts
one double-width or two single- width PMC mezzanine modules.
Once connected, the PMC modules are accessed via front panel
connections of the carrie r card. In addition, I/O lines are brought out to the
carrier card’s rear 2mm pin and socket connectors, allowing rear panel
connections in systems such as the CPX8216T chassis.
Key features of the CPX8540 are:
❏Supports standard (IEEEP1386.1) PMC mezzanine modules
❏Holds one double-width or two single-width modules
❏All PMC I/O brought out to the front panel and to rear connectors
❏Single CompactPCI loa d via DEC 21154 bridge
❏Supports 5.0 or 3.3 Volt PMC modules
❏Supports Plug and Pla y
3-1
CPX8540 Carrier Car d
The CPX8540 reports itself to the system as a bridge c hip with the PMC
functions behind it.
The following two figures provide ove rvi ews of the card.
3
J5
PMC2
J3
PMC1
J2
Bridge
J1
Figure 3-1. PMC Modules to CPX8540 Carrier Card
3-2Computer Group Literature Center Web Site
CPX8540 Carrier Card
3
J21
J23
J11
J13
J22
J24
J12
J14
Single Width
PMC Module
Figure 3-2. Installing a PMC Module
http://www.motorola.com/computer/literature3-3
CPX8540 Carrier Car d
Connector Pinouts
The tables in this sectio n provide the connector pinout information f or the
6PMC1IO40PMC1IO39PMC1IO38PMC1IO37PMC1IO366
5PMC1IO45PMC1IO44PMC1IO43PMC1IO42PMC1IO415
4PMC1IO50PMC1IO49PMC1IO48 PMC1IO47PMC1IO464
3PMC1IO55PMC1IO54PMC1IO53PMC1IO52PMC1IO513
2PMC1IO60PMC1IO59PMC1IO58PMC1IO57 PMC1IO562
1V(I/O)PMC1IO64PMC1IO63PMC1IO62PMC1IO611
NOTE: PMC1IO* signal s are those connected to the lower PMC slot, or slot 1.
This chapter provides reference information for the PMC module
supported in the CPX8216 system.
SCSI-2 Controller PMC
The SCSI-2 controller provide s fast and wide, single-ended, SCSI-2
(Small Computer System Interface-2) high throughput connectivity for
host carrier boards equipped with PMC (PCI Mezzanine Card)
connections.
The PMC adapter is a plug-and-play device with systems that are
compliant with the PCI Local Bus Specification (revision 2.0).
This controller has the following capabilities:
4PMC Modules
4
❏Single-wide PMC module
❏32-bit wide PCI bus support
❏128Kb onboard flas h memory
❏20 Mbps Fast and W ide SCSI-2
❏Single-ended SCSI-2 interfaces
❏Front and rear User I/ O
❏68-pin front panel connector
❏64-pin JN4/P N4 rear connector
❏+3.3V and +5V signaling
❏Compliance to PCI local bus specification (Revision 2.0)
4-1
PMC Modules
The following figure shows the PMC150 component layout a nd front
panel.
PN4
PN2
4
PN1
U5
U31
JP40
U1
U13U14U15
S1
4118 0702
4-2Computer Group Literature Center Web Site
Switch Settings
Use this table as a guideline for configuring the 6-position dip switch on
your PMC.
SwitchOn FunctionOff FunctionDefault
1Use INTANo Use INTAOn
2Use INTBNo Use INTBOff
3Use INTCNo Use INTCOff
4Use INTDNo Use INTDOff
5TERM EnableTERM DisableOn
6Little EndianBig EndianOn
Configure the Big/Litt le endian mode to your ap propriate appli cation for pr oper
software operation.
Make sure only one INTx line switch is in the ON position.
Enable TERM ENAB is On only if this SCSI controlle r is physically at the end
of the SCSI bus. If the SCSI controller is in a ny other pos ition on the bus, TERM
ENAB must be in the OFF mode.
Switch Settings
Table 4-1. PMC Switch Settings
4
T erminators - The SCSI bus (cable) must be properly term inated at each
end of the bus. The first and last device on the bus should be the only
devices that are set to termina te the bus.
T erminator Power - The SCSI terminators requir e adequate voltage to
properly te rminate t he SCSI bus. All SCSI host a dapter s o n the bus should
be set to supply terminator power; and where possible, be located at the
end of the bus and serve as bus terminators. The terminator resistors must
be present on the first and last devi ce on the bus only.
For further informa tion on this PMC, vis it the T e chnobox, Inc . we b site at
http://www.technobox.com.
http://www.motorola.com/computer/literature4-3
PMC Modules
Connector Pin Assignments
The table below provides the connector pin assignments for the SCSI
connector on the PMC adapter. The connector uses a 68-pin Euro-style
SCSI cable, either shielded for external or interna l cabinet applications or
non-shielded for interna l cabinet applications only. For rear I/O, a 64-pin
4
conductor cable is used. The pin assignmen ts are also provided in the
following table.
The CPX750HATM transition module provides the interface between the
standard Paralle l Port, EIDE port, floppy port, keyboar d/mouse port, Seria l
Port connector s, and the CPX750HA CompactP CI Single Board Computer
module.
5-1
Transition/Bridge Modules
The CPX750HATM transition module includes:
❏Industry-sta ndard connectors for these inte rfa ces:
–Two asynchronous RJ-45 serial ports (DTE)
–Two asynchronous/synchronous HD-26 serial ports, label ed
Serial 3 and Serial 4 on t he face plate, whic h can be configured
for EIA-232-D, EIA-530, V.35, or X.21 interfaces (DCE or
DTE) through the installation of Motorola ’s Serial Interface
5
❏Two 60-pin Serial Interface Module (SIM) connectors for
❏One 40-pin header for EIDE port
❏One 34-pin header for floppy por t
❏Two 64-pin headers for PMCIO (1 gr ound pi n provided wi th ea ch
Modules (SIMs)
–One parallel port (IEEE Standard 1284-I compliant)
–One combination keyboard/mouse port
configuring the asynchronous/synchronous serial port s
PMCIO signal)
Figure 5-1 on page 5-3 shows the CPX750HATM transition module
component layout and the front panel. See Co nnectors on page 5-4 for a
list of the front panel por t connectors.
Serial Ports 3 and 4 Defaul t Configuratio n
The CPX750HATM serial ports 3 and 4 are factory configured as follows:
❏Serial Port 3: DTE (with SIMM 01-W3877B01A insta lled)
❏Serial Port 4: DCE (with SIMM 01-W3876B01A installed)
5-2Computer Group Literature Center Web Site
Serial Ports 3 and 4 Default Configuration
2214 98 04
34
33
40
39
41
J19
USB 0
J17
J15
2
1
2
J4
J8
J9J13
J3J5
64
J21
2
1
2
1
3
1
3
1
63
64
1
2
J14
63
J2
1
41
J18
J16
82
71
J11
82
71
J10
J7
59
60
J23
1
2
60
59
J1
1
2
171
3418
J6
131
2614
J24
131
2614
USB 1
KB/MS
COM 1
COM 2
SERIAL 3PARALLEL
SERIAL 4
5
Figure 5-1. CPX750HATM Transition Module
http://www.motorola.com/computer/literature5-3
Transition/Bridge Modules
Serial Port Interface Jumper (J8 and J9)
J8 (for serial port 3) and J9 (for serial port 4) set the serial ports to either
DTE or DCE communication. For more inf ormation a bout configurin g the
serial port, se e Installing the Serial Interface Modules on page 5-16.
5
123123
DTE
DCE
11650 9610
Figure 5-2. Serial Port Interface Jum per (J9) Settin gs
Connect ors
Refer to Figure 5-1 on page 5-3 for the location of the following conne ctors
Backplane Connectors (J3/J4/J5)
I/O signals and power are provided to the CPX750HATM from the
CPX750 through CompactPCI connectors J3 and J5. The J4 connect or is
for physical alignment purposes only and has no functional pin
connections or assignments.
Connector J3 is a 95- pin AMP Z-pac k 2mm har d metric typ e B conne ctor.
This connector route s the I/O signa ls for t he PMC I/O a nd ser ial cha nnels.
The pin assignments for J3 are as follows (outer row F is assigned and used
as ground pins but is not shown in the table):
Connector J4 is a 110-p in 2mm hard metri c type A connect or. This
connector is pl aced on the board for alignment purposes only . The keying
tabs on the type A connect or assist with al ignment of pins in t he backplane
connector during insertion of the boards. No signals are connected to J4
except the row F ground pins.
Connector J5 is a 110 -pin AMP Z-pack 2mm hard metric type B connector .
This connector routes the I/O signals for the IDE (secondary port), the
keyboard, the mouse, the two USB ports, and the printer ports. The pin
5-4Computer Group Literature Center Web Site
Connectors
assignments for J5 are as follows ( the outer row F is assigned and used as
ground pins but is not shown in the table):
T able 5-2 and T abl e 5-3 provide the pin assi gnments and signal mnemonic s
Row F is assigned and us ed as ground pins but is not shown in the table
Asynchronous Serial Port Connectors (J10 and J11)
The interface for the asynchronous serial ports, COM1 and COM2, is
provided with two RJ-45 connectors, J11 and J10. The connector shields
5-6Computer Group Literature Center Web Site
for these ports are tied to chassis ground. The pin assignments and signal
mnemonics for these connector s are listed in the next table.
Table 5-4. COM1 (J11) and COM2 (J10)
PinSignal
1DCD
2RTS
3GND
4TXD
5RXD
6GND
7CTS
8DTR
Asynchronous/Synchronous Serial Port Connectors (J6 and J24)
Connectors
5
The interface for the asynchronous/synchronous serial ports 3 and 4 is
provided by two HD-26 connec tors, J6 and J24. The connector shi elds for
these ports a re tied to chassis ground.
The pin assignments and signal mnemonics for Serial Port 3 are listed in
Table 5-5, and the pin assignm ents and si gna l mnemonics f or S erial Port 4
The interface for the parallel port is a standard IEEE P1284-C, 36-pin
connector, J7. The functionality of each signal depends on the mode of
operation of this bidire ctional Parallel Peripheral Interface. Refer to the
IEEE P1284 D2.00 Standard for a complete description of each signal
function. The connector shield is tied to chassis ground.
The pin assignment s and sign al mnemoni cs for t his connec tor are liste d in
the next table.
The Keyboard/Mouse interface is prov ide d by a 6-pin circular DIN
connector. To use the keyboard function only, a keyboard may be
connected directly to this connector. To use both the keyboard and the
mouse functions, use the Y-adapter cable provided with the
CPX750HATM. Refer to the following table for pin assignments.
Table 5-8. Keyboard/Mouse Connector (J16)
5
PinSignal
1KBD DAT
2MSDAT
3GND
4+5Vdc Fused
5KBDCLK
6MSCLK
USB Connectors (J19 and J18)
The standard version of the CPX750 routes the USB port signals only to
the CPX750 front panel US B connectors J18 and J17. Therefore the USB
port connectors (J19 and J18) on the CPX750HATM are not active. The
USB ports can be routed to the CPX750HATM using an alternate build
option of the CPX750. C ontact your lo cal Motorola S ales offic e for det ails.
5-10Computer Group Liter ature Center Web Site
EIDE Connector (J15)
The CPX750HATM provides a 40-pin header (J15) to interface to the
CPX750 secondary E IDE port. The pin ass ignments and signal mnemonics
for this connector are listed in the next table.
The CPX750HATM provides a 34-pin header ( J17) to interface to a floppy
disk drive. The pin assignments and signal mnemonics for this connector
are listed in the next table.
The CPX750HATM has a 4-pin header that can be used to pr ovide +5Vdc
power to offboard devices. This power is derived from the fused +5Vdc
power on the CPX750. Any external device powered from this connector
5-12Computer Group Liter ature Center Web Site
must not draw more than 200mA. The pin assignments are list ed in the
following table.
Table 5-11. +5Vdc Power Connector (J14)
PinSignal
1+5Vdc
2GND
3GND
4No Connect
Speaker Output Connector (J13)
The 2-pin header (J13) provides connection to an external speaker fr om the
CPX750 PCB Counter 2 output. The speaker driver, located on the
CPX750 PCB, consists of a 500 m A (max) curr ent si nk tra nsistor in ser ies
with a 33 ohm resistor. The pin assignments are listed in the following
table.
Connectors
5
Table 5-12. Speaker Output Connector (J13)
PinSignal
1GND
2SPKROC_L
http://www.motorola.com/computer/literature5-13
Transition/Bridge Modules
PMC I/O Connectors
The PMC I/O connectors consist of two 64-pin header connectors J2 and
J21. The pin assignments and signal mnemonics for the se connectors are
listed below.
Configure the serial ports 3 and 4 for the required interface by installing
the appropriate SIM.
5-16Computer Group Liter ature Center Web Site
Installing the Serial Interface Modules
Prior to installing the SIMs, set the jumpers on header J8 (for Serial Port
3) and header J9 (fo r Serial Por t 4) for eith er DCE or DTE. Set the jum per
to position 1-2 if the SIM is for a DTE interface. Set the jumper to position
2-3 if the SIM is for a DCE interface.
123123
DTE
DCE
You must set the jumpers and install the SIMs prior to installing the
CPX750HATM transition module in the system chassis.
The SIMs plug int o connector J23 (for Serial Port 3) or J1 ( for Serial Port
4) on the CPX750HATM transition module.
Install the SIMs on the CPX750HA TM transit ion module per the foll owing
procedure:
1.Align the SIM so that P1 on the SIM lin es up with the ap propriate SIM
connector (J23 for Seria l Port 3 or J1 for Serial P ort 4) o n the trans ition
module. Note the position of the alignment key on P1. See the next
figure.
5
2.Place the SIM onto the transition module SIM connector , making sure
that the mounting holes a lso li ne up with the standof fs on th e transitio n
module.
Mounting Hole
P1
Alignment
Key
Mounting Hole
http://www.motorola.com/computer/literature5-17
11637 961 0
Transition/Bridge Modules
3.Gently press the top of the SIM to seat it on the transition module SIM
connector. If the SIM does not seat with gentle pressure, re-check the
alignment of the connectors.
NoteDo not force the SIM onto the transition module.
4.Secure the SIM to the transition module standoffs with the two
Phillips-head screws pr ovided. Do not over tighten the screws.
5
Port Configuration Diagrams
The following sec tions describe the configuration s for COM1 and COM2
asynchronous serial ports.
COM1 and COM2 Asynchronous Serial Ports
The asynchronous s erial port (COM1 and C OM2) c onfiguration is shown
in Figure 5-3 on page 5-19.
5-18Computer Group Liter ature Center Web Site
COM1
(Front
Panel)
J15
9
1
6
8
2
4
7
3
5
SOUT1
RTS1#
DTR1#
SIN1
CTS1#
DSR1#
DCD1#
RI1#
PC87307
Port Configuration Diagrams
5
TXD
4
RTS
2
DTR
8
RXD
5
CTS
7
COM1
(J11)
DCD
1
3
GND
J5
6
TXD
RTS
DTR
RXD
CTS
DCD
GND
4
2
8
5
7
1
3
6
2105 9710
COM2
(J10)
SOUT2
RTS2#
DTR2#
SIN2
CTS2#
DSR2#
DCD2
RI2#
CPX750
CPX750HATM
Transition Module
Figure 5-3. DTE Port Configuration (COM1 and COM2)
http://www.motorola.com/computer/literature5-19
Transition/Bridge Modules
Asynchronous/Synchronous Serial Ports
The asynchronous/synchr onous serial port (Port 3 and Port 4) interface
configuration diagr ams are on the fol lowing pages.
5
5-20Computer Group Liter ature Center Web Site
Port Configuration Diagrams
Z85230 SCC
TXD
RTS#
RXD
CTS#
DCD#
TRXC
RTXC
Z8536 CIO
DTR#
LLB#
RLB#
J3/MX
3
2
1
J8, J9
RXD
CTS#
TXD
RTS#
DTR#
TXC
RXC#
ETXC
DCD#
TM#
RI#
DB25
3
5
2
4
20
15
17
24
8
25
22
5
DSR#
RI#
TM#
CPX750
CPX750HATM
Tran sition Module
DSR#
RL
LL
GND
EIA-232-D DCE SIM
6
21
18
7
2106 971
Figure 5-4. EIA-232-D DCE Port Configuration (Ports 3 and 4)
http://www.motorola.com/computer/literature5-21
Transition/Bridge Modules
Z85230 SCC
TXD
RTS#
RXD
CTS#
5
DCD#
3
TRXC
RTXC
Z8536 CIO
DTR#
LLB#
RLB#
J3/MX
2
1
J8, J9
TXD
RTS#
RXD
CTS#
DCD#
ETXC
TXC#
RXC
DTR
LL
RL
DB25
2
4
3
5
8
24
15
17
20
18
21
DSR#
RI#
TM#
GND#
2107 971
6
22
25
7
DSR#
RI#
TM#
CPX750
CPX750HATM
Transition Module
EIA-232-D DTE SIM
Figure 5-5. EIA-232-D DTE Port Configuration (Ports 3 and 4)
5-22Computer Group Liter ature Center Web Site
Port Configuration Diagrams
0
Z85230 SCC
TXD
RTS_
RXD
CTS_
DCD_
TRXC
RTXC
Z8536 CIO
DTR_
LL_
RL_
DSR_
RI_
TM_
J3/MX
3
2
1
J8, J9
DB25
RXDB
RXDA
CTSB
CTSA
+
+
+
-
+
-
+
-
+
-
-V
-V
TXDB
TXDA
RTSB
RTSA
DTRB
DTRA
TXCB
TXCA
RXCB
RXCA
ETXCB
ETXCA
DCDB
DCDA
TM
RI
DSRB
DSRA
RL
LL
GND
16
3
13
5
14
2
19
4
23
20
20
12
15
15
9
17
17
11
24
10
8
25
26
22
6
21
18
7
5
CPX750
CPX750HATM
Transition Module
EIA-530-D DCE SIM
2108 971
Figure 5-6. EIA-530 DCE Port Configuration (Ports 3 and 4)
http://www.motorola.com/computer/literature5-23
Transition/Bridge Modules
Z85230 SCC
TXD
RTS_
RXD
5
CTS_
DCD_
+
+
+
-
3
TRXC
2
1
+
-
J8, J9
RTXC
J3/MX
+
-
Z8536 CIO
DTR_
LL_
RL_
DSR_
RI_
TM_
+
-
+
-
-V
-V
TXDB
TXDA
RTSB
RTSA
RXDB
RXDA
CTSB
CTSA
DTRB
DTRA
ETXCB
ETXCA
TXCB
TXCA
RXCB
RTXCA
DTRB
DTRA
LL
RL
DSRB
DSRA
(R)
TM
GND
DB25
14
2
19
4
16
3
13
5
10
20
8
11
15
24
12
17
15
9
17
23
20
18
21
22
6
26
25
7
CPX750
CPX750HATM
Transition Module
EIA-530-D DTE SIM
2109 9710
Figure 5-7. EIA-530 DTE Port Configuration (Ports 3 and 4)
5-24Computer Group Liter ature Center Web Site
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