Motorola HC12, CPU12 Refrence Manual

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Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intendedforsurgicalimplant intothe body,or otherapplications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.

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Paragraph Page

SECTION 1

INTRODUCTION

1.1 CPU12 Features ..............................................................................................1-1

1.2 Readership.......................................................................................................1-1

1.3 Symbols and Notation......................................................................................1-2

SECTION 2

OVERVIEW

2.1 Programming Model.........................................................................................2-1

2.2 Data Types.......................................................................................................2-5

2.3 Memory Organization.......................................................................................2-5

2.4 Instruction Queue.............................................................................................2-5

SECTION 3

ADDRESSING MODES

3.1 Mode Summary................................................................................................3-1

3.2 Effective Address.............................................................................................3-2

3.3 Inherent Addressing Mode...............................................................................3-2

3.4 Immediate Addressing Mode ...........................................................................3-2

3.5 Direct Addressing Mode...................................................................................3-3

3.6 Extended Addressing Mode.............................................................................3-3

3.7 Relative Addressing Mode...............................................................................3-4

3.8 Indexed Addressing Modes..............................................................................3-5

3.9 Instructions Using Multiple Modes .................................................................3-10

3.10 Addressing More than 64 Kbytes...................................................................3-12

SECTION 4

INSTRUCTION QUEUE

4.1 Queue Description ...........................................................................................4-1

4.2 Data Movement in the Queue..........................................................................4-2

4.3 Changes in Execution Flow..............................................................................4-2

SECTION 5

INSTRUCTION SET OVERVIEW

5.1 Instruction Set Description...............................................................................5-1

5.2 Load and Store Instructions.............................................................................5-1

5.3 Transfer and Exchange Instructions ................................................................5-2

5.4 Move Instructions.............................................................................................5-3

5.5 Addition and Subtraction Instructions...............................................................5-3

5.6 Binary Coded Decimal Instructions..................................................................5-4

5.7 Decrement and Increment Instructions............................................................5-4

5.8 Compare and Test Instructions........................................................................5-5

5.9 Boolean Logic Instructions...............................................................................5-6

5.10 Clear, Complement, and Negate Instructions..................................................5-6

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TABLE OF CONTENTS

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5.11 Multiplication and Division Instructions ............................................................5-7

5.12 Bit Test and Manipulation Instructions.............................................................5-7

5.13 Shift and Rotate Instructions............................................................................5-8

5.14 Fuzzy Logic Instructions...................................................................................5-9

5.15 Maximum and Minimum Instructions..............................................................5-11

5.16 Multiply and Accumulate Instruction...............................................................5-11

5.17 Table Interpolation Instructions......................................................................5-12

5.18 Branch Instructions ........................................................................................5-13

5.19 Loop Primitive Instructions.............................................................................5-16

5.20 Jump and Subroutine Instructions..................................................................5-17

5.21 Interrupt Instructions ......................................................................................5-18

5.22 Index Manipulation Instructions......................................................................5-19

5.23 Stacking Instructions......................................................................................5-20

5.24 Pointer and Index Calculation Instructions.....................................................5-20

5.25 Condition Code Instructions...........................................................................5-21

5.26 STOP and WAIT Instructions.........................................................................5-21

5.27 Background Mode and Null Operations.........................................................5-22

SECTION 6

INSTRUCTION GLOSSARY

6.1 Glossary Information........................................................................................6-1

6.2 Condition Code Changes.................................................................................6-2

6.3 Object Code Notation.......................................................................................6-2

6.4 Source Forms...................................................................................................6-3

6.5 Cycle-by-Cycle Execution................................................................................6-5

6.6 Glossary...........................................................................................................6-8

SECTION 7

EXCEPTION PROCESSING

7.1 Types of Exceptions.........................................................................................7-1

7.2 Exception Priority.............................................................................................7-2

7.3 Resets..............................................................................................................7-2

7.4 Interrupts..........................................................................................................7-3

7.5 Unimplemented Opcode Trap..........................................................................7-5

7.6 Software Interrupt Instruction...........................................................................7-6

7.7 Exception Processing Flow..............................................................................7-6

SECTION 8

DEVELOPMENT AND DEBUG SUPPORT

8.1 External Reconstruction of the Queue.............................................................8-1

8.2 Instruction Queue Status Signals.....................................................................8-1

8.3 Implementing Queue Reconstruction...............................................................8-3

8.4 Background Debug Mode ................................................................................8-6

8.5 Instruction Tagging.........................................................................................8-13

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TABLE OF CONTENTS

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8.6 Breakpoints....................................................................................................8-14

SECTION 9

FUZZY LOGIC SUPPORT

9.1 Introduction ......................................................................................................9-1

9.2 Fuzzy Logic Basics ..........................................................................................9-1

9.3 Example Inference Kernel................................................................................9-7

9.4 MEM Instruction Details...................................................................................9-9

9.5 REV, REVW Instruction Details .....................................................................9-13

9.6 WAV Instruction Details .................................................................................9-22

9.7 Custom Fuzzy Logic Programming................................................................9-26

SECTION 10

MEMORY EXPANSION

10.1 Expansion System Description ......................................................................10-1

10.2 CALL and Return from Call Instructions.........................................................10-3

10.3 Address Lines for Expansion Memory ...........................................................10-4

10.4 Overlay Window Controls...............................................................................10-4

10.5 Using Chip-Select Circuits .............................................................................10-5

10.6 System Notes.................................................................................................10-7

APPENDIX A

INSTRUCTION REFERENCE

A.1 Instruction Set Summary..................................................................................A-1

A.2 Opcode Map.....................................................................................................A-1

A.3 Indexed Addressing Postbyte Encoding ..........................................................A-1

A.4 Transfer and Exchange Postbyte Encoding.....................................................A-1

A.5 Loop Primitive Postbyte Encoding ...................................................................A-1

APPENDIX B

M68HC11 TO M68HC12 UPGRADE PATH

B.1 CPU12 Design Goals.......................................................................................B-1

B.2 Source Code Compatibility...............................................................................B-1

B.3 Programmer’s Model and Stacking..................................................................B-3

B.4 True 16-Bit Architecture...................................................................................B-3

B.5 Improved Indexing............................................................................................B-6

B.6 Improved Performance.....................................................................................B-9

B.7 Additional Functions.......................................................................................B-11

APPENDIX C

HIGH-LEVEL LANGUAGE SUPPORT

C.1 Data Types...................................................................................................... C-1

C.2 Parameters and Variables...............................................................................C-1

C.3 Increment and Decrement Operators.............................................................. C-3

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C.4 Higher Math Functions.................................................................................... C-3

C.5 Conditional If Constructs................................................................................. C-4

C.6 Case and Switch Statements.......................................................................... C-4

C.7 Pointers........................................................................................................... C-4

C.8 Function Calls................................................................................................. C-4

C.9 Instruction Set Orthogonality........................................................................... C-5

APPENDIX D

ASSEMBLY LISTING

INDEX

SUMMARY OF CHANGES

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LIST OF ILLUSTRATIONS

Figure Page

2-1 Programming Model.........................................................................................2-1

6-1 Example Glossary Page...................................................................................6-1

7-2 Exception Processing Flow Diagram...............................................................7-7

8-1 Queue Status Signal Timing............................................................................8-2

8-2 BDM Host to Target Serial Bit Timing..............................................................8-8

8-3 BDM Target to Host Serial Bit Timing (Logic 1)...............................................8-8

8-4 BDM Target to Host Serial Bit Timing (Logic 0)...............................................8-9

8-5 Tag Input Timing............................................................................................8-13

9-1 Block Diagram of a Fuzzy Logic System..........................................................9-3

9-2 Fuzzification Using Membership Functions......................................................9-4

9-3 Fuzzy Inference Engine...................................................................................9-8

9-4 Defining a Normal Membership Function.......................................................9-10

9-5 MEM Instruction Flow Diagram......................................................................9-11

9-6 Abnormal Membership Function Case 1........................................................9-12

9-7 Abnormal Membership Function Case 2........................................................9-13

9-8 Abnormal Membership Function Case 3........................................................9-13

9-9 REV Instruction Flow Diagram.......................................................................9-16

9-10 REVW Instruction Flow Diagram....................................................................9-21

9-11 WAV and wavr Instruction Flow Diagram.......................................................9-25

9-12 Endpoint Table Handling................................................................................9-28

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LIST OF TABLES

Table Page

3-1 M68HC12 Addressing Mode Summary............................................................3-1

3-2 Summary of Indexed Operations.....................................................................3-6

3-3 PC Offsets for Move Instructions...................................................................3-11

5-1 Load and Store Instructions.............................................................................5-2

5-2 Transfer and Exchange Instructions................................................................5-3

5-3 Move Instructions.............................................................................................5-3

5-4 Addition and Subtraction Instructions...............................................................5-4

5-5 BCD Instructions..............................................................................................5-4

5-6 Decrement and Increment Instructions............................................................5-5

5-7 Compare and Test Instructions........................................................................5-5

5-8 Boolean Logic Instructions...............................................................................5-6

5-9 Clear, Complement, and Negate Instructions..................................................5-6

5-10 Multiplication and Division Instructions............................................................5-7

5-11 Bit Test and Manipulation Instructions.............................................................5-7

5-12 Shift and Rotate Instructions............................................................................5-8

5-13 Fuzzy Logic Instructions.................................................................................5-10

5-14 Minimum and Maximum Instructions..............................................................5-11

5-15 Multiply and Accumulate Instructions.............................................................5-12

5-16 Table Interpolation Instructions......................................................................5-12

5-17 Short Branch Instructions...............................................................................5-14

5-18 Long Branch Instructions...............................................................................5-15

5-19 Bit Condition Branch Instructions...................................................................5-16

5-20 Loop Primitive Instructions.............................................................................5-16

5-21 Jump and Subroutine Instructions..................................................................5-17

5-22 Interrupt Instructions......................................................................................5-18

5-23 Index Manipulation Instructions......................................................................5-19

5-24 Stacking Instructions......................................................................................5-20

5-25 Pointer and Index Calculation Instructions.....................................................5-21

5-26 Condition Codes Instructions.........................................................................5-21

5-27 STOP and WAIT Instructions.........................................................................5-22

5-28 Background Mode and Null Operation Instructions........................................5-22

7-1 CPU12 Exception Vector Map.........................................................................7-1

7-2 Stacking Order on Entry to Interrupts...............................................................7-5

8-1 IPIPE[1:0] Decoding.........................................................................................8-2

8-2 BDM Commands Implemented in Hardware..................................................8-10

8-3 BDM Firmware Commands............................................................................8-11

8-4 BDM Register Mapping..................................................................................8-11

8-5 Tag Pin Function............................................................................................8-13

10-1 Mapping Precedence.....................................................................................10-2

A-1 Instruction Set Summary..................................................................................A-2

A-2 CPU12 Opcode Map......................................................................................A-20

A-3 Indexed Addressing Mode Summary.............................................................A-22

A-4 Indexed Addressing Mode Postbyte Encoding (xb).......................................A-23

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LIST OF TABLES

A-5 Transfer and Exchange Postbyte Encoding...................................................A-24

A-6 Loop Primitive Postbyte Encoding (lb)...........................................................A-25

B-1 Translated M68HC11 Mnemonics....................................................................B-2

B-2 Instructions with Smaller Object Code.............................................................B-3

B-3 Comparison of Math Instruction Speeds........................................................B-10

B-4 New M68HC12 Instructions...........................................................................B-11

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SECTION 1

INTRODUCTION

This manual describes the features and operation of the CPU12 processing unit used in all M68HC12 microcontrollers.

1.1 CPU12 Features

The CPU12 is a high-speed, 16-bit processing unit that has a programming model identical to that of the industry standard M68HC11 CPU. The CPU12 instruction set is a proper superset of the M68HC11 instruction set, and M68HC11 source code is accepted by CPU12 assemblers with no changes.

The CPU12 has full 16-bit data paths and can perform arithmetic operations up to 20 bits wide for high-speed math execution.

Unlike many other 16-bit CPUs, the CPU12 allows instructions with odd byte counts, including many single-byte instructions. This allows much more efficient use of ROM space.

An instruction queue buffers program information so the CPU has immediate access to at least three bytes of machine code at the start of every instruction.

In addition to the addressing modes found in other Motorola MCUs, the CPU12 offers an extensive set of indexed addressing capabilities including:

• Using the stack pointer as an index register in all indexed operations

• Using the program counter as an index register in all but auto inc/dec mode

• Accumulator offsets allowed using A, B, or D accumulators

• Automatic pre- or post-increment or pre- or post-decrement (by

–8 to +8)

• 5-bit, 9-bit, or 16-bit signed constant offsets

• 16-bit offset indexed-indirect and accumulator D offset indexed-indirect addressing

1.2 Readership

This manual is written for professionals and students in electronic design and software development. The primary goal is to provide information necessary to implement control systems using M68HC12 devices. Basic knowledge of electronics, microprocessors, and assembly language programming is required to use the manual effectively. Because the CPU12 has a great deal of commonality with the M68HC11 CPU, prior knowledge of M68HC11 devices is helpful, but is not essential. The CPU12 also includes features that are new and unique. In these cases, there is supplementary material in the text to explain the new technology.

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1.3 Symbols and Notation

The following symbols and notation are used throughout the manual. More specialized usages that apply only to the instruction glossary are described at the beginning of that section.

1.3.1 Abbreviations for System Resources

A — Accumulator A B — Accumulator B D — Double accumulator D (A : B) X — Index register X

Y — Index register Y SP — Stack pointer PC — Program counter

CCR — Condition code register

S – STOP instruction control bit X– Non-maskable interrupt control bit H – Half-carry status bit I – Maskable interrupt control bit N – Negative status bit Z – Zero status bit V – Two’s complement overflow status bit C – Carry/Borrow status bit

1.3.2 Memory and Addressing

M — 8-bit memory location pointed to by the effective address of the in-

struction

M : M+1 — 16-bit memory location. Consists of the location pointed to by the

effective address concatenated with the next higher memory location. The most significant byte is at location M.

M~M+3

(Y)~M(Y+3)

— 32-bit memory location. Consists of the effective address of the

instruction concatenated with the next three higher memory locations. The most significant byte is at location M or M

— Memory locations pointed to by index register X

(X)

(Y+3)

— Memory locations pointed to by the stack pointer

(SP)

Memory locations pointed to by index register Y plus 3,

—

respectively.

PPAGE — Program overlay page (bank) number for extended memory

(>64K).

Page — Program overlay page

XH— High-order byte

— Low-order byte

( ) — Content of register or memory location

$ — Hexadecimal value

% — Binary value

(Y)

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1.3.3 Operators

–

•

⊕

⇒

⇔

—

Addition

—

Subtraction

—

Logical AND

—

Logical OR (inclusive)

—

Logical exclusive OR

—

Multiplication

—

Division

—

Negation. One’s complement (invert each bit of M)

—

Concatenate

Example:A:Bmeans: “The 16-bit value formed by concatenating 8-bit accumulator A with 8-bit accumulator B.” A is in the high order position.

—

Transfer

Example: (A) ⇒ M means: “The content of accumulator A is transferred to memory location M.”

—

Exchange

Example: D ⇔ X means: “Exchange the contents of D with those of X.”

1.3.4 Conventions

Logic level one is the voltage that corresponds to the True (1) state. Logic level zero is the voltage that corresponds to the False (0) state. Set refers specifically to establishing logic level one on a bit or bits. Cleared refers specifically to establishing logic level zero on a bit or bits. Asserted means that a signal is in active logic state. An active low signal changes

from logic level one to logic level zero when asserted, and an active high signal changes from logic level zero to logic level one.

Negated means that an asserted signal changes logic state. An active low signal changes from logic level zero to logic level one when negated, and an active high signal changes from logic level one to logic level zero.

ADDR is the mnemonic for address bus. DATA is the mnemonic for data bus. LSB means least significant bit or bits; MSB, most significant bit or bits. LSW means least significant word or words; MSW, most significant word or words. A specific mnemonic within a range is referred to by mnemonic and number. A7 is

bit 7 of accumulator A. A range of mnemonics is referred to by mnemonic and the numbers that define the range. DATA[15:8] form the high byte of the data bus.

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SECTION 2

OVERVIEW

This section describes the CPU12 programming model, register set, the data types used, and basic memory organization.

2.1 Programming Model

The CPU12 programming model, shown in Figure 2-1, is the same as that of the M68HC11 CPU. The CPU has two 8-bit general-purpose accumulators (A and B) that can be concatenated into a single 16-bit accumulator (D) for certain instructions. It also has two index registers (X and Y), a 16-bit stack pointer (SP), a 16-bit program counter (PC), and an 8-bit condition code register (CCR).

NSXHI ZVC

8-BIT ACCUMULATORS A AND B

16-BIT DOUBLE ACCUMULATOR D

INDEX REGISTER X

INDEX REGISTER Y

STACK POINTER

PROGRAM COUNTER

CONDITION CODE REGISTER

Figure 2-1 Programming Model

HC12 PROG MODEL

2.1.1 Accumulators

General-purpose 8-bit accumulators A and B are used to hold operands and results of operations. Some instructions treat the combination of these two 8-bit accumulators (A : B) as a 16-bit double accumulator (D).

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Most operations can use accumulator A or B interchangeably. However, there are a few exceptions. Add, subtract, and compare instructions involving both A and B (ABA, SBA, and CBA) only operate in one direction, so it is important to make certain the correct operand is in the correct accumulator. The decimal adjust accumulator A (DAA) instruction is used after binary-coded decimal (BCD) arithmetic operations. There is no equivalent instruction to adjust accumulator B.

2.1.2 Index Registers

16-bit index registers X and Y are used for indexed addressing. In the indexed addressing modes, the contents of an index register are added to 5-bit, 9-bit, or 16-bit constants or to the content of an accumulator to form the effective address of the instruction operand. The second index register is especially useful for moves and in cases where operands from two separate tables are used in a calculation.

2.1.3 Stack Pointer

The CPU12 supports an automatic program stack. The stack is used to save system context during subroutine calls and interrupts, and can also be used for temporary data storage. The stack can be located anywhere in the standard 64-Kbyte address space and can grow to any size up to the total amount of memory available in the system.

The stack pointer holds the 16-bit address of the last stack location used. Normally, the SP is initialized by one of the first instructions in an application program. The stack grows downward from the address pointed to by the SP. Each time a byte is pushed onto the stack, the stack pointer is automatically decremented, and each time a byte is pulled from the stack, the stack pointer is automatically incremented.

When a subroutine is called, the address of the instruction following the calling instruction is automatically calculated and pushed onto the stack. Normally, a return from subroutine (RTS) or a return from call (RTC) instruction is executed at the end of a subroutine. The return instruction loads the program counter with the previously stacked return address and execution continues at that address.

When an interrupt occurs, the current instruction finishes execution (REV, REVW, and WAV instructions can be interrupted, and resume execution once the interrupt has been serviced), the address of the next instruction is calculated and pushed onto the stack, all the CPU registers are pushed onto the stack, the program counter is loaded with the address pointed to by the interrupt vector, and execution continues at that address. The stacked registers are referred to as an interrupt stack frame. The CPU12 stack frame is the same as that of the M68HC11.

2.1.4 Program Counter

Theprogram counter (PC) is a 16-bit registerthat holds the address of the next instruction to be executed. It is automatically incremented each time an instruction is fetched.

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2.1.5 Condition Code Register

This register contains five status indicators, two interrupt masking bits, and a STOP instruction control bit. It is named for the five status indicators.

The status bits reflect the results of CPU operation as it executes instructions. The five flags are half carry (H), negative (N), zero (Z), overflow (V), and carry/borrow (C). The half-carry flag is used only for BCD arithmetic operations. The N, Z, V, and C status bits allow for branching based on the results of a previous operation.

In some architectures, only a few instructions affect condition codes, so that multiple instructions must be executed in order to load and test a variable. Since most CPU12 instructions automatically update condition codes, it is rarely necessary to execute an extra instruction for this purpose. The challenge in using the CPU12 lies in finding instructions that do not alter the condition codes. The most important of these instructions are pushes, pulls, transfers, and exchanges.

It is always a good idea to refer to an instruction set summary (see APPENDIX A IN-

STRUCTION REFERENCE) to check which condition codes are affected by a partic-

ular instruction. The following paragraphs describe normal uses of the condition codes. There are oth-

er, more specialized uses. For instance, the C status bit is used to enable weighted fuzzy logic rule evaluation. Specialized usages are described in the relevant portions of this manual and in SECTION 6 INSTRUCTION GLOSSARY.

2.1.5.1 S Control Bit

Setting the S bit disables the STOP instruction. Execution of a STOP instruction causes the on-chip oscillator to stop. This may be undesirable in some applications. If the CPU encounters a STOP instruction while the S bit is set, it is treated like a no-operation (NOP) instruction, and continues to the next instruction.

2.1.5.2 X Mask Bit

XIRQ input is an updated version of the NMI input found on earlier generations of

The MCUs. Non-maskable interrupts are typically used to deal with major system failures, such as loss of power. However, enabling non-maskable interrupts before a system is fully powered andinitialized can lead to spurious interrupts. The X bit provides a mechanism for enabling non-maskable interrupts after a system is stable.

By default, the X bit is set to one during reset. As long as the X bit remains set, interrupt service requests made via the the X bit to enable non-maskable interrupt service requests made via the

XIRQ pin are not recognized. An instruction must clear

XIRQ pin. Once the X bit has been cleared to zero, software cannot reset it to one by writing to the CCR. The X bit is not affected by maskable interrupts.

When an

XIRQ interrupt occurs after non-maskable interrupts are enabled, both the X bit and the I bit are automatically set to prevent other interrupts from being recognized during the interrupt service routine. The mask bits are set after the registers are stacked, but before the interrupt vector is fetched.

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Normally, an RTI instruction at the end of the interrupt service routine restores register values that were present before the interrupt occurred. Since the CCR is stacked before the X bit is set, the RTI normally clears the X bit, and thus re-enables nonmaskable interrupts. While it is possible to manipulate the stacked value of X so that X is set after an RTI, there is no software method to re-set X (and disable

NMI) once

X has been cleared.

2.1.5.3 H Status Bit

The H bit indicates a carry from accumulator A bit 3 during an addition operation. The DAA instruction uses the value of the H bit to adjust a result in accumulator A to correct BCD format. H is updated only by the ABA, ADD, and ADC instructions.

2.1.5.4 I Mask Bit

The I bit enables and disables maskable interrupt sources. By default, the I bit is set to one during reset. An instruction must clear the I bit to enable maskable interrupts. While the I bit is set, maskable interrupts can become pending and are remembered, but operation continues uninterrupted until the I bit is cleared.

When an interrupt occurs after interrupts are enabled, the I bit is automatically set to prevent other maskable interrupts during the interrupt service routine. The I bit is set after the registers are stacked, but before the interrupt vector is fetched.

Normally, an RTI instruction at the end of the interrupt service routine restores register values that were present before the interrupt occurred. Since the CCR is stacked before the I bit is set, the RTI normally clears the I bit, and thus re-enables interrupts. Interrupts can be re-enabled by clearing the I bit within the service routine, but implementing a nested interrupt management scheme requires great care, and seldom improves system performance.

2.1.5.5 N Status Bit

The N bit shows the state of the MSB of the result. N is most commonly used in two’s complement arithmetic, where the MSB of a negative number is one and the MSB of a positive number is zero, but it has other uses. For instance, if the MSB of a register or memory location is used as a status flag, the user can test status by loading an accumulator.

2.1.5.6 Z Status Bit

The Z bit is set when all the bits of the result are zeros. Compare instructions perform an internal implied subtraction, and the condition codes, including Z, reflect the results of that subtraction. The INX, DEX, INY, and DEY instructions affect the Z bit and no other condition flags. These operations can only determine = and ≠.

2.1.5.7 V Status Bit

The V bit is set when two’s complement overflow occurs as a result of an operation.

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2.1.5.8 C Status Bit

The C bit is set when a carry occurs during addition or a borrow occurs during subtraction. The C bit also acts as an error flag for multiply and divide operations. Shift and rotate instructions operate through the C bit to facilitate multiple-word shifts.

2.2 Data Types

The CPU12 uses the following types of data:

• Bits

• 5-bit signed integers

• 8-bit signed and unsigned integers

• 8-bit, 2-digit binary coded decimal numbers

• 9-bit signed integers

• 16-bit signed and unsigned integers

• 16-bit effective addresses

• 32-bit signed and unsigned integers

Negative integers are represented in two’s complement form. Five-bit and 9-bit signed integers are used only as offsets for indexed addressing

modes. Sixteen-bit effective addresses are formed during addressing mode computations. Thirty-two-bit integer dividends are used by extended division instructions. Extended

multiply and extended multiply-and-accumulate instructions produce 32-bit products.

2.3 Memory Organization

The standard CPU12 address space is 64 Kbytes. Some M68HC12 devices support a paged memory expansion scheme that increases the standard space by means of predefined windows in address space. The CPU12 has special instructions that support use of expanded memory. See SECTION 10 MEMORY EXPANSION for more information.

Eight-bit values can be stored at any odd or even byte address in available memory. Sixteen-bit values are stored in memory as two consecutive bytes; the high byte occupies the lowest address, but need not be aligned to an even boundary. Thirty-two-bit valuesare stored in memory asfour consecutive bytes; the high byte occupies the lowest address, but need not be aligned to an even boundary.

All I/O and all on-chip peripherals are memory-mapped. No special instruction syntax is required to access these addresses. On-chip registers and memory are typically grouped in blocks which can be relocated within the standard 64-Kbyte address space. Refer to device documentation for specific information.

2.4 Instruction Queue

The CPU12 uses an instruction queue to buffer program information. The mechanism is called a queue rather than a pipeline because a typical pipelined CPU executes more than one instruction at the same time, while the CPU12 always finishes executing an instruction before beginning to execute another. Refer to SECTION 4 IN-

STRUCTION QUEUE for more information.

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MOTOROLA OVERVIEW CPU12 2-6 REFERENCE MANUAL

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SECTION 3

ADDRESSING MODES

Addressing modes determine how the CPU accesses memory locations to be operated upon. This section discusses the various modes and how they are used.

3.1 Mode Summary

Addressing modes are an implicit part of CPU12 instructions. APPENDIX A IN-

STRUCTION REFERENCE shows the modes used by each instruction. All CPU12

addressing modes are shown in Table 3-1.

Table 3-1 M68HC12 Addressing Mode Summary

Addressing Mode Source Format Abbreviation Description

INST #

INST

INST [

INST [D,

INST

operands)

opr8i

opr16i

opr8a

opr16a

rel8

INST

rel16

oprx5,xysp

oprx3,–xys

oprx3,+xys

oprx3,xys

abd,xysp

oprx9,xysp

oprx16,xysp

xysp

INH Operands (if any) are in CPU registers

IMM

DIR EXT Operand is a 16-bit address

REL

IDX 5-bit signed constant offset from x, y, sp, or pc

IDX Auto pre-decrement x, y, or sp by 1 ~ 8

IDX Auto pre-increment x, y, or sp by 1 ~ 8

– IDX Auto post-decrement x, y, or sp by 1 ~ 8

+ IDX Auto post-increment x, y, or sp by 1 ~ 8

IDX

IDX1

IDX2

] [IDX2]

] [D,IDX]

Operand is included in instruction stream

8- or 16-bit size implied by context

Operand is the lower 8-bits of an address

in the range $0000 – $00FF

An 8-bit or 16-bit relative offset from the current

pc is supplied in the instruction

Indexed with 8-bit (A or B) or 16-bit (D)

accumulator offset from x, y, sp, or pc

9-bit signed constant offset from x, y, sp, or pc

(lower 8-bits of offset in one extension byte)

16-bit constant offset from x, y, sp, or pc

(16-bit offset in two extension bytes)

Pointer to operand is found at...

16-bit constant offset from x, y, sp, or pc

(16-bit offset in two extension bytes)

Pointer to operand is found at...

x, y, sp, or pc plus the value in D

Inherent

Immediate

Direct INST

Extended INST

Relative

Indexed

(5-bit offset)

Indexed

(pre-decrement)

Indexed

(pre-increment)

Indexed

(post-decrement)

Indexed

(post-increment)

Indexed

(accumulator offset)

Indexed

(9-bit offset)

Indexed

(16-bit offset)

Indexed-Indirect

(16-bit offset)

Indexed-Indirect

(D accumulator

offset)

(no externally supplied

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The CPU12 uses all M68HC11 modes as well as new forms of indexed addressing. Differencesbetween M68HC11 and M68HC12 indexed modes aredescribed in 3.8 In-

dexed Addressing Modes. Instructions that use more than one mode are discussed

in 3.9 Instructions Using Multiple Modes.

3.2 Effective Address

Each addressing mode except inherent mode generates a 16-bit effective address whichis used during the memory reference portion of the instruction. Effectiveaddress computations do not require extra execution cycles.

3.3 Inherent Addressing Mode

Instructions that use this addressing mode either have no operands or all operands are in internal CPU registers. In either case, the CPU does not need to access any memory locations to complete the instruction.

Examples:

NOP ;this instruction has no operands INX ;operand is a CPU register

3.4 Immediate Addressing Mode

Operands for immediate mode instructions are included in the instruction stream, and are fetched into the instruction queue one 16-bit word at a time during normal program fetch cycles. Since program data is read into the instruction queue several cycles before it is needed, when an immediate addressing mode operand is called for by an instruction, it is already present in the instruction queue.

The pound symbol (#) is used to indicate an immediate addressing mode operand. One very commonprogramming error is to accidentally omit the # symbol. This causes the assembler to misinterpret the following expression as an address rather than explicitly provided data. For example LDAA #$55 means to load the immediate value $55 into the A accumulator, while LDAA $55 means to load the value from address $0055 into the A accumulator. Without the # symbol the instruction is erroneously interpreted as a direct addressing mode instruction.

Examples:

LDAA #$55 LDX #$1234 LDY #$67

These are common examples of 8-bit and 16-bit immediate addressing mode. The size of the immediate operand is implied by the instruction context. In the third example, the instruction implies a 16-bit immediate value but only an 8-bit value is supplied. In this case the assembler will generate the 16-bit value $0067 because the CPU expects a 16-bit value in the instruction stream.

BRSET FOO,#$03,THERE

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In this example, extended addressing mode is used to access the operand FOO, immediate addressing mode is used to access the mask value $03, and relative addressing mode is used to identify the destination address of a branch in case the branch-taken conditions are met. BRSET is listed as an extended mode instruction even though immediate and relative modes are also used.

3.5 Direct Addressing Mode

This addressing mode is sometimes called zero-page addressing because it is used to access operands in the address range $0000 through $00FF. Since these addresses always begin with $00, only the eight low-order bits of the address need to be included in the instruction, which saves program space and execution time. A system canbe optimized by placing the most commonly accessed data in this area of memory. The eight low-order bits of the operand address are supplied with the instruction and the eight high-order bits of the address are assumed to be zero.

Examples:

LDAA $55

This is a very basic example of direct addressing. The value $55 is taken to be the low-order half of an address in the range $0000 through $00FF. The high order half of the address is assumed to be zero. During execution of this instruction, the CPU combines the value $55 from the instruction with the assumed value of $00 to form the address $0055, which is then used to access the data to be loaded into accumulator A.

LDX $20

In this example, the value $20 is combined with the assumed value of $00 to form the address $0020. Since the LDX instruction requires a 16-bit value, a 16-bit word of data is read from addresses $0020 and $0021. After execution of this instruction, the X index register will have the value from address $0020 in its high-order half and the value from address $0021 in its low-order half.

3.6 Extended Addressing Mode

In this addressing mode, the full 16-bit address of the memory location to be operated on is provided in the instruction. This addressing mode can be used to access any location in the 64-Kbyte memory map.

Example:

LDAA $F03B

This is a very basic example of extended addressing. The value from address $F03B is loaded into the A accumulator.

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3.7 Relative Addressing Mode

The relative addressing mode is used only by branch instructions. Short and long conditional branch instructions use relative addressing mode exclusively, but branching versions of bit manipulation instructions (BRSET and BRCLR) use multiple addressing modes, including relative mode. Refer to 3.9 Instructions Using Multiple Modes for more information.

Short branch instructions consist of an 8-bit opcode and a signed 8-bit offset contained in the byte that follows the opcode. Long branch instructions consist of an 8-bit prebyte, an 8-bit opcode and a signed 16-bit offset contained in the two bytes that follow the opcode.

Each conditional branch instruction tests certain status bits in the condition code register. If the bits are in a specified state, the offset is added to the address of the next memory location after the offset to form an effective address, and execution continues at that address; if the bits are not in the specified state, execution continues with the instruction immediately following the branch instruction.

Bit-condition branches test whether bits in a memory byte are in a specific state. Various addressing modes can be used to access the memory location. An 8-bit mask operand is used to test the bits. If each bit in memory that corresponds to a one in the mask is either set (BRSET) or clear (BRCLR), an 8-bit offset is added to the address of the next memory location after the offset to form an effective address, and execution continues at that address; if all the bits in memory that correspond to a one in the mask are not in the specified state, execution continues with the instruction immediately following the branch instruction.

Both 8-bit and 16-bit offsets are signed two’s complement numbers to support branching upward and downward in memory. The numeric range of short branch offset values is $80 (–128) to $7F (127). The numeric range of long branch offset values is $8000 (–32768) to $7FFF (32767). If the offset is zero, the CPU executes the instruction immediately following the branch instruction, regardless of the test involved.

Since the offset is at the end of a branch instruction, using a negative offset value can cause the PC to point to the opcode and initiate a loop. For instance, a branch always (BRA) instruction consists of two bytes, so using an offset of $FE sets up an infinite loop; the same is true of a long branch always (LBRA) instruction with an offset of $FFFC.

An offset that points to the opcode can cause a bit-condition branch to repeat execution until the specified bit condition is satisfied. Since bit condition branches can consist of four, five, or six bytes depending on the addressing mode used to access the byte in memory, the offset value that sets up a loop can vary. For instance, using an offset of $FC with a BRCLR that accesses memory using an 8-bit indexed postbyte sets up a loop that executes until all the bits in the specified memory byte that correspond to ones in the mask byte are cleared.

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3.8 Indexed Addressing Modes

The CPU12 uses redefined versions of M68HC11 indexed modes that reduce execution time and eliminate code size penalties for using the Y index register. In most cases, CPU12 code size for indexed operations is the same or is smaller than that for the M68HC11. Execution time is shorter in all cases. Execution time improvementsare due to both a reduced number of cycles for all indexed instructions and to faster system clock speed.

The indexed addressing scheme uses a postbyte plus 0, 1, or 2 extension bytes after the instruction opcode. The postbyte and extensions do the following tasks:

1. Specify which index register is used.

2. Determine whether a value in an accumulator is used as an offset.

3. Enable automatic pre or post increment or decrement.

4. Specify size of increment or decrement.

5. Specify use of 5-, 9-, or 16-bit signed offsets.

This approach eliminates the differences between X and Y register use while dramatically enhancing the indexed addressing capabilities.

Major advantages of the CPU12 indexed addressing scheme are:

• The stack pointer can be used as an index register in all indexed operations.

• The program counter can be used as an index register in all but autoincrement and autodecrement modes.

• A, B, or D accumulators can be used for accumulator offsets.

• Automatic pre- or post-increment or pre- or post-decrement by –8 to +8

• A choice of 5-, 9-, or 16-bit signed constant offsets.

• Use of two new indexed-indirect modes. — Indexed-indirect mode with 16-bit offset — Indexed-indirect mode with accumulator D offset

Table 3-2 is a summary of indexed addressing mode capabilities and a description of

postbyte encoding. The postbyte is noted as xb in instruction descriptions. Detailed descriptions of the indexed addressing mode variations follow the table.

All indexed addressing modes use a 16-bit CPU register and additional information to create an effective address. In most cases the effective address specifies the memory location affected by the operation. In some variations of indexed addressing, the effective address specifies the location of a value that points to the memory location affected by the operation.

Indexed addressing mode instructions use a postbyte to specify X, Y, SP, or PC as the base index register and to further classify the way the effective address is formed. A special group of instructions (LEAS, LEAX, and LEAY) cause this calculated effective address to be loaded into an index register for further calculations.

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Table 3-2 Summary of Indexed Operations

Postbyte

Code (xb)

rr0nnnnn,rn,r

111rr0zs

111rr011 [n,r]

rr1pnnnn

111rr1aa

111rr111 [D,r]

Source Code

Syntax

-n,r

n,r

-n,r

n,-r n,+r n,rn,r+

A,r B,r D,r

Comments

rr; 00 = X, 01 = Y, 10 = SP, 11 = PC

5-bit constant offset n = –16 to +15 r can specify X, Y, SP, or PC

Constant offset (9- or 16-bit signed) z- 0 = 9-bit with sign in LSB of postbyte(s) -256 < n < 255

1 = 16-bit 0 < n < 65,535 if z = s = 1, 16-bit offset indexed-indirect (see below) r can specify X, Y, SP, or PC

16-bit offset indexed-indirect

rr can specify X, Y, SP, or PC 0 < n < 65,535 Auto pre-decrement/increment or Auto post-decrement/increment;

p = pre-(0) or post-(1), n = –8 to –1, +1 to +8 r can specify X, Y, or SP (PC not a valid choice)

+8 = 0111

…

+1 = 0000

-1 = 1111

…

-8 = 1000

Accumulator offset (unsigned 8-bit or 16-bit) aa- 00 = A

01 = B

10 = D (16-bit)

11 = see accumulator D offset indexed-indirect r can specify X, Y, SP, or PC

Accumulator D offset indexed-indirect

r can specify X, Y, SP, or PC

3.8.1 5-Bit Constant Offset Indexed Addressing

This indexed addressing mode uses a 5-bit signed offset which is included in the instruction postbyte. This short offset is added to the base index register (X, Y, SP, or PC) to form the effective address of the memory location that will be affected by the instruction. This gives a range of

–16 through +15 from the value in the base index reg-

ister. Although other indexed addressing modes allow 9- or 16-bit offsets, those modes also require additional extension bytes in the instruction for this extra information. The majority of indexed instructions in real programs use offsets that fit in the shortest 5-bit form of indexed addressing.

Examples:

LDAA 0,X STAB –8,Y

For these examples, assume X has a value of $1000 and Y has a value of $2000 before execution. The 5-bit constant offset mode does not change the value in the index register, so X will still be $1000 and Y will still be $2000 after execution of these instructions. In the first example, A will be loaded with the value from address $1000. In the second example,the value from the B accumulator will be stored at address $1FF8 ($2000 – $8).

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3.8.2 9-Bit Constant Offset Indexed Addressing

This indexed addressing mode uses a 9-bit signed offset which is added to the base index register (X, Y, SP, or PC) to form the effective address of the memory location affected by the instruction. This gives a range of

–256 through +255 from the value in

the base index register. The most significant bit (sign bit) of the offset is included in the instruction postbyte and the remaining eight bits are provided as an extension byte after the instruction postbyte in the instruction flow.

Examples:

LDAA $FF,X LDAB –20,Y

For these examples assume X is $1000 and Y is $2000 before execution of these instructions. (These instructions do not alter the index registers so they will still be $1000 and $2000 respectively after the instructions.) The first instruction will load A with the value from address $10FF and the second instruction will load B with the value from address $1FEC.

This variation ofthe indexed addressing mode in the CPU12 is similar to the M68HC11 indexed addressing mode, but is functionally enhanced. The M68HC11 CPU provides for unsigned 8-bit constant offset indexing from X or Y, and use of Y requires an extra instruction byte and thus, an extra execution cycle. The 9-bit signed offset used in the CPU12 covers the same range of positive offsets as the M68HC11, and adds negative offset capability. The CPU12 can use X, Y, SP or PC as the base index register.

3.8.3 16-Bit Constant Offset Indexed Addressing

This indexed addressing mode uses a 16-bit offset which is added to the base index register (X, Y, SP, or PC) to form the effective address of the memory location affected by the instruction. This allows access to any address in the 64-Kbyte address space. Since the address bus and the offset are both 16 bits, it does not matter whether the offset value is considered to be a signed or an unsigned value ($FFFF may be thought of as +65,535 or as

–1). The 16-bit offset is provided as two extension bytes after the

instruction postbyte in the instruction flow.

3.8.4 16-Bit Constant Indirect Indexed Addressing

This indexed addressing mode adds a 16-bit instruction-supplied offset to the base index register to form the address of a memory location that contains a pointer to the memory location affected by the instruction. The instruction itself does not point to the address of the memory location to be acted upon, but rather to the location of a pointer to the address to be acted on. The square brackets distinguish this addressing mode from 16-bit constant offset indexing.

Example:

LDAA [10,X]

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In this example, X holds the base address of a table of pointers. Assume that X has an initial value of $1000, and that the value $2000 is stored at addresses $100A and $100B. The instruction first adds the value 10 to the value in X to form the address $100A. Next, an address pointer ($2000) is fetched from memory at $100A. Then, the value stored in location $2000 is read and loaded into the A accumulator.

3.8.5 Auto Pre/Post Decrement/Increment Indexed Addressing

This indexed addressing mode provides four ways to automatically change the value in a base index register as a part of instruction execution. The index register can be incremented or decremented by an integer value either before or after indexing takes place. The base index register may be X, Y, or SP (auto-modify modes would not make sense on PC).

Pre decrement and pre increment versions of the addressing mode adjust the value of the index register before accessing the memory location affected by the instruction — the index register retains the changed value after the instruction executes. Post-decrement and post-increment versions of the addressing mode use the initial value in the index register to access the memory location affected by the instruction, then change the value of the index register.

The CPU12 allowsthe index register to be incremented or decremented by any integer value in the ranges –8 through –1, or 1 through 8. The value need not be related to the size of the operand for the current instruction. These instructions can be used to incorporate an index adjustment into an existing instruction rather than using an additional instruction and increasing execution time. This addressing mode is also used to perform operations on a series of data structures in memory.

When an LEAS, LEAX, or LEAY instruction is executed using this addressing mode, and the operation modifies the index register that is being loaded, the final value in the register is thevalue that would have been used to access a memory operand (premodification is seen in the result but postmodification is not).

Examples:

STAA 1,–SP ;equivalent to PSHA STX 2,–SP ;equivalent to PSHX LDX 2,SP+ ;equivalent to PULX LDAA 1,SP+ ;equivalent to PULA

For a “last-used” type of stack like the CPU12 stack, these four examples are equivalent to common push and pull instructions. For a “next-available” stack like the M68HC11 stack, PSHA is equivalent to STAA 1,SP– and PULA is equivalent to LDAA 1,+SP. However, in the M68HC11,16-bit operations like PSHX and PULX require multiple instructions to decrement the SP by one, then store X, then decrement SP by one again.

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In the STAA 1,–SP example, the stack pointer is pre-decremented by one and then A is stored to the address contained in the stack pointer. Similarly the LDX 2,SP+ first loads X from the address in the stack pointer, then post-increments SP by two.

Example:

MOVW 2,X+,4,+Y

This example demonstrates how to work with data structures larger than bytes and words. With this instruction in a program loop, it is possible to move words of data from a list having one word per entry into a second table that has four bytes per table element. In this example the source pointer is updated after the data is read from memory (post-increment) while the destination pointer is updated before it is used to access memory (pre-increment).

3.8.6 Accumulator Offset Indexed Addressing

In this indexed addressing mode, the effective address is the sum of the values in the base index register and an unsigned offset in one of the accumulators. The value in the index register itself is not changed. The index register can be X, Y, SP, or PC and the accumulator can be either of the 8-bit accumulators (A or B) or the 16-bit D accumulator.

Example:

LDAA B,X

This instruction internally adds B to X to form the address from which A will be loaded. B and X are not changed by this instruction. This example is similar to the following two-instruction combination in an M68HC11.

ABX LDAA 0,X

However, this two-instruction sequence alters the index register. If this sequence was part of a loop where B changed on each pass, the index register would have to be reloaded with the reference value on each loop pass. The use of LDAA B,X is more efficient in the CPU12.

3.8.7 Accumulator D Indirect Indexed Addressing

This indexed addressing mode adds the value in the D accumulator to the value in the base index register to form the address of a memory location that contains a pointer to the memory location affected by the instruction. The instruction operand does not point to the address of the memory location to be acted upon, but rather to the location of a pointer to the address to be acted upon. The square brackets distinguish this addressing mode from D accumulator offset indexing.

Example:

JMP [D,PC] GO1 DC.W PLACE1 GO2 DC.W PLACE2 GO3 DC.W PLACE3

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This example is a computed GOTO. The values beginning at GO1 are addresses of potential destinations of the jump instruction. At the time the JMP [D,PC] instruction is executed, PC points to the address GO1, and D holds one of the values $0000, $0002, or $0004 (determined by the program some time before the JMP).

Assume that the value in D is $0002. The JMP instruction adds the values in D and PC to form the address of GO2. Next the CPU reads the address PLACE2 from memory at GO2 and jumps to PLACE2. The locations of PLACE1 through PLACE3 were known at the time of program assembly but the destination of the JMP depends upon the value in D computed during program execution.

3.9 Instructions Using Multiple Modes

Several CPU12 instructions use more than one addressing mode in the course of execution.

3.9.1 Move Instructions

Move instructions use separate addressing modes to access the source and destination of a move. There are move variations for most combinations of immediate, extended, and indexed addressing modes.

The only combinations of addressing modes that are not allowed are those with an immediate mode destination (the operand of an immediate mode instruction is data, not an address). For indexed moves, the reference index register may be X, Y, SP, or PC.

Move instructions do not support indirect modes, or 9- or 16-bit offset modes requiring extra extension bytes. There are special considerations when using PC-relative addressing with move instructions.

PC-relative addressing uses the address of the location immediately following the last byte of object code for the current instruction as a reference point. The CPU12 normally corrects for queue offset and for instruction alignment so that queue operation is transparent to the user. However, move instructions pose three special problems:

1. Some moves use an indexed source and an indexed destination.

2. Some moves have object code that is too long to fit in the queue all at one time, so the PC value changes during execution.

3. All moves do not have the indexed postbyte as the last byte of object code.

These cases are not handled by automatic queue pointer maintenance, but it is still possible to use PC-relative indexing with move instructions by providing for PC offsets in source code.

Table 3-3 shows PC offsets from the location immediately following the current in-

struction by addressing mode.

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Table 3-3 PC Offsets for Move Instructions

MOVE Instruction Addressing Modes Offset Value

IMM ⇒ IDX + 1 EXT ⇒ IDX + 2

MOVB

MOVW

IDX ⇒ EXT – 2

IDX ⇒ IDX

IMM ⇒ IDX + 2 EXT ⇒ IDX + 2 IDX ⇒ EXT – 2

IDX ⇒ IDX

– 1 for 1st Operand

+ 1 for 2nd Operand

– 1 for 1st Operand

+ 1 for 2nd Operand

Example:

1000 18 09 C2 20 00 MOVB $2000 2,PC

Moves a byte of data from $2000 to $1009 The expected location of the PC = $1005. The offset = +2. (1005 + 2 (for 2,PC) + 2 (for correction) = 1009) $18 is the page pre-byte, 09 is the MOVB opcode for ext-idx, C2 is the indexed post-

byte for 2,PC (without correction). The Motorola MCUasm assembler produces corrected object code for PC-relative

moves (18 09 C0 20 00 for the example shown). Note that, instead of assembling the 2,PC as C2, the correction has been applied to make it C0. Check whether an assembler makes the correction before using PC-relative moves.

3.9.2 Bit Manipulation Instructions

Bit manipulation instructions use either a combination of two or a combination of three addressing modes.

The BCLR and BSET instructions use an 8-bit mask to determine which bits in a memory byte are to be changed. The mask must be supplied with the instruction as an immediate mode value. The memory location to be modified can be specified by means of direct, extended, or indexed addressing modes.

The BRCLR and BRSET instructions use an 8-bit mask to test the states of bits in a memory byte. The mask is supplied with the instruction as an immediate mode value. The memory locationto be tested is specified by means of direct, extended, or indexed addressing modes. Relative addressing mode is used to determine the branch address. A signed 8-bit offset must be supplied with the instruction.

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3.10 Addressing More than 64 Kbytes

Some M68HC12 devices incorporate hardware that supports addressing a larger memory space than the standard 64 Kbytes. The expanded memory system uses fast on-chip logic to implement a transparent bank-switching scheme.

Increased code efficiency is the greatest advantage of using a switching scheme instead of a large linear address space. In systems with large linear address spaces, instructions require more bits of information to address a memory location, and CPU overhead is greater. Other advantages include the ability to change the size of system memory and the ability to use various types of external memory.

However, the add-on bank switching schemes used in other microcontrollers have known weaknesses. These include the cost of external glue logic, increased programming overhead to change banks, and the need to disable interrupts while banks are switched.

The M68HC12 system requires no external glue logic. Bank switching overhead is reduced by implementing control logic in the MCU. Interrupts do not need to be disabled during switching because switching tasks are incorporated in special instructions that greatly simplify program access to extended memory.

MCUs with expanded memory treat the 16 Kbytes of memory space from $8000 to $BFFF as a program memory window. Expanded-memory devices also have an 8-bit program page register (PPAGE), which allows up to 256 16-Kbyte program memory pages to be switched into and out of the program memory window. This provides for up to 4 Megabytes of paged program memory.

The CPU12 instruction set includes CALL and RTC (return from call) instructions, which greatly simplify the use of expanded memory space. These instructions also execute correctly on devices that do not have expanded-memory addressing capability, thus providing for portable code.

The CALL instruction is similar to the JSR instruction. When CALL is executed, the current value in PPAGE is pushed onto the stack with a return address, and a new instruction-supplied value is written to PPAGE. This value selects the page the called subroutine resides upon, and can be considered to be part of the effective address. For all addressing mode variations except indexed indirect modes, the new pagevalue is provided by an immediate operand in the instruction. For indexed indirect variations of CALL, a pointer specifies memory locations where the new page value and the address of the called subroutine are stored. Use of indirect addressing for both the page value and the address within the page frees the program from keeping track of explicit values for either address.

The RTC instruction restores the saved program page value and the return address from the stack. This causes execution to resume at the next instruction after the original CALL instruction.

Refer to SECTION 10 MEMORY EXPANSION for a detailed discussion of memory expansion.

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SECTION 4

INSTRUCTION QUEUE

The CPU12 uses an instruction queue to increase execution speed. This section describes queue operation during normal program execution and changes in execution flow. These concepts augment the descriptions of instructions and cycle-by-cycle instruction execution in subsequent sections, but it is important to note that queue operation is automatic, and generally transparent to the user.

The material in this section is general. SECTION 6 INSTRUCTION GLOSSARY contains detailed information concerning cycle-by-cycle execution of each instruction.

SECTION 8 DEVELOPMENT AND DEBUG SUPPORT contains detailed information

about tracking queue operation and instruction execution.

4.1 Queue Description

The fetching mechanism in the CPU12 is best described as a queue rather than as a pipeline. Queue logic fetches program information and positions it for execution, but instructions are executed sequentially. A typical pipelined CPU can execute more than one instruction at the same time, but interactions between the prefetch and execution mechanismscan make tracking and debugging difficult. The CPU12 thus gains the advantages of independentfetches, yet maintains a straightforward relationship between bus and execution cycles.

There are two 16-bit queue stages and one 16-bit buffer. Program information is fetched in aligned 16-bit words. Unless buffering is required, program information is first queued into stage 1, then advanced to stage 2 for execution.

At least two words of program information are available to the CPU when execution begins. The first byte of object code is in either the even or odd half ofthe word in stage 2, and at least two more bytes of object code are in the queue.

Queue logic manages the position of program information so that the CPU itself does notdeal with alignment. As itis executed, each instruction initiates at least enough program word fetches to replace its own object code in the queue.

The buffer is used when a program word arrives before the queue can advance. This occurs during execution of single-byte and odd-aligned instructions. For instance, the queue cannot advance after an aligned, single-byte instruction is executed, because the first byte of the next instruction is also in stage 2. In these cases, information is latched into the buffer until the queue can advance.

Two external pins, IPIPE[1:0], provide time-multiplexed information about data movement in the queue and instruction execution. Decoding and use of these signals is discussed in SECTION 8 DEVELOPMENT AND DEBUG SUPPORT.

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4.2 Data Movement in the Queue

All queue operations are combinations of four basic queue movement cycles. Descriptions of each of these cycles follows. Queue movement cycles are only one factor in instruction execution time, and should not be confused with bus cycles.

4.2.1 No Movement

There is no data movement in the instruction queue during the cycle. This occurs during execution of instructions that must perform a number of internal operations, such as division instructions.

4.2.2 Latch Data from Bus

All instructions initiate fetches to refill the queue as execution proceeds. However, a number of conditions, including instruction alignment and the length of previous instructions, affect when the queue advances. If the queue is not ready to advance when fetched information arrives, the information is latched into the buffer. Later, when the queue does advance, stage 1 is refilled from the buffer. If more than one latch cycle occurs before the queue advances, the buffer is filled on the first latch event and subsequent latch events are ignored until the queue advances.

4.2.3 Advance and Load from Data Bus

The content of queue stage 1 advances to stage 2, and stage 1 is loaded with a word of program information from the data bus. The information was requested two bus cycles earlier but has only become available this cycle, due to access delay.

4.2.4 Advance and Load from Buffer

The content of queue stage 1 advances to stage 2, and stage 1 is loaded with a word of program information from the buffer. The information in the buffer was latched from the data bus during a previous cycle because the queue was not ready to advance when it arrived.

4.3 Changes in Execution Flow

During normal instruction execution, queue operations proceed as a continuous sequence of queue movement cycles. However, situations arise which call for changes in flow. These changes are categorized as resets, interrupts, subroutine calls, conditional branches, and jumps. Generally speaking, resets and interrupts are considered to be related to events outside the current program context that require special processing, while subroutine calls, branches, and jumps are considered to be elements of program structure.

During design, great care is taken to assure that the mechanism that increases instruction throughput during normal program execution does not cause bottlenecks during changes of program flow, but internal queue operation is largely transparent to the user. The following information is provided to enhance subsequent descriptions of instruction execution.

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4.3.1 Exceptions

Exceptions are events that require processing outside the normal flow of instruction execution. CPU12 exceptions include four types of resets, an unimplemented opcode trap, a software interrupt instruction, X-bit interrupts, and I-bit interrupts. All exceptions use the same microcode, but the CPU follows different execution paths for each type of exception.

CPU12 exception handling is designed to minimize the effect of queue operation on context switching. Thus, an exception vector fetch is the first part of exception processing, and fetches to refill the queue from the address pointed to by the vector are interleaved with the stacking operations that preserve context, so that program access time does not delay the switch. Refer to SECTION 7 EXCEPTION PROCESSING for detailed information.

4.3.2 Subroutines

The CPU12 can branch to (BSR), jump to (JSR), or CALL subroutines. BSR and JSR are used to access subroutines in the normal 64-Kbyte address space. The CALL instruction is intended for use in MCUs with expanded memory capability.

BSR uses relative addressing mode to generate the effective address of the subroutine, while JSR can use various other addressing modes. Both instructions calculate a return address, stack the address, then perform three program word fetches to refill the queue. The first two words fetched are queued during the second and third cycles of the sequence. The third fetch cycle is performed in anticipation of a queue advance, which may occur during the fourth cycle of the sequence. If the queue is not yet ready to advance at that time, the third word of program information is held in the buffer.

Subroutines in the normal 64-Kbyte address space are terminated with a return from subroutine (RTS) instruction. RTS unstacks the return address, then performs three program word fetches from that address to refill the queue.

CALL is similar to JSR. MCUs with expanded memory treat 16 Kbytes of addresses from $8000 to $BFFF as a memory window. An 8-bit PPAGE register switches memory pages into and out of the window. When CALL is executed, a return address is calculated, then it and the current PPAGE value are stacked, and a new instructionsupplied value is written to PPAGE. The subroutine address is calculated, then three program word fetches are made from that address.

The RTC instruction is used to terminate subroutines in expanded memory. RTC unstacks the PPAGE value and the return address, then performs three program word fetches from that address to refill the queue.

CALL and RTC execute correctly in the normal 64-Kbyte address space, thus providing for portable code. However, since extra execution cycles are required, routinely substituting CALL/RTC for JSR/RTS is not recommended.

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4.3.3 Branches

Branchinstructions cause execution flow to change when specific pre-conditions exist. The CPU12 instruction set includes short conditional branches, long conditional branches, and bit-condition branches. Types and conditions of branch instructions are described in 5.18 Branch Instructions. All branch instructions affect the queue similarly, but there are differences in overall cycle counts between the various types. Loop primitive instructions are a special type of branch instruction used to implement counter-based loops.

Branch instructions have two execution cases. Either the branch condition is satisfied, and a change of flow takes place, or the condition is not satisfied, and no change of flow occurs.

4.3.3.1 Short Branches

The “not-taken” case for short branches is simple. Since the instruction consists of a single word containing both an opcode and an 8-bit offset, the queue advances, another program word is fetched, and execution continues with the next instruction.

The “taken” case for short branches requires that the queue be refilled so that execution can continue at a new address. First, the effective address of the destination is calculated using the relative offset in the instruction. Then, the address is loaded into the program counter, and the CPU performs three program word fetches at the new address. The first two words fetched are loaded into the instruction queue during the second and third cycles of the sequence. The third fetch cycle is performed in anticipation of a queue advance, which may occur during the first cycle of the next instruction. If the queue is not yet ready to advance at that time, the third word of program information is held in the buffer.

4.3.3.2 Long Branches

The “not-taken” case for all long branches requires three cycles, while the “taken” case requires four cycles. This is due to differences in the amount of program information needed to fill the queue.

Long branch instructions begin with a $18 prebyte which indicates that the opcode is on page 2 of the opcode map. The CPU12 treats the prebyte as a special one-byte instruction. If the prebyte is not aligned, the first cycle is used to perform a program word access; if the prebyte is aligned, the first cycle is used to perform a free cycle. The first cycle for the prebyte is executed whether or not the branch is taken.

The first cycle of the branch instruction is an optional cycle. Optional cycles make the effects of byte-sized and misaligned instructions consistent with those of aligned wordlength instructions. Optional cycles are always performed, but serve different purposes determined by instruction alignment. Program information is always fetched as aligned 16-bit words. When an instruction consists of an odd number of bytes, and the first byte is aligned with an even byte boundary, an optional cycle is used to make an additional program word access that maintains queue order. In all other cases, the optional cycle appears as a free cycle.

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In the “not-taken” case, the queue must advance so that execution can continue with the next instruction. Two cycles are used to refill the queue. Alignment determines how the second of these cycles is used.

In the “taken” case, the effective address of the branch is calculated using the 16-bit relative offset contained in the second word of the instruction. This address is loaded into the program counter, then the CPU performs three program word fetches at the new address. The first two words fetched are loaded into the instruction queue during the second and third cycles of the sequence. The third fetch cycle is performed in anticipation of a queue advance, which may occur during the first cycle of the next instruction. If the queue is not yet ready to advance, the third word of program information is held in the buffer.

4.3.3.3 Bit Condition Branches

Bit-conditional branch instructions read a location in memory, and branch if the bits in that location are in a certain state. These instructions can use direct, extended, or indexed addressing modes. Indexed operations require varying amounts of information to determine the effective address, so instruction length varies according to the mode used, which in turn affects the amount of program information fetched. In order to shorten execution time, these branches perform one program word fetch in anticipation of the “taken” case. The data from this fetch is overwritten by subsequent fetches in the “not-taken” case.

4.3.3.4 Loop Primitives

The loop primitive instructions test a counter value in a register or accumulator, and branch to an address specified by a 9-bit relative offset contained in the instruction if a specified pre-condition is met. There are auto-increment and auto-decrement versions of the instructions. The test and increment/decrement operations are performed on internal CPU registers, and require no additional program information. In order to shorten execution time, these branches perform one program word fetch in anticipation of the “taken” case. The data from this fetch is overwritten by subsequent fetches in the “not-taken” case. The “taken” case performs two additional program word fetches at the new address. In the “not-taken” case, the queue must advance so that execution can continue with the next instruction. Two cycles are used to refill the queue.

4.3.4 Jumps

JMP is the simplest change of flow instruction. JMP can use extended or indexed addressing. Indexed operations require varying amounts of information to determine the effective address, so instruction length varies according to the mode used, which in turn affects the amount of program information fetched. All forms of JMP perform three program word fetches at the new address. The first two words fetched are loaded into the instruction queue during the second and third cycles of the sequence. The third fetch cycle is performed in anticipation of a queue advance, which may occur during the first cycle of the next instruction. If the queue is not yet ready to advance, the third word of program information is held in the buffer.

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SECTION 5

INSTRUCTION SET OVERVIEW

This section contains general information about the CPU12 instruction set. It is organized into instruction categories grouped by function.

5.1 Instruction Set Description

CPU12 instructions are a superset of the M68HC11 instruction set. Code written for an M68HC11 can be reassembled and run on a CPU12 with no changes. The CPU12 provides expanded functionality and increased code efficiency.

In the M68HC12 architecture, all memory and I/O are mapped in a common 64-Kbyte address space (memory-mapped I/O). This allows the same set of instructions to be used to access memory, I/O, and control registers. General-purpose load, store, transfer, exchange, and move instructions facilitate movement of data to and from memory and peripherals.

The CPU12 has a full set of 8-bit and 16-bit mathematical instructions. There are instructions for signed and unsigned arithmetic, division and multiplication with 8-bit, 16bit, and some larger operands.

Special arithmetic and logic instructions aid stacking operations, indexing, BCD calculation, and condition code register manipulation. There are also dedicated instructions for multiply and accumulate operations, table interpolation, and specialized fuzzy logic operations that involve mathematical calculations.

Refer to SECTION 6 INSTRUCTION GLOSSARY for detailed information about individual instructions. APPENDIX A INSTRUCTION REFERENCE contains quick-reference material, including an opcode map and postbyte encoding for indexed addressing, transfer/exchange instructions, and loop primitive instructions.

5.2 Load and Store Instructions

Load instructions copy memory content into an accumulator or register. Memory content is not changed by the operation. Load instructions (but not LEA_ instructions) affect condition code bits so no separate test instructions are needed to check the loaded values for negative or zero conditions.

Store instructions copy the content of a CPU register to memory. Register/accumulator content is not changed by the operation. Store instructions automatically update the N and Z condition code bits, which can eliminate the need for a separate test instruction in some programs.

Table 5-1 is a summary of load and store instructions.

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Table 5-1 Load and Store Instructions

Load Instructions

Mnemonic Function Operation

LDAA Load A (M) ⇒ A LDAB Load B (M) ⇒ B

LDD Load D (M : M + 1) ⇒ (A:B) LDS Load SP (M : M + 1) ⇒ SP LDX Load Index Register X (M : M + 1) ⇒ X

LDY Load Index Register Y (M : M + 1) ⇒ Y LEAS Load Effective Address into SP Effective Address ⇒ SP LEAX Load Effective Address into X Effective Address ⇒ X LEAY Load Effective Address into Y Effective Address ⇒ Y

Store Instructions

Mnemonic Function Operation

STAA Store A (A) ⇒ M STAB Store B (B) ⇒ M

STD Store D (A) ⇒ M, (B) ⇒ M + 1

STS Store SP (SP) ⇒ M : M + 1

STX Store X (X) ⇒ M : M + 1

STY Store Y (Y) ⇒ M : M + 1

5.3 Transfer and Exchange Instructions

Transfer instructions copy the content of a register or accumulator into anotherregister or accumulator. Source content is not changed by the operation. TFR is a universal transfer instruction, but other mnemonics are accepted for compatibility with the M68HC11. The TAB and TBA instructions affect the N, Z, and V condition code bits in the same way as M68HC11 instructions. The TFR instruction does not affect the condition code bits.

Exchange instructions exchange the contents of pairs of registers or accumulators. The SEX instruction is a special case of the universal transfer instruction that is used

to sign-extend 8-bit two’s complement numbers so that they can be used in 16-bit operations. The 8-bit number is copied from accumulator A, accumulator B, or the condition codes register to accumulator D, the X index register, the Y index register, or the stack pointer. All the bits in the upper byte of the 16-bit result are given the value of the MSB of the 8-bit number.

SECTION 6 INSTRUCTION GLOSSARY contains information concerning other

transfers and exchanges between 8- and 16-bit registers.

Table 5-2 is a summary of transfer and exchange instructions.

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Table 5-2 Transfer and Exchange Instructions

Transfer Instructions

Mnemonic Function Operation

TAB Transfer A to B (A) ⇒ B TAP Transfer A to CCR (A) ⇒ CCR TBA Transfer B to A (B) ⇒ A TFR Transfer Register to Register (A, B, CCR, D, X, Y, or SP) ⇒ A, B, CCR, D, X, Y, or SP TPA Transfer CCR to A (CCR) ⇒ A TSX Transfer SP to X (SP) ⇒ X TSY Transfer SP to Y (SP) ⇒ Y TXS Transfer X to SP (X) ⇒ SP TYS Transfer Y to SP (Y) ⇒ SP

Exchange Instructions

Mnemonic Function Operation

EXG Exchange Register to Register (A, B, CCR, D, X, Y, or SP) ⇔ (A, B, CCR, D, X, Y, or SP) XGDX Exchange D with X (D) ⇔ (X) XGDY Exchange D with Y (D) ⇔ (Y)

Sign Extension Instruction

Mnemonic Function Operation

SEX Sign Extend 8-Bit Operand (A, B, CCR) ⇒ X, Y, or SP

5.4 Move Instructions

These instructions move data bytes or words from a source (M1,M:M+11) to a destination (M

,M:M+12) in memory. Six combinations of immediate, extended, and in-

dexed addressing are allowed to specify source and destination addresses (IMM ⇒ EXT, IMM ⇒ IDX, EXT ⇒ EXT, EXT ⇒ IDX, IDX ⇒ EXT, IDX ⇒ IDX).

Table 5-3 shows byte and word move instructions.

Table 5-3 Move Instructions

Mnemonic Function Operation

MOVB Move Byte (8-bit) (M

MOVW Move Word (16-bit) (M : M + 11) ⇒ M : M + 1

) ⇒ M

5.5 Addition and Subtraction Instructions

Signed and unsigned 8- and 16-bit addition can be performed between registers or between registers and memory. Special instructions support index calculation. Instructions that add the CCR carry bit facilitate multiple precision computation.

Signed and unsigned 8- and 16-bit subtraction can be performed between registers or between registers and memory. Special instructions support index calculation.Instructions that subtract the CCR carry bit facilitate multiple precision computation. Refer to

Table 5-4 for addition and subtraction instructions.

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Table 5-4 Addition and Subtraction Instructions

Addition Instructions

Mnemonic Function Operation

ABA Add A to B (A) + (B) ⇒ A ABX Add B to X (B) + (X) ⇒ X

ABY Add B to Y (B) + (Y) ⇒ Y ADCA Add with Carry to A (A) + (M) + C ⇒ A ADCB Add with Carry to B (B) + (M) + C ⇒ B ADDA Add without Carry to A (A) + (M) ⇒ A ADDB Add without Carry to B (B) + (M) ⇒ B

ADDD Add to D (A:B) + (M : M + 1) ⇒ A : B

Subtraction Instructions

Mnemonic Function Operation

SBA Subtract B from A (A) – (B) ⇒ A SBCA Subtract with Borrow from A (A) – (M) – C ⇒ A SBCB Subtract with Borrow from B (B) – (M) – C ⇒ B SUBA Subtract Memory from A (A) – (M) ⇒ A SUBB Subtract Memory from B (B) – (M) ⇒ B SUBD Subtract Memory from D (A:B) (D) – (M : M + 1) ⇒ D

5.6 Binary Coded Decimal Instructions

To add binary coded decimal operands, use addition instructions that set the half-carry bit in the CCR, then adjust the result with the DAA instruction. Table 5-5 is a summary of instructions that can be used to perform BCD operations.

Table 5-5 BCD Instructions

Mnemonic Function Operation

ABA Add B to A (A) + (B) ⇒ A ADCA Add with Carry to A (A) + (M) + C ⇒ A ADCB Add with Carry to B (B) + (M) + C ⇒ B ADDA Add Memory to A (A) + (M) ⇒ A ADDB Add Memory to B (B) + (M) ⇒ B

DAA Decimal Adjust A (A)

5.7 Decrement and Increment Instructions

These instructions are optimized 8- and 16-bit addition and subtraction operations. They are generally used to implement counters. Because they do not affect the carry bit in the CCR, they are particularly well suited for loop counters in multiple-precision computation routines. Refer to 5.19 Loop Primitive Instructions for information concerning automatic counter branches. Table 5-6 is a summary of decrement and increment instructions.

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Table 5-6 Decrement and Increment Instructions

Decrement Instructions

Mnemonic Function Operation

DEC Decrement Memory (M) – $01 ⇒ M DECA Decrement A (A) – $01 ⇒ A DECB Decrement B (B) – $01 ⇒ B

DES Decrement SP (SP) – $0001 ⇒ SP

DEX Decrement X (X) – $0001 ⇒ X

DEY Decrement Y (Y) – $0001 ⇒ Y

Increment Instructions

Mnemonic Function Operation

INC Increment Memory (M) + $01 ⇒ M INCA Increment A (A) + $01 ⇒ A INCB Increment B (B) + $01 ⇒ B

INS Increment SP (SP) + $0001 ⇒ SP

INX Increment X (X) + $0001 ⇒ X

INY Increment Y (Y) + $0001 ⇒ Y

5.8 Compare and Test Instructions

Compare and test instructions perform subtraction between a pair of registers or between a register and memory. The result is not stored, but condition codes are set by the operation. These instructions are generally used to establish conditions for branch instructions. In this architecture, most instructions update condition code bits automatically, so it is often unnecessary to include separate test or compare instructions. Ta-

ble 5-7 is a summary of compare and test instructions.

Table 5-7 Compare and Test Instructions

Compare Instructions

Mnemonic Function Operation

CBA Compare A to B (A) – (B) CMPA Compare A to Memory (A) – (M) CMPB Compare B to Memory (B) – (M)

CPD Compare D to Memory (16-bit) (A : B) – (M : M + 1)

CPS Compare SP to Memory (16-bit) (SP) – (M : M + 1)

CPX Compare X to Memory (16-bit) (X) – (M : M + 1)

CPY Compare Y to Memory (16-bit) (Y) – (M : M + 1)

Test Instructions

Mnemonic Function Operation

TST Test Memory for Zero or Minus (M) – $00

TSTA Test A for Zero or Minus (A) – $00 TSTB Test B for Zero or Minus (B) – $00

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5.9 Boolean Logic Instructions

These instructions perform a logic operation between an 8-bit accumulator or the CCR and a memory value. AND, OR, and exclusive OR functions are supported. Table 5-

8 summarizes logic instructions.

Table 5-8 Boolean Logic Instructions

Mnemonic Function Operation

ANDA AND A with Memory (A) • (M) ⇒ A ANDB AND B with Memory (B) • (M) ⇒ B

ANDCC AND CCR with Memory (Clear CCR Bits) (CCR) • (M) ⇒ CCR

EORA Exclusive OR A with Memory (A) EORB Exclusive OR B with Memory (B) ORAA OR A with Memory (A) + (M) ⇒ A ORAB OR B with Memory (B) + (M) ⇒ B ORCC OR CCR with Memory (Set CCR Bits) (CCR) + (M) ⇒ CCR

⊕ (M) ⇒ A ⊕ (M) ⇒ B

5.10 Clear, Complement, and Negate Instructions

Each of these instructions performs a specific binary operation on a value in an accumulator or in memory. Clear operations clear the value to zero, complement operations replace the value with its one’s complement, and negate operations replace the value with its two’s complement. Table 5-9 is a summary of clear, complement and negate instructions.

Table 5-9 Clear, Complement, and Negate Instructions

Mnemonic Function Operation

CLC Clear C Bit in CCR 0 ⇒ C

CLI Clear I Bit in CCR 0 ⇒ I

CLR Clear Memory $00 ⇒ M

CLRA Clear A $00 ⇒ A CLRB Clear B $00 ⇒ B

CLV Clear V bit in CCR 0 ⇒ V

COM One’s Complement Memory $FF – (M) ⇒ M or ( COMA One’s Complement A $FF – (A) ⇒ A or ( COMB One’s Complement B $FF – (B) ⇒ B or (

NEG Two’s Complement Memory $00 – (M) ⇒ M or ( NEGA Two’s Complement A $00 – (A) ⇒ A or ( NEGB Two’s Complement B $00 – (B) ⇒ B or (

M) ⇒ M A) ⇒ A

B) ⇒ B M) + 1 ⇒ M A) + 1 ⇒ A B) + 1 ⇒ B

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5.11 Multiplication and Division Instructions

There are instructions for signed and unsigned 8- and 16-bit multiplication. Eight-bit multiplication operations have a 16-bit product. Sixteen-bit multiplication operations have 32-bit products.

Integer and fractional division instructions have 16-bit dividend, divisor, quotient, and remainder. Extended division instructions use a 32-bit dividend and a 16-bit divisor to produce a 16-bit quotient and a 16-bit remainder.

Table 5-10 is a summary of multiplication and division instructions.

Table 5-10 Multiplication and Division Instructions

Multiplication Instructions

Mnemonic Function Operation

EMUL 16 by 16 Multiply (Unsigned) (D) × (Y) ⇒ Y : D

EMULS 16 by 16 Multiply (Signed) (D) × (Y) ⇒ Y : D

MUL 8 by 8 Multiply (Unsigned) (A) × (B) ⇒ A : B

Division Instructions

Mnemonic Function Operation

(Y : D) ÷ (X)

EDIV 32 by 16 Divide (Unsigned)

EDIVS 32 by 16 Divide (Signed)

FDIV 16 by 16 Fractional Divide

IDIV 16 by 16 Integer Divide (Unsigned)

IDIVS 16 by 16 Integer Divide (Signed)

Quotient ⇒ Y

Remainder ⇒ D

(Y : D) ÷ (X)

Quotient ⇒ Y

Remainder ⇒ D

(D) ÷ (X) ⇒ X

remainder ⇒ D

(D) ÷ (X) ⇒ X

remainder ⇒ D

(D) ÷ (X) ⇒ X

remainder ⇒ D

5.12 Bit Test and Manipulation Instructions

These operations use a mask value to test or change the value of individual bits in an accumulator or in memory. BITA and BITB provide a convenient means of testing bits without altering the value of either operand. Table 5-11 is a summary of bit test and manipulation instructions.

Table 5-11 Bit Test and Manipulation Instructions

Mnemonic Function Operation

BCLR Clear Bits in Memory (M) • (

BITA Bit Test A (A) • (M) BITB Bit Test B (B) • (M)

BSET Set Bits in Memory (M) + (mm) ⇒ M

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5.13 Shift and Rotate Instructions

There are shifts and rotates for all accumulators and for memory bytes. All pass the shifted-out bit through the C status bit to facilitate multiple-byte operations. Because logical and arithmetic left shifts are identical, there are no separate logical left shift operations. LSL mnemonics are assembled as ASL operations. Table 5-12 shows shift and rotate instructions.

Table 5-12 Shift and Rotate Instructions

Logical Shifts

Mnemonic Function Operation

LSL LSLA LSLB

Logic Shift Left Memory

Logic Shift Left A Logic Shift Left B

LSLD Logic Shift Left D

LSR LSRA LSRB

Logic Shift Right Memory

Logic Shift Right A Logic Shift Right B

LSRD Logic Shift Right D

Arithmetic Shifts

Mnemonic Function Operation

ASL ASLA ASLB

Arithmetic Shift Left Memory

Arithmetic Shift Left A Arithmetic Shift Left B

ASLD Arithmetic Shift Left D

b0A

ASR ASRA ASRB

Arithmetic Shift Right Memory

Arithmetic Shift Right A Arithmetic Shift Right B

Rotates

Mnemonic Function Operation

ROL ROLA ROLB

ROR

RORA RORB

Rotate Left Memory Through Carry

Rotate Left A Through Carry Rotate Left B Through Carry

Rotate Right Memory Through Carry

Rotate Right A Through Carry Rotate Right B Through Carry

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5.14 Fuzzy Logic Instructions

The CPU12 instruction set includes instructions that support efficient processing of fuzzy logic operations. The descriptions of fuzzy logic instructions that follow are functional overviews. Table 5-13 summarizes the fuzzy logic instructions. Refer to SEC-

TION 9 FUZZY LOGIC SUPPORT for detailed discussion.

5.14.1 Fuzzy Logic Membership Instruction

The MEM instruction is used during the fuzzification process. During fuzzification, current system input values are compared against stored input membership functions to determine the degree to which each label of each system input is true. This is accomplished by finding the y value for the current input on a trapezoidal membership function for each label of each system input. The MEM instruction performs this calculation for one label of one system input. To perform the complete fuzzification task for a system, several MEM instructions must be executed, usually in a program loop structure.

5.14.2 Fuzzy Logic Rule Evaluation Instructions

The REV and REVW instructions perform MIN-MAX rule evaluations that are central elements of a fuzzy logic inference program. Fuzzy input values are processed using a list of rules from the knowledge base to produce a list of fuzzy outputs. The REV instruction treats all rules as equally important. The REVW instruction allows each rule to have a separate weighting factor. The two rule evaluation instructions also differ in the way rules are encoded into the knowledge base. Because they require a number of cycles to execute, rule evaluation instructions can be interrupted. Once the interrupt has been serviced, instruction execution resumes at the point the interrupt occurred.

5.14.3 Fuzzy Logic Averaging Instruction

The WAV instruction provides a facility for weighted average calculations. In order to be usable, the fuzzy outputs produced by rule evaluation must be defuzzified to produce a single output value which represents the combined effect of all of the fuzzy outputs. Fuzzy outputs correspond to the labels of a system output and each is defined by a membership function in the knowledge base. The CPU12 typically uses singletons for output membership functions rather than the trapezoidal shapes used for inputs. As with inputs, the x-axis represents the range of possible values for a system output. Singleton membership functions consist of the x-axis position for a label of the system output. Fuzzy outputs correspond to the y-axis height of the corresponding output membership function. The WAV instruction calculates the numerator and denominator sums for a weighted average of the fuzzy outputs. Because WAV requires a number of cycles to execute, it can be interrupted. The wavr pseudo-instruction causes execution to resume at the point it was interrupted.

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Table 5-13 Fuzzy Logic Instructions

Mnemonic Function Operation

⇒ M

MEM Membership Function

µ (grade)

(X) + 4 ⇒ X; (Y) + 1 ⇒ Y; A unchanged

if (A) < P1 or (A) > P2, then µ = 0, else

µ = MIN [((A) – P1) × S1, (P2 – (A)) × S2, $FF]

where:

A = current crisp input value X points to a four byte data structure that describes a trap-

ezoidal membership function as base intercept points and slopes (P1, P2, S1, S2)

Y points at fuzzy input (RAM location)

See instruction details for special cases

Find smallest rule input (MIN)

Store to rule outputs unless fuzzy output is larger (MAX)

Rules are unweighted

(Y)

REV MIN-MAX Rule Evaluation

REVW MIN-MAX Rule Evaluation

Calculates Numerator (Sum of Products)

and Denominator (Sum of Weights) for

WAV

Weighted Average Calculation

Results Are Placed in Correct Registers

For EDIV immediately After WAV

Each rule input is an 8-bit offset from a base address in Y Each rule output is an 8-bit offset from a base address in Y $FE separates rule inputs from rule outputs $FF terminates the rule list

REV can be interrupted

Find smallest rule input (MIN)

Multiply by a rule weighting factor (optional)

Store to rule outputs unless fuzzy output is larger (MAX)

Each rule input is the 16-bit address of a fuzzy input Each rule output is the 16-bit address of a fuzzy output Address $FFFE separates rule inputs from rule outputs $FFFF terminates the rule list Weights are 8-bit values in a separate table

REVW can be interrupted

SiF

∑

Y:D

⇒

wavr

Resumes Execution of

Interrupted WAV Instruction

Recover immediate results from stack

rather than initializing them to zero.

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5.15 Maximum and Minimum Instructions

These instructions are used to make comparisons between an accumulator and a memory location. These instructions can be used for linear programming operations, such as Simplex-method optimization or for fuzzification.

MAX and MIN instructions use accumulator A to perform 8-bit comparisons, while EMAX and EMIN instructions use accumulator D to perform 16-bit comparisons. The result (maximum or minimum value) can be stored in the accumulator (EMAXD, EMIND, MAXA, MINA) or the memory address (EMAXM, EMINM, MAXM, MINM).

Table 5-14 is a summary of minimum and maximum instructions.

Table 5-14 Minimum and Maximum Instructions

Minimum Instructions

Mnemonic Function Operation

EMIND

EMINM

MINA

MINM

Mnemonic Function Operation

EMAXD

EMAXM

MAXA

MAXM

MIN of Two Unsigned 16-Bit Values

Result to Accumulator

MIN of Two Unsigned 16-Bit Values

Result to Memory

MIN of Two Unsigned 8-Bit Values

Result to Accumulator

MIN of Two Unsigned 8-Bit Values

Result to Memory

Maximum Instructions

MAX of Two Unsigned 16-Bit Values

Result to Accumulator

MAX of Two Unsigned 16-Bit Values

Result to Memory

MAX of Two Unsigned 8-Bit Values

Result to Accumulator

MAX of Two Unsigned 8-Bit Values

Result to Memory

MIN ((D), (M : M + 1))

MIN ((A), (M))

MAX ((D), (M : M + 1))

MAX ((A), (M))

MAX((A), (M))

⇒ D

⇒ M : M+1

⇒ A

⇒ M

⇒ D

⇒ M : M + 1

⇒ A

⇒ M

5.16 Multiply and Accumulate Instruction

The EMACS instruction multiplies two 16-bit operands stored in memory and accumulates the 32-bit result in a third memory location. EMACS can be used to implement simple digital filters and defuzzification routines that use 16-bit operands. The WAV instruction incorporates an 8- to 16-bit multiply and accumulate operation that obtains a numerator for the weighted average calculation. The EMACS instruction can automate this portion of the averaging operation when 16-bit operands are used. Table 5-

15 shows the EMACS instruction.

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Table 5-15 Multiply and Accumulate Instructions

Mnemonic Function Operation

EMACS

Multiply and Accumulate (Signed)

16 × 16 Bit

⇒ 32 Bit

((M

(X):M(X+1)

) × (M

(Y):M(Y+1)

)) + (M ~ M + 3) ⇒ M ~ M + 3

5.17 Table Interpolation Instructions

The TBL and ETBL instructions interpolate values from tables stored in memory. Any function that can be represented as a series of linear equations can be represented by a table of appropriate size. Interpolation can be used for many purposes, including tabular fuzzy logic membership functions. TBL uses 8-bit table entries and returns an 8bit result; ETBL uses 16-bit table entries and returns a 16-bit result. Use of indexed addressing mode provides great flexibility in structuring tables.

Consider each of the successive values stored in a table to be y-values for the endpoint of a line segment. The value in the B accumulator before instruction execution begins represents change in x from the beginning of the line segment to the lookup point divided by total change in x from the beginning to the end of the line segment. B is treated as an 8-bit binary fraction with radix point left of the MSB, so each line segment is effectively divided into 256 smaller segments. During instruction execution, the change in y between the beginning and end of the segment (a signed byte for TBL or a signed word for ETBL) is multiplied by the content of the B accumulator to obtain an intermediate delta-y term. The result (stored in the A accumulator by TBL, and in the D accumulator by ETBL) is the y-value of the beginning point plus the signed intermediate delta-y value. Table 5-16 shows the table interpolation instructions.

Table 5-16 Table Interpolation Instructions

Mnemonic Function Operation

(M : M + 1) + [(B) × ((M + 2 : M + 3) – (M : M + 1))]

ETBL

TBL

16-Bit Table Lookup and Interpolate

(no indirect addressing modes allowed)

8-Bit Table Lookup and Interpolate

(no indirect addressing modes allowed.)

Initialize B, and index before ETBL.

<ea> points to the first table entry (M : M + 1)

B is fractional part of lookup value

(M) + [(B) × ((M + 1) – (M))]

Initialize B, and index before TBL.

<ea> points to the first 8-bit table entry (M)

B is fractional part of lookup value.

⇒ D

⇒ A

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5.18 Branch Instructions

Branch instructions cause sequence to change when specific conditions exist. The CPU12 uses three kinds of branch instructions. These are short branches, long branches, and bit-conditional branches.

Branch instructions can also be classified by the type of condition that must be satisfied in order for a branch to be taken. Some instructions belong to more than one classification.

Unary branch instructions always execute. Simple branches are taken when a specific bit in the condition code register is in a

specific state as a result of a previous operation. Unsigned branches are taken when comparison or test of unsigned quantities re-

sults in a specific combination of condition code register bits. Signed branches are taken when comparison or test of signed quantities results in

a specific combination of condition code register bits.

5.18.1 Short Branch Instructions

Short branch instructions operate as follows. When a specified condition is met, a signed 8-bit offset is added to the value in the program counter. Program execution continues at the new address.

The numeric range of short branch offset values is $80 (–128) to $7F (127) from the address of the next memory location after the offset value.

Table 5-17 is a summary of the short branch instructions.

5.18.2 Long Branch Instructions

Long branch instructions operate as follows. When a specified condition is met, a signed 16-bit offset is added to the value in the program counter. Program execution continues at the new address. Long branches are used when large displacements between decision-making steps are necessary.

The numeric range of long branch offset values is $8000 (–32,768) to $7FFF (32,767) from the address of the next memory location after the offset value. This permits branching from any location in the standard 64-Kbyte address map to any other location in the map.

Table 5-18 is a summary of the long branch instructions.

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Table 5-17 Short Branch Instructions

Unary Branches

Mnemonic Function Equation or Operation

BRA Branch Always 1 = 1 BRN Branch Never 1 = 0

Simple Branches

Mnemonic Function Equation or Operation

BCC Branch if Carry Clear C = 0 BCS Branch if Carry Set C = 1 BEQ Branch if Equal Z = 1

BMI Branch if Minus N = 1

BNE Branch if Not Equal Z = 0

BPL Branch if Plus N = 0 BVC Branch if Overflow Clear V = 0 BVS Branch if Overflow Set V= 1

Unsigned Branches

Mnemonic Function Relation Equation or Operation

BHI Branch if Higher R > MC+ Z = 0 BHS Branch if Higher or Same R ≥ MC= 0 BLO Branch if Lower R < MC= 1

BLS Branch if Lower or Same R ≤ MC+ Z = 1

Signed Branches

Mnemonic Function Relation Equation or Operation

BGE Branch if Greater Than or Equal R ≥ MN⊕ V = 0 BGT Branch if Greater Than R > MZ+ (N ⊕ V) = 0

BLE Branch if Less Than or Equal R ≤ MZ+ (N ⊕ V) = 1 BLT Branch if Less Than R < MN⊕ V = 1

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Table 5-18 Long Branch Instructions

Unary Branches

Mnemonic Function Equation or Operation

LBRA Long Branch Always 1 = 1 LBRN Long Branch Never 1 = 0

Simple Branches

Mnemonic Function Equation or Operation

LBCC Long Branch if Carry Clear C = 0 LBCS Long Branch if Carry Set C = 1 LBEQ Long Branch if Equal Z = 1

LBMI Long Branch if Minus N = 1

LBNE Long Branch if Not Equal Z = 0

LBPL Long Branch if Plus N = 0 LBVC Long Branch if Overflow Clear V = 0 LBVS Long Branch if Overflow Set V = 1

Unsigned Branches

Mnemonic Function Equation or Operation

LBHI Long Branch if Higher C + Z = 0 LBHS Long Branch if Higher or Same C = 0 LBLO Long Branch if Lower Z = 1

LBLS Long Branch if Lower or Same C + Z = 1

Signed Branches

Mnemonic Function Equation or Operation

LBGE Long Branch if Greater Than or Equal N LBGT Long Branch if Greater Than Z+ (N

LBLE Long Branch if Less Than or Equal Z + (N LBLT Long Branch if Less Than N

⊕ V = 0

⊕ V) = 0 ⊕ V) = 1

⊕ V = 1

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5.18.3 Bit Condition Branch Instructions

These branches are taken when bits in a memory byte are in a specific state. A mask operand is used to test the location. If all bits in that location that correspond to ones in the mask are set (BRSET) or cleared (BRCLR), the branch is taken.

The numeric range of 8-bit offset values is $80 (

–128) to $7F (127) from the address

of the next memory location after the offset value. Table 5-19 is a summary of bit-condition branches.

Table 5-19 Bit Condition Branch Instructions

Mnemonic Function Equation or Operation

BRCLR Branch if Selected Bits Clear (M) • (mm) = 0 BRSET Branch if Selected Bits Set (

M) • (mm) = 0

5.19 Loop Primitive Instructions

The loop primitives can also be thought of as counter branches. The instructions test a counter value in a register or accumulator (A, B, D, X, Y, or SP) for zero or nonzero value as a branch condition. There are predecrement, preincrement and test-only versions of these instructions.

The numeric range of 8-bit offset values is $80 (

–128) to $7F (127) from the address

of the next memory location after the offset value. Table 5-20 is a summary of loop primitive branches.

Table 5-20 Loop Primitive Instructions

Mnemonic Function Equation or Operation

DBEQ

DBNE

IBEQ

IBNE

TBEQ

TBNE

Decrement counter and branch if = 0

(counter = A, B, D, X, Y, or SP)

Decrement counter and branch if ≠ 0

(counter = A, B, D, X, Y, or SP)

Increment counter and branch if = 0

(counter = A, B, D, X, Y, or SP)

Increment counter and branch if ≠ 0

(counter = A, B, D, X, Y, or SP)

Test counter and branch if = 0

(counter = A, B, D, X,Y, or SP)

Test counter and branch if ≠ 0

(counter = A, B, D, X,Y, or SP)

(counter) – 1

If (counter) = 0, then branch

else continue to next instruction

(counter) – 1 If (counter) not = 0, then branch else continue to next instruction

(counter) + 1

If (counter) = 0, then branch

else continue to next instruction

(counter) + 1 If (counter) not = 0, then branch else continue to next instruction

If (counter) = 0, then branch

else continue to next instruction If (counter) not = 0, then branch

else continue to next instruction

⇒ counter

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5.20 Jump and Subroutine Instructions

Jump instructions cause immediate changes in sequence. The JMP instruction loads the PC with an address in the 64-Kbyte memory map, and program execution continues at that address. The address can be provided as an absolute 16-bit address or determined by various forms of indexed addressing.

Subroutine instructions optimize the process of transferring control to a code segment that performs a particular task. A short branch (BSR), a jump (JSR), or an expandedmemory call (CALL) can be used to initiate subroutines. There is no LBSR instruction, but a PC-relative JSR performs the same function. A return address is stacked, then execution begins at the subroutine address. Subroutines in the normal 64-Kbyte address space are terminated with an RTS instruction. RTS unstacks the return address so that execution resumes with the instruction after BSR or JSR.

The CALL instruction is intended for use with expanded memory. CALL stacks the value in the PPAGE register and the return address, then writes a new value to PPAGE to select the memory page where the subroutine resides. The page value is an immediate operand in all addressing modes except indexed indirect modes; in these modes, an operand points to locations in memory where the new page value and subroutine address are stored. The RTC instruction is used to terminate subroutines in expanded memory. RTC unstacks the PPAGE value and the return address so that execution resumes with the next instruction after CALL. For software compatibility, CALL and RTC execute correctly on devices that do not have expanded addressing capability.

Table 5-21 summarizes the jump and subroutine instructions.

Table 5-21 Jump and Subroutine Instructions

Mnemonic Function Operation

⇒ SP

SP – 2

BSR Branch to Subroutine

CALL Call Subroutine in Expanded Memory

JMP Jump Subroutine Address ⇒ PC

JSR Jump to Subroutine

RTC Return from Call

RTS Return from Subroutine

RTN

: RTN

Subroutine address ⇒ PC

RTN

Subroutine address

RTN

Subroutine address ⇒ PC

(SP)

⇒ M

(SP)

⇒ SP

SP – 2

:RTN

⇒ M

(SP)

SP – 1 ⇒ SP

(PPAGE)

Page ⇒ PPAGE

: RTN

: M

⇒ M

⇒ SP

SP – 2

⇒ M

(SP)

⇒ PC

(SP+1)

SP + 2 ⇒ SP

⇒ PPAGE

(SP)

SP + 1

⇒ SP

⇒ PC

(SP+1)

SP + 2 ⇒ SP

: M

(SP)

⇒ PC

: M

(SP+1)

: PC

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5.21 Interrupt Instructions

Interrupt instructions handle transfer of control to a routine that performs a critical task. Software interrupts are a type of exception. SECTION 7 EXCEPTION PROCESSING covers interrupt exception processing in detail.

The SWI instruction initiates synchronous exception processing. First, the return PC value is stacked. After CPU context is stacked, execution continues at the address pointed to by the SWI vector.

Execution of the SWI instruction causes an interrupt without an interrupt service request. SWI is not inhibited by global mask bits I and X in the CCR, and execution of SWI sets the I mask bit. Once an SWI interrupt begins, maskable interrupts are inhibited until the I bit in the CCR is cleared. This typically occurs when an RTI instruction at the end of the SWI service routine restores context.

The CPU12 uses the software interrupt for unimplemented opcode trapping. There are opcodes in all 256 positions in the page 1 opcode map, but only 54 of the 256 positions on page 2 of the opcode map are used. If the CPU attempts to execute one of the unimplemented opcodes on page 2, an opcode trap interrupt occurs. Traps are essentially interrupts that share the $FFF8:$FFF9 interrupt vector.

The RTI instruction is used to terminate all exception handlers, including interrupt service routines. RTI first restores the CCR, B:A, X, Y, and the return address from the stack. If no other interrupt is pending, normal execution resumes with the instruction following the last instruction that executed prior to interrupt.

Table 5-22 is a summary of interrupt instructions.

Table 5-22 Interrupt Instructions

Mnemonic Function Operation

) ⇒ CCR; (SP) + $0001 ⇒ SP

(SP)

RTI Return from Interrupt

SWI Software Interrupt

TRAP Software Interrupt

: M

(SP)

: M

(SP)

: M

(SP)

: M

(SP)

SP – 2 ⇒ SP; RTNH: RTN

SP – 2 ⇒ SP; YH: Y SP – 2 ⇒ SP; XH: X

SP – 2 ⇒ SP; B : A ⇒ M

SP – 2 ⇒ SP; RTNH: RTN

SP – 2 ⇒ SP; YH: Y SP – 2 ⇒ SP; XH: X

SP – 2 ⇒ SP; B : A ⇒ M

) ⇒ B : A; (SP) + $0002 ⇒ SP

(SP+1)

) ⇒ XH: XL; (SP) + $0004 ⇒ SP

(SP+1)

) ⇒ PCH: PCL; (SP) + $0002 ⇒ SP

(SP+1)

) ⇒ YH: YL; (SP) + $0004 ⇒ SP

(SP+1)

⇒ M

SP – 1 ⇒ SP; CCR ⇒ M

⇒ M

SP – 1 ⇒ SP; CCR ⇒ M

⇒ M

(SP) (SP)

(SP)

(SP) (SP)

(SP)

: M : M

: M

(SP) (SP)

: M : M

: M

(SP)

: M

(SP+1) (SP+1)

(SP+1)

: M

(SP+1) (SP+1)

(SP+1)

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5.22 Index Manipulation Instructions

These instructions perform 8- and 16-bit operations on the three index registers and accumulators, other registers, or memory, as shown in Table 5-23.

Table 5-23 Index Manipulation Instructions

Addition Instructions

Mnemonic Function Operation

ABX Add B to X (B) + (X) ⇒ X ABY Add B to Y (B) + (Y) ⇒ Y

Compare Instructions

Mnemonic Function Operation

CPS Compare SP to Memory (SP) – (M : M + 1) CPX Compare X to Memory (X) – (M : M + 1) CPY Compare Y to Memory (Y) – (M : M + 1)

Load Instructions

Mnemonic Function Operation

LDS Load SP from Memory M : M+1 LDX Load X from Memory (M : M + 1) ⇒ X

LDY Load Y from Memory (M : M + 1) ⇒ Y LEAS Load Effective Address into SP Effective Address ⇒ SP LEAX Load Effective Address into X Effective Address ⇒ X LEAY Load Effective Address into Y Effective Address ⇒ Y

Store Instructions

Mnemonic Function Operation

STS Store SP in Memory (SP)

STX Store X in Memory (X) ⇒ M : M + 1

STY Store Y in Memory (Y) ⇒ M : M + 1

Transfer Instructions

Mnemonic Function Operation

TFR Transfer Register to Register (A, B, CCR, D, X, Y, or SP) ⇒ A, B, CCR, D, X, Y, or SP

TSX Transfer SP to X (SP) ⇒ X

TSY Transfer SP to Y (SP) ⇒ Y

TXS Transfer X to SP (X) ⇒ SP

TYS Transfer Y to SP (Y) ⇒ SP

Exchange Instructions

Mnemonic Function Operation

EXG Exchange Register to Register (A, B, CCR, D, X, Y, or SP) ⇔ (A, B, CCR, D, X, Y, or SP)

XGDX EXchange D with X (D) ⇔ (X) XGDY EXchange D with Y (D) ⇔ (Y)

⇒ SP

⇒ M:M+1

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5.23 Stacking Instructions

There are two types of stacking instructions, as shown in Table 5-24. Stack pointer instructions use specialized forms of mathematical and data transfer instructions to perform stack pointer manipulation. Stack operation instructions save information on and retrieve information from the system stack.

Table 5-24 Stacking Instructions

Stack Pointer Instructions

Mnemonic Function Operation

CPS Compare SP to Memory (SP) – (M : M + 1) DES Decrement SP (SP) – 1 ⇒ SP

INS Increment SP (SP) + 1 ⇒ SP

LDS Load SP (M : M + 1) ⇒ SP

LEAS Load Effective Address into SP Effective Address ⇒ SP

STS Store SP (SP) ⇒ M : M + 1 TSX Transfer SP to X (SP) ⇒ X TSY Transfer SP to Y (SP) ⇒ Y TXS Transfer X to SP (X) ⇒ SP TYS Transfer Y to SP (Y) ⇒ SP

Stack Operation Instructions

Mnemonic Function Operation

PSHA Push A (SP) – 1 ⇒ SP; (A) ⇒ M PSHB Push B (SP) – 1 ⇒ SP; (B) ⇒ M PSHC Push CCR (SP) – 1 ⇒ SP; (A) ⇒ M PSHD Push D (SP) – 2 ⇒ SP; (A : B) ⇒ M PSHX Push X (SP) – 2 ⇒ SP; (X) ⇒ M PSHY Push Y (SP) – 2 ⇒ SP; (Y) ⇒ M PULA Pull A (M PULB Pull B (M PULC Pull CCR (M PULD Pull D (M

(SP)

PULX Pull X (M PULY Pull Y (M

) ⇒ A; (SP) + 1 ⇒ SP

(SP)

) ⇒ B; (SP) + 1 ⇒ SP

(SP)

) ⇒ CCR; (SP) + 1 ⇒ SP

(SP)

: M

(SP) (SP)

) ⇒ A : B; (SP) + 2 ⇒ SP

(SP+1)

: M : M

) ⇒ X; (SP) + 2 ⇒ SP

(SP+1)

) ⇒ Y; (SP) + 2 ⇒ SP

(SP+1)

(SP) (SP)

(SP)

(SP) (SP) (SP)

: M : M

: M

(SP+1) (SP+1)

(SP+1)

5.24 Pointer and Index Calculation Instructions

The load effective address instructions allow 5-, 8-, or 16-bit constants, or the contents of 8-bit accumulators A and B or 16-bit accumulator D to be added to the contents of the X and Y index registers, the SP, or the PC. Table 5-25 is a summary of pointer and index instructions.

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Table 5-25 Pointer and Index Calculation Instructions

Mnemonic Function Operation

r ± Constant ⇒ SP or

(r) + (Accumulator) ⇒ SP

r = X, Y, SP, or PC r ± Constant ⇒X or

(r) + (Accumulator) ⇒X

r = X, Y, SP, or PC r ± Constant ⇒Y or

(r) + (Accumulator) ⇒ Y

r = X, Y, SP, or PC

LEAS

LEAX

LEAY

Load Result of Indexed Addressing Mode

Effective Address Calculation

into Stack Pointer

Load Result of Indexed Addressing Mode

Effective Address Calculation

into X Index Register

Load Result of Indexed Addressing Mode

Effective Address Calculation

into Y Index Register

5.25 Condition Code Instructions

Condition code instructions are special forms of mathematical and data transfer instructions that can be used to change the condition code register. Table 5-26 shows instructions that can be used to manipulate the CCR.

Table 5-26 Condition Codes Instructions

Mnemonic Function Operation

ANDCC Logical AND CCR with Memory (CCR) • (M) ⇒ CCR

CLC Clear C Bit 0 ⇒ C

CLI Clear I Bit 0 ⇒ I

CLV Clear V Bit 0 ⇒ V

ORCC Logical OR CCR with Memory (CCR) + (M)

PSHC Push CCR onto Stack (SP) – 1 ⇒ SP; (CCR) ⇒ M PULC Pull CCR from Stack (M

SEC Set C Bit 1 ⇒ C

SEI Set I Bit 1 ⇒ I SEV Set V Bit 1 ⇒ V TAP Transfer A to CCR (A) ⇒ CCR TPA Transfer CCR to A (CCR) ⇒ A

) ⇒ CCR; (SP) + 1 ⇒ SP

(SP)

⇒ CCR

(SP)

5.26 Stop and Wait Instructions

As shown in Table 5-27, there are two instructions that put the CPU12 in an inactive state that reduces power consumption.

The stop instruction (STOP) stacks a return address and the contents of CPU registers and accumulators, then halts all system clocks.

The wait instruction (WAI) stacks a return address and the contents of CPU registers and accumulators, then waits for an interrupt service request; however, system clock signals continue to run.

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Both STOP and WAI require that either an interrupt or a reset exception occur before normal execution of instructions resumes. Although both instructions require the same number of clock cycles to resume normal program execution after an interrupt service request is made, restarting after a STOP requires extra time for the oscillator to reach operating speed.

Table 5-27 Stop and Wait Instructions

Mnemonic Function Operation

STOP Stop

WAI Wait for Interrupt

⇒ SP; RTN

SP – 2

SP – 2 ⇒ SP; YH: Y SP – 2 ⇒ SP; XH: X

SP – 2 ⇒ SP; B : A ⇒ M

SP – 1 ⇒ SP; CCR ⇒ M

STOP CPU Clocks

SP – 2

⇒ SP; RTN

SP – 2 ⇒ SP; YH: Y SP – 2 ⇒ SP; XH: X

SP – 2 ⇒ SP; B : A ⇒ M

SP – 1 ⇒ SP; CCR ⇒ M

: RTN

L L

⇒ M ⇒ M

⇒ M

(SP) (SP)

(SP)

⇒ M

(SP) (SP)

(SP)

: M : M

: M

(SP)

: M : M

: M

(SP)

5.27 Background Mode and Null Operations

: M

(SP+1) (SP+1)

(SP+1)

: M

(SP+1) (SP+1)

(SP+1)

Background debug mode is a special CPU12 operating mode that is used for system development and debugging. Executing BGND when BDM is enabled puts the CPU12 in this mode. For complete information refer to SECTION 8 DEVELOPMENT AND

DEBUG SUPPORT.

Nulloperations are often used to replace otherinstructions during software debugging. Replacing conditional branch instructions with BRN, for instance, permits testing a decision-making routine without actually taking the branches.

Table 5-28 shows the BGND and NOP instructions.

Table 5-28 Background Mode and Null Operation Instructions

Mnemonic Function Operation

BGND Enter Background Debug Mode

BRN Branch Never Does not branch

LBRN Long Branch Never Does not branch

NOP Null operation —

If BDM enabled, enter BDM;

else, resume normal processing

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SECTION 6

INSTRUCTION GLOSSARY

This section is a comprehensive reference to the CPU12 instruction set.

6.1 Glossary Information

The glossary contains an entry for each assembler mnemonic, in alphabetic order.

Figure 6-1 is a representation of a glossary page.

MNEMONIC

SYMBOLIC DESCRIPTION

OF OPERATION

DETAILED DESCRIPTION

OF OPERATION

EFFECT ON

CONDITION CODE REGISTER

STATUS BITS

DETAILED SYNTAX

AND

CYCLE-BY-CYCLE

OPERATION

LDX

Operation: (M: M+1)

Load Inde

⇒

Description: Loads the mostsignifica

memory at the addres

C onditi on Code s and Bool e an For m

SX H

——

N: Set if MSB of resu

Set if resultis $00

V: 0; Cleared.

∆

Addressing Modes, Machine Code, an

Source Form

LDX

#opr16i

LDX

opr8a

LDX

opr16a

LDX

oprx0_xysp

LDX

oprx9,xysp

LDX

oprx16,xysp

LDX

[D,xysp]

LDX

[oprx16,xysp]

Address Mode

IMM

DIR

EXT

IDX IDX1 IDX2

[D,IDX]

[IDX2]

Obje

CE jj DE d

FE h EE

E E

EX GLO PG

Figure 6-1 Example Glossary Page

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Page 62

Each entry contains symbolic and textual descriptions of operation, information concerning the effect of operation on status bits in the condition code register, and a table that describes assembler syntax, cycle count, and cycle-by-cycle execution of the instruction.

6.2 Condition Code Changes

The following special characters are used to describe the effects of instruction execution on the status bits in the condition codes register.

– — Status bit not affected by operation. 0 — Status bit cleared by operation. 1 — Status bit set by operation.

∆ — Status bit affected by operation.

⇓ — Status bit may be cleared or remain set, but is not set by operation. ⇑ — Status bit may be set or remain cleared, but is not cleared by operation.

? — Status bit may be changed by operation but the final state is not defined.

! — Status bit used for a special purpose.

6.3 Object Code Notation

The digits 0 to 9 and the upper case letters A to F are used to express hexadecimal values. Pairs of lower case letters represent the 8-bit values as described below.

dd — 8-bit direct address $0000 to $00FF. (High byte assumed to be $00). ee — High-order byte of a 16-bit constant offset for indexed addressing. eb — Exchange/Transfer post-byte.

ff — Low-order eight bits of a 9-bit signed constant offset for indexed addressing, or

low-order byte of a 16-bit constant offset for indexed addressing.

hh — High-order byte of a 16-bit extended address.

ii — 8-bit immediate data value. jj — High-order byte of a 16-bit immediate data value.

kk — Low-order byte of a 16-bit immediate data value.

lb — Loop primitive (DBNE) post-byte.

ll — Low-order byte of a 16-bit extended address.

mm — 8-bit immediate mask value for bit manipulation instructions.

Set bits indicate bits to be affected. pg — Program overlay page (bank) number used in CALL instruction. qq — High-order byte of a 16-bit relative offset for long branches.

tn — Trap number $30–$39 or $40–$FF.

rr — Signed relative offset $80 (–128) to $7F (+127).

Offset relative to the byte following the relative offset byte, or

low-order byte of a 16-bit relative offset for long branches. xb — Indexed addressing post-byte.

MOTOROLA INSTRUCTION GLOSSARY CPU12 6-2 REFERENCE MANUAL

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6.4 Source Forms

The glossary pages provide only essential information about assembler source forms. Assemblers generally support a number of assembler directives, allow definition of program labels, and have special conventions for comments. For complete information about writing source files for a particular assembler, refer to the documentation provided by the assembler vendor.

Assemblers are typically very flexible about the use of spaces and tabs. Often, any number of spaces or tabs can be used where a single space is shown on the glossary pages. Spaces and tabs are also normally allowed before and after commas. When program labels are used, there must also be at least one tab or space before all instruction mnemonics. This required space is not apparent in the source forms.

Everything in the source forms columns,

except expressions in italic characters

, is literal information which must appear in the assembly source file exactly as shown. The initial 3- to 5-letter mnemonic is always a literal expression. All commas, pound signs (#), parentheses, square brackets ( [ or ] ), plus signs (+), minus signs (–), and the register designation D (as in [D,... ), are literal characters.

Groups of italic characters in the columns represent variable information to be supplied by the programmer. These groups can include any alphanumeric character orthe underscore character, but cannot include a space or comma. For example, the groups

xysp

and

oprx0_xysp

are both valid, but the two groups

oprx0 xysp

are not valid be-

cause there is a space between them. Permitted syntax is described below. The definition of a legal label or expression varies from assembler to assembler. As-

semblers also vary in the way CPU registers are specified. Refer to assembler documentation for detailed information. Recommended register designators are a, A, b, B, ccr, CCR, d, D, x, X, y, Y, sp, SP, pc, and PC.

abc

— Any one legal register designator for accumulators A or B or the CCR.

abcdxys

abdxys

opr16i

opr8a

— Any one legal register designator for accumulators A or B, the CCR, the double

accumulator D, index registers X or Y, or the SP. Some assemblers may accept t2, T2, t3, or T3 codes in certain cases of transfer and exchange instructions, but these forms are intended for Motorola use only.

abd

— Any one legal register designator for accumulators A or B or the double accumu-

lator D.

— Any one legal register designator for accumulators A or B,the double accumulator

D, index register X or Y, or the SP.

dxys

— Any one legal register designation for the double accumulator D, index registers X

or Y, or the SP.

msk8

— Any label or expression that evaluates to an 8-bit value. Some assemblers require

a # symbol before this value.

opr8i

— Any label or expression that evaluates to an 8-bit immediate value. — Any label or expression that evaluates to a 16-bit immediate value. — Any label or expression that evaluates to an 8-bit value. The instruction treats this

8-bit value as the low order 8-bits of an address in the direct page of the 64-Kbyte address space ($00xx).

CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-3

Page 64

opr16a

oprx0_xysp

oprx3 oprx5 oprx9

oprx16

page

rel8

rel9

rel16

trapnum

xys

xysp

— Any label or expression that evaluates to a 16-bit value. The instruction treats this

value as an address in the 64-Kbyte address space.

— This word breaks down into one of the following alternative forms that assemble

to an 8-bit indexed addressing postbyte code. These forms generate the same object code except for the value of the postbyte code, which is designated as xb in the object code columns of the glossary pages. As with the source forms, treat all commas, plus signs, and minus signs as literal syntax elements. The italicized words used in these forms are included in this key.

oprx5,xysp oprx3,–xys oprx3,+xys oprx3,xys oprx3,xys

–

abd,xysp

— Any label or expression that evaluates to a value in the range +1 to +8. — Any label or expression that evaluates to a 5-bit value in the range –16 to +15. — Any label or expression that evaluates to a 9-bit value in the range –256 to +255. — Any label or expression that evaluates to a 16-bit value. Since the CPU12 has a

16-bit address bus, this can be either a signed or an unsigned value.

— Any label or expression that evaluates to an 8-bit value. The CPU12 recognizes

up to an 8-bit page value for memory expansion but not all MCUs that include the CPU12 implement all of these bits. It is the programmer’s responsibility to limit the page value to legal values for the intended MCU system. Some assemblers require a # symbol before this value.

— Any label or expression that refers to an address that is within –256 to +255 loca-

tions from the next address after the last byte of object code for the current instruction. The assembler will calculate the 8-bit signed offset and include it in the object code for this instruction.

— Any label or expression that refers to an address that is within –512 to +511 loca-

tions from the next address after the last byte of object code for the current instruction. The assembler will calculate the 9-bit signed offset and include it in the object code for this instruction. The sign bit for this 9-bit value is encoded by the assembler as a bit in the looping postbyte (lb) of one of the loop control instructions DBEQ, DBNE, IBEQ, IBNE, TBEQ, or TBNE. The remainingeight bits of the offset are included as an extra byte of object code.

— Any label or expression that refers to an address anywhere in the 64-Kbyte ad-

dress space. The assembler willcalculate the 16-bit signed offset between this address and the next address after the last byte of object code for this instruction, and include it in the object code for this instruction.

— Any label or expression that evaluates to an 8-bit number in the range $30–$39 or

$40–$FF. Used for TRAP instruction. — Any one legal register designation for index registers X or Y or the SP. — Any one legal register designation for index registers X or Y, the SP, or the PC.

The reference point for PC relative instructions is the next address after the last

byte of object code for the current instruction.

MOTOROLA INSTRUCTION GLOSSARY CPU12 6-4 REFERENCE MANUAL

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6.5 Cycle-by-Cycle Execution

This information is found in the tables at the bottom of each instruction glossary page. Entries show how many bytes of information are accessed from different areas of memory during the course of instruction execution. With this information and knowledge of the type and speed of memory in the system, a user can determine the execution time for any instruction in any system.

A single letter code in the column represents a single CPU cycle. Upper case letters indicate 16-bit access cycles. There are cycle codes for each addressing mode variation of each instruction. Simply count code letters to determine the execution time of an instruction in a best-case system. An example of a best-case system is a singlechip 16-bit system with no 16-bit off-boundary data accesses to any locations other than on-chip RAM.

Many conditions can cause one or more instruction cycles to be stretched, but the CPU is not aware of the stretch delays because the clock to the CPU is temporarily stopped during these delays.

The following paragraphs explain the cycle code letters used and note conditions that can cause each type of cycle to be stretched.

f — Free cycle. This indicates a cycle where the CPU does not require use of the

system buses. An f cycle is always one cycle of the system bus clock. These

cycles can be used by a queue controller or the background debug system to

perform single cycle accesses without disturbing the CPU.

g — Read 8-bit PPAGE register. These cycles are only used with the CALL instruc-

tion to read the current value of the PPAGE register, and are not visible on the

external bus. Since the PPAGE register is an internal 8-bitregister, these cycles

are never stretched.

I — Read indirect pointer. Indexed indirect instructions use this 16-bit pointer from

memory to address the operand for the instruction. These are always 16-bit

reads but they can be either aligned or misaligned. These cycles are extended

to two bus cycles if the MCU is operating with an 8-bit external data bus and the

corresponding data is stored in external memory. There can be additional

stretching when the address space is assigned to a chip-select circuit pro-

grammed for slow memory. These cycles are also stretched if they correspond

to misaligned access to a memory that is not designed for single-cycle mis-

aligned access.

i — Read indirect PPAGE value. These cycles are only used with indexed indirect

versions of the CALL instruction, where the 8-bit value for the memory expan-

sion page register of the CALL destination is fetched from an indirect memory

location.These cycles arestretched only whencontrolled by a chip-selectcircuit

that is programmed for slow memory.

n — Write8-bit PPAGE register. These cycles are only used with the CALL andRTC

instructions to write the destination value of the PPAGE register and are not vis-

ible on the external bus. Since the PPAGE register is an internal 8-bit register,

these cycles are never stretched.

CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-5

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O — Optional cycle. Program information is always fetched as aligned 16-bit words.

When aninstruction consists of an odd number of bytes, and thefirst byte is mis-

aligned,an O cycleis used tomake an additionalprogram word access (P) cycle

that maintains queue order. In all other cases, the O cycle appears as a free (f)

cycle. The $18 prebyte for page two opcodes is treated as a special one-byte

instruction. If the prebyte is misaligned, the O cycle is used as a program word

access for the prebyte; if the prebyte is aligned, the O cycle appears as a free

cycle. If the remainder of the instruction consists of an odd number of bytes, an-

other O cycle is required some time before the instruction is completed. If the O

cyclefor the prebyte is treatedas a P cycle,any subsequent O cycle inthe same

instruction is treated as an f cycle; if the O cycle for the prebyte is treated as an

f cycle, any subsequent O cycle in the same instruction is treated as a P cycle.

Optional cycles used for program word accesses can be extended to two bus

cycles if the MCU is operating with an 8-bit external data bus and the program

is stored in external memory. There can be additional stretching when the ad-

dress space is assigned to a chip-select circuit programmed for slow memory.

Optional cycles used as free cycles are never stretched.

P — Program word access. Program information is fetched as aligned 16-bit words.

These cycles are extended to two bus cycles if the MCU is operating with an 8-

bit external data bus and the program is stored externally. There can be addi-

tional stretching when the address space is assigned to a chip-select circuit pro-

grammed for slow memory.

r — 8-bitdataread. These cyclesare stretched onlywhen controlled bya chip-select

circuit programmed for slow memory.

R — 16-bit data read. These cycles are extended to two bus cycles if the MCU is op-

erating with an 8-bit external data bus and the corresponding data is stored in

external memory. There can be additional stretching when the address space is

assigned to a chip-select circuit programmed for slow memory. These cycles

are also stretched if they correspond to misaligned accesses to memory that is

not designed for single-cycle misaligned access.

s — Stack 8-bit data. These cycles are stretched only when controlled by a chip-se-

lect circuit programmed for slow memory.

S — Stack 16-bit data. These cycles are extended to two bus cycles if the MCU is

operating with an 8-bit external data bus and the SP is pointing to external mem-

ory. There can be additional stretching if the address space is assigned to a

chip-select circuit programmed for slow memory. These cycles are also

stretched if they correspond to misaligned accesses to a memory that is not de-

signed for single cycle misaligned access. The internal RAM is designed to al-

low single cycle misaligned word access.

w — 8-bit data write. These cycles are stretched only when controlled by a chip-se-

lect circuit programmed for slow memory.

W — 16-bit data write. These cycles are extended to two bus cycles if the MCU is op-

erating with an 8-bit external data bus and the corresponding data is stored in

external memory. There can be additional stretching when the address space is

assigned to a chip-select circuit programmed for slow memory. These cycles

are also stretched if they correspond to misaligned access to a memory that is

not designed for single-cycle misaligned access.

u — Unstack 8-bit data. These cycles are stretched only when controlled by a chip-

select circuit programmed for slow memory.

MOTOROLA INSTRUCTION GLOSSARY CPU12 6-6 REFERENCE MANUAL

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U — Unstack16-bit data. These cycles are extended to two bus cycles if the MCU is

operating with an 8-bit external data bus and the SP is pointing to external mem-

ory. There can be additional stretching when the address space is assigned to

a chip-select circuit programmed for slow memory. These cycles are also

stretched if they correspond to misaligned accesses to a memory that is not de-

signed for single-cycle misaligned access. The internal RAM is designed to al-

low single-cycle misaligned word access.

V — Vectorfetch. Vectors are always aligned 16-bit words. These cycles are extend-

ed to two bus cycles if the MCU is operating with an 8-bit external data bus and

the program is stored in external memory. There can be additional stretching

when the address space is assigned to a chip-select circuit programmed for

slow memory.

t — 8-bit conditional read. These cycles are either data read cycles or free cycles,

depending upon the data and flow of the REVW instruction. These cycles are

only stretched when controlled by a chip-select circuit programmed for slow

memory.

T — 16-bit conditional read. These cycles are either data read cycles or free cycles,

depending upon the data and flow of the REV or REVW instruction. These cy-

clesare extended to twobus cycles ifthe MCU is operatingwith an 8-bitexternal

data bus and the corresponding data is stored in external memory. There can

be additional stretching when the address space is assigned to a chip-select cir-

cuit programmed for slow memory. These cycles are also stretched if they cor-

respond to misaligned accesses to a memory that is not designed for single-

cycle misaligned access.

x — 8-bit conditional write. These cycles are either data write cycles or free cycles,

depending upon the data and flow of the REV or REVW instruction. These cy-

cles are only stretched when controlled by a chip-select circuit programmed for

slow memory.

Special Notation for Branch Taken/Not Taken Cases

PPP/P — Short branches require three cycles if taken, one cycle if not taken. Since the

instruction consists of a single word containing both an opcode and an 8-bit off-

set, the not-taken case is simple — the queue advances, another program word

fetchis made, and execution continues withthe next instruction. The taken case

requires that the queue be refilled so that execution can continue at a new ad-

dress.First, the effective addressof the destination is determined,then the CPU

performs three program word fetches from that address.

OPPP/OPO — Longbranches require four cycles if taken, three cycles if not taken. Optional cy-

cles are required because all long branches are page two opcodes, and thus

include the $18 prebyte. The CPU12 treats the prebyte as a special 1-byte in-

struction. Ifthe prebyte is misaligned, the optional cycle is usedto perform a pro-

gramword access; if the prebyte is aligned,the optional cycle is used to perform

a free cycle. As a result, both the taken and not-taken cases use one optional

cycle for the prebyte. In the not-taken case, the queue must advance so that ex-

ecution can continue with the next instruction, and another optional cycle is re-

quired to maintain the queue. The taken case requires that the queue be refilled

so that execution can continue at a new address. First, the effective address of

the destination is determined, then the CPU performs three program word fetch-

es from that address.

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Page 68

6.6 Glossary

Add Accumulator B To

ABA

Operation: (A) + (B) ⇒ A Description: Adds the content of accumulator B to the content of accumulator A and

places the result in A. The content of B is not changed. This instruction affects the H status bit so it is suitable for use in BCD arithmetic operations (see DAA instruction for additional information).

Condition Codes and Boolean Formulas:

SXHI NZVC

––∆ – ∆∆∆∆

H: A3 • B3 + B3 • R3 + R3 • A3

Set if there was a carry from bit 3; cleared otherwise. N: Set if MSB of result is set; cleared otherwise. Z: Set if result is $00; cleared otherwise. V: A7 • B7 • R7 + A7 • B7 • R7

Set if a two’s complement overﬂow resulted from the operation;

cleared otherwise. C: A7 • B7 + B7 • R7 + R7 • A7

Set if there was a carry from the MSB of the result; cleared otherwise.

Accumulator A

ABA

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

ABA INH 18 06 2 OO

MOTOROLA INSTRUCTION GLOSSARY CPU12 6-8 REFERENCE MANUAL

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Add Accumulator B to

ABX

Operation: (B) + (X) ⇒ X Description: Adds the 8-bit unsigned content of accumulator B to the content of index

register X considering the possible carry out of the low-order byte of X; places the result in X. The content of B is not changed.

This mnemonic is implemented by the LEAX B,X instruction. The LEAX instruction allows A, B, D, or a constant to be added to X. For compatibility with the M68HC11, the mnemonic ABX is translated into the LEAX B,X instruction by the assembler.

Condition Codes and Boolean Formulas:

SXHI NZVC

––––––––

None affected.

Addressing Modes, Machine Code, and Execution Times:

Index Register X

ABX

Source Form Address Mode Object Code Cycles Access Detail

ABX

translates to...

LEAX B,X Notes:

1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction.

IDX 1A E5 2 PP

CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-9

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Add Accumulator B to

ABY

Operation: (B) + (Y) ⇒ Y Description: Adds the 8-bit unsigned content of accumulator B to the content of index

register Y considering the possible carry out of the low-order byte of Y; places the result in Y. The content of B is not changed.

This mnemonic is implemented by the LEAY B,Y instruction. The LEAY instruction allows A, B, D, or a constant to be added to Y. For compatibility with the M68HC11, the mnemonic ABY is translated into the LEAY B,Y instruction by the assembler.

Condition Codes and Boolean Formulas:

SXHI NZVC

––––––––

None affected.

Addressing Modes, Machine Code, and Execution Times:

Index Register Y

ABY

Source Form Address Mode Object Code Cycles Access Detail

ABY

translates to...

LEAY B,Y Notes:

1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction.

IDX 19 ED 2 PP

MOTOROLA INSTRUCTION GLOSSARY CPU12 6-10 REFERENCE MANUAL

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ADCA

Add with Carry to A

ADCA

Operation: (A) + (M) + C ⇒ A Description: Adds the content of accumulator A to the content of memory location M,

then adds the value of the C bit and places the result in A. This instruction affects the H status bit, so it is suitable for use in BCD arithmetic operations (see DAA instruction for additional information).

Condition Codes and Boolean Formulas:

SXHI NZVC

––∆ – ∆∆∆∆

H: X3 • M3 + M3 • R3 + R3 • X3

Set if there was a carry from bit 3; cleared otherwise. N: Set if MSB of result is set; cleared otherwise. Z: Set if result is $00; cleared otherwise. V: X7 • M7 • R7 + X7 • M7 • R7

Setif two’scomplement overflowresulted fromthe operation; cleared

otherwise. C: X7 • M7 + M7 • R7 + R7 • X7

Set if there was a carry from the MSB of the result; cleared otherwise.

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

ADCA # ADCA

opr8a

ADCA

opr16a

ADCA

oprx0_xysp

ADCA

oprx9,xysp

ADCA

oprx16,xysp

ADCA [D ADCA [

opr8i

,xysp

]

oprx16,xysp

IMM

DIR

EXT

IDX IDX1 IDX2

[D,IDX]

]

[IDX2]

89 ii 99 dd B9 hh ll A9 xb A9 xb ff A9 xb ee ff A9 xb A9 xb ee ff

1 3 3 3 3 4 6 6

P rfP rOP rfP rPO frPP fIfrfP fIPrfP

CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-11

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ADCB

Add with Carry to B

ADCB

Operation: (B) + (M) + C ⇒ B Description: Adds the content of accumulator B to the content of memory location M,

then adds the value of the C bit and places the result in B. This instruction affects the H status bit, so it is suitable for use in BCD arithmetic operations (see DAA instruction for additional information).

Condition Codes and Boolean Formulas:

SXHI NZVC

––∆ – ∆∆∆∆

H: X3 • M3 + M3 • R3 + R3 • X3

Set if there was a carry from bit 3; cleared otherwise. N: Set if MSB of result is set; cleared otherwise. Z: Set if result is $00; cleared otherwise. V: X7 • M7 • R7 + X7 • M7 • R7

Setif two’scomplement overflowresulted fromthe operation; cleared

otherwise. C: X7 • M7 + M7 • R7 + R7 • X7

Set if there was a carry from the MSB of the result; cleared otherwise.

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

ADCB # ADCB

opr8a

ADCB

opr16a

ADCB

oprx0_xysp

ADCB

oprx9,xysp

ADCB

oprx16,xysp

ADCB [D ADCB [

opr8i

,xysp

]

oprx16,xysp

IMM

DIR

EXT

IDX IDX1 IDX2

[D,IDX]

]

[IDX2]

C9 ii D9 dd F9 hh ll E9 xb E9 xb ff E9 xb ee ff E9 xb E9 xb ee ff

1 3 3 3 3 4 6 6

P rfP rOP rfP rPO frPP fIfrfP fIPrfP

MOTOROLA INSTRUCTION GLOSSARY CPU12 6-12 REFERENCE MANUAL

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ADDA

Add without Carry to A

ADDA

Operation: (A) + (M) ⇒ A Description: Adds the content of memory location M to accumulator A and places the

result in A. This instruction affects the H status bit, so it is suitable for use in BCD arithmetic operations (see DAA instruction for additional information).

Condition Codes and Boolean Formulas:

SXHI NZVC

––∆ – ∆∆∆∆

H: X3 • M3 + M3 • R3 + R3 • X3

Set if there was a carry from bit 3; cleared otherwise. N: Set if MSB of result is set; cleared otherwise. Z: Set if result is $00; cleared otherwise. V: X7 • M7 • R7 + X7 • M7 • R7

Setif two’scomplement overflowresulted fromthe operation; cleared

otherwise. C: X7 • M7 + M7 • R7 + R7 • X7

Set if there was a carry from the MSB of the result; cleared otherwise.

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

ADDA # ADDA

opr8a

ADDA

opr16a

ADDA

oprx0_xysp

ADDA

oprx9,xysp

ADDA

oprx16,xysp

ADDA [D ADDA [

opr8i

,xysp

]

oprx16,xysp

IMM

DIR

EXT

IDX IDX1 IDX2

[D,IDX]

]

[IDX2]

8B ii 9B dd BB hh ll AB xb AB xb ff AB xb ee ff AB xb AB xb ee ff

1 3 3 3 3 4 6 6

P rfP rOP rfP rPO frPP fIfrfP fIPrfP

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ADDB

Add without Carry to B

ADDB

Operation: (B) + (M) ⇒ B Description: Adds the content of memory location M to accumulator B and places the

result in B. This instruction affects the H status bit, so it is suitable for use in BCD arithmetic operations (see DAA instruction for additional information).

Condition Codes and Boolean Formulas:

SXHI NZVC

––∆ – ∆∆∆∆

H: X3 • M3 + M3 • R3 + R3 • X3

Set if there was a carry from bit 3; cleared otherwise. N: Set if MSB of result is set; cleared otherwise. Z: Set if result is $00; cleared otherwise. V: X7 • M7 • R7 + X7 • M7 • R7

Setif two’scomplement overflowresulted fromthe operation; cleared

otherwise. C: X7 • M7 + M7 • R7 + R7 • X7

Set if there was a carry from the MSB of the result; cleared otherwise.

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

ADDB # ADDB

opr8a

ADDB

opr16a

ADDB

oprx0_xysp

ADDB

oprx9,xysp

ADDB

oprx16,xysp

ADDB [D ADDB [

opr8i

,xysp

]

oprx16,xysp

IMM

DIR

EXT

IDX IDX1 IDX2

[D,IDX]

]

[IDX2]

CB ii DB dd FB hh ll EB xb EB xb ff EB xb ee ff EB xb EB xb ee ff

1 3 3 3 3 4 6 6

P rfP rOP rfP rPO frPP fIfrfP fIPrfP

MOTOROLA INSTRUCTION GLOSSARY CPU12 6-14 REFERENCE MANUAL

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ADDD

Add Double Accumulator

ADDD

Operation: (A : B) + (M : M+1) ⇒ A : B Description: Adds the content of memory location M concatenated with the content of

memory location M +1 to the content of double accumulator D and places the result in D. Accumulator A forms the high-order half of 16-bit double accumulator D; accumulator B forms the low-order half.

Condition Codes and Boolean Formulas:

SXHI NZVC

––––∆∆∆∆

N: Set if MSB of result is set; cleared otherwise. Z: Set if result is $0000; cleared otherwise. V: D15 • M15 • R15 + D15 • M15 • R15

Setif two’scomplement overflowresulted fromthe operation; cleared otherwise.

C: D15 • M15 + M15 • R15 + R15 • D15

Set if there was a carry from the MSB of the result; cleared otherwise.

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

ADDD # ADDD

opr8a

ADDD

opr16a

ADDD

oprx0_xysp

ADDD

oprx9,xysp

ADDD

oprx16,xysp

ADDD [D ADDD [

opr16i

,xysp

]

oprx16,xysp

IMM

DIR

EXT

IDX IDX1 IDX2

[D,IDX]

]

[IDX2]

C3 jj kk D3 dd F3 hh ll E3 xb E3 xb ff E3 xb ee ff E3 xb E3 xb ee ff

2 3 3 3 3 4 6 6

OP RfP ROP RfP RPO fRPP fIfRfP fIPRfP

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ANDA

Logical AND A

ANDA

Operation: (A) • (M) ⇒ A Description: Performs logical AND between the content of memory location M and

the content of accumulator A. The result is placed in A. After the operation is performed, each bit of A is the logical AND of the corresponding bits of M and of A before the operation began.

Condition Codes and Boolean Formulas:

SXHI NZVC

––––∆∆0–

N: Set if MSB of result is set; cleared otherwise. Z: Set if result is $00; cleared otherwise. V: 0; Cleared.

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

ANDA # ANDA

opr8a

ANDA

opr16a

ANDA

oprx0_xysp

ANDA

oprx9,xysp

ANDA

oprx16,xysp

ANDA [D ANDA [

opr8i

,xysp

]

oprx16,xysp

IMM

DIR

EXT

IDX IDX1 IDX2

[D,IDX]

]

[IDX2]

84 ii 94 dd B4 hh ll A4 xb A4 xb ff A4 xb ee ff A4 xb A4 xb ee ff

1 3 3 3 3 4 6 6

P rfP rOP rfP rPO frPP fIfrfP fIPrfP

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ANDB

Logical AND B

ANDB

Operation: (B) • (M) ⇒ B Description: Performs logical AND between the content of memory location M and

the content of accumulator B. The result is placed in B. After the operation is performed, each bit of B is the logical AND of the corresponding bits of M and of B before the operation began.

Condition Codes and Boolean Formulas:

SXHI NZVC

––––∆∆0–

N: Set if MSB of result is set; cleared otherwise. Z: Set if result is $00; cleared otherwise. V: 0; Cleared.

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

ANDB # ANDB

opr8a

ANDB

opr16a

ANDB

oprx0_xysp

ANDB

oprx9,xysp

ANDB

oprx16,xysp

ANDB [D ANDB [

opr8i

,xysp

]

oprx16,xysp

IMM

DIR

EXT

IDX IDX1 IDX2

[D,IDX]

]

[IDX2]

C4 ii D4 dd F4 hh ll E4 xb E4 xb ff E4 xb ee ff E4 xb E4 xb ee ff

1 3 3 3 3 4 6 6

P rfP rOP rfP rPO frPP fIfrfP fIPrfP

CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-17

Page 78

ANDCC

Operation: (CCR) • (Mask) ⇒ CCR Description: Performs bitwise logical AND between the content of a mask operand

and the content of the CCR. The result is placed in the CCR. After the operation is performed, each bit of the CCR is the result of a logical AND with the corresponding bits of the mask. To clear CCR bits, clear the corresponding mask bits. CCR bits that correspond to ones in the mask are not changed by the ANDCC operation.

If the I mask bit is cleared, there is a one cycle delay before the system allows interrupt requests. This prevents interrupts from occurring between instructions in the sequences CLI, WAI and CLI, SEI (CLI is equivalent to ANDCC #$EF).

Condition Codes and Boolean Formulas:

SXHI NZVC

⇓⇓⇓⇓⇓⇓⇓⇓

Logical AND CCR with Mask

ANDCC

Condition code bits are cleared if the corresponding bit was zero before the operation or if the corresponding bit in the mask is zero.

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

ANDCC #

opr8i

IMM 10 ii 1 P

MOTOROLA INSTRUCTION GLOSSARY CPU12 6-18 REFERENCE MANUAL

Page 79

Arithmetic Shift Left Memory

ASL

(same as LSL)

ASL

Operation:

b7 – – – – – – b0 C0

Description: Shifts all bits of memory location M one bit position to the left. Bit 0 is

loaded with a zero. The C status bit is loaded from the most significant bit of M.

Condition Codes and Boolean Formulas:

SXHI NZVC

––––∆∆∆∆

N: Set if MSB of result is set; cleared otherwise. Z: Set if result is $00; cleared otherwise. V: N ⊕ C = [N • C] + [N • C] (for N and C after the shift)

Set if (N is set and C is cleared) or (N is cleared and C is set); cleared otherwise (for values of N and C after the shift).

C: M7

Set if the MSB of M was set before the shift; cleared otherwise.

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

ASL

opr16a

ASL

oprx0_xysp

ASL

oprx9,xysp

ASL

oprx16,xysp

ASL [D ASL [

oprx16,xysp

,xysp

EXT

IDX IDX1 IDX2

]

[D,IDX]

[IDX2]

78 hh ll 68 xb 68 xb ff 68 xb ee ff 68 xb 68 xb ee ff

4 3 4 5 6 6

rOPw rPw rPOw frPPw fIfrPw fIPrPw

CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-19

Page 80

Arithmetic Shift Left A

ASLA

Operation:

Description: Shifts all bits of accumulator A one bit position to the left. Bit 0 is loaded

with a zero. The C status bit is loaded from the most significant bit of A.

Condition Codes and Boolean Formulas:

SXHI NZVC

––––∆∆∆∆

N: Set if MSB of result is set; cleared otherwise. Z: Set if result is $00; cleared otherwise. V: N ⊕ C = [N • C] + [N • C] (for N and C after the shift)

Set if (N is set and C is cleared) or (N is cleared and C is set); cleared otherwise (for values of N and C after the shift).

C: A7

Set if the MSB of A was set before the shift; cleared otherwise.

(same as LSLA)

b7 – – – – – – b0 C0

ASLA

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

ASLA INH 48 1 O

MOTOROLA INSTRUCTION GLOSSARY CPU12 6-20 REFERENCE MANUAL

Page 81

Arithmetic Shift Left B

ASLB

Operation:

Description: Shifts all bits of accumulator B one bit position to the left. Bit 0 is loaded

with a zero. The C status bit is loaded from the most significant bit of B.

Condition Codes and Boolean Formulas:

SXHI NZVC

––––∆∆∆∆

N: Set if MSB of result is set; cleared otherwise. Z: Set if result is $00; cleared otherwise. V: N ⊕ C = [N • C] + [N • C] (for N and C after the shift)

Set if (N is set and C is cleared) or (N is cleared and C is set); cleared otherwise (for values of N and C after the shift).

C: B7

Set if the MSB of B was set before the shift; cleared otherwise.

(same as LSLB)

b7 – – – – – – b0 C0

ASLB

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

ASLB INH 58 1 O

CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-21

Page 82

ASLD

Operation:

Arithmetic Shift Left Double Accumulator

(same as LSLD)

ASLD

Description: Shifts all bits of double accumulator D one bit position to the left. Bit 0 is

loaded with a zero. The C status bit is loaded from the most significant bit of D.

Condition Codes and Boolean Formulas:

SXHI NZVC

––––∆∆∆∆

N: Set if MSB of result is set; cleared otherwise. Z: Set if result is $0000; cleared otherwise. V: N ⊕ C = [N • C] + [N • C] (for N and C after the shift)

C: D15

Addressing Modes, Machine Code, and Execution Times:

b7 – – – – – – b0

Set if (N is set and C is cleared) or (N is cleared and C is set); cleared otherwise (for values of N and C after the shift).

Set if the MSB of D was set before the shift; cleared otherwise.

b7 – – – – – – b0

Source Form Address Mode Object Code Cycles Access Detail

ASLD INH 59 1 O

MOTOROLA INSTRUCTION GLOSSARY CPU12 6-22 REFERENCE MANUAL

Page 83

ASR

Operation:

Arithmetic Shift Right Memory

ASR

b7 – – – – – – b0

Description: Shifts all bits of memory location M one place to the right. Bit 7 is held

constant. Bit 0 is loaded into the C status bit. This operation effectively divides a two’s complement value by two without changing its sign. The carry bit can be used to round the result.

Condition Codes and Boolean Formulas:

SXHI NZVC

––––∆∆∆∆

N: Set if MSB of result is set; cleared otherwise. Z: Set if result is $00; cleared otherwise. V: N ⊕ C = [N • C] + [N • C] (for N and C after the shift)

Set if (N is set and C is cleared) or (N is cleared and C is set); cleared otherwise (for values of N and C after the shift).

C: M0

Set if the LSB of M was set before the shift; cleared otherwise.

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

ASR

opr16a

ASR

oprx0_xysp

ASR

oprx9,xysp

ASR

oprx16,xysp

ASR [D ASR [

CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-23

,xysp

]

oprx16,xysp

]

EXT

IDX IDX1 IDX2

[D,IDX]

[IDX2]

77 hh ll 67 xb 67 xb ff 67 xb ee ff 67 xb 67 xb ee ff

4 3 4 5 6 6

rOPw rPw rPOw frPPw fIfrPw fIPrPw

Page 84

ASRA

Operation:

Arithmetic Shift Right A

ASRA

b7 – – – – – – b0

Description: Shifts all bits of accumulator A one place to the right. Bit 7 is held con-

stant. Bit 0 is loaded into the C status bit. This operation effectively divides a two’s complement value by two without changing its sign. The carry bit can be used to round the result.

Condition Codes and Boolean Formulas:

SXHI NZVC

––––∆∆∆∆

N: Set if MSB of result is set; cleared otherwise. Z: Set if result is $00; cleared otherwise. V: N ⊕ C = [N • C] + [N • C] (for N and C after the shift)

Set if (N is set and C is cleared) or (N is cleared and C is set); cleared otherwise (for values of N and C after the shift).

C: A0

Set if the LSB of A was set before the shift; cleared otherwise.

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

ASRA INH 47 1 O

MOTOROLA INSTRUCTION GLOSSARY CPU12 6-24 REFERENCE MANUAL

Page 85

ASRB

Operation:

Arithmetic Shift Right B

ASRB

b7 – – – – – – b0

Description: Shifts all bits of accumulator B one place to the right. Bit 7 is held con-

stant. Bit 0 is loaded into the C status bit. This operation effectively divides a two’s complement value by two without changing its sign. The carry bit can be used to round the result.

Condition Codes and Boolean Formulas:

SXHI NZVC

––––∆∆∆∆

N: Set if MSB of result is set; cleared otherwise. Z: Set if result is $00; cleared otherwise. V: N ⊕ C = [N • C] + [N • C] (for N and C after the shift)

Set if (N is set and C is cleared) or (N is cleared and C is set); cleared otherwise (for values of N and C after the shift).

C: B0

Set if the LSB of B was set before the shift; cleared otherwise.

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

ASRB INH 57 1 O

CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-25

Page 86

Branch if Carry Cleared

BCC

(Same as BHS)

BCC

Operation: If C = 0, then (PC) + $0002 + Rel ⇒ PC

Simple branch

Description: Tests the C status bit and branches if C = 0.

See 3.7 Relative Addressing Mode for details of branch execution.

Condition Codes and Boolean Formulas:

SXHI NZVC

––––––––

None affected.

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

BCC

rel8

Notes:

1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.

REL 24 rr 3 /1 PPP/P

Branch Complementary Branch

Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment

r>m BGT 2E Z + (N r≥m BGE 2C N r=m BEQ 27 Z = 1 r≠m BNE 26 Signed r≤m BLE 2F Z + (N r<m BLT 2D N r>m BHI 22 C + Z = 0 r≤m BLS 23 Unsigned r≥m BHS/BCC 24 C = 0 r<m BLO/BCS 25 Unsigned r=m BEQ 27 Z = 1 r≠m BNE 26 Unsigned r≤m BLS 23 C + Z = 1 r>m BHI 22 Unsigned r<m BLO/BCS 25 C = 1 r≥m BHS/BCC 24 Unsigned

Carry BCS 25 C = 1 No Carry BCC 24 Simple Negative BMI 2B N = 1 Plus BPL 2A Simple Overflow BVS 29 V = 1 No Overflow BVC 28 Simple

r=0 BEQ 27 Z = 1 r≠0 BNE 26 Simple

Always BRA 20 — Never BRN 21 Unconditional

⊕ V) = 0 r≤m BLE 2F Signed

⊕ V = 0 r<m BLT 2D Signed

⊕ V) = 1 r>m BGT 2E Signed

⊕ V = 1 r≥m BGE 2C Signed

MOTOROLA INSTRUCTION GLOSSARY CPU12 6-26 REFERENCE MANUAL

Page 87

BCLR

Clear Bits in Memory

BCLR

Operation: (M) • (Mask) ⇒ M Description: Clears bits in location M. To clear a bit, set the corresponding bit in the

mask byte. Bits in M that correspond to zeros in the mask byte are not changed. Mask bytes can be located at PC + 2, PC + 3, or PC + 4, depending on addressing mode used.

Condition Codes and Boolean Formulas:

SXHI NZVC

––––∆∆0–

N: Set if MSB of result is set; cleared otherwise. Z: Set if result is $00; cleared otherwise. V: 0; Cleared.

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode

BCLR

opr8a, msk8

BCLR

opr16a, msk8

BCLR

oprx0_xysp, msk8

BCLR

oprx9,xysp, msk8

BCLR

oprx16,xysp, msk8

Notes:

1. Indirect forms of indexed addressing cannot be used with this instruction.

DIR

EXT

IDX IDX1 IDX2

Object Code Cycles Access Detail

4D dd mm 1D hh ll mm 0D xb mm 0D xb ff mm 0D xb ee ff mm

4 4 4 4 6

rPOw rPPw rPOw rPwP frPwOP

CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-27

Page 88

Branch if Carry Set

BCS

(Same as BLO)

BCS

Operation: If C = 1, then (PC) + $0002 + Rel ⇒ PC

Simple branch

Description: Tests the C status bit and branches if C = 1.

See 3.7 Relative Addressing Mode for details of branch execution.

Condition Codes and Boolean Formulas:

SXHI NZVC

––––––––

None affected.

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

BCS

rel8

Notes:

1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.

REL 25 rr 3/1 PPP/P

Branch Complementary Branch

Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment

Carry BCS 25 C = 1 No Carry BCC 24 Simple Negative BMI 2B N = 1 Plus BPL 2A Simple Overflow BVS 29 V = 1 No Overflow BVC 28 Simple

r=0 BEQ 27 Z = 1 r≠0 BNE 26 Simple

Always BRA 20 — Never BRN 21 Unconditional

⊕ V) = 0 r≤m BLE 2F Signed

⊕ V = 0 r<m BLT 2D Signed

⊕ V) = 1 r>m BGT 2E Signed

⊕ V = 1 r≥m BGE 2C Signed

MOTOROLA INSTRUCTION GLOSSARY CPU12 6-28 REFERENCE MANUAL

Page 89

BEQ

Branch if Equal

BEQ

Operation: If Z = 1, then (PC) + $0002 + Rel ⇒ PC

Simple branch

Description: Tests the Z status bit and branches if Z = 1.

See 3.7 Relative Addressing Mode for details of branch execution.

Condition Codes and Boolean Formulas:

SXHI NZVC

––––––––

None affected.

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

BEQ

rel8

Notes:

1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.

REL 27 rr 3/1 PPP/P

Branch Complementary Branch

Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment

Carry BCS 25 C = 1 No Carry BCC 24 Simple Negative BMI 2B N = 1 Plus BPL 2A Simple Overflow BVS 29 V = 1 No Overflow BVC 28 Simple

r=0 BEQ 27 Z = 1 r≠0 BNE 26 Simple

Always BRA 20 — Never BRN 21 Unconditional

⊕ V) = 0 r≤m BLE 2F Signed

⊕ V = 0 r<m BLT 2D Signed

⊕ V) = 1 r>m BGT 2E Signed

⊕ V = 1 r≥m BGE 2C Signed

CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-29

Page 90

BGE

Branch if Greater than or Equal to Zero

BGE

Operation: If N ⊕ V = 0, then (PC) + $0002 + Rel ⇒ PC

For signed two’s complement values if (Accumulator)

≥ (Memory), then branch

Description: If BGE is executed immediately after execution of CBA, CMPA, CMPB,

CMPD, CPX, CPY, SBA, SUBA, SUBB, or SUBD, a branch occurs if and only if the signed two’s complement number in the accumulator is greater than or equal to the signed two’s complement number in memory.

See 3.7 Relative Addressing Mode for details of branch execution.

Condition Codes and Boolean Formulas:

SXHI NZVC

––––––––

None affected.

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

BGE

rel8

Notes:

1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.

Branch Complementary Branch

Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment

Carry BCS 25 C = 1 No Carry BCC 24 Simple Negative BMI 2B N = 1 Plus BPL 2A Simple Overflow BVS 29 V = 1 No Overflow BVC 28 Simple

r=0 BEQ 27 Z = 1 r≠0 BNE 26 Simple

Always BRA 20 — Never BRN 21 Unconditional

REL 2C rr 3/1 PPP/P

⊕ V) = 0 r≤m BLE 2F Signed

⊕ V = 0 r<m BLT 2D Signed

⊕ V) = 1 r>m BGT 2E Signed

⊕ V = 1 r≥m BGE 2C Signed

MOTOROLA INSTRUCTION GLOSSARY CPU12 6-30 REFERENCE MANUAL

Page 91

BGND

Description: BGND operates like a software interrupt, except that no registers are

stacked. First, the current PC value is stored in internal CPU register TMP2. Next, the BDM ROM and background register block become active. The BDM ROM contains a substitute vector, mapped to the address of the software interrupt vector, which points to routines in the BDM ROM that control background operation. The substitute vector is fetched, and execution continues from the address that it points to. Finally, the CPU checks the location that TMP2 points to. If the value stored in that location is $00 (the BGND opcode), TMP2 is incremented, so that the instruction that follows the BGND instruction is the first instruction executed when normal program execution resumes.

For all other types of BDM entry, the CPU performs the same sequence of operations as for a BGND instruction, but the value stored in TMP2 already points to the instruction that would have executed next had BDM not become active. If active BDM is triggered just as a BGND instruction is about to execute, the BDM firmware does increment TMP2, but the change does not affect resumption of normal execution.

Enter Background Debug Mode

BGND

While BDM is active, the CPU executes debugging commands received via a special single-wire serial interface. BDM is terminated by the execution of specific debugging commands. Upon exit from BDM, the background/boot ROM and registers are disabled, the instruction queue is refilled starting with the return address pointed to by TMP2, and normal processing resumes.

BDM is normally disabled to avoid accidental entry. While BDM is disabled, BGND executes as described, but the firmware causes execution to return to the user program. Refer to SECTION 8 DEVELOPMENT

AND DEBUG SUPPORT for more information concerning BDM.

Condition Codes and Boolean Formulas:

SXHI NZVC

––––––––

None affected.

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

BGND INH 00 5 VfPPP

CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-31

Page 92

BGT

Branch if Greater than Zero

BGT

Operation: If Z +(N ⊕ V) = 0, then (PC) + $0002 + Rel ⇒ PC

For signed two’s complement values if (Accumulator)

> (Memory), then branch

Description: If BGT is executed immediately after execution of CBA, CMPA, CMPB,

CMPD, CPX, CPY, SBA, SUBA, SUBB, or SUBD, a branch occurs if and only if the signed two’s complement number in the accumulator is greater than the signed two’s complement number in memory.

See 3.7 Relative Addressing Mode for details of branch execution.

Condition Codes and Boolean Formulas:

SXHI NZVC

––––––––

None affected.

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

BGT

rel8

Notes:

1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.

Branch Complementary Branch

Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment

r>m BGT 2E Z + (N r≥m BGE 2C N r=m BEQ 27 Z = 1 r≠m BNE 26 Signed r≤m BLE 2F Z + (N r<m BLT 2D N r>m BHI 22 C r≥m BHS/BCC 24 C = 0 r<m BLO/BCS 25 Unsigned r=m BEQ 27 Z = 1 r≠m BNE 26 Unsigned r≤m BLS 23 C r<m BLO/BCS 25 C = 1 r≥m BHS/BCC 24 Unsigned

Carry BCS 25 C = 1 No Carry BCC 24 Simple Negative BMI 2B N = 1 Plus BPL 2A Simple Overflow BVS 29 V = 1 No Overflow BVC 28 Simple

r=0 BEQ 27 Z = 1 r≠0 BNE 26 Simple

Always BRA 20 — Never BRN 21 Unconditional

REL 2E rr 3/1 PPP/P

⊕ V) = 0 r≤m BLE 2F Signed

⊕ V = 0 r<m BLT 2D Signed

⊕ V) = 1 r>m BGT 2E Signed

⊕ V = 1 r≥m BGE 2C Signed

+ Z = 0 r≤m BLS 23 Unsigned

+ Z = 1 r>m BHI 22 Unsigned

MOTOROLA INSTRUCTION GLOSSARY CPU12 6-32 REFERENCE MANUAL

Page 93

BHI

Branch if Higher

Operation: If C + Z = 0, then (PC) + $0002 + Rel ⇒ PC

BHI

For unsigned values, if (Accumulator)

> (Memory), then branch

Description: If BHI is executed immediately after execution of CBA, CMPA, CMPB,

CMPD, CPX, CPY, SBA, SUBA, SUBB, or SUBD, a branch occurs if and only if the unsigned binary number in the accumulator was greater than the unsigned binary number in memory. Generally not useful after INC/ DEC, LD/ST, TST/CLR/COM because these instructions do not affect the C status bit.

See 3.7 Relative Addressing Mode for details of branch execution.

Condition Codes and Boolean Formulas:

SXHI NZVC

––––––––

None affected.

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

BHI

rel8

Notes:

1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.

REL 22 rr 3/1 PPP/P

Branch Complementary Branch

Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment

Carry BCS 25 C = 1 No Carry BCC 24 Simple Negative BMI 2B N = 1 Plus BPL 2A Simple Overflow BVS 29 V = 1 No Overflow BVC 28 Simple

r=0 BEQ 27 Z = 1 r≠0 BNE 26 Simple

Always BRA 20 — Never BRN 21 Unconditional

CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-33

⊕ V) = 0 r≤m BLE 2F Signed

⊕ V = 0 r<m BLT 2D Signed

⊕ V) = 1 r>m BGT 2E Signed

⊕ V = 1 r≥m BGE 2C Signed

Page 94

Branch if Higher or Same

BHS

(Same as BCC)

Operation: If C = 0, then (PC) + $0002 + Rel ⇒ PC

BHS

For unsigned values, if (Accumulator)

≥ (Memory), then branch

Description: If BHS is executed immediately after execution of CBA, CMPA, CMPB,

See 3.7 Relative Addressing Mode for details of branch execution.

Condition Codes and Boolean Formulas:

SXHI NZVC

––––––––

None affected.

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

BHS

rel8

Notes:

1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.

REL 24 rr 3/1 PPP/P

Branch Complementary Branch

Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment

Carry BCS 25 C = 1 No Carry BCC 24 Simple Negative BMI 2B N = 1 Plus BPL 2A Simple Overflow BVS 29 V = 1 No Overflow BVC 28 Simple

r=0 BEQ 27 Z = 1 r≠0 BNE 26 Simple

Always BRA 20 — Never BRN 21 Unconditional

MOTOROLA INSTRUCTION GLOSSARY CPU12 6-34 REFERENCE MANUAL

⊕ V) = 0 r≤m BLE 2F Signed

⊕ V = 0 r<m BLT 2D Signed

⊕ V) = 1 r>m BGT 2E Signed

⊕ V = 1 r≥m BGE 2C Signed

Page 95

BITA

Bit Test A

BITA

Operation: (A) • (M)

Description: Performs bitwise logical AND on the content of accumulator A and the

content of memory location M, and modifies the condition codes accordingly. Each bit of the result is the logical AND of the corresponding bits of the accumulator and the memory location. Neither the content of the accumulator nor the content of the memory location is affected.

Condition Codes and Boolean Formulas:

SXHI NZVC

––––∆∆0–

N: Set if MSB of result is set; cleared otherwise. Z: Set if result is $00; cleared otherwise. V: 0; Cleared.

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

BITA # BITA

opr8a

BITA

opr16a

BITA

oprx0_xysp

BITA

oprx9,xysp

BITA

oprx16,xysp

BITA [D BITA [

opr8i

,xysp

]

oprx16,xysp

IMM

DIR

EXT

IDX IDX1 IDX2

[D,IDX]

]

[IDX2]

85 ii 95 dd B5 hh ll A5 xb A5 xb ff A5 xb ee ff A5 xb A5 xb ee ff

1 3 3 3 3 4 6 6

P rfP rOP rfP rPO frPP fIfrfP fIPrfP

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Page 96

BITB

Bit Test B

BITB

Operation: (B) • (M)

Description: Performs bitwise logical AND on the content of accumulator B and the

Condition Codes and Boolean Formulas:

SXHI NZVC

––––∆∆0–

N: Set if MSB of result is set; cleared otherwise. Z: Set if result is $00; cleared otherwise. V: 0; Cleared.

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

BITB # BITB

opr8a

BITB

opr16a

BITB

oprx0_xysp

BITB

oprx9,xysp

BITB

oprx16,xysp

BITB [D BITB [

opr8i

,xysp

]

oprx16,xysp

IMM

DIR

EXT

IDX IDX1 IDX2

[D,IDX]

]

[IDX2]

C5 ii D5 dd F5 hh ll E5 xb E5 xb ff E5 xb ee ff E5 xb E5 xb ee ff

1 3 3 3 3 4 6 6

P rfP rOP rfP rPO frPP fIfrfP fIPrfP

MOTOROLA INSTRUCTION GLOSSARY CPU12 6-36 REFERENCE MANUAL

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BLE

Branch if Less Than or Equal to Zero

BLE

Operation: If Z + (N ⊕ V) = 1, then (PC) + $0002 + Rel ⇒ PC

For signed two’s complement numbers if (Accumulator)

≤ (Memory), then branch

Description: If BLE is executed immediately after execution of CBA, CMPA, CMPB,

CMPD, CPX, CPY, SBA, SUBA, SUBB, or SUBD, a branch occurs if and only if the two’s complement number in the accumulator was less than or equal to the two’s complement number in memory.

See 3.7 Relative Addressing Mode for details of branch execution.

Condition Codes and Boolean Formulas:

SXHI NZVC

––––––––

None affected.

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

BLE

rel8

Notes:

1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.

Branch Complementary Branch

Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment

Carry BCS 25 C = 1 No Carry BCC 24 Simple Negative BMI 2B N = 1 Plus BPL 2A Simple Overflow BVS 29 V = 1 No Overflow BVC 28 Simple

r=0 BEQ 27 Z = 1 r≠0 BNE 26 Simple

Always BRA 20 — Never BRN 21 Unconditional

REL 2F rr 3/1 PPP/P

⊕ V) = 0 r≤m BLE 2F Signed

⊕ V = 0 r<m BLT 2D Signed

⊕ V) = 1 r>m BGT 2E Signed

⊕ V = 1 r≥m BGE 2C Signed

CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-37

Page 98

Branch if Lower

BLO

(Same as BCS)

BLO

Operation: If C = 1, then (PC) + $0002 + Rel ⇒ PC

For unsigned values, if (Accumulator) < (Memory), then branch

Description: If BLO is executed immediately after execution of CBA, CMPA, CMPB,

CMPD, CPX, CPY, SBA, SUBA, SUBB, or SUBD, a branch occurs if and only if the unsigned binary number in the accumulator is less than the unsigned binary number in memory. Generally not useful after INC/DEC, LD/ST, TST/CLR/COM because these instructions do not affect the C status bit.

See 3.7 Relative Addressing Mode for details of branch execution.

Condition Codes and Boolean Formulas:

SXHI NZVC

––––––––

None affected.

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

BLO

rel8

Notes:

1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.

Branch Complementary Branch

Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment

Carry BCS 25 C = 1 No Carry BCC 24 Simple Negative BMI 2B N = 1 Plus BPL 2A Simple Overflow BVS 29 V = 1 No Overflow BVC 28 Simple

r=0 BEQ 27 Z = 1 r≠0 BNE 26 Simple

Always BRA 20 — Never BRN 21 Unconditional

REL 25 rr 3/1 PPP/P

⊕ V) = 0 r≤m BLE 2F Signed

⊕ V = 0 r<m BLT 2D Signed

⊕ V) = 1 r>m BGT 2E Signed

⊕ V = 1 r≥m BGE 2C Signed

MOTOROLA INSTRUCTION GLOSSARY CPU12 6-38 REFERENCE MANUAL

Page 99

BLS

Branch if Lower or Same

Operation: If C + Z = 1, then (PC) + $0002 + Rel ⇒ PC

BLS

For unsigned values, if (Accumulator)

≤ (Memory), then branch

Description: If BLS is executed immediately after execution of CBA, CMPA, CMPB,

CMPD, CPX, CPY, SBA, SUBA, SUBB, or SUBD, a branch occurs if and only if the unsigned binary number in the accumulator is less than or equal to the unsigned binary number in memory. Generally not useful after INC/DEC, LD/ST, TST/CLR/COM because these instructions do not affect the C status bit.

See 3.7 Relative Addressing Mode for details of branch execution.

Condition Codes and Boolean Formulas:

SXHI NZVC

––––––––

None affected.

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

BLS

rel8

Notes:

1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.

REL 23 rr 3/1 PPP/P

Branch Complementary Branch

Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment

Carry BCS 25 C = 1 No Carry BCC 24 Simple Negative BMI 2B N = 1 Plus BPL 2A Simple Overflow BVS 29 V = 1 No Overflow BVC 28 Simple

r=0 BEQ 27 Z = 1 r≠0 BNE 26 Simple

Always BRA 20 — Never BRN 21 Unconditional

CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-39

⊕ V) = 0 r≤m BLE 2F Signed

⊕ V = 0 r<m BLT 2D Signed

⊕ V) = 1 r>m BGT 2E Signed

⊕ V = 1 r≥m BGE 2C Signed

Page 100

BLT

Branch if Less than Zero

BLT

Operation: If N ⊕ V = 1, then (PC) + $0002 + Rel ⇒ PC

For signed two’s complement numbers if (Accumulator)

< (Memory), then branch

Description: If BLT is executed immediately after execution of CBA, CMPA, CMPB,

CMPD, CPX, CPY, SBA, SUBA, SUBB, or SUBD, a branch occurs if and only if the two’s complement number in the accumulator is less than the two’s complement number in memory.

See 3.7 Relative Addressing Mode for details of branch execution.

Condition Codes and Boolean Formulas:

SXHI NZVC

––––––––

None affected.

Addressing Modes, Machine Code, and Execution Times:

Source Form Address Mode Object Code Cycles Access Detail

BLT

rel8

Notes:

1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.

Branch Complementary Branch

Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment

Carry BCS 25 C = 1 No Carry BCC 24 Simple Negative BMI 2B N = 1 Plus BPL 2A Simple Overflow BVS 29 V = 1 No Overflow BVC 28 Simple

r=0 BEQ 27 Z = 1 r≠0 BNE 26 Simple

Always BRA 20 — Never BRN 21 Unconditional

REL 2D rr 3/1 PPP/P

⊕ V) = 0 r≤m BLE 2F Signed

⊕ V = 0 r<m BLT 2D Signed

⊕ V) = 1 r>m BGT 2E Signed

⊕ V = 1 r≥m BGE 2C Signed

MOTOROLA INSTRUCTION GLOSSARY CPU12 6-40 REFERENCE MANUAL