MOTOROLA CPU08 User Manual
M68HC08
Microcontrollers
CPU08
Central Processor Unit
Reference Manual
CPU08RM/AD
Rev. 3, 2/2001
WWW.MOTOROLA.COM/SEMICONDUCTORS
blank
CPU08
Central Processor Unit
Reference Manual
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vary over time. All operating parameters, including "Typicals" must be validated for
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CPU08 — Rev. 3.0 Reference Manual
MOTOROLA 3
Reference Manual
Reference Manual CPU08 — Rev. 3.0
4 MOTOROLA
Reference Manual — CPU08
Section 1. General Description . . . . . . . . . . . . . . . . . . . .19
Section 2. Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . .23
Section 3. Resets and Interrupts . . . . . . . . . . . . . . . . . . .37
Section 4. Addressing Modes . . . . . . . . . . . . . . . . . . . . .55
Section 5. Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . .89
Section 6. Instruction Set Examples . . . . . . . . . . . . . . .189
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
List of Sections
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
CPU08 — Rev. 3.0 Reference Manual
MOTOROLA List of Sections 5
List of Sec ti o ns
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6 List of Sections MOTOROLA
Reference Manual — CPU08
1.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.4 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5 Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.6 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.7 Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table of Contents
Section 1. General Description
1.8 Binary-Coded Decimal (BCD) Arithmetic Support . . . . . . . . . .22
1.9 High-Level Language Support . . . . . . . . . . . . . . . . . . . . . . . . .2 2
1.10 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Section 2. Architecture
2.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.3 CPU08 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.3.2 Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.3.3 Stack Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.3.4 Program Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.3.5 Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . .28
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2.4 CPU08 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . .30
2.4.1 Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.4.2 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.4.3 Execution Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.4.4 Instruction Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Section 3. Resets and In ter r upts
3.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
3.3 Elements of Reset and Interrupt Processing . . . . . . . . . . . . . .39
3.3.1 Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
3.3.2 Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
3.3.3 Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
3.3.4 Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
3.3.5 Returning to Calling Program. . . . . . . . . . . . . . . . . . . . . . . .45
3.4 Reset Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
3.4.1 Initial Conditions Established . . . . . . . . . . . . . . . . . . . . . . . .47
3.4.2 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
3.4.3 Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . .47
3.4.4 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
3.4.5 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.4.6 Active Reset from an Internal Source. . . . . . . . . . . . . . . . . .49
3.5 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.5.1 Interrupt Sources and Priority. . . . . . . . . . . . . . . . . . . . . . . .51
3.5.2 Interrupts in Stop and Wait Modes. . . . . . . . . . . . . . . . . . . .52
3.5.3 Nesting of Multiple Interrupts . . . . . . . . . . . . . . . . . . . . . . . .52
3.5.4 Allocating Scratch Space on the Stack . . . . . . . . . . . . . . . .53
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Section 4. Addressing Modes
4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
4.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
4.3.1 Inherent. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
4.3.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
4.3.3 Direct. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
4.3.5 Indexed, No Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
4.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
4.3.7 Indexed, 16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
4.3.8 Stack Pointer, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . .68
4.3.9 Stack Pointer, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . .68
4.3.10 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
4.3.11 Memory-to-Memory Immediate to Direct . . . . . . . . . . . . . . .73
4.3.12 Memory-to-Memory Direct to Direct. . . . . . . . . . . . . . . . . . .73
4.3.13 Memory-to-Memory Indexed to Direct
with Post Increment. . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
4.3.14 Memory-to-Memory Direct to Indexed
with Post Increment. . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
4.3.15 Indexed with Post Increment . . . . . . . . . . . . . . . . . . . . . . . .77
4.3.16 Indexed, 8-Bit Offset with Post Increment . . . . . . . . . . . . . .78
4.4 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
4.5 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Section 5. Instruction Set
5.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
5.3 Nomenclature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
5.4 Convention Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
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5.5 Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
ADC Add with Carry. . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
ADD Add without Carry . . . . . . . . . . . . . . . . . . . . . . . . . 98
AIS Add Immediate Value (Signed)
to Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . 99
AIX Add Immediate Value (Signed)
to Index Register . . . . . . . . . . . . . . . . . . . . . . 100
AND Logical AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
ASL Arithmetic Shift Left. . . . . . . . . . . . . . . . . . . . . . . 102
ASR Arithmetic Shift Right. . . . . . . . . . . . . . . . . . . . . . 103
BCC Branch if Carry Bit Clear . . . . . . . . . . . . . . . . . . . 104
BCLR n Clear Bit n in Memory . . . . . . . . . . . . . . . . . . . . . 105
BCS Branch if Carry Bit Set. . . . . . . . . . . . . . . . . . . . . 106
BEQ Branch if Equal . . . . . . . . . . . . . . . . . . . . . . . . . . 107
BGE Branch if Greater Than or Equal To . . . . . . . . . . 108
BGT Branch if Greater Than . . . . . . . . . . . . . . . . . . . . 109
BHCC Branch if Half Carry Bit Clear . . . . . . . . . . . . . . . 110
BHCS Branch if Half Carry Bit Set. . . . . . . . . . . . . . . . . 111
BHI Branch if Higher. . . . . . . . . . . . . . . . . . . . . . . . . . 112
BHS Branch if Higher or Same . . . . . . . . . . . . . . . . . . 113
BIH Branch if IRQ Pin High . . . . . . . . . . . . . . . . . . . . 114
BIL Branch if IRQ Pin Low. . . . . . . . . . . . . . . . . . . . . 115
BIT Bit Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
BLE Branch if Less Than or Equal To. . . . . . . . . . . . . 117
BLO Branch if Lower . . . . . . . . . . . . . . . . . . . . . . . . . . 118
BLS Branch if Lower or Same. . . . . . . . . . . . . . . . . . . 119
BLT Branch if Less Than . . . . . . . . . . . . . . . . . . . . . . 120
BMC Branch if Interrupt Mask Clear. . . . . . . . . . . . . . . 121
BMI Branch if Minus . . . . . . . . . . . . . . . . . . . . . . . . . . 122
BMS Branch if Interrupt Mask Set . . . . . . . . . . . . . . . . 123
BNE Branch if Not Equal . . . . . . . . . . . . . . . . . . . . . . . 124
BPL Branch if Plus . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
BRA Branch Always. . . . . . . . . . . . . . . . . . . . . . . . . . . 126
BRA Branch Always. . . . . . . . . . . . . . . . . . . . . . . . . . . 127
BRCLR n Branch if Bit n in Memory Clear. . . . . . . . . . . . . . 128
BRN Branch Never . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
BRSET n Branch if Bit n in Memory Set . . . . . . . . . . . . . . . 130
BSET n Set Bit n in Memory. . . . . . . . . . . . . . . . . . . . . . . 131
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BSR Branch to Subroutine . . . . . . . . . . . . . . . . . . . . . . 132
CBEQ Compare and Branch if Equal. . . . . . . . . . . . . . . 133
CLC Clear Carry Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . 134
CLI Clear Interrupt Mask Bit. . . . . . . . . . . . . . . . . . . . 135
CLR Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
CMP Compare Accumulator with Memory. . . . . . . . . . 137
COM Complement (One’s Complement) . . . . . . . . . . . 138
CPHX Compare Index Register with Memory . . . . . . . . 139
CPX Compare X (Index Register Low)
with Memory. . . . . . . . . . . . . . . . . . . . . . . . . . 140
DAA Decimal Adjust Accumulator . . . . . . . . . . . . . . . . 141
DBNZ Decrement and Branch if Not Zero . . . . . . . . . . . 143
DEC Decrement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
DIV Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
EOR Exclusive-OR Memory with Accumulator . . . . . . 146
INC Increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
JMP Jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
JSR Jump to Subroutine . . . . . . . . . . . . . . . . . . . . . . . 149
LDA Load Accumulator from Memory. . . . . . . . . . . . . 150
LDHX Load Index Register from Memory . . . . . . . . . . . 151
LDX Load X (Index Register Low) from Memory. . . . . 152
LSL Logical Shift Left . . . . . . . . . . . . . . . . . . . . . . . . . 153
LSR Logical Shift Right . . . . . . . . . . . . . . . . . . . . . . . . 154
MOV Move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
MUL Unsigned Multiply . . . . . . . . . . . . . . . . . . . . . . . . 156
NEG Negate (Two’s Complement). . . . . . . . . . . . . . . . 157
NOP No Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
NSA Nibble Swap Accumulator. . . . . . . . . . . . . . . . . . 159
ORA Inclusive-OR Accumulator and Memory . . . . . . . 160
PSHA Push Accumulator onto Stack. . . . . . . . . . . . . . . 161
PSHH Push H (Index Register High) onto Stack . . . . . . 162
PSHX Push X (Index Register Low) onto Stack . . . . . . 163
PULA Pull Accumulator from Stack. . . . . . . . . . . . . . . . 164
PULH Pull H (Index Register High) from Stack . . . . . . . 165
PULX Pull X (Index Register Low) from Stack. . . . . . . . 166
ROL Rotate Left through Carry . . . . . . . . . . . . . . . . . . 167
ROR Rotate Right through Carry . . . . . . . . . . . . . . . . . 168
RSP Reset Stack Pointer. . . . . . . . . . . . . . . . . . . . . . . 169
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RTI Return from Interrupt. . . . . . . . . . . . . . . . . . . . . . 170
RTS Return from Subroutine. . . . . . . . . . . . . . . . . . . . 171
SBC Subtract with Carry . . . . . . . . . . . . . . . . . . . . . . . 172
SEC Set Carry Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
SEI Set Interrupt Mask Bit . . . . . . . . . . . . . . . . . . . . . 174
STA Store Accumulator in Memory. . . . . . . . . . . . . . . 175
STHX Store Index Register . . . . . . . . . . . . . . . . . . . . . . 176
STOP Enable IRQ Pin, Stop Oscillator . . . . . . . . . . . . . 177
STX Store X (Index Register Low) in Memory . . . . . . 178
SUB Subtract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
SWI Software Interrupt . . . . . . . . . . . . . . . . . . . . . . . . 180
TAP Transfer Accumulator to Processor
Status Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . 181
TAX Transfer Accumulator to X
(Index Register Low) . . . . . . . . . . . . . . . . . . . 182
TPA Transfer Processor Status Byte
to Accumulator . . . . . . . . . . . . . . . . . . . . . . . . 183
TST Test for Negative or Zero . . . . . . . . . . . . . . . . . . 184
TSX Transfer Stack Pointer to Index Register . . . . . . 185
TXA Transfer X (Index Register Low)
to Accumulator . . . . . . . . . . . . . . . . . . . . . . . . 186
TXS Transfer Index Register to Stack Pointer . . . . . . 187
WAIT Enable Interrupts; Stop Processor . . . . . . . . . . . 188
Section 6. Instruction Set Examples
6.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
6.3 M68HC08 Unique Instructions . . . . . . . . . . . . . . . . . . . . . . . .190
6.4 Code Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
AIS Add Immediate Value (Signed)
to Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . 192
AIX Add Immediate Value (Signed)
to Index Register . . . . . . . . . . . . . . . . . . . . . . 194
BGE Branch if Greater Than or Equal To . . . . . . . . . . 195
BGT Branch if Greater Than . . . . . . . . . . . . . . . . . . . . 196
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BLE Branch if Less Than or Equal To. . . . . . . . . . . . . 197
BLT Branch if Less Than . . . . . . . . . . . . . . . . . . . . . . 198
CBEQ Compare and Branch if Equal. . . . . . . . . . . . . . . 199
CBEQA Compare A with Immediate. . . . . . . . . . . . . . . . . 200
CBEQX Compare X with Immediate. . . . . . . . . . . . . . . . . 201
CLRH Clear H (Index Register High). . . . . . . . . . . . . . . 202
CPHX Compare Index Register with Memory . . . . . . . . 203
DAA Decimal Adjust Accumulator . . . . . . . . . . . . . . . . 204
DBNZ Decrement and Branch if Not Zero . . . . . . . . . . . 205
DIV Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
LDHX Load Index Register with Memory . . . . . . . . . . . 209
MOV Move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
NSA Nibble Swap Accumulator. . . . . . . . . . . . . . . . . . 211
PSHA Push Accumulator onto Stack. . . . . . . . . . . . . . . 212
PSHH Push H (Index Register High) onto Stack . . . . . . 213
PSHX Push X (Index Register Low) onto Stack. . . . . . . 214
PULA Pull Accumulator from Stack. . . . . . . . . . . . . . . . 215
PULH Pull H (Index Register High) from Stack . . . . . . . 216
PULX Pull X (Index Register Low) from Stack. . . . . . . . 217
STHX Store Index Register . . . . . . . . . . . . . . . . . . . . . . 218
TAP Transfer Accumul ator
to Condition Code Register . . . . . . . . . . . . . . 219
TPA Transfer Condition Code Register
to Accumulator . . . . . . . . . . . . . . . . . . . . . . . . 220
TSX Transfer Stack Pointer to Index Register . . . . . . 221
TXS Transfer Index Register to Stack Pointer . . . . . . 222
Glossary
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
Index
Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
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Reference Manual — CPU08
Figure Title P age
2-1 CPU08 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . .24
2-2 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2-3 Index Register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2-4 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2-5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2-6 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . .28
2-7 CPU08 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2-8 Internal Timing Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2-9 Control Unit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2-10 Instruction Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2-11 Instruction Execution Timing Diagram . . . . . . . . . . . . . . . . . . .35
List of Figures
3-1 Interrupt Stack Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
3-2 H Register Storage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
3-3 Interrupt Processing Flow and Timing . . . . . . . . . . . . . . . . . . .42
3-4 Interrupt Recognition Example 1 . . . . . . . . . . . . . . . . . . . . . . .43
3-5 Interrupt Recognition Example 2 . . . . . . . . . . . . . . . . . . . . . . .44
3-6 Interrupt Recognition Example 3 . . . . . . . . . . . . . . . . . . . . . . .44
3-7 Exiting Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
CPU08 — Rev. 3.0 Reference Manual
MOTOROLA List of Figures 15
List of Figu r e s
Reference Manual CPU08 — Rev. 3.0
16 List of Figures MOTOROLA
Reference Manual — CPU08
Table Title Page
3-1 Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
3-2 M68HC08 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
4-1 Inherent Addressing Instructions . . . . . . . . . . . . . . . . . . . . . . .58
4-2 Immediate Addressing Instructions. . . . . . . . . . . . . . . . . . . . . .60
4-3 Direct Addressing Instructions . . . . . . . . . . . . . . . . . . . . . . . . .62
4-4 Extended Addressing Instructions . . . . . . . . . . . . . . . . . . . . . .64
4-5 Indexed Addressing Instructions. . . . . . . . . . . . . . . . . . . . . . . .67
4-6 Stack Pointer Addressing Instructions . . . . . . . . . . . . . . . . . . .70
4-7 Relative Addressing Instructions . . . . . . . . . . . . . . . . . . . . . . .72
4-8 Memory-to-Memory Move Instructions. . . . . . . . . . . . . . . . . . .7 7
4-9 Indexed and Indexed, 8-Bit Offset
with Post Increment Instructions . . . . . . . . . . . . . . . . . . . . .78
4-10 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
4-11 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
List of Tables
5-1 Branch Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . .127
5-2 DAA Function Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
CPU08 — Rev. 3.0 Reference Manual
MOTOROLA List of Tables 17
List of Tables
Reference Manual CPU08 — Rev. 3.0
18 List of Tables MOTOROLA
Reference Manual — CPU08
1.1 Contents
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.4 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5 Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.6 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.7 Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.8 Binary-Coded Decimal (BCD) Arithmetic Support . . . . . . . . . .22
Section 1. General Descr ip tion
1.2 Introduction
1.9 High-Level Language Support . . . . . . . . . . . . . . . . . . . . . . . . .22
1.10 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
The CPU08 is the central processor unit (CPU) of the Motorola
M68HC08 Family of microcontroller units (MCU). The fully object code
compatible CPU08 offers M68HC05 users increased performance with
no loss of time or software investment in their M68HC05-based
applications. The CPU08 also appeals to users of other MCU
architectures who need the CPU08 combination of speed, low power,
processing capabilities, and cost effectiveness.
CPU08 — Rev. 3.0 Reference Manual
MOTOROLA General Description 19
General Description
1.3 Features
CPU08 features include:
• Full object-code compatibility with M68HC05 Family
• 16-bit stack pointer with stack manipulation instructions
• 16-bit index register (H:X) with high-byte and low-byte
manipulation instructions
• 8-MHz CPU standard bus frequency
• 64-Kbyte program/data memory space
• 16 addressing modes
• 78 new opcodes
• Memo ry-to-memory data moves without using accumulator
• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
• Enhanced binary-coded decimal (BCD) data handling
• Expandable internal bus definition for extension of addressing
• Flexible internal bus definition to accommodate CPU
• Low-power stop and wait modes
1.4 Programming Model
The CPU08 programming model consists of:
• 8-bit accumulator
• 16-bit index register
• 16-bit stack pointer
• 16-bit program counter
range beyond 64 Kbytes
performance-enhancing peripherals such as a direct memory
access (DMA) controller
• 8-bit condition code register
See Figure 2-1. CPU08 Programming Model .
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20 General Descri ptio n MOTOR OLA
1.5 Me mory Space
Program memory space and data memory space are cont iguous over a
64-Kbyte addressing range. Addition of a page-switching peripheral
allows extension of the addressing range beyond 64 Kbytes.
1.6 Addressing Modes
The CPU08 has a total of 16 addressing modes:
• Inherent
• Immediate
• Direct
• Extended
General Description
Memory Space
• Indexed
– No offset
– No offset, post increment
– 8-bit offset
– 8-bit offset, post increment
– 16-bit offset
• Stack pointer
– 8-bit offset
– 16-bit offset
• Relative
• Memory-to-memory (four modes)
Refer to Sectio n 4 . Addres sing Mo des for a detail ed descriptio n of the
CPU08 addressing modes.
CPU08 — Rev. 3.0 Ref erence Manual
MOTOROLA General Description 21
General Description
1.7 Arithmetic Instructions
The CPU08 arithmetic functions include:
• Addition with and without carry
• Subtraction with and without carry
• A fast 16-bit by 8-bit unsigned division
• A fast 8-bit by 8-bit unsigned multiply
1.8 Binary-Coded Decimal (BCD) Arithmetic Support
To support binary-coded decimal (BCD) arithmetic applications, the
CPU08 has a de cimal adjust accumulator (DAA) instruction a nd a nibble
swap accumulator (NSA) instruction.
1.9 High-Level Language Support
The 16-bit index register, 16-bit stack pointer, 8-bit signed branch
instructions, and associated instructions are designed to support the
efficient use of high-level language (HLL) compilers with the CPU08.
1.10 Low-Power Modes
The WAIT and S TOP instr uctions red uce th e po w er consum ption of th e
CPU08-based MCU. The WAIT instruction stops only the CPU clock and
therefore us es more pow er than the STOP instru ction, which stops both
the CPU clock and the peripheral clocks. In most modules, clocks can
be shut off in wait mode.
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22 General Descri ptio n MOTOR OLA
Reference Manual — CPU08
2.1 Contents
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.3 CPU08 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.3.2 Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.3.3 Stack Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.3.4 Program Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.3.5 Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.4 CPU08 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . .30
2.4.1 Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.4.2 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.4.3 Execution Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.4.4 Instruction Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Section 2. Architecture
2.2 Introduction
This section describes the CPU08 registers.
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MOTOROLA Architecture 23
Architecture
2.3 CPU08 Registers
Figure 2-1 shows the five CPU08 registers. The CPU08 registers are
not part of the memory map.
70
A ACCUMULATOR (A)
15 8 7 0
H X INDEX REGISTER (H:X)
15 0
STACK POINTER (SP)
15 0
PROGRAM COUNTER (PC)
70
V11H I NZC
TWO’S COMPLEMENT OVERFLOW
FLAG (V)
ZERO FLAG (Z)
HALF-CARRY FLAG (H)
NEGATIVE FLAG (N)
INTERRU PT MASK (I )
CONDITION CODE
REGISTER (CCR)
CARRY/BORROW FLAG (C)
Figure 2-1. CPU08 Programming Model
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24 Architecture MOTOROLA
2.3.1 Accumulator
2.3.2 Index Register
Architecture
CPU08 Registers
The accumulator (A) shown in Figure 2-2 is a general-purpose 8-bit
register. The central processo r unit (CPU ) uses the accumulator to hol d
operands and results of arithmetic and non-arithmetic operations.
Bit 7654321Bit 0
Read:
Write:
Reset:XXXXXXXX
X = Indeterminate
Figure 2-2. Accumulator (A)
The 16-bit index register (H:X) shown in Figure 2-3 allows the user to
index or address a 64-Kbyte memory space. The concatenated 16-bit
register is called H:X. The upper byte of the index register is called H.
The lower byte of the index register is called X. H is cleared by reset.
When H = 0 and no instructions that affect H are used, H:X is functionally
identical to the IX register of the M6805 Family.
In the indexed addressing mod es, the CPU uses the conten ts of H:X to
determine th e effective ad dress of th e operand . H:X can also serv e as a
temporary data storage location. See 4.3.5 Indexed, No Offset;
4.3.6 Indexed, 8-Bit Offs et; and 4.3.7 Indexed, 16-Bit Offset.
Bit 151413121110987654321Bit 0
Read:
Write:
Reset:X XXXXXXXXXXXXXXX
X = Indeterminate
Figure 2-3. Index Register (H:X)
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MOTOROLA Architecture 25
Architecture
2.3.3 Stack Pointer
NOTE: The reset stack pointer (RSP) instruction sets the least significant byte
The stack pointer (SP) shown in Figure 2-4 is a 16-bit register that
contains the addr ess of the next location on the stack. During a reset, the
stack pointer is preset to $00FF to provide compatibility with the M6805
Family.
to $FF and does not affect the most significant byte.
The address in the stack pointer decremen ts as data is pushe d onto the
stack and increments as data is pulled from the stack. The SP always
points to the next available (empty) byte on the stack.
The CPU08 ha s stack poin ter 8- and 16-bit offse t addressing m odes that
allow the stack pointer to be used as an index register to access
temporary variab les on the stack. The CPU uses the contents in the SP
register to determine the effective address of the operand. See
4.3.8 Stack Pointer, 8-Bit Offset and 4.3.9 Stack Pointer, 16-Bit
Offset.
Bit 151413121110987654321Bit 0
Read:
Write:
Reset:0 000000011111111
Figure 2-4. Stack Pointe r (SP)
NOTE: Although pres et to $00FF, the loca tion of the sta ck is arbi trary and may
be relocated by the user to anywhere that random-access memory
(RAM) resides within the memory map. Moving the SP out of page 0
($0000 to $00FF) will free up address space, which may be accessed
using the efficient direct addressing mode.
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26 Architecture MOTOROLA
2.3.4 Program Counter
The program counter (PC) shown in Figure 2-5 is a 16-bit register that
contains the address of the next instruction or operand to be fetched.
Normally, the address in the pr ogra m counte r auto matical ly incre ments
to the next sequential memory location every time an instruction or
operand is fetched. Jump, branch, and interrupt operations load the
program counter with an address other than that of the next sequential
location.
During reset, the PC is loaded with the contents of the reset vector
located at $FFFE and $FFFF. This represents the address of the first
instruction to be executed after the reset state is exited.
Architecture
CPU08 Registers
Bit 151413121110987654321Bit 0
Read:
Write:
Reset: Loaded with vector from $FFFE and $FFFF
Figure 2-5. Program Counter (PC)
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MOTOROLA Architecture 27
Architecture
2.3.5 Condition Code Register
The 8-bit condition code register (CCR) shown in Figure 2-6 contains
the interrupt mask and five flags that indicate the result s of the instruction
just executed. Bits five and six are permanently set to logic 1.
Read:
Write:
Reset:X11X1XXX
X = Indeterminate
V — Overflow Flag
Bit 7654321Bit 0
V11H I NZC
Figure 2-6. Condition Code Register (CCR)
The CPU sets the overflow flag when a two's complement overflow
occurs as a result of an operation. The overflow flag bit is utilized by
the signed branch instructions:
Branch if greater than, BGT
Branch if greater than or equal to, BGE
Branch if less than or equal to, BLE
Branch if less than, BLT
This bit is set by th ese instr uctions, although its r esulting value h olds
no meaning:
Arithmetic shift left, ASL
Arithmetic shift right, ASR
Logical shift left, LSL
Logical shift right, LSR
Rotate left through carry, ROL
Rotate right through carry, ROR
H — Half-Carry Flag
The CPU sets the half-carry fla g when a carr y occurs betwee n bits 3
and 4 of the accumulator during an add-without-carry (ADD) or
add-with-carry (ADC) operation. The half-carry flag is required for
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28 Architecture MOTOROLA
CPU08 Registers
binary-coded (BCD) arithmetic operations. The decimal adjust
accumulator (DAA) instruction uses the state of the H and C flags to
determine the appropriate correction factor.
I — Interrupt Mask
When the interrupt mask is set, all interrupts are disabled. Interrupts
are enabled when the interrupt mask is cleared. When an interrupt
occurs, the interr upt mask is automatica lly set after the CPU reg isters
are saved on the stack, but before the interrupt vector is fetched.
NOTE: To maintain M6805 compatibility, the H register is not stacked
automatically . If the interrupt service routine uses X (and H is not clea r),
then the user must stack and unstack H using the push H (index register
high) onto stack (PSHH) and pull H (index register high) from stack
(PULH) instructions within the interrupt service routine.
Architecture
If an interrupt occurs while the interrupt mask is set, the interrupt is
latched. Interrupts in or der of priority are ser viced as soon as the I bit
is cleared.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack, restoring the interrupt mask to its cleared state. After any
reset, the interrupt mask i s set and can only be clea red by a sof tware
instruction. See Section 3. Resets and Interrupts.
N — Negative Flag
The CPU sets t he negative fl ag when an ar it hmet ic ope rati on , log ical
operation, or data manipulation produces a negative result.
Z — Zero Flag
The CPU sets the zero flag when an arithmetic operation, logical
operation, or data manipulation produces a result of $00.
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some logical operations and data
manipulation instructions also clear or set the carr y/borrow flag (as in
bit test and branch instructions and shifts and rotates).
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MOTOROLA Architecture 29
Architecture
2.4 CPU08 Functional Description
This subsection is an overview of the architectur e of the M68HC08 CPU
with functional descriptions of the major blocks of the CPU.
The CPU08, as shown in Figure 2-7, is divided into two main blocks:
• Control unit
• Execution unit
The control unit contains a finite state machine along with miscellaneou s
control and timing logic. The outputs of this block drive the execution
unit, which contains the arithmetic logic unit (ALU), registers, and bus
interface.
CONTR OL UNIT
CONTROL
SIGNALS
EXECUTION UNIT
STATUS
SIGNALS
ADDRESS BUS
Figure 2-7. CPU08 Block Diagram
INTERNAL
DATA BUS
INTER NAL
Reference Manual CPU08 — Rev. 3.0
30 Architecture MOTOROLA
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