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CPCI-6020 CompactPCI Single Board
Computer
Installation and Use
6806800A51C
February 2008
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©
Copyright 2008, 2007 Motorola
All rights reserved.
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Motorola® and the stylized M logo are trademarks registered in the U.S. Patent and Trademark Office.
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Corporation.
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mentioned in this document are trademarks or registered trademarks of their respective holders.
All other product or service names mentioned in this document are the property of their respective holders.
Notice
While reasonable efforts have been made to assure the accuracy of this document, Motorola assumes no liability resulting from any
omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document
and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or
changes.
Electronic versions of this material may be read online, downloaded for personal use, or referenced in another document as a URL to
a Motorola website. The text itself may not be published commercially in print or electronic form, edited, translated, or otherwise altered
without the permission of Motorola,
It is possible that this publication may contain reference to or information about Motorola products (machines and programs),
programming, or services that are not available in your country. Such references or information must not be construed to mean that
Motorola intends to announce such Motorola products, programming, or services in your country.
Limited and Restricted Rights Legend
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otherwise agreed to in writing by Motorola.
Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of the Rights in Technical
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at DFARS 252.227-7014 (Jun. 1995).
Contact Address
Motorola Inc.
ECC Embedded Communications Computing
2900 South Diablo Way, Suite 190
Tempe, Arizona 85282
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Contents
About this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Safety Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Sicherheitshinweise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.2 Standard Compliances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.3.1 Supported Board Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.3.2 Board Accessories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2 Hardware Preparation and Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2 Unpacking and Inspecting the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.3 Overview of Start-up Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.4 Equipment Required . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.5 Environmental and Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.5.1 Environmental Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.5.2 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.5.3 Thermal Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.6 Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.7 CPCI-6020 Baseboard Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.8 Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.8.1 Flash Bank Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.8.2 Harrier Power Up Configuration Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.8.3 PMC 66 MHz Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.8.4 Enable/Disable +12 V and -12 V Use. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.8.5 Enable/Disable Lockdown of One or More Flash Blocks for Bank A . . . . . . . . . . . . . . . 43
2.8.6 Enable Write-Protect for Entire Flash on Bank A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.8.7 Remote Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.9 Hardware Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.10 PMC Module Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.11 CompactFlash Memory Card Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.12 Before You Install or Remove a Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.12.1 Watch for Bent Pins or Other Damage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.12.2 Use Caution When Installing or Removing Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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2.12.3 Understanding Hot Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.12.4 Recognize Different Injector/Ejector Lever Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.12.5 Verify Slot Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.12.6 Preserve EMI Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.13 Installing and Removing a Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2.14 Startup and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.15 System Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3 Controls, LEDs, and Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.2 CPCI-6020 Baseboard Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.3 Front Panel Connectors and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.3.1 Front Panel Ethernet Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.3.2 Front Panel Asynchronous Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.3.3 Front Panel USB ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.3.4 ABORT# Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.3.5 RESET# Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.3.6 Front Panel LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.4 Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.4.1 CompactPCI Bus Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.4.2 CompactPCI User I/O Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.4.3 CompactPCI User I/O Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.4.4 CompactPCI User I/O Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.4.5 Memory Mezzanine Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.4.6 PCI Mezzanine Card (PMC) Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.4.7 Lock Down Flash Enable Jumper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.4.8 PMC 66 Mhz Disable Jumper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.4.9 Remote Switch Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.4.10 Flash Write Protect Enable Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.4.11 Harrier Power Up Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.4.12 Xport Flash Bank Select Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.4.13 RISCWatch Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.4.14 Mictor Debug Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.3 Local PCI Bus Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.3.1 PCI Bus A Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.3.1.1 Local CompactPCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.3.1.2 Remote (Expansion) CompactPCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.3.1.3 Primary Ethernet Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.3.1.4 ISA Bridge, Including EIDE Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.3.1.5 EIDE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.3.1.6 ISA Bus Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
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4.3.1.7 Synchronous Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.3.1.8 USB Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.4 PCI Bus B Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.4.1 PMC Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.4.2 Secondary Ethernet Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.5 Processor Bus Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.5.1 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.5.2 L2 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.6 Harrier System Memory Controller and PCI Host Bridge ASIC . . . . . . . . . . . . . . . . . . . . . . . . 87
4.6.1 Dual Harrier Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.6.2 Harrier Power-Up Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.6.3 Debug Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.6.4 PPC Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.7 ECC Memory Bus Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.7.1 Harrier A Memory Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.7.2 Harrier B Memory Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.7.3 RAM500 Memory Mezzanine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.8 Harrier Xport Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.8.1 Harrier A, Channel 0 - Onboard Bank A Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.8.2 Harrier A, Channel 1 - Socketed Bank B Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.8.3 Harrier A, Channel 2 - NVRAM, RTC, External Register Set . . . . . . . . . . . . . . . . . . . . . 92
4.8.4 Harrier A, Channel 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.8.5 Harrier B, Channel 0, 1, 2 and 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.9 Other Harrier Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.9.1 I2C Bus Resources - Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.9.2 Asynchronous Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.9.3 32-Bit Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.9.4 Watchdog Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.10 Other Board Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.10.1 Miscellaneous Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.10.2 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.10.3 Onboard Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.10.4 Board Reset Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.10.5 Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.10.6 Front Panel Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.10.7 ABORT# and RESET# Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.10.8 On-Board LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.10.9 Harrier Power Up Configuration Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.11 Hot Swap Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.12 High Availability Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.12.1 HSC Bridge Board Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.12.2 Local CompactPCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.12.3 Secondary Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.12.4 Secondary Bus Tri-Stating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.12.5 System Slot Hot Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.13 EIDE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
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4.14 Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.15 Hot Swap Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.16 PMC Interface Module (PIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.17 Asynchronous Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.18 Synchronous Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.19 I/O Signal Multiplexing (IOMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.20 Serial Interface Modules (SIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.21 PMC Interface Module (PIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.22 PMC Interface Module Form Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.23 PMC Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.24 Host I/O Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.25 Speaker Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.26 Floppy Disk Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.27 Mouse and Keyboard Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5 Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.1 PPCBug Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.2 PPCBug Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.3 Memory Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.4 PPCBug Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.5 MPU, Hardware and Firmware Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.6 Using PPCBug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.7 Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.8 Diagnostic Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6 RAM500 Memory Expansion Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.2 RAM500 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.3 RAM500 Module Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.4.1 SROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.4.2 Host Clock Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.4.3 Serial Presence Detect (SPD) Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.5 RAM500 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.5.1 Bottom Side Memory Expansion Connector (P1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.5.2 Top Side Memory Expansion Connector (J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.6 RAM500 Programming Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7 Transition Module Preparation and Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
7.2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
7.2.1 Component Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
7.2.2 Rear Panel Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
7.3 Unpacking and Inspecting the RTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
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7.4 Preparing the Transition Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
7.4.1 Serial Ports 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
7.4.2 Serial Ports 3 and 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
7.4.3 Serial Interface Module Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
7.4.4 Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
7.5 Installing the SIMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
7.6 Installing the PIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
7.7 Installing and Removing the Transition Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
7.8 Connectors and Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
7.9 Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
7.9.1 CompactPCI Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
7.9.2 PMC I/O Module Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
7.9.3 10BaseT/100BaseTx Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
7.9.4 COM1 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
7.9.5 COM2 Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
7.9.6 EIDE Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
7.9.7 Floppy Port Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
7.9.8 +5VDC Power Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
7.9.9 Keyboard/Mouse Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
7.9.10 Sync/Async Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
7.9.11 Speaker Output Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
8 CNFG and ENV Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
8.2 CNFG - Configure Board Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
8.3 ENV - Set Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
8.4 Configuring the PPCBug Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
A Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
A.1 Embedded Communications Computing Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
A.2 Manufacturers’ Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
A.3 Related Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
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List of Tables
Table 1-1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 1-2 Board Standard Compliances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 2-1 Startup Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 2-2 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 2-3 Baseboard and RTM Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 2-4 Slot Usage Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 3-1 Ethernet Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 3-2 COM1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 3-3 USB Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 3-4 USB Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 3-5 Front Panel LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 3-6 J1 CompactPCI Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 3-7 J2 CompactPCI Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 3-8 J3 CompactPCI User I/O Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 3-9 Signal Descriptions for the J3 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 3-10 J4 Local PCI Expansion Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 3-11 J5 User I/O Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 3-12 J5 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 3-13 J8 and J27 Memory Mezzanine Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 3-14 PMC Connector J11 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 3-15 J12 PMC Connector J12 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 3-16 PMC Connector J13 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 3-17 PMC Connector J14 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 3-18 J17 Lock Down Flash Enable Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 3-19 J21 PMC 66 MHz Disable Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 3-20 J19 Remote Switch Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 3-21 J20 Flash Write Protect Enable Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 3-22 J22 Harrier Power Up Configuration Header Pin Assignments . . . . . . . . . . . . . . . . . . 74
Table 3-23 J24 Xport Flash Bank Select Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 3-24 J25 RISCWatch Header Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 3-25 J28 Debug Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 4-1 Special Function Processor PMC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 4-2 Harrier Power-Up Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 4-3 Expansion SDRAM Memory Mezzanine Size Options . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 4-4 Bank A Flash Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 4-5 PPC to PCI Clock Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 4-6 Reset Sources and Devices Affected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 4-7 Multiplexing Sequence of the IOMX Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 5-1 Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 5-2 Diagnostic Test Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
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Table 6-1 RAM500 SDRAM Memory Size Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 6-2 RAM500 Feature Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 6-3 RAM500 Bottom Side Connector (P1) Pin Assignments . . . . . . . . . . . . . . . . . . . . . . 120
Table 6-4 RAM500 Top Side Connector (J1) Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 7-1 SIM Model Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 7-2 Rear Transition Module Connectors/Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 7-3 Rear Transition Module Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 7-4 PMC I/O Module - Host I/O Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . 143
Table 7-5 PMC I/O Module - PMC I/O Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . 144
Table 7-6 10BaseT/100BaseTx Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 7-7 COM1 Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 7-8 COM2 Header Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 7-9 EIDE Header Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 7-10 Floppy Header Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 7-11 +5Vdc Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 7-12 Keyboard/Mouse Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 7-13 Sync/Async Serial Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 7-14 Speaker Output Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table A-1 Embedded Communications Computing Documents . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table A-2 Manufacturers’ Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table A-3 Related Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
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List of Figures
Figure 2-1 Header Locations and Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 2-2 Injector/Ejector Lever Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 2-3 Start Up Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 3-1 Headers, Connectors and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 3-2 Front Panel Connectors and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 4-1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 4-2 Reset Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 4-3 Serial Port Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 4-4 P2MX Signal Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 4-5 PMC Interface Module Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 7-1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 7-2 Component Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 7-3 Rear Panel Connectors, Cut-outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 7-4 Ports 3 and 4 Header Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 7-5 EIA-232-D DCE Ports 3 and 4 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 7-6 EIA-232-D DTE Ports 3 and 4 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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List of Figures
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CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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About this Manual
Overview of Contents
This manual provides the information required to install and configure an CPCI-6020 Single
Board Computer. Moreover, this manual provides specific preparation and installation
information and data applicable to the board. The CPCI-6020 was previously offered as the
MCP820 Single Board Computer.
The CPCI-6020 is a high-performance CompactPCI single board computer featuring the
MPC7410 with Alti-Vec™ technology for algorithmic intensive computational capabilities.
This manual is divided into the following chapters and appendices:
Safety Notes, a collection of standard product safety notes for the CPCI-6020 in English.
Sicherheitshinweise, a collection of standard product safety ntoes for the CPCI-6020 translated
to German.
Chapter 1, Introduction, lists the features of the CPCI-6020 baseboard, standards compliances,
model numbers for boards, memory, and RTMs.
Chapter 2, Hardware Preparation and Installation, includes a description of the CPCI-6020,
unpacking instructions, environmental and power requirement, and how to prepare and install
the CompactFlash, a PMC module, and the CPCI-6020 baseboard.
Chapter 3, Controls, LEDs, and Connectors provides illustrations of the board components and
face plate details. This chapter also gives descriptions for the onboard and front panel LEDs
and connections and pinout information for connectors, headers and jumpers.
Chapter 4, Functional Description describes the major features of the CPCI-6020 baseboard
and the CPCI-6020-MCPTM-01 transition module. These descriptions include both
programming and hardware characteristics of major components.
Chapter 5, Firmware describes the role, process and commands employed by the CPCI-6020
diagnostic and initialization firmware PPCBug. This chapter also briefly describes how to use
the debugger commands.
Chapter 6, RAM500 Memory Expansion Module provides information for installing the RAM500
memory mezzanine. If also provides information on pinouts and features.
Chapter 7, Transition Module Preparation and Installation, includes a description of the CPCI-
6020-MCPTM-01 rear transition module. The chapter provides illustrations of the RTM
components and face plate details. It describes jumper settings, port configuration diagrams,
and procedures for installing SIMs and PIMs. Pin assignment tables for the RTM are included
in this chapter.
Chapter 8, CNFG and ENV Commands describes how to use the CNFG and ENV commands
of PPCBug to modify certain parameters within the CPCI-6020.
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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About this Manual
Appendix A, Related Documentation provides listings for Motorola publications, manufacturer’s
documents and related industry specification for this product.
Abbreviations
This document uses the following abbreviations:
Abbreviation Description
ACE Asynchronous Communications Element
ANSI American National Standards Institute
ASIC Application Specific Integrated Circuit
BBRAM Battery Backed-up RAM
BDFL Board Fail
CF Compact Flash
CHRP Common Hardware Reference Platform
CMOS Complementary metal oxide semiconductor
DCE Data Circuit Termination
DTE Data Terminal Equipment
EIDE Enhanced Integrated Design Electronics
EMI Electro Magnetic Interference
ESD Electro Static Discharge
FDD Floppy Disk Drive
GB Gigabyte
HA High Availability
HDD Hard Disk Drive
HSC Hot Swap Controller
IOMUX I/O Signal Multiplexing
ISA Industry Standard Architecture
KB Kilobyte
MAC Media Access Controller
MPU Microprocessing Unit
Mbps Megabits per second
MB Megabyte
NVRAM Non Volatile Random Access Memory
OHCI Open Host Controller Interface
PF Port Format
PHB PCI Host Bridge
PHY Physical Layer
PIB PCI Arbiter
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Abbreviation Description
PIM PMC Interface Module
PIO Parallel Input Output
PIRQx PCI Interrupts
PMC Peripheral Mezzanine Card
PRP PowerPC Reference Platform
PrPMC Processor PMC
RISC Reduced Instruction Set Computer
RoHS Restriction of Hazardous Substances
SIM Serial Interface Module
SMC System Memory Controller
SPD Serial Presence Detect
TA Ter m i n a l A t t ac h
UART Universal Asynchronous Receiver-Transmitter
USB Universal Serial Bus
VPD Vital Product Data
About this Manual
Conventions
The following table describes the conventions used throughout this manual.
Notation Description
0x00000000 Typical notation for hexadecimal numbers (digits
0b0000 Same for binary numbers (digits are 0 and 1)
bold Used to emphasize a word
Screen Used for on-screen output and code related
Courier + Bold Used to characterize user input and to separate it
Reference Used for references and for table and figure
File > Exit Notation for selecting a submenu
<text> Notation for variables and keys
[text] Notation for software buttons to click on the
... Repeated item for example node 1, node 2, ...,
are 0 through F), for example used for addresses
and offsets
elements or commands in body text
from system output
descriptions
screen and parameter description
node 12
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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About this Manual
Notation Description
.
.
.
.. Ranges, for example: 0..4 means one of the
| Logical OR
Omission of information from example/command
that is not necessary at the time being
integers 0,1,2,3, and 4 (used in registers)
Indicates a hazardous situation which, if not
avoided, could result in death or serious injury
Indicates a hazardous situation which, if not
avoided, may result in minor or moderate injury
Indicates a property damage message
Summary of Changes
This manual has been revised and replaces all prior editions.
Part Number Publication Date Description
6806800A36A First release. Replaces MCP820 SBC.
6806800A36B January 2007 J24 Xport flash bank select header
6806800A36C January 2008 Remove Winbond PC97317 for 6/6 version.
No danger encountered. Pay attention to
important information
description corrected.
Legacy functionality remains via serial,
Ethernet, and CompactFlash components.
RoHS 6/6 compliancy.
Editorial and style changes to manual.
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Comments and Suggestions
We welcome and appreciate your comments on our documentation. We want to know what you
think about our manuals and how we can make them better.
Mail comments to:
z Motorola, Inc.
Embedded Communications Computing
2900 South Diablo Way, Suite 190
Tempe, Arizona 85282
z reader-comments@ecc.mot.com
In all your correspondence, please list your name, position, and company. Be sure to include
the title, part number, and revision of the manual and tell how you used it.
About this Manual
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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About this Manual
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Safety Notes
This section provides warnings that precede potentially dangerous procedures
throughout this manual. Instructions contained in the warnings must be followed during
all phases of operation, service, and repair of this equipment. You should also employ
all other safety precautions necessary for the operation of the equipment in your
operating environment. Failure to comply with these precautions or with specific
warnings elsewhere in this manual could result in personal injury or damage to the
equipment.
Motorola intends to provide all necessary information to install and handle the product
in this manual. Because of the complexity of this product and its various uses, we do not
guarantee that the given information is complete. If you need additional information, ask
your Motorola representative.
The product has been designed to meet the standard industrial safety requirements. It
must not be used except in its specific area of office telecommunication industry and
industrial control.
EMC
Only personnel trained by Motorola or persons qualified in electronics or electrical
engineering are authorized to install, remove or maintain the product.
The information given in this manual is meant to complete the knowledge of a specialist
and must not be used as replacement for qualified personnel.
Keep away from live circuits inside the equipment. Operating personnel must not
remove equipment covers. Only Factory Authorized Service Personnel or other qualified
service personnel may remove equipment covers for internal subassembly or
component replacement or any internal adjustment.
Do not install substitute parts or perform any unauthorized modification of the
equipment or the warranty may be voided. Contact your local Motorola representative for
service and repair to make sure that all safety features are maintained.
This equipment has been tested and found to comply with the limits for a Class A digital
device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide
reasonable protection against harmful interference when the equipment is operated in a
commercial environment. This equipment generates, uses, and can radiate radio
frequency energy and, if not installed and used in accordance with the instruction
manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference
in which case the user will be required to correct the interference at his own expense.
Changes or modifications not expressly approved by Motorola Embedded
Communications Computing could void the user's authority to operate the equipment.
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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Safety Notes
Board products are tested in a representative system to show compliance with the above
mentioned requirements. A proper installation in a compliant system will maintain the
required performance. Use only shielded cables when connecting peripherals to assure
that appropriate radio frequency emissions compliance is maintained.
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Operation
Damage of Module Surface
High humidity and condensation on the product surface causes short circuits.
Do not operate the product outside the specified environmental limits. Make sure the
product is completely dry and there is no moisture on any surface before applying
power.
Overheating and Damage of the Product
Operating the product without forced air cooling may lead to overheating and thus
damage of the product.
When operating the product, make sure that forced air cooling is available in the shelf.
Signaling Requirements
Ensure the backplane does not bus J3, J4 or J5 signals to other slots.
Set the VIO on the backplane to either +3.3 V or +5 V, depending upon your system’s
signaling requirements.
Safety Notes
Data Loss
Powering down or removing a board before the operating system or other software
running on the board has been properly shut down may cause corruption of data or file
systems.
Make sure all software is completely shut down before removing power from the board
or removing the board from the chassis.
Data Loss
Although a command that allows erasing and reprogramming of flash memory is
available, note that reprogramming any portion of the CPCI-6020 baseboard’s flash
memory (Bank B) will erase everything currently contained in the baseboard flash,
including the PPCBug debugger.
Use caution when reprogramming or erasing flash memory. Refer to the programming
documents listed in Appendix A, Related Documentation.
Installation
Personal Injury
Dangerous voltages capable of causing death exist.
To prevent injury, use extreme caution when handling, testing and adjusting this
equipment.
Damage of Circuits
Electrostatic discharge and incorrect module installation and removal can damage
circuits or shorten their life.
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Safety Notes
Before touching the module or electronic components, make sure that you are working
in an ESD-safe environment.
Damage of Module and Additional Devices
Incorrect installation of additional devices or modules may damage the product or the
additional devices or modules.
Before installing or removing an additional device or module, read the respective
documentation.
Board Damage
Inserting or removing modules that are not HA capable with power applied may result in
damage to module components.
Verify that your board is HA capable.
Product Damage
Prevent possible damage to module components by verifying the proper slot usage for
your configuration.
Check the icons and colored card rails for slot purpose prior to installing a module.
Damage to the Product/Backplane or System Components
Bent pins or loose components can cause damage to the product, the backplane, or
other system components.
Therefore, carefully inspect the product and the backplane for both pin and component
integrity before installation.
Embedded Communications Computing and our suppliers take significant steps to
ensure there are no bent pins on the backplane or connector damage to the boards prior
to leaving the factory. Bent pins caused by improper installation or by inserting boards
with damaged connectors could void the ECC warranty for the backplane or boards.
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Preserve EMI Compliance
To preserve compliance with applicable standards and regulations for electromagnetic
interference (EMI), during operation all front and rear openings on the chassis or board
face plates must be filled with an appropriate card or covered with a filler panel. If the
EMI barrier is open, devices may cause or be susceptible to excessive interference.
Rear Transition Module
Product Damage
Inserting or removing modules in a non-hot swap chassis with the power applied may
result in damage to the module components. The CPCI-6020-MCPTM-01 is not a hot
swap board, but it may be installed in a hot swap chassis with power applied if the
corresponding CPCI-6020 is removed from the front slot first.
Environment
Always dispose of used AMC modules, system components and RTMs according to
your country’s legislation and manufacturer’s instructions.
Safety Notes
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Safety Notes
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Sicherheitshinweise
Dieses Kapitel enthält Hinweise, die potentiell gefährlichen Prozeduren innerhalb dieses
Handbuchs vorrangestellt sind. Beachten Sie unbedingt in allen Phasen des Betriebs,
der Wartung und der Reparatur des Systems die Anweisungen, die diesen Hinweisen
enthalten sind. Sie sollten außerdem alle anderen Vorsichtsmaßnahmen treffen, die für
den Betrieb des Produktes innerhalb Ihrer Betriebsumgebung notwendig sind. Wenn Sie
diese Vorsichtsmaßnahmen oder Sicherheitshinweise, die an anderer Stelle diese
Handbuchs enthalten sind, nicht beachten, kann das Verletzungen oder Schäden am
Produkt zur Folge haben.
Motorola ist darauf bedacht, alle notwendigen Informationen zum Einbau und zum
Umgang mit dem Produkt in diesem Handbuch bereit zu stellen. Da es sich jedoch um
ein komplexes Produkt mit vielfältigen Einsatzmöglichkeiten handelt, können wir die
Vollständigkeit der im Handbuch enthaltenen Informationen nicht garantieren. Falls Sie
weitere Informationen benötigen sollten, wenden Sie sich bitte an die für Sie zuständige
Geschäftsstelle von Motorola.
EMV
Das System erfüllt die für die Industrie geforderten Sicherheitsvorschriften und darf
ausschließlich für Anwendungen in der Telekommunikationsindustrie und im
Zusammenhang mit Industriesteuerungen verwendet werden.
Einbau, Wartung und Betrieb dürfen nur von durch Motorola ausgebildetem oder im
Bereich Elektronik oder Elektrotechnik qualifiziertem Personal durchgeführt werden.
Die in diesem Handbuch enthaltenen Informationen dienen ausschließlich dazu, das
Wissen von Fachpersonal zu ergänzen, können dieses jedoch nicht ersetzen.
Halten Sie sich von stromführenden Leitungen innerhalb des Produktes fern. Entfernen
Sie auf keinen Fall Abdeckungen am Produkt. Nur werksseitig zugelassenes
Wartungspersonal oder anderweitig qualifiziertes Wartungspersonal darf Abdeckungen
entfernen, um Komponenten zu ersetzen oder andere Anpassungen vorzunehmen.
Installieren Sie keine Ersatzteile oder führen Sie keine unerlaubten Veränderungen am
Produkt durch, sonst verfällt die Garantie. Wenden Sie sich für Wartung oder Reparatur
bitte an die für Sie zuständige Geschäftsstelle von Motorola. So stellen Sie sicher, dass
alle sicherheitsrelevanten Aspekte beachtet werden.
Das Produkt wurde in einem Motorola Standardsystem getestet. Es erfüllt die für digitale
Geräte der Klasse A gültigen Grenzwerte in einem solchen System gemäß den FCCRichtlinien Abschnitt 15 bzw. EN 55022 Klasse A. Diese Grenzwerte sollen einen
angemessenen Schutz vor Störstrahlung beim Betrieb des Produktes in Gewerbe- sowie
Industriegebieten gewährleisten.
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Sicherheitshinweise
Das Produkt arbeitet im Hochfrequenzbereich und erzeugt Störstrahlung. Bei
unsachgemäßem Einbau und anderem als in diesem Handbuch beschriebenen Betrieb
können Störungen im Hochfrequenzbereich auftreten.
Wird das Produkt in einem Wohngebiet betrieben, so kann dies mit grosser
Wahrscheinlichkeit zu starken Störungen führen, welche dann auf Kosten des
Produktanwenders beseitigt werden müssen. Änderungen oder Modifikationen am
Produkt, welche ohne ausdrückliche Genehmigung von Motorola ECC durchgeführt
werden, können dazu führen, dass der Anwender die Genehmigung zum Betrieb des
Produktes verliert. Boardprodukte werden in einem repräsentativen System getestet,
um zu zeigen, dass das Board den oben aufgeführten EMV-Richtlinien entspricht. Eine
ordnungsgemässe Installation in einem System, welches die EMV-Richtlinien erfüllt,
stellt sicher, dass das Produkt gemäss den EMV-Richtlinien betrieben wird. Verwenden
Sie nur abgeschirmte Kabel zum Anschluss von Zusatzmodulen. So ist sichergestellt,
dass sich die Aussendung von Hochfrequenzstrahlung im Rahmen der erlaubten
Grenzwerte bewegt.
Warnung! Dies ist eine Einrichtung der Klasse A. Diese Einrichtung kann im
Wohnbereich Funkstörungen verursachen. In diesem Fall kann vom Betreiber verlangt
werden, angemessene Maßnahmen durchzuführen.
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Betrieb
Beschädigung des Produktes
Hohe Luftfeuchtigkeit und Kondensat auf der Oberfläche des Produktes können zu
Kurzschlüssen führen.
Betreiben Sie das Produkt nur innerhalb der angegebenen Grenzwerte für die relative
Luftfeuchtigkeit und Temperatur. Stellen Sie vor dem Einschalten des Stroms sicher,
dass sich auf dem Produkt kein Kondensat befindet.
Überhitzung und Beschädigung des Produktes
Betreiben Sie das Produkt ohne Zwangsbelüftung, kann das Produkt überhitzt und
schließlich beschädigt werden.
Bevor Sie das Produkt betreiben, müssen Sie sicher stellen, dass das Shelf über eine
Zwangskühlung verfügt.
Anforderungen hinsichtlich Signalverbindungen
Stellen Sie sicher, dass J3, J4 und J5 Signale nicht über die Backplane mit anderen Slots
verbunden sind.
Setzen Sie die VIO der Backplane auf entweder +3.3 V oder +5 V, gemäss den jeweiligen
Systemanforderungen.
Sicherheitshinweise
Datenverlust
Das Herunterfahren oder die Deinstallation eines Boards bevor das Betriebssystem oder
andere auf dem Board laufende Software ordnungsmemäss beendet wurde, kann zu
partiellem Datenverlust sowie zu Schäden am Filesystem führen.
Stellen Sie sicher, dass sämtliche Software auf dem Board ordnungsgemäss beendet
wurde, bevor Sie das Board herunterfahren oder das Board aus dem Chassis entfernen.
Datenverlust
Obwohl das Board über ein Softwarekommando verfügt, welches das Löschen und die
Neuprogrammierung eines Flashes erlaubt, beachten Sie, dass die Neuprogrammierung
auch nur irgendeines Abschnittes des Flashes (Bank B) auf dem CPCI-6020 zur
Löschung sämtlicher Inhalte des Flashes führt, einschliesslich des PPC-Debuggers.
Gehen Sie sehr sorgfältig vor, wenn Sie einen Flash löschen oder neu programmieren.
Weitere Informationen finden Sie in den Softwarebeschreibungen im Abschnitt
Appendix A, Related Documentation.
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Sicherheitshinweise
Installation
Schwere Verletzungen oder Tod
Dieses System wird mit gefährlichen Spannungen betrieben, die schwere Verletzungen
oder Tod verursachen können.
Gehen Sie deshalb extrem vorsichtig vor, wenn Sie mit dem System oder seinen
Komponenten umgehen, es testen oder anpassen.
Beschädigung des Produktes und von Zusatzmodulen
Fehlerhafte Installation von Zusatzmodulen, kann zur Beschädigung des Produktes und
der Zusatzmodule führen.
Lesen Sie daher vor der Installation von Zusatzmodulen die zugehörige Dokumentation.
Beschädigung von Schaltkreisen
Elektrostatische Entladung und unsachgemäßer Ein- und Ausbau des Produktes kann
Schaltkreise beschädigen oder ihre Lebensdauer verkürzen.
Bevor Sie das Produkt oder elektronische Komponenten berühren, vergewissern Sie
sich, daß Sie in einem ESD-geschützten Bereich arbeiten.
Beschädigung des Boards
Die Installation oder Deinstallation eines nicht HA-fähigen Modules in ein System/aus
einem System, dessen Spannungsversorgung eingeschaltet ist, kann zur Beschädigung
des Modules führen.
Stellen Sie sicher, dass das Modul HA-fähig ist.
Beschädigung des Produktes
Vermeiden Sie eine mögliche Beschädigung des Modules, indem Sie sicherstellen, dass
der zu verwendende Slot für Ihr Modul und Ihre Systemkonfiguration geeignet ist.
Überprüfen Sie, bevor Sie das Modul installieren, die grafischen Symbole und die mit
Farbcodes versehenen Führungsschienen. Diese geben Auskunft über den
Verwendungszweck des Slots.
Beschädigung des Produktes, der Backplane oder von System Komponenten
Verbogene Pins oder lose Komponenten können zu einer Beschädigung des Produktes,
der Backplane oder von Systemkomponenten führen.
Überprüfen Sie daher das Produkt sowie die Backplane vor der Installation sorgältig und
stellen Sie sicher, dass sich beide in einwandfreien Zustand befinden und keine Pins
verbogen sind.
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Sicherheitshinweise
Motorola Embedded Communications Computing (ECC) und unsere Zulieferer
unternehmen größte Anstrengungen um sicherzustellen, dass sich Pins und Stecker
von Boards vor dem Verlassung der Produktionsstätte in einwandfreiem Zustand
befinden. Verbogene Pins, verursacht durch fehlerhafte Installation oder durch
Installation von Boards mit beschädigten Steckern kann die durch ECC gewährte
Garantie für Boards und Backplanes erlöschen lassen.
Sicherstellung der EMV-Konformität
Stellen Sie sicher, dass während des Betriebes alle Slots an der Vorder- und Rückseite
des Chassis entweder mit einem geeignetem Board/Module oder mit einer Blindblende
bestückt sind. So ist sichergestellt, dass alle Standards und Richtlinien hinsichtlich EMV
erfüllt sind. Sobald die EMV-Abschirmung des Chassis durchlässig wird, können
Boards/Module sowohl starke Störstrahlung aussenden als auch selber starker
Störstrahlung ausgesetzt sein.
Rear Transition Module
Beschädigung des Produktes
Die Installation oder Deinstallation eines Modules in ein nicht Hot-Swap-fähiges
System/aus einem nicht Hot-Swap-fähigem System, dessen Spannungsversorgung
eingeschaltet ist, kann zur Beschädigung des Modules führen. Das CPCI-6020-MCPTM01 ist kein Hot-Swap-fägiges Board, aber es kann in ein Hot-Swap-fähiges Chassis
installiert werden bei eingeschalteter Spannungsversorgung, unter der Voraussetzung,
dass das zugehörige CPCI-6020-Board zuvor aus dem Slot an der Vorderseite entfernt
wurde.
Umweltschutz
Entsorgen Sie alte Batterien und/oder Blades/Systemkomponenten/RTMs stets gemäß
der in Ihrem Land gültigen Gesetzgebung, wenn möglich immer umweltfreundlich.
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Sicherheitshinweise
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Introduction
1.1 Features
The following table summarizes the features of the CPCI-6020 single-board computers.
Table 1-1 Features
Feature Description
Processor Single MPC7410 Processor
L2 Cache 2 MB back side L2 Cache using pipeline burst-mode SRAMS
Flash Xport Channel 0 (Bank A): 32 MB on-board using one 256 megabit device.
SDRAM Double-Bit-Error detect, Single-Bit-Error correct across 72 bits
Memory Controllers Harriers’ SMC (System Memory Controller).
PCI Host Bridges Harriers’ PHB (PCI Host Bridge).
Interrupt Controller Harriers’ MPIC (Multi-Processor Interrupt Controller).
PCI Interfaces Dual 33 MHz, 32/64-bit PCI 2.1 busses bridging from the processor bus, one
Ethernet Interface Two 10BaseT/100BaseTx interfaces based on Intel 82551IT device.
SROM Two 8 KB dual-address I
CompactPCI
Interface
Form Factor 6U Eurocard
1
Core Frequency up to 500 MHz for MPC7410
Bus Clock Frequency of 100 MHz
Address and data bus parity
Data bus parity
Xport Channel 1 (Bank B): 1 MB socketed flash using two 512 kilobit devices.
Bank A/B Reset vector select jumpers.
Two connectors, one behind each Harrier, for use with RAM500 stacking
SDRAM mezzanines. Using 512 megabit SDRAM devices on the mezzanine
will allow a maximum of 2 GB memory.
PCI Bus also capable of 66 MHz
+3.3 V/+5 V universal signaling interface
One PMC slot
Connection through the J4 connector to the backplane
Address/data parity per PCI specification
One port is routed to the backplane, the other port is routed to front panel
(standard product). The latter port can also be routed to backplane, but it is
determined by a custom-build option. Contact the custom solution center for
more information.
AT93C46 SROMs for 82551IT configuration
2
and user configuration data
256-byte standard I2C serial EEPROMs (on mezzanines) for memory SPD
Intel 21154 PCI-to-PCI Bridge interfaces to Compact PCI Bus
Capable of driving seven slots
64-bit primary bus/64-bit secondary bus interface
Up to 33 MHz operation
C serial EEPROM devices for Vital Product Data
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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Introduction Standard Compliances
Table 1-1 Features (continued)
Feature Description
RTC/NVRAM 32 KB NVRAM/RTC/WDT provided by M48T37V
Connected to Harrier A Xport 2 configured as 8-bit port
Watchdog Timers Two independent programmable timers in each Harrier
One programmable timer in M48T37V
Peripheral Support USB host/hub interface
10BaseT/100BaseTX Ethernet interface
IDE Interface for IDE flash and external IDE drive support
Two 16550-compatible async serial ports (Harrier UART0/UART1)
Two sync/async serial ports
CPCI-6020 (5E Only)
One PS/2 Keyboard and one PS/2 Mouse
Floppy disk controller
PMC Slot One 32/64-bit PMC slot with front-panel I/O plus rear I/O, 33/66 MHz capable
Local PCI Bus
Expansion
Front Panel Asynchronous COM port via RJ-45
Debug Support 16550-compatible async serial port (in Harrier) with RS-232 interface
Local 64-bit PCI bus routed to J4 to support additional PCI-to-PCI bridge and
CompactPCI bus on companion card
10/100 MB Ethernet via RJ-45
Two USB ports
Recessed RESET and ABORT switches
CPU Activity and Board Fail LEDs
Switch in handle to support hot swap
Processor JTAG Interface
RESET and ABORT signals
Access to processor bus via Mictor connector
1.2 Standard Compliances
The CPCI-6020 is designed to be CE compliant and to meet the following standard
requirements.
Table 1-2 Board Standard Compliances
Standard Description
32
UL 60950-1
EN 60950-1
IEC 60950-1
CAN/CSA C22.2 No 60950-1
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
Safety Requirements (legal)
Page 33
Ordering Information Introduction
Table 1-2 Board Standard Compliances (continued)
Standard Description
CISPR 22
CISPR 24
EN 55022
EN 55024
FCC Part 15
Industry Canada ICES-003
VCCI Japan
AS/NZS CISPR 22
EN 300 386
NEBS Standard GR-1089 CORE
NEBS Standard GR-63-CORE
ETSI EN 300 019 series
Directive 2002/95/EC Directive on the restriction of the use of certain hazardous
EMC requirements (legal) on system level (predefined Motorola
system)
Environmental Requirements
substances in electrical and electronic equipment (RoHS)
1.3 Ordering Information
When ordering board variants or board accessories, use the order numbers given in the
following tables.
1.3.1 Supported Board Models
At the time of publication of this manual, the CPCI-6020 Single Board Computer is available in
the configurations shown below. Memory is purchased separately according to the following
table.
Model Number Description
CPCI-60206E-500 MPC7410, 500 MHz, memory separate (configured), no Super I/O
CPCI-60206E-505 MPC7410, 500 MHz, memory separate (configured), no USB, no Super
CPCI-6020-500 MPC7410, 500 MHz, memory separate (configured), 5E
CPCI-6020-505 MPC7410, 500 MHz, memory separate (configured), no USB, 5E
I/O
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Introduction Board Accessories
1.3.2 Board Accessories
This table lists the available memory modules and Rear Transition Module available for the
CPCI-6020.
Model Number Description
RAM5006E-005 Top memory: 128 MB
RAM5006E-015 Bottom memory: 128 MB
RAM5006E-006 Top memory: 256 MB
RAM5006E-016 Bottom memory: 256 MB
RAM5006E-010 Top memory: 512 MB
RAM5006E-020 Bottom memory: 512 MB
RAM500-005 Top memory: 128 MB, 5E
RAM500-015 Bottom memory: 128 MB, 5E
RAM500-006 Top memory: 256 MB, 5E
RAM500-016 Bottom memory: 256 MB, 5E
RAM500-010 Top memory: 512 MB, 5E
RAM500-020 Bottom memory: 512 MB, 5E
CFLASH5E-256 CompactFlash 256 MB
CFLASH5E-512 CompactFlash 512 MB
CPCI-60206E-MCPTM-01 CPCI-6020 Rear Transition Module
CPCI-6020-MCPTM-01 CPCI-6020 Rear Transition Module, 5E
SIM232DCE6E Serial Interface Module, EIA-232-D DCE
SIM232DTE6E Serial Interface Module, EIA-232-D DTE
34
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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Hardware Preparation and Installation
2.1 Overview
This chapter provides startup and safety instructions related to this product, hardware
preparation instructions, including: default jumper settings; system considerations, and
installation instructions for the baseboard; as well as the PMC, memory mezzanines, and
transition module associated with this board.
A fully implemented CPCI-6020 consists of the baseboard plus:
z A single-wide PCI mezzanine card (PMC) for added versatility.
z One or two RAM500 SDRAM memory mezzanines per mezzanine site (two sites available)
for a maximum of 2 GB of added memory.
z One CPCI-6020-MCPTM-01 rear transition module for support of the mapped I/O from the
CPCI-6020 baseboard to the J3 and J5 CompactPCI connectors.
2
2.2 Unpacking and Inspecting the Board
Read all notices and cautions prior to unpacking the product.
Damage of Circuits
Electrostatic discharge and incorrect installation and removal can damage circuits or
shorten their life.
Before touching the AMC or electronic components, make sure that you are working
in an ESD-safe environment.
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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Hardware Preparation and Installation Overview of Start-up Procedure
Shipment Inspection
To inspect the shipment, perform the following steps:
1. Verify that you have received all items of your shipment.
2. Check for damage and report any damage or differences to customer service.
3. Remove the desiccant bag shipped together with the board and dispose of it
according to your country’s legislation.
The product is thoroughly inspected before shipment. If any damage occurred during
transportation or any items are missing, contact customer service immediately.
2.3 Overview of Start-up Procedure
The following table lists the things you will need to do before you can use this board and tells
you where to find the information you need to perform each step. Be sure to read this entire
chapter, including all Caution and Warning notes, before you begin.
Table 2-1 Startup Overview
Task Page
Unpack the hardware. Chapter 2, Unpacking and Inspecting the Board, on
Configure the hardware by setting jumpers
on the boards.
Ensure CompactFlash card is installed (if
required).
Ensure memory mezzanines are properly
installed on the board.
Install PMC Module
(if required).
Install the CPCI-6020 in the chassis. Chapter 2, Installing and Removing a Module, on page
Install PIM on CPCI-6020-MCPTM-01
(if required)
Install peripherals, and any other devices or
equipment used.
Power up the system. Chapter 2, Hardware Preparation and Installation
Ensure that the debugger initializes the
CPCI-6020
page 35
Chapter 2, Jumper Settings, on page 41
Chapter 2, CompactFlash Memory Card Installation,
on page 46
Chapter 6, RAM500 Module Installation, on page 118
Chapter 2, PMC Module Installation, on page 44
51
Chapter 7, Installing the PIM, on page 138
Appendix A, Manufacturers’ Documents, on page 161
Chapter 5, Firmware
36
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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Equipment Required Hardware Preparation and Installation
Table 2-1 Startup Overview (continued)
Task Page
Initialize the system clock. Chapter 5, Firmware
Examine and/or change environmental
parameters.
Program the board as needed for your
applications.
Chapter 8, CNFG and ENV Commands
CPCI-6020 CompactPCI Single Board Computer
Programmer’s Reference Guide
Harrier Application Specific Integrated Circuit (ASIC)
Programmer’s Reference Guide
2.4 Equipment Required
The following equipment is recommended to complete an CPCI-6020 system:
z CompactPCI system enclosure (in compliance with CompactPCI Specification, PICMG 2.0,
Rev. 2.1)
z System console terminal
z Operating system (and/or application software)
z Disk drives (and/or other I/O) and controllers
z Transition module (CPCI-6020-MCPTM-01) and connecting cables
CPCI-6020 modules are designed with front and rear panel I/O. Front panel I/O includes two
USB ports, one Ethernet port (unless run to rear), a UART Port 0 and a PMC I/O port (if a PMC
is installed). The rear panel I/O is provided via a CPCI-6020-MCPTM-01 Transition Module and
includes two Ethernet ports (only port 2 is connected in standard product configuration. Contact
custom solution center for connecting port 1 through custom build options), two USB ports, two
UART ports (one may be run to front), and two synchronous COM ports.
2.5 Environmental and Power Requirements
You must make sure that the blade, when operated in your particular system configuration,
meets the environmental requirements specified in the next section.
2.5.1 Environmental Requirements
The following table lists the currently available specifications for the environmental
characteristics of the CPCI-6020. A complete functional description of the CPCI-6020
baseboard appears in Chapter 4, Functional Description .
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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Hardware Preparation and Installation Environmental Requirements
You must make sure that the board, when operated in your particular system configuration,
meets the environmental requirements specified below.
Operating temperatures refer to the temperature of the air circulating around the board
and not to the component temperature.
Table 2-2 Specifications
Characteristics Operating Nonoperating
Operating temperature 0°C to +55°C (32°F to 131°F) entry
air with forced-air cooling
Temperature change +/-0.5° C/min according to NEBS
Standard GR-63-CORE
Forced Air Flow 250 LFM @ 55°C (131°F ambient
temperature
Relative humidity 5% to 90% 5% to 90%
Vibration 1.0G sine sweep, 5-200 Hz, .25
octaves/min, all 3 axis (operating)
Shock Half-sine, 11 mSec, 30 m/Sec Blade level packaging
Free Fall Blade level packaging
–40°C to +70° C (104°F to ‘158°F)
5-20 Hz @ 0.01 g/Hz
20-200 Hz @ -3.0 dB/octave
Random 5-20 Hz @ 1 m/Sec
Random 20-200 Hz @ -3 dB/oct
Half-sine, 6 mSec at 180 m/Sec
100mm (unpackaged) per GR-63CORE
38
Product Damage
High humidity and condensation on the board surface causes short circuits.
Do not operate the board outside the specified environmental limits.
Make sure the board is completely dry and there is no moisture on any surface before
applying power.
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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Power Requirements Hardware Preparation and Installation
2.5.2 Power Requirements
The CPCI-6020 module draws +3.3VDC, +5VDC, VIO, +12VDC and -12VDC, with a voltage
variation of -/+ 5% from the standard value, from the CompactPCI backplane connector J1.
Typical power consumption of only the CPCI-6020 is approximately 15 W at +5VDC and 9 W at
+ 3.3VDC.
Table 2-3 Baseboard and RTM Power Requirements
Board ID +3.3 V +5 V +12 V
CPCI-6020-500 2.6 A typ 2.8 A typ. 15 mA typ.
3.5 A max 3.75 A max. 20 mA max.
CPCI-6020-MCPTM-01 0.0 A typ. 50 mA typ 0.0 A typ.
0.0 A max. 100 mA max. 0.0 A max.
The CPCI-6020 supplies +3.3VDC, +5.0VDC, +12VDC and -12VDC to J3 and J5 for use by the
transition module. Separately fused +5VDC is also provided for the keyboard/mouse. Separate
+5VDC fused power is also provided for each USB channel and the PMC slot +5VDC.
No more than 0.5 of an amp is allowed per power pin (IEEE 1386.1 specification) on any power
connector.
2.5.3 Thermal Requirements
The CPCI-6020 module requires a minimum air flow of 250 LFM when operating at a 55°C
(131°F) ambient temperature.
Most of the heat is generated by CPU at the top layer. Make sure that there is sufficient airflow
to the CPU heatsink.
2.6 Hardware Configuration
To produce the desired configuration and ensure proper operation of the CPCI-6020, you may
need to carry out certain hardware modifications before installing the module.S ome hardware
modifications are controlled through manual installation or removal of header jumpers or
interface modules on the baseboard or the associated transition module. These modifications
are described in the next section.
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Hardware Preparation and Installation CPCI-6020 Baseboard Preparation
The CPCI-6020 also provides configuration modification via software control by setting bits in
control registers after installing the module in a system. The CPCI-6020 control registers are
described in the CPCI-6020 CompactPCI Single Board Computer Programmer’s Reference
Guide, and the Harrier Application Specific Integrated Circuit (ASIC) Programmer’s Reference
Guide.
2.7 CPCI-6020 Baseboard Preparation
Prior to installing any memory, flash, or PMC modules on the CPCI-6020 baseboard, ensure
that all jumpers that are user configurable are set properly. To do this, refer to Figure 2-1 or the
board itself for the location of specific jumpers. Set the jumpers according to the following
descriptions. Manually configured items on the baseboard include:
z Flash bank selection (J24)
z Harrier Power up configuration header (J22)
z PMC 66 MHz optional setting (J21)
z Enable/disable +12 V and -12 V use on the CPCI-6020 (J18)
z Enable/disable lockdown of one or more flash blocks of Bank A (J17)
z Enable/disable write-protect for all of flash Bank A (J20)
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CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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Jumper Settings Hardware Preparation and Installation
z Remote switch (J19)
z Jumpers J7 and J25 are only for factory use
Figure 2-1 Header Locations and Jumper Settings
J18
J19
J17
U18
U19
J21
2.8 Jumper Settings
The following sections describe the on-board jumpers and their configurations for the CPCI-
6020. For jumper locations, see Figure 2-1.
2.8.1 Flash Bank Selection
The CPCI-6020 contains one bank of 32 MB 16-bit flash memory soldered on-board (Bank A)
and 1 MB of 16-bit socketed flash memory (Bank B). Bank A is 64-bits wide and Bank B is 16bits wide. Bank B contains the on-board debugger and diagnostics, PPCBug.
U31
J20
1
3
J24
J22
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Hardware Preparation and Installation Harrier Power Up Configuration Header
To enable Flash Bank A, place a jumper across pins 1 and 2 of header J24. To enable Flash
Bank B, place a jumper across pins 2 and 3 of header J24.
J24 Jumper On
1-2 Flash Bank A Enabled (32 MB, soldered)
2-3 Flash Bank B Enabled (1 MB, sockets)
Factory Configuration
2.8.2 Harrier Power Up Configuration Header
A 2 mm, 8-pin low profile header located on side 1 of the CPCI-6020 provides the means to
change some of the Harrier power up configuration settings. The pin assignments for this
header, along with the power up setting with the jumper on or off, are as follows (boards are
shipped with all jumpers off):
J22 Jumper On Jumper Off
1-2 PUST0 = 0
Harrier PUST Bit 0 in GCSR Register
3-4 PUST1 = 0
Harrier PUST Bit 1 in GCSR Register
5-6 PUST2 = 0
Harrier PUST Bit 2 in GCSR Register
7-8 PUST3 = 0
Harrier PUST Bit 2 in GCSR Register
PUST0 = 1
PUST1 = 1
PUST2 = 1
PUST3 = 1
2.8.3 PMC 66 MHz Disable
This 0.1 inch, 2-pin header (J21) located on the CPCI-6020 is used to disable 66 MHz
operation on PCI Bus B. When a jumper is installed between pins 1 and 2, PCI Bus B will
operate at 33 MHz regardless of whether the PMC is capable of 66 MHz. This prevents the
secondary Ethernet controller from being disabled if a 66 MHz capable PMC is installed. The
jumper pulls the M66EN signal low so the PMC can be aware that the bus is operating at 33
MHz.
J21
GND
M66EN
2.8.4 Enable/Disable +12 V and -12 V Use
This 0.1 inch, 2-pin header (J18) located on the CPCI-6020 is used to disable +/-12 V on the
board.
42
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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Enable/Disable Lockdown of One or More Flash Blocks for Bank A Hardware Preparation and Installation
When using the +12 V and -12 V power disable (J18 jumper is installed), +12 V and -12 V power
is not provided to on-board CPCI-6020 electronics or to the rear transition module. This may
affect operation of any modules installed, such as: a PMC on the CPCI-6020 or a PIM or SIM
on the rear transition module. For example, COM Port 3 and COM Port 4 on the rear transition
module will not operate when the J18 jumper is installed. Generally, this jumper should be
installed when there is no +/-12 V power coming from the chassis.
2.8.5 Enable/Disable Lockdown of One or More Flash Blocks for Bank A
This 0.1 inch, 2-pin header (J17) located on the CPCI-6020 is used to enable lockdown of one
or more flash blocks of bank A. When a jumper is installed between pins 1 and 2, one or more
blocks of bank A are locked. Blocks in lockdown cannot be unlocked with the Flash Unlock
command.
2.8.6 Enable Write-Protect for Entire Flash on Bank A
This 0.1 inch, 2-pin header (J20) located on the CPCI-6020 is used to enable write-protect for
the entire flash on bank A. When a jumper is installed between pins 1 and 2, memory contents
cannot be altered in the entire flash.
2.8.7 Remote Switch
This 0.1 inch, 3-pin header (J19) located on the CPCI-6020 allows you to connect a remote
switch that performs the same function as front panel reset and abort switch. The pin
configuration is as follows:
Pin # Signal
1 Abort
2GND
3 RESET
2.9 Hardware Installation
The following sections discuss the installation of a PMC module on the CPCI-6020 baseboard,
the installation of CompactFlash, and the installation of the complete CPCI-6020 assembly into
a CompactPCI chassis. Also described are the start-up procedure and system considerations
relevant to installation. Before installing the CPCI-6020, ensure that the serial ports and all
jumpers are properly configured, refer t o CPCI-6020 Baseboard Preparation on page 40 and
Preparing the Transition Module on page 131 for serial port configurations.
In most cases, the memory mezzanine card (RAM500) is already in place on the baseboard.
The user-configured jumpers are accessible with the mezzanines installed. At least one
RAM500 memory mezzanine card must be installed on the CPCI-6020 prior to operation in
order for the board to function properly. To install one or more RAM500 memory mezzanine
cards, refer to Chapter 6, RAM500 Memory Expansion Module.
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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Hardware Preparation and Installation PMC Module Installation
Should it be necessary to install a PMC mezzanine on the baseboard, refer to PMC Module
Installation in this chapter for a description of that installation procedure.
Damage of Circuits
Electrostatic discharge and incorrect module installation and removal can damage
circuits or shorten their life.
Before touching the module or electronic components, make sure that you are
working in an ESD-safe environment.
2.10 PMC Module Installation
Procedure
The PCI mezzanine card (PMC) module mounts beside the RAM500 mezzanine on top of the
CPCI-6020 baseboard. To install a PMC module, proceed as follows:
1. Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the
chassis as a ground. The ESD strap must be secured to your wrist and to ground
throughout the procedure.
2. If the PMC module is being installed in a non-hot swap chassis, perform an
operating system shutdown. Turn the AC or DC power off and remove the AC cord
or DC power lines from the system. Remove the chassis or system cover(s) as
necessary for access to the CompactPCI.
Product Damage
Inserting or removing PMC modules with power applied may result in damage to
module components.
Before installing or removing additional devices or modules, read the documentation
that came with the product.
Personal Injury or Death
Dangerous voltages capable of causing death exist.
To prevent injury, use extreme caution when handling, testing and adjusting this
equipment.
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PMC Module Installation Hardware Preparation and Installation
3. Carefully remove the CPCI-6020 from the CompactPCI card slot and place it on a
clean and adequately protected working surface with connectors J1 through J5
facing you.
Product Damage
Avoid touching areas of integrated circuitry; static discharge can damage these
circuits.
Before touching the board or electronic components, make sure you are working in
an ESD-safe environment.
4. Remove the PCI filler from the front panel.
5. Slide the edge connector of the PMC module into the front panel opening from
behind and place the PMC module on top of the baseboard. The four connectors on
the underside of the PMC module should then connect smoothly with the
corresponding connectors (J11/12/13/14) on the CPCI-6020.
6. Insert the four short phillips-head screws (provided with the PMC) through the holes
on the bottom side of the CPCI-6020 and the PMC front bezel and into rear
standoffs. Tighten the screws.
7. Reinstall the CPCI-6020 assembly in its proper card slot. Be sure the module is well
seated in the backplane connectors. Do not damage or bend connector pins.
8. If the PMC module was installed in a non-hot swap chassis, replace the chassis or
system cover(s), reconnect the system to the AC or DC power source and turn the
equipment power on.
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Hardware Preparation and Installation CompactFlash Memory Card Installation
2.11 CompactFlash Memory Card Installation
Procedure
The CompactFlash memory card mounts on the CPCI-6020 baseboard. To upgrade or install a
CompactFlash memory card, refer to the next figure and proceed as follows:
1. Attach an ESD strap to your wrist. Attach the other end of the strap to the chassis
(for proper grounding). The ESD strap must be secured to your wrist and to chassis
ground throughout the procedure.
2. If you are installing the board in a non-hot swap chassis, perform an operating
system shutdown. Turn the AC or DC power off and remove the AC cord or DC
power lines from the system. Remove the chassis or system cover(s) as necessary
to access the compact PCI module.
Board Damage
Inserting or removing modules that are not HA capable with power applied may result
in damage to module components.
Verify that your board is HA capable.
46
Personal Injury
Dangerous voltages capable of causing death exist.
To prevent injury, use extreme caution when handling, testing and adjusting this
equipment.
3. Carefully remove the CPCI-6020 from the CompactPCI card slot and place it on a
clean and adequately protected working surface with connectors J1 through J5
facing you.
Product Damage
Avoid touching areas of integrated circuitry; static discharge can damage these
circuits.
Before touching the board or electronic components, make sure you are working in
an ESD-safe environment.
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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Before You Install or Remove a Board Hardware Preparation and Installation
4. Slide the CompactFlash memory card into the J15 connector and make sure that
pin 1 of the card aligns with pin 1 of J15.
Insert CompactFlash
5. If you are installing RAM500 memory cards or a PMC module on this board, follow
the installation instructions in Chapter 6, RAM500 Memory Expansion Module, on
page 117 and PMC Module Installation on page 44. If not, read the next section nad
then reinstall the CPCI-6020 assembly in the proper card slot. Check that the board
is properly seated in the backplane connectors. Take care not to damage or bend
connector pins.
2.12 Before You Install or Remove a Board
Boards may be damaged if improperly installed or handled. Please read and follow the
guidelines in this section to protect your equipment.
Damage of Circuits
Electrostatic discharge and incorrect board installation and removal can damage
circuits or shorten their life
Before touching the board or electronic components make sure that you are working
in an ESD-safe environment.
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Hardware Preparation and Installation Watch for Bent Pins or Other Damage
2.12.1 Watch for Bent Pins or Other Damage
Product Damage
Bent pins or loose components can cause damage to the board, the backplane or
other system components.
Carefully inspect your board and the backplane for both pin and component integrity
before installation.
ECC and our suppliers take significant steps to ensure there are no bent pins on the backplane
or connector damage to the boards prior to leaving our factory. Bent pins caused by improper
installation or by boards with damaged connectors could void the ECC warranty for the
backplane or boards.
If a system contains one or more crushed pins, power off the system and contact your local
sales representative to schedule delivery of a replacement chassis assembly.
2.12.2 Use Caution When Installing or Removing Boards
Product Damage
Bent pins or loose components can cause damage to the board, the backplane or
other system components.
Carefully inspect your board and the backplane for both pin and component integrity
before installation.
When first installing boards in an empty chassis, we recommend that you start at the left of the
card cage and work to the right when cards are vertically aligned; in horizontally aligned cages,
work from bottom to top.
When inserting or removing a board in a slot adjacent to other boards, use extra caution to
avoid damage to the pins and components located on the primary or secondary sides of the
boards.
2.12.3 Understanding Hot Swap
The PICMG 2.1 Hot Swap specification defines varying levels of hot swap. A board that is
compliant with the specification can be inserted and removed safely with system power on
without damage to on-board circuitry. If a module is not hot swap compliant, you should
remove power to the slot or system before inserting or removing the module.
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Recognize Different Injector/Ejector Lever Types Hardware Preparation and Installation
The CPCI-6020 does not support a hot swap LED. You may need to manually shut down
applications or operating systems running on the board prior to board removal.
Data Loss
Powering down or removing a board before the operating system or other software
running on the board has been properly shut down may cause corruption of data or
file systems.
Make sure all software is completely shut down before removing power from the
board or removing the board from the chassis.
Refer to the documents listed in Appendix A, Related Documentation for more information
about hot swap and the PCI Industrial Computer Manufacturers Group (PICMG) Hot Swap
Specification.
2.12.4 Recognize Different Injector/Ejector Lever Types
The modules you install may have different ejector handles and latching mechanisms. The
following illustration shows the typical board ejector handles used with ECC payload cards: (A)
Elma Latching, (B) Rittal Type II, (C) Rittal Type IV. All handles are compliant with the
CompactPCI specification and are designed to meet the IEEE1101.10 standards.
Figure 2-2 Injector/Ejector Lever Types
B CA
Each lever type has a latching mechanism to prevent the lever from being opened accidentally.
You must press the lever release before you can open the lever. Never force the lever. If the
lever does not open easily, you may not have pressed firmly enough on the release. If the lever
does not close easily, the board may not be properly seated in the chassis.
z To open a lever, press the release and move the lever outward away from the face plate.
z To close a lever, move the lever inward toward the face plate until the latch engages.
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Hardware Preparation and Installation Verify Slot Usage
2.12.5 Verify Slot Usage
Product Damage
Prevent possible damage to module components by verifying the proper slot usage
for your configuration.
Check the icons and colored card rails for slot purpose prior to installing a module.
In most cases, connector keying will prevent insertion of a board into an incompatible slot.
However, as an extra precaution, you should be familiar with the glyphs and colored card rails
used to indicate slot purpose.
The following table lists the colors and glyphs common to ECC chassis.
Table 2-4 Slot Usage Indicators
Card Rail
Color Glyph Usage
Tan none MXP: Alarm Management Controller slot
CPX: Hot Swap Controller or Bridge slot
Red MXP: Fabric Switch Card slot
CPX: System Controller slot
Black MXP: Payload Card slot
CPX: Non-system Controller or I/O Card slot
2.12.6 Preserve EMI Compliance
Preserve EMI Compliance
To preserve compliance with applicable standards and regulations for
electromagnetic interference (EMI), during operation all front and rear openings on
the chassis or board face plates must be filled with an appropriate card or covered
with a filler panel. If the EMI barrier is open, devices may cause or be susceptible to
excessive interference.
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Installing and Removing a Module Hardware Preparation and Installation
2.13 Installing and Removing a Module
This section describes a recommended procedure for installing and removing a board module
in a chassis. Before you install your module, please read all cautions, warnings and instructions
presented in this section and the guidelines explained in Before You Install or Remove a Board
on page 47.
Installation Procedure
Hot swap compliant modules may be installed while the system is powered on. If a module is
not hot swap compliant, you should remove power to the slot or system before installing the
module. See Understanding Hot Swap on page 48 for more information.
Signaling Requirements
Ensure the backplane does not bus J3, J4 or J5 signals to other slots.
Set the VIO on the backplane to either +3.3 V or +5 V, depending upon your system’s
signaling requirements.
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Hardware Preparation and Installation Installing and Removing a Module
Refer to the following illustration and perform these steps when installing modules. Note that
this illustration is for general reference only and may not accurately depict the connectors and
handles on the board you are installing.
Stage 2
(Detail)
J5
P5
J4
P4
J3
P3
J2
P2
J1
P1
J5
P5
J4
P4
J3
P3
J2
P2
J1
P1
Stage 1 Stage 3Stage 2
1. Open the injector levers on your board (see Recognize Different Injector/Ejector
Lever Types on page 49).
2. Verify the proper slot for the module you are inserting (see Verify Slot Usage on
page 50). Align the edges of the module with the card cage rail guides in the
appropriate slot. Insert the board by holding the injector levers, do not exert
unnecessary pressure on the face plate.
3. Using your thumbs, apply equal and steady pressure as necessary to carefully slide
the module into the card cage rail guides (Stage 1). Continue to gently push until the
prealignment guide pegs engage with the backplane connector (Stage 2) and the
injector levers make contact with the chassis rails. Do not force the board into the
backplane slot.
52
4. Use the injector levers to seat the module in the slot by closing the levers until they
latch into the locked position (Stage 3). If the levers do not completely latch, remove
the module from the chassis and visually inspect the slot to ensure there are no bent
pins.
5. When the module you are installing is completely latched, secure it by tightening the
captive screws at both ends of the face plate.
This section describes a recommended procedure for removing a board module from a chassis.
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Installing and Removing a Module Hardware Preparation and Installation
Before you remove your module, please read all cautions, warnings and instructions presented
in this section and the guidelines explained in Before You Install or Remove a Board on page 47.
Hot swap compliant modules may be removed while the system is powered on. If a module is
not hot swap compliant, you should remove power to the slot or system before removing the
module. See Understanding Hot Swap on page 48 for more information.
Data Loss
Powering down or removing a board before the operating system or other software
running on the board has been properly shut down may cause corruption of data or
file systems.
Make sure all software is completely shut down before removing power from the
board or removing the board from the chassis.
Removal Procedure
To remove a board module, follow these steps:
1. Loosen the module’s captive screws at both ends of the front panel.
2. Begin to remove your module by unlatching the ejector lever (the lower lever on
vertically mounted boards). See Recognize Different Injector/Ejector Lever Types on
page 49. Do not remove the module immediately.
3. Once the applications and operating system running on the board have stopped and
it is safe to remove the board, open both ejector levers to partially unseat the module
from the backplane connectors.
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Hardware Preparation and Installation Startup and Operation
If your module is hot swap compliant and you are running fully functional hot swapaware software, unlatching this ejector lever will start the shutdown process on the
board.
4. Carefully pull the module from the chassis.
2.14 Startup and Operation
This section describes startup information used with the CPCI-6020 family of single board
computers in a system configuration. The information includes system considerations, a brief
explanation and graphic of the power-up sequence performed by the firmware.
Power-up Procedure
Perform the following steps to ensure proper board operation:
1. Before applying power, ensure you configure the hardware properly (for example,
jumper settings, memory installation, flash installation, PMC installation and other
hardware features).
2. Check all connections and ensure the installation is complete (cabling, transition
module connections, if applicable).
3. Once everything is verified, power up the system.
When the power is turned on, the MPU, the hardware and the firmware initialization processes
are performed. The firmware initializes the devices on the CPCI-6020 in preparation for booting
the operating system.
The firmware is shipped from the factory with an appropriate set of defaults. In most cases, it is
not necessary to modify the firmware configuration before booting the operating system.
54
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System Considerations Hardware Preparation and Installation
The following flowchart shows the basic initialization process that takes place during system
startup. Refer to a detailed initialization list in Chapter 5, Firmware, on page 107.
Figure 2-3 Start Up Flow Diagram
Startup
System
Initialization
Console Detection
Run Self Tests
(if enabled)
Auto Boot
(if enabled)
Operating
System
2.15 System Considerations
The CPCI-6020 is designed to operate as a CompactPCI system slot board. As a system slot
board, the CPCI-6020 provides system clocks and arbitration for other peripheral slots in the
subrack. Consequently, the CPCI-6020 must be installed in a subrack system slot marked with
a triangle symbol.
The CPCI-6020 provides seven peripheral slot clock outputs (CLK0-CLK6) per CompactPCI
specification 2.0 R2.1. Arbitration for the seven peripheral slot bus masters is provided by the
CPCI-6020.
On the CPCI-6020 baseboard, the standard serial console port (COM1) serves as the PPCBug
debugger console port. The firmware console should be set up as follows:
z Eight bits per character
z One stop bit per character
z Parity disabled (no parity)
z Baud rate of 9600 baud
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Hardware Preparation and Installation System Considerations
A default baud rate of 9600 is used for serial ports on CPCI-6020 boards. After power-up, the
baud rate can be changed using the PPCBug PF (Port Format) command via the command line
interface. Whatever the baud rate, some type of hardware handshaking; either XON/OFF or via
the RTS/CTS line is desirable if the system supports it.
56
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Controls, LEDs, and Connectors
3.1 Overview
This chapter summarizes the controls, LEDs, and pin assignments for the CPCI-6020
baseboard. Controls, LEDs, and pin assignments for the CPCI-6020-MCPTM-01 transition
module and RAM500 memory modules can be found in Chapter 7, Transition Module
Preparation and Installation and Chapter 6, RAM500 Memory Expansion Module respectively.
3.2 CPCI-6020 Baseboard Layout
The next figure illustrates the placement of the headers, connectors and LED indicators on the
CPCI-6020.
Figure 3-1 Headers, Connectors and LEDs
3
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Controls, LEDs, and Connectors Front Panel Connectors and LEDs
3.3 Front Panel Connectors and LEDs
The CPCI-6020 front panel provides access to recessed Abort and Reset push-button
switches, Board Fail, and CPU Bus Activity LEDs, an RJ-45 Ethernet connector, an RJ-45 serial
port connector, two USB connectors and the PMC front panel.
This section describes the baseboard connectors and LEDs.
Figure 3-2 Front Panel Connectors and LEDs
10/100 BASE T
USB1
PCI MEZZANINE CARD
COM1
ABT
RST
CPU
FAIL
USB0
HOLD
3.3.1 Front Panel Ethernet Port
A 10BaseT/100BaseTx RJ-45 receptacle is located on the front panel of the CPCI-6202 to
provide Ethernet I/O. The pin assignments for this connector are:
Table 3-1 Ethernet Connector Pin Assignments
58
Pin Signal
1TD+
2TD-
3RD+
4 AC Terminated
5 AC Terminated
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Front Panel Asynchronous Serial Port Controls, LEDs, and Connectors
Table 3-1 Ethernet Connector Pin Assignments (continued)
Pin Signal
6RD-
7 AC Terminated
8 AC Terminated
3.3.2 Front Panel Asynchronous Serial Port
An RJ-45 receptacle is located on the front panel of the CPCI-6020 to provide the interface to
the COM1 serial port. This port is configured as DCE. The pin assignments for this connector
is as follows:
Table 3-2 COM1 Pin Assignments
Signal Pin
1DCD
2RTS
3GND
4TXD
5RXD
6GND
7CTS
8DTR
3.3.3 Front Panel USB ports
There are two USB Series A receptacles located on the front panel of the CPCI-6020. The pin
assignments are shown in the next tables:
Table 3-3 USB Port 1
Pin Number Pin Name
1 USBVOUT1
2 USB1DATA_N
3 USB1DATA_P
4GND
Table 3-4 USB Port 0
Pin Name Pin Number
1 USBVOUT0
2 USB0DATA_N
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Controls, LEDs, and Connectors ABORT# Switch
Table 3-4 USB Port 0 (continued)
Pin Name Pin Number
3 USB0DATA_P
4GND
3.3.4 ABORT# Switch
The ABORT# switch is recessed to reduce the likelihood of accidental activation. The ABORT#
signal is connected to the Harrier Abort Switch (ABTSW_L) input and generates an MPIC
internal interrupt. This signal is debounced in the Harrier ASIC.
3.3.5 RESET# Switch
The RESET# switch is recessed to reduce the likelihood of accidental activation. The signal is
connected to the Harrier Reset Switch (RSTSW_L) input which will generate a Harrier Reset
Out, which is ORed with the board reset logic. This signal is debounced in the Harrier ASIC.
3.3.6 Front Panel LEDs
The CPCI-6020 provides these LEDs on the front panel. Refer to the Harrier Application
Specific Integrated Circuit (ASIC) Programmer’s Reference guide for details of the BDFL bit.
Table 3-5 Front Panel LEDs
LED/Color Description Status
CPU/green Illuminated
Extinguished
BDFL/yellow Illuminated
Extinguished
3.4 Connector Pin Assignments
The following tables describe connectors available on the CPCI-6020 base board. Note that the
pin assignments for connectors J3, J4 and J5 apply to the transition module, as well as the
CPCI-6020.
3.4.1 CompactPCI Bus Connectors
The CPCI-6020 implements a 64-bit CompactPCI interface on connectors J1 and J2. Each of
these connectors conform to the CompactPCI specification. The pinout for connectors J1 and
J2 are shown in Table 3-6 on page 61 below and Table 3-7 on page 61.
z J1 is a 110 pin AMP Z-pack 2 mm hard metric type A connector with keying for +3.3 V or
+5 V
Processor bus active
Processor bus inactive
BDFL bus active
BDFL bus inactive
60
z J2 is a 110 pin AMP Z-pack 2 mm hard metric type B connector
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CompactPCI Bus Connectors Controls, LEDs, and Connectors
Pin D15 of J1 is used in peripheral slots for the BD_SEL# signal supporting hot swap. In the
system slot, this pin is defined as GND. The CPCI-6020 interprets this pin as BD_SEL_L. In a
non-High Availablility (HA) chassis, this signal is GND (always asserted) and hence this usage
is backwardly compatible.
Table 3-6 J1 CompactPCI Connector
Pin Row A Row B Row C Row D Row E Pin
25 +5 V REQ64_L ENUM_L +3.3 V +5 V 25
24 AD1 +5 V VIO AD0 ACK64_L 24
23 +3.3 V AD4 AD3 +5 V AD2 23
22 AD7 GND +3.3 V AD6 AD5 22
21 +3.3 V AD9 AD8 GND CBE0_L 21
20 AD12 GND VIO AD11 AD10 20
19 +3.3 V AD15 AD14 GND AD13 19
18 SERR_L GND +3.3 V PAR CBE1_L 18
17 +3.3 V No Connect
16 DEVSEL_L GND VIO STOP_L No Connect
15 +3.3 V FRAME_L IRDY_L BD_SEL_L TRDY_L 15
12 -14 KEY AREA 12 -
11 AD18 AD17 AD16 GND CBE2_L 11
10 AD21 GND +3.3 V AD20 AD19 10
9 CBE3_L IDSEL AD23 GND AD22 9
8 AD26 GND VIO AD25 AD24 8
7 AD30 AD29 AD28 GND AD27 7
6 REQ_L GND +3.3 V CLK AD31 6
5 No Connect
(BRSVP1A5)
4 No Connect
(BRSVP1A4)
3 INTA_L INTB_L INTC_L +5 V INTD_L 3
2TCK +5 V TMS TDO TDI 2
1 +5 V -12 V TRST_L +12 V +5 V 1
(SDONE)
No Connect
(BRSVP1B5)
HEALTHY_L VIO No Connect
No Connect
(SBO_L)
RST_L GND GNT_L 5
GND PERR_L 17
(LOCK_L)
No Connect
(INTP)
(INTS)
16
14
4
Table 3-7 J2 CompactPCI Connector
Pin Row A Row B Row C Row D Row E Pin
22 GA4 GA3 GA2 GA1 GA0 22
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Controls, LEDs, and Connectors CompactPCI Bus Connectors
Table 3-7 J2 CompactPCI Connector (continued)
Pin Row A Row B Row C Row D Row E Pin
21 No Connect
(CLK6)
20 No Connect
CLK5
19 GND GND No Connect
18 No Connect
BRSVP2A18
17 No Connect
BRSVP2A17
16 No Connect
BRSVP2A16
15 No Connect
BRSVP2A15
14 AD35 AD34 AD33 GND AD32 14
13 AD38 GND VIO AD37 AD36 13
12 AD42 AD41 AD40 GND AD39 12
11 AD45 GND VIO AD44 AD43 11
10 AD49 AD48 AD47 GND AD46 10
9 AD52 GND VIO AD51 AD50 9
8 AD56 AD55 AD54 GND AD53 8
7 AD59 GND VIO AD58 AD57 7
6 AD63 AD62 AD61 GND AD60 6
5 CBE5_L 64EN-L VIO CBE4_L PAR64 5
4 VIO No Connect
3 No Connect
(CLK4)
2 No Connect
(CLK2)
1 No Connect
(CLK1)
GND No Connect
GND No Connect
No Connect
BRSVP2B18
GND No Connect
No Connect
BRSVP2B16
GND No Connect
BRSVP2B4
GND No Connect
No Connect
(CLK3)
GND No Connect
(RSV)
(RSV)
(RSV)
No Connect
BRSVP2C18
(PRST_L)
No Connect
(DEG_L)
(FAL_L)
CBE7_L GND CBE6_L 4
(GNT3_L)
No Connect
(SYSEN_L)
(REQ1_L)
No Connect
(RSV)
GND No Connect
No Connect
(RSV)
GND No Connect
No Connect
(REQ6_L)
GND No Connect
No Connect
(REQ5_L)
No Connect
(REQ4_L)
No Connect
(GNT2_L)
No Connect
(GNT1_L)
No Connect
(RSV)
(RSV)
No Connect
(RSV)
BRSVP2E18
No Connect
(GNT6_L)
(BRSVP2E16)
No Connect
(GNT5_L)
No Connect
(GNT4_L)
No Connect
(REQ3_L)
No Connect
REQ2_L
21
20
19
18
17
16
15
3
2
1
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CompactPCI User I/O Connector Controls, LEDs, and Connectors
3.4.2 CompactPCI User I/O Connector
Connector J3 is a 110 pin AMP Z-pack 2 mm hard metric type B connector. This connector
routes the I/O signals for the PMC I/O, serial port and USB ports. The pin assignments for J3
on the processor board and on the transition module are shown in Table 3-8 below (outer row
F is assigned and used as ground pins but is not shown in the table):
Table 3-8 J3 CompactPCI User I/O Connector
Pin Row A Row B Row C Row D Row E Pin
19 RESERVED +12 V -12 V RXD3 RXD4 19
18 HSC_REQ_L GND RSC3 GND RXC4 18
17 HSC_GNT_L MXCLK MXDI MXSYNC_L MXDO 17
16 HSC_FLOAT GND TXC3 GND TXC4 16
15 HSC_EJECT_L RESERVED RESERVED TXD3 TXD4 15
14 +3.3 V +3.3 V +3.3 V +5 V +5 V 14
13 PMCIO5 PMCIO4 PMCIO3 PMCIO2 PMCIO1 13
12 PMCIO10 PMCIO9 PMCIO8 PMCIO7 PMCIO6 12
11 PMCIO15 PMCIO14 PMCIO13 PMCIO12 PMCIO11 11
10 PMCIO20 PMCIO19 PMCIO18 PMCIO17 PMCIO16 10
9 PMCIO25 PMCIO24 PMCIO23 PMCIO22 PMCIO21 9
8 PMCIO30 PMCIO29 PMCIO28 PMCIO27 PMCIO26 8
7 PMCIO35 PMCIO34 PMCIO33 PMCIO32 PMCIO31 7
6 PMCIO40 PMCIO39 PMCIO38 PMCIO37 PMCIO36 6
5 PMCIO45 PMCIO44 PMCIO43 PMCIO42 PMCIO41 5
4 PMCIO50 PMCIO49 PMCIO48 PMCIO47 PMCIO46 4
3 PMCIO55 PMCIO54 PMCIO53 PMCIO52 PMCIO51 3
2 PMCIO60 PMCIO59 PMCIO58 PMCIO57 PMCIO56 2
1 PMCVIO PMCIO64 PMCIO63 PMCIO62 PMCIO61 1
Table 3-9 on page 63 shows the signal descriptions for the J3 Connector:
Table 3-9 Signal Descriptions for the J3 Connector
Pin Definition
RXDn Receive Data
TXDn Transmit data
RXCn Synchronous channel receive clock
TXCn Synchronous channel transmit clock
MXCLK Clock for multiplexed data containing synchronization port control signals.
MXDI Multiplexed data input
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Controls, LEDs, and Connectors CompactPCI User I/O Connector
3.4.3 CompactPCI User I/O Connector
Connector J4 is a 110 pin AMP Z-pack 2 mm hard metric type B connector. This connector
routes the PCI bus of Harrier A to hot swap controller bridge board. The pin assignments for J4
on the processor board are shown in Table 3-10 (outer row F is assigned and used as ground
pins but is not shown in the table).
Table 3-10 J4 Local PCI Expansion Connector Pinout
Pin Row A Row B Row C Row D Row E Pin
25 AD36 AD35 AD34 AD33 AD32 25
24 AD40 AD39 AD38 GND AD37 24
23 AD45 AD44 AD43 AD42 AD41 23
22 AD49 +3.3 V AD48 AD47 AD46 22
21 AD53 AD52 AD51 GND AD50 21
20 AD57 +3.3 V AD56 AD55 AD54 20
19 AD61 AD60 AD59 GND AD58 19
18 CBE4# +3.3 V PAR64 AD63 AD62 18
17 REQ64# CBE7# CBE6# GND CBE5# 17
16 AD2 +3.3 V AD1 AD0 ACK64# 16
15 AD6 AD5 AD4 GND AD3 15
11 AD9 AD8 CBE0# GND AD7 11
10 AD13 +5.0V AD12 AD11 AD10 10
9 PAR CBE1# AD15 GND AD14 9
8 STOP# +5.0V LOCK# PERR# SERR# 8
7 FRAME# IRDY# TRDY# GND DEVSEL# 7
6 AD18 +5.0V AD17 AD16 CBE2# 6
5 AD21 CLK AD20 GND AD19 5
4 CBE3# +5.0V RESERVED AD23 AD22 4
3 AD28 AD27 AD26 AD25 AD24 3
2 GNT# REQ# AD31 AD30 AD29 2
1 INTA# INTB# INTC# INTD# RST# 1
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CompactPCI User I/O Connector Controls, LEDs, and Connectors
3.4.4 CompactPCI User I/O Connector
Connector J5 is a 110 pin AMP Z-pack 2 mm hard metric type B connector. This connector
routes the I/O signals for the two COM ports, the IDE secondary port, the keyboard, the mouse,
the two USB ports and the two ethernet ports. Table 3-11 show the pin assignments (row F is
assigned as ground pins but is not shown in the table) and Table 3-12 describes the signals:
Table 3-11 J5 User I/O Connector
PinRow ARow BRow CRow DRow EPin
22 RESERVED GND RESERVED +5.0 V SPKROC_L 22
21 KBDDAT KBDCLK KBAUXVCC AUXDAT AUXCLK 21
20 RESERVED RESERVED RESERVED GND RESERVED 20
19 RESERVED GND UVCC0 UDATA0+ UDATA0- 19
18 RESERVED UDATA1+ UDATA1- GND UVCC1 18
17 RESERVED ENET1_T+ ENET2_T+ ENET1_R+ ENET2_R+ 17
16 RESERVED ENET1_T- ENET2_T- ENET1_R- ENET2_R- 16
15 RESERVED RESERVED RESERVED RESERVED RESERVED 15
14 RTSa CTSa RIa GND DTRa 14
13 DCDa +5.0 V RXDa DSRa TXDa 13
12 RTSb CTSb RIb 5.0V DTRb 12
11 DCDb GND RXDb DSRb TXDb 11
10 TR0_L WPROT_L RDATA_L HDSEL_L DSKCHG_L 10
9 MTR1_L DIR_L STEP_L WDATA_L WGATE_L 9
8 RESERVED INDEX_L MTR0_L DS1_L DS0_L 8
7 CS1FX_L CS3FX_L DA1 RESERVED RESERVED 7
6 RESERVED GND RESERVED DA0 DA2 6
5 DMARQ IORDY DIOW_L DMACK_L DIOR_L 5
4 DD14 DD0 GND DD15 INTRQ 4
3 DD3 DD12 DD2 DD13 DD1 3
2 DD9 DD5 DD10 DD4 DD11 2
1 RESET_L DRESET_L DD7 DD8 DD6 1
Table 3-12 J5 Signal Descriptions
Signal Description
AUXCLK Clock for the PS/2 auxiliary device (mouse)
AUXDAT Serial data line for PS/2 auxiliary device (mouse)
CS1FX_L Chip-select drive 0 or command register block select.
CS3FX_L Chip select drive 1 or command register block select.
CTSn Clear to send
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Table 3-12 J5 Signal Descriptions (continued)
Signal Description
DA (2:0) Drive register and data port address lines.
DCDn Data carrier detected
DD (15:0) Data lines
DIOR_L I/O read
DIOW_L I/O write
DIR_L Controls the direction of the floppy head reader.
DMACK_L DMA acknowledge
DMARQ DMA Request
DRESET_L Reset signal to drive
DS (1:0) Select disk drives
DSKCHG_L Indicates drive door has been opened
DSRn Data set ready
DTRn Data terminal ready
EIDE port (ATA-2), TTL Levels
ENETn_R- Low side of differential receive data
ENETn_R+ High side of differential receive data
ENETn_T- Low side of differential transmit data
ENETn_T+ High side of differential transmit data
Ethernet Ports 1 & 2:
Floppy Disk, TTL levels:
HDSEL_L Selects the top or bottom head
INDEX_L Indicates the beginning of track
INTRQ Drive the interrupt request.
IORDY Indicates the drive ready for I/O
KBAUXVCC Fused power for the keyboard and auxiliary device.
KBDDAT Clock for the PC/AT or PS/2 keyboard
Keyboard/Auxiliary Device TTL:
MTR (1:0) Enable/ Disable motor
RDATA_L Data read
RESET_L Board hard reset output, TTL
Rin Ring indicator
RTSn Request to send
RXDn Serial receive data
Serial COM Ports (a & b), RS-232 levels:
SPKROC_L PC/AT Speaker output, open collector
STEP_L Step head
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Memory Mezzanine Connectors Controls, LEDs, and Connectors
Table 3-12 J5 Signal Descriptions (continued)
Signal Description
TR0_L Track 0 indicator
TXDn Serial transmit data
UDATAn- Low signal of differential data for USB channel
UDATAn+ High signal of differential data for USB channel
Universal Serial Bus (USB 0 & 1), USB levels
UVCCn Fused power for USB channel.
WDATA_L Write data
WGATE_L Enables the head write circuitry
WPROT_L Indicates the disk is write protected.
3.4.5 Memory Mezzanine Connectors
Table 3-13 on page 67 shows the pin assignments for the two 140-pin AMP 0.6 mm Free Height
mating connectors, which provide a memory expansion capability and include common ground
contacts that mate.
Table 3-13 J8 and J27 Memory Mezzanine Connector
Pin Pin Name Pin Name Pin Pin Pin Name Pin Name Pin
1 GND * GND * 2 73 DQ56 DQ57 74
3 DQ00 DQ01 4 75 DQ58 DQ59 76
5 DQ02 DQ03 6 77 DQ60 DQ61 78
7 DQ04 DQ05 8 79 GND * GND * 80
9 DQ06 DQ07 10 81 DQ62 DQ63 82
11 +3.3 V +3.3 V 12 83 CKD00 CKD01 84
13 DQ08 DQ09 14 85 CKD02 CKD03 86
15 DQ10 DQ11 16 87 CKD04 CKD05 88
17 DQ12 DQ13 18 89 +3.3 V +3.3 V 90
19 DQ14 DQ15 20 91 CKD06 CKD07 92
21 GND * GND * 22 93 BA1 BA0 94
23 DQ16 DQ17 24 95 A12 A11 96
25 DQ18 DQ19 26 97 A10 A09 98
27 DQ20 DQ21 28 99 GND * GND * 100
29 DQ22 DQ23 30 101 A08 A07 102
31 +3.3 V +3.3 V 32 103 A06 A05 104
33 DQ24 DQ25 34 105 A04 A03 106
35 DQ26 DQ27 36 107 A02 A01 108
37 DQ28 DQ29 38 109 +3.3 V +3.3 V 110
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Table 3-13 J8 and J27 Memory Mezzanine Connector (continued)
Pin Pin Name Pin Name Pin Pin Pin Name Pin Name Pin
39 DQ30 DQ31 40 111 A00 CS_C0_L 112
41 GND * GND * 42 113 CS_E0_L GND* 114
43 DQ32 DQ33 44 115 CS_C1_L CS_E1_L 116
45 DQ34 DQ35 46 117 WE_L RAS_L 118
47 DQ36 DQ37 48 119 GND * GND * 120
49 DQ38 DQ39 50 121 CAS_L +3.3 V 122
51 +3.3 V +3.3 V 52 123 +3.3 V DQMB0 124
53 DQ40 DQ41 54 125 DQMB1 SCL 126
55 DQ42 DQ43 56 127 SDA A1_SPD 128
57 DQ44 DQ45 58 129 A0_SPD MEZZ1_L 130
59 DQ46 DQ47 60 131 MEZZ2_L GND 132
61 GND * GND * 62 133 GND SDRAMCLK1 134
63 DQ48 DQ49 64 135 SDRAMCLK3 +3.3 V 136
137 SDRAMCLK4 SDRAMCLK2 138
67 DQ52 DQ53 68 139 GND * GND * 140
69 +3.3 V +3.3 V 70
71 DQ54 DQ55 72
3.4.6 PCI Mezzanine Card (PMC) Connectors
There are four 64-pin EIA E700 AAAB SMT connectors on the CPCI-6020 to provide the 64-bit
(2x32) PCI interface and optional I/O interface to the PMC, J11 through J14. The following table
shows the J11 pin assignments:
Table 3-14 PMC Connector J11 Pin Assignments
Pin Signal Signal Pin
1 TCK -12 V 2
3GND INTA# 4
5INTB# INTC# 6
7 PRESENT# +5 V 8
9 INTD# PCI_RSVD 10
11 GND PCI_RSVD 12
13 CLK GND 14
15 GND GNT#/XREQ0# 16
17 REQ#/XGNT0# +5 V 18
19 VIO AD31 20
21 AD28 AD27 22
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Table 3-14 PMC Connector J11 Pin Assignments (continued)
Pin Signal Signal Pin
23 AD25 GND 24
25 GND C/BE3# 26
27 AD22 AD21 28
29 AD19 +5 V 30
31 VIO AD17 32
33 FRAME# GND 34
35 GND IRDY# 36
37 DEVSEL# +5 V 38
39 GND LOCK# 40
41 SDONE# SBO# 42
43 PAR GND 44
45 VIO AD15 46
47 AD12 AD11 48
49 AD09 +5 V 50
51 GND C/BE0# 52
53 AD06 AD05 54
55 AD04 GND 56
57 VIO AD03 58
59 AD02 AD01 60
61 AD00 +5 V 62
63 GND REQ64# 64
The following table shows the pin assignments for J12.
Table 3-15 J12 PMC Connector J12 Pin Assignments
Pin Signal Signal Pin
1 +12 V TRST# 2
3TMS TDO 4
5TDI GND 6
7 GND PCI_RSVD 8
9 PCI_RSVD PCI_RSVD 10
11 MOT_RSVD +3.3 V 12
13 RST# MOT_RSVD 14
15 +3.3 V MOT_RSVD 16
17 PCI_RSVD GND 18
19 AD30 AD29 20
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Table 3-15 J12 PMC Connector J12 Pin Assignments (continued)
Pin Signal Signal Pin
21 GND AD26 22
23 AD24 +3.3 V 24
25 IDSEL AD23 26
27 +3.3 V AD20 28
29 AD18 GND 30
31 AD16 C/BE2# 32
33 GND IDSELB 34
35 TRDY# +3.3 V 36
37 GND STOP# 38
39 PERR# GND 40
41 +3.3 V SERR# 42
43 C/BE1# GND 44
45 AD14 AD13 46
47 M66EN AD10 48
49 AD08 +3.3 V 50
51 AD07 REQB_L 52
53 +3.3 V GNTB_L 54
55 MOT_RSVD GND 56
57 MOT_RSVD EREADY 58
59 GND NC (RESETOUT_L) 60
61 ACK64# +3.3 V 62
63 GND NC (MONARCH#) 64
70
Table 3-16 shows the J13 pin assignments:
Table 3-16 PMC Connector J13 Pin Assignments
Pin Signal Signal Pin
1 PCI_RSVD GND 2
3 GND C/BE7# 4
5 C/BE6# C/BE5# 6
7 C/BE4# GND 8
9 VIO PAR64 10
11 AD63 AD62 12
13 AD61 GND 14
15 GND AD60 16
17 AD59 AD58 18
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Table 3-16 PMC Connector J13 Pin Assignments (continued)
Pin Signal Signal Pin
19 AD57 GND 20
21 VIO AD56 22
23 AD55 AD54 24
25 AD53 GND 26
27 GND AD52 28
29 AD51 AD50 30
31 AD49 GND 32
33 GND A D48 34
35 AD47 AD46 36
37 AD45 GND 38
39 VIO AD44 40
41 AD43 AD42 42
43 AD41 GND 44
45 GND AD40 46
47 AD39 AD38 48
49 AD37 GND 50
51 GND AD36 52
53 AD35 AD34 54
55 AD33 GND 56
57 VIO AD32 58
59 NC NC 60
61 NC GND 62
63 GND NC 64
The following table shows the J14 pin assignments.
Table 3-17 PMC Connector J14 Pin Assignments
Pin Signal Signal Pin
1 PMCIO1 PMCIO2 2
3 PMCIO3 PMCIO4 4
5 PMCIO5 PMCIO6 6
7 PMCIO7 PMCIO8 8
9 PMCIO9 PMCIO10 10
11 PMCIO11 PMCIO12 12
13 PMCIO13 PMCIO14 14
15 PMCIO15 PMCIO16 16
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Controls, LEDs, and Connectors Lock Down Flash Enable Jumper
Table 3-17 PMC Connector J14 Pin Assignments (continued)
Pin Signal Signal Pin
17 PMCIO17 PMCIO18 18
19 PMCIO19 PMCIO20 20
21 PMCIO21 PMCIO22 22
23 PMCIO23 PMCIO24 24
25 PMCIO25 PMCIO26 26
27 PMCIO27 PMCIO28 28
29 PMCIO29 PMCIO30 30
31 PMCIO31 PMCIO32 32
33 PMCIO33 PMCIO34 34
35 PMCIO35 PMCIO36 36
37 PMCIO37 PMCIO38 38
39 PMCIO39 PMCIO40 40
41 PMCIO41 PMCIO42 42
43 PMCIO43 PMCIO44 44
45 PMCIO45 PMCIO46 46
47 PMCIO47 PMCIO48 48
49 PMCIO49 PMCIO50 50
51 PMCIO51 PMCIO52 52
53 PMCIO53 PMCIO54 54
55 PMCIO55 PMCIO56 56
57 PMCIO57 PMCIO58 58
59 PMCIO59 PMCIO60 60
61 PMCIO61 PMCIO62 62
63 PMCIO63 PMCIO64 64
3.4.7 Lock Down Flash Enable Jumper
A 0.1 inch, 2-pin header (J17) located on the CPCI-6020 enables lock down of one or more
bank A flash. When a jumper is installed between pins 1 and 2, the lock down is enabled.
Table 3-18 J17 Lock Down Flash Enable Jumper
Pin Signal
1WP_L
2 GND
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PMC 66 Mhz Disable Jumper Controls, LEDs, and Connectors
3.4.8 PMC 66 Mhz Disable Jumper
A 0.1 inch, 2-pin header (J21) located on the CPCI-6020 disables 66 MHz operation on PCI Bus
B if jumpered. When a jumper is installed between pins 1 and 2, the PCI Bus B operates at
33MHz, regardless of the PMC’s capability. This jumper setting prevents the secondary
Ethernet controller from being disabled if a 66 MHz capable PMC is installed. The jumper pulls
the M66EN signal low so the PMC knows the bus is running at 33 MHz.
Table 3-19 J21 PMC 66 MHz Disable Jumper
Pin Signal
1GND
2 M66EN
3.4.9 Remote Switch Connector
A 0.1 inch, 3-pin header (J19) located on the CPCI-6020 can be used to extend the front panel's
Reset and Abort switches functions through the cables to a remote location.
Table 3-20 J19 Remote Switch Connector
Pin Signal
1 Abort
2 GND
3 Reset
3.4.10 Flash Write Protect Enable Jumper
A 0.1 inch, 2-pin header (J20) located on the CPCI-6020 enables write protect of bank A flash.
When a jumper is installed between pins 1 and 2, the flash cannot be written.
Table 3-21 J20 Flash Write Protect Enable Jumper
Pin Signal
1 VPP
2 GND
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Controls, LEDs, and Connectors Harrier Power Up Configuration
3.4.11 Harrier Power Up Configuration
An 8-pin header on the CPCI-6020 provides the means to change some of the Harrier powerup configuration settings. The pin assignments for this header, along with the power-up setting
with the shunt on or off, are as follows:
Table 3-22 J22 Harrier Power Up Configuration Header Pin Assignments
Pin Signal Signal Pin Shunt On Shunt Off
1 XAD[20]
termination
3 XAD[21]
termination
5 XAD[22]
termination
7 XAD[23]
termination
GND 2 PUST0=0 PUST0=1
GND 4 PUST1 =0 PUST1 =1
GND 6 PUST2=0 PUST2=1
GND 8 PUST3 =0 PUST3 =1
3.4.12 Xport Flash Bank Select Header
A 0.1 inch, 3-pin header located on the CPCI-6020 controls the state of the Harrier RVEN0 bit
during power up and selects which Flash bank functions as the source for the reset vector.
Placing the jumper between pins 1 and 2 of J24 selects Xport 0 (Flash Bank A). Placing the
jumper between pins 2 and 3 selects Xport 1 (Flash Bank B). The pin assignments for this
header are as follows:
Table 3-23 J24 Xport Flash Bank Select Header
Pin Signal
1 +3.3 V
2 BANKB_SEL_L
3GND
3.4.13 RISCWatch Header
The CPCI-6020 provides a standard 2x8 0.1” header for the RISCWatch interface. The pin
assignments for this header are as follows:
Table 3-24 J25 RISCWatch Header Pin Assignments
Pin Signal Signal Pin
1 CPUTDO No Connect 2
3 CPUTDI CPUTRST_L 4
5 No Connect PULLUP 6
7 CPUTCK No Connect 8
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Mictor Debug Connector Controls, LEDs, and Connectors
Table 3-24 J25 RISCWatch Header Pin Assignments (continued)
Pin Signal Signal Pin
9 CPUTMS No Connect 10
11 SRESET_L No Connect 12
13 CPURST_L VOID 14
15 CKSTPO_L GND 16
3.4.14 Mictor Debug Connector
A 190-pin Mictor connector provides access to the processor bus (MPU Bus) and some
bridge/memory controller signals. It can be used for debugging purposes. The pin assignments
are listed in the following table.
Table 3-25 J28 Debug Connector
Pin Signal Signal Pin
1PA0
3PA2 PA3 4
5PA4 PA5 6
7PA6 PA7 8
9PA8 PA9 10
11 PA10 PA11 12
13 PA12 PA13 14
15 PA14 PA15 16
17 PA16 PA17 18
19 PA18 PA19 20
21 PA20 PA21 22
23 PA22 PA23 24
25 PA24 PA25 26
27 PA26 PA27 28
29 PA28 PA29 30
31 PA30 PA31 32
3 3 PA PAR 0 PA PA R1 3 4
3 5 PA PAR 2 PA PA R3 3 6
37 APE_L RSRV_L 38
GND
PA 1 2
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Controls, LEDs, and Connectors Mictor Debug Connector
Table 3-25 J28 Debug Connector (continued)
Pin Signal Signal Pin
39 PD0
41 PD2 PD3 42
43 PD4 PD5 44
45 PD6 PD7 46
47 PD8 PD9 48
49 PD10 PD11 50
51 PD12 PD13 52
53 PD14 PD15 54
55 PD16 PD17 56
57 PD18 PD19 58
59 PA20 PD21 60
61 PD22 PD23 62
63 PD24 PD25 64
65 PD26 PD27 66
67 PD28 PD29 68
69 PD30 PD31 70
71 PD32 PD33 72
73 PD34 PD35 74
75 PD36 PD37 76
+5 V
PD1 40
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Table 3-25 J28 Debug Connector (continued)
Pin Signal Signal Pin
77 PD38
79 PD40 PD41 80
81 PD42 PD43 82
83 PD44 PD45 84
85 PD46 PD47 86
87 PD48 PD49 88
89 PA50 PD51 90
91 PD52 PD53 92
93 PD54 PD55 94
95 PD56 PD57 96
97 PD58 PD59 98
99 PD60 PD61 100
101 PD62 PD63 102
103 PDPAR0 PDPAR1 104
105 PDPAR2 PDPAR3 106
107 PDPAR4 PDPAR5 108
109 PDPAR6 PDPAR7 110
111 Reserved Reserved 112
113 DPE_L DBDIS_L 114
GND
PD39 78
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Table 3-25 J28 Debug Connector (continued)
Pin Signal Signal Pin
115 TT0
117 TT1 TSIZ1 118
119 TT2 TSIZ2 120
121 TT3 Reserved 122
123 TT4 Reserved 124
125 CI_L Reserved 126
127 WT_L Reserved 128
129 GLOBAL_L Reserved 130
131 SHARED_L DBWO_L 132
133 AACK_L TS_L 134
135 ARTY_L XATS_L 136
137 DRTY_L TBST_L 138
139 TA_L Reserved 140
141 TEA_L Reserved 142
143 Reserved DBG_L 144
145 Reserved DBB_L 146
147 Reserved ABB_L 148
149 TCLK_OUT CPUGNT0_L 150
151 Reserved CPUREQ0_L 152
+3.3 V
TSIZ0 116
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Mictor Debug Connector Controls, LEDs, and Connectors
Table 3-25 J28 Debug Connector (continued)
Pin Signal Signal Pin
153 CPUREQ1_L INT0_L 154
155 CPUGNT1_L MCHK0_L 156
157 WDT1TO_L SMI_L 158
159 WDT2TO_L CKSTPI_L 160
161 L2BR_L CKSTPO_L 162
163 L2BG_L HALTED 164
165 L2CLAIM_L TLBISYNC_L 166
167 Reserved TBEN 168
169 Reserved Reserved 170
171 Reserved GND Reserved 172
173 SRESET_L Reserved 174
175 HRESET_L NAPRUN 176
177 SRST1_L QREQ_L 178
179 SRESET0_D_L QACK_L 180
181 HRESET_L CPUTDO 182
183 GND CPUTDI 184
185 CPUCLK CPUTCK 186
187 CPUCLK CPUTMS 188
189 CPUCLK CPUTRST# 190
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Functional Description
4.1 Overview
The CPCI-6020 is a CompactPCI system slot controller based on the PowerPlus III architecture
and includes support for the Motorola High Availability (HA) architecture (such as the
CPX8216). It consists of the MPC7410 processor and L2 backside cache, dual Harrier System
Memory Controller /PCI Host Bridge ASICs, 32 MB plus1 MB of flash memory, and 128 MB to
2 GB of ECC-protected SDRAM on mezzanines. Front panel access is provided for one of the
two 10 BaseT/100 Base TX Ethernet channels, an RS-232 serial debug port, two USB ports
and the single PMC slot.
The front Ethernet port may also be routed (by means of custom-build option) to the backplane
via the CompactPCI J3 and J5 connectors. Other I/O routed to the backplane include a second
Ethernet port, two 16550 compatible asynchronous serial ports, two high speed synchronous
serial ports, and IDE. A CompactFlash Type I/II compatible socket residing on the IDE Bus is
included onboard.
4
The floppy disk controller, keyboard, and mouse are supported only on the CPCI-6060 5E
variants. A parallel port, which was available on the previous generation board, has been
eliminated in favor of routing the Ethernet ports to the backplane connectors.
The CPCI-6020 features two host bridges, which allow two totally independent PCI Bus
hierarchies. One bus supports the single PMC and the secondary Ethernet port. This bus may
be run at 33 MHz or 66 MHz depending on the capability of the installed PMC. When run at 66
MHz, the secondary Ethernet is disabled because it is not 66 MHz capable. The other PCI Bus
supports all other onboard PCI resources and runs at a fixed speed of 33 MHz.
The CPCI-6020 board has a 190-pin Mictor connector attached to the processor bus to support
board debug. There is also access provided to the MPC7410 processor JTAG port via a
standard 16 pin header.
The block diagram for the CPCI-6020 module is shown in Figure 4-1 on page 82.
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Functional Description Block Diagram
4.2 Block Diagram
The following figure is a block diagram of the CPCI-6020 architecture.
Figure 4-1 Block Diagram
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Local PCI Bus Resources Functional Description
4.3 Local PCI Bus Resources
As stated earlier in this chapter, the CPCI-6020 features two host bridges (provided by Harrier
A and B ASICs), which allow for two independent PCI Bus hierarchies. The resources of these
two buses are described in the following subsections.
4.3.1 PCI Bus A Resources
The Harrier A ASIC serves as the bridge from the processor bus (marked PowerPC Bus on the
block diagram) to local PCI Bus A. In addition to the Harrier A ASIC, PCI Bus A is connected to
two CompactPCI domains: a local domain using a transparent PCI-to-PCI bridge and the J1
and J2 connectors and a remote domain for connection to a Motorola HA chassis using the J4
connector. PCI Bus A also serves as an interface to the primary Ethernet port on the front panel,
a PCI/ISA bridge connecting ESCC, CIO, and four USB ports. All features on PCI Bus A are
described in the following subsections.
4.3.1.1 Local CompactPCI Bus
PCI Bus A provides a local CompactPCI Bus interface by using the Intel 21154 PCI-to-PCI
bridge chip. This device implements a 64-bit primary data bus and 64-bit secondary data bus
interface and is PCI 2.1 compliant. The 21154 provides read/write data buffering in both
directions.
The 21154 supports +3.3 V or +5 V signalling at the PCI busses with a separate VIO pin for the
primary and secondary bus buffers. The primary bus signalling voltage is tied to +5 V. The
secondary bus signalling voltage is tied to the CPCI Bus VIO, so the CPCI-6020 is a universal
board that may operate in a +3.3 V or +5 V chassis.
A CompactPCI Bus interface will support a maximum of seven CompactPCI cards/loads per
segment when operating at 33 MHz. This CompactPCI Bus interface is compliant with the
CompactPCI 2.0 specification as listed in Appendix A, Related Documentation.
4.3.1.2 Remote (Expansion) CompactPCI Bus
PCI Bus A is also routed to the J4 connector. In a Motorola HA chassis this is routed across the
backplane to a bridge card. On the bridge card this bus interfaces to the remote CompactPCI
Bus through a transparent PCI-to-PCI bridge. The interrupts INTA-D# coming from the bridge
card are kept separate from the interrupts INTA-INTD# from sources on the CPCI-6020 even
though they share the same bus segment.
4.3.1.3 Primary Ethernet Channel
The CPCI-6020 uses an Intel GD82551IT Ethernet Controller to implement a primary
10BaseT/100BaseTx Ethernet channel on PCI Bus A. The GD82551IT consists of both the
Media Access Controller (MAC) and the physical layer (PHY) in a single integrated package.
The standard board configuration provides for a front panel Ethernet connection via an RJ-45
connector. A custom-build option is available for a rear I/O Ethernet by routing the Ethernet
transmit and receive signal pairs to the J5 connector.
This GD82551IT resides on PCI Bus A and always runs at 33 MHz and 64 bits.
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Functional Description PCI Bus A Resources
The 82551IT interfaces to an AT93C46 serial EEPROM device which provides power up
configuration information for the 82551IT. This is a 1 KB device organized as 64 16-bit words.
Refer to the corresponding VPD information in Appendix A, Related Documentation for the
contents of this device.
4.3.1.4 ISA Bridge, Including EIDE Function
The CPCI-6020 uses the Winbond W83C554F Peripheral Bus Controller (PBC) device to
interface to ISA and EIDE devices, and for additional system resources. The PBC provides the
following additional features:
z ISA Bus arbitration for DMA devices
z Functionality of two 82C59 Interrupt Controllers to support 14 ISA interrupts
z Edge/Level control for ISA interrupts
z Steerable PCI interrupts (Note: Feature not used. Interrupt steering is via the Harrier ASIC)
z Seven independently programmable DMA channels (functionality of two 82C37SA devices)
z Three interval Counter/Timer (82C54 functionality)
4.3.1.5 EIDE Interface
The PBC EIDE interface is capable of accelerated PIO transfers, as well as acting as a PCI Bus
master on behalf of an IDE DMA slave device. This resource provides a primary and secondary
EIDE interface for up to four EIDE devices, and also supports ATAPI-compliant devices.
The primary EIDE interface is routed to the CompactFLASH memory card. The secondary
EIDE interface is routed to the J5 User I/O connector for interfacing to external EIDE devices.
Some Motorola HA chassis route the EIDE Bus across the backplane to the peripheral bay. The
secondary EIDE interface is implemented in such a way to support these chassis. This includes
short traces matched in length, targeted impedance of 80 ohms and onboard termination.
4.3.1.6 ISA Bus Resources
The PBC provides an ISA Bus compatible master and slave interface. The ISA interface
supports the following types of cycles:
z PCI master initiated I/O and memory cycles to the ISA Bus
z DMA compatible cycles between main memory and ISA I/O
z ISA master initiated memory cycles to PCI and ISA master initiated I/O cycles to internal
PBC registers
4.3.1.7 Synchronous Serial Ports
The two sync/async ports are implemented with the Z85230 ESCC. Since the Z85230 does not
have all modem control lines, a Z8536 CIO is used to provide the missing modem lines.
84
A PLD device is used to perform decode for the Z85230 and the Z8536 for register accesses
and pseudo interrupt acknowledge cycles in ISA I/O space. DMA support for the Z85230 is
provided by the PBC.
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PCI Bus B Resources Functional Description
The clock input to the Z85230 PCLK pin is a 10 MHz clock. The two ports will support data
transfers up to 2.5 Mbs/sec. The Z85230 supplies an interrupt vector during a pseudo interrupt
acknowledge cycle. The vector is modified based upon the interrupt source within the Z85230.
All modem control lines from the ESCC are multiplexed/de-multiplexed through J3 by the P2MX
function due to I/O pin limitations.
4.3.1.8 USB Controller
The NEC uPD720101 device provides five USB ports (only four are used) for connectivity with
any USB compliant device or hub. It is an USB2.0 host controller, having one EHCI (Enhanced
Host Controller Interface) and two OHCI (Open Host Controller Interface) integrated onto a
single chip. It is a +3.3 V / +5 V device and supports PCI specification Rev.2.2 (32-bit, 33 MHz).
This device supports USB2.0 specification and is also backward compatible with USB1.1
specification. Hi-speed, full-speed or low-speed peripherals are supported along with all of the
USB transfer types: control, interrupt, bulk, or isochronous.
Two ports are routed to standard USB Series A receptacle at the front panel. The other two
ports are routed to J5 User I/O connector.
The four ports may be independently powered on and off through the use of an external USB
power control switch provided on board. Legacy keyboard and mouse interrupts from this
device are not supported on the CPCI-6020.
4.4 PCI Bus B Resources
The Harrier B ASIC bridges from the processor bus to PCI Bus B. Other than the Harrier, there
are only two resources on the bus; the secondary Ethernet controller and a PMC slot. The PMC
slot includes secondary arbitration and IDSEL signals as defined in the VITA 32-199x Processor
PMC Standard which allows for two possible devices on the PMC on this bus segment. PCI Bus
B is compliant to PCI Revision 2.1, including 64-bit expansion signals. It runs at +3.3 V levels
but is tolerant of +5 V signalling from the PMC. This bus runs at 33 MHz unless a 66 MHz
capable PMC is installed in which case the ethernet controller is disabled and the bus runs at
66 MHz.
4.4.1 PMC Slot
The CPCI-6020 contains four EIA-E700 AAAB connectors which provide a 32/64-bit PCI
interface to an IEEE P1386.1 compliant PMC. Connectors J11-J13 provide the 32/64-bit PCI
interface while J14 provides a user I/O path from the PMC slot to the CompactPCI backplane.
PMC user I/O signals are routed from the PMC J14 connector to the CompactPCI J3 connector
following the PIM differential signalling recommendations. A cutout in the CPCI-6020 allows for
front I/O through the PMC face plate.
If a 66 MHz capable PMC is installed, which is indicated by the state of its M66EN pin, PCI Bus
B is also configured at power up to run at 66 MHz. In this case, the 82551IT Ethernet device on
this bus, which is not 66 MHz capable, is disabled. If no PMC is installed, or if the PMC is not
66 MHz capable, then the bus runs at 33 MHz and the Ethernet device remains enabled. A
jumper is provided to override the M66EN pin from the PMC and force the bus to run at 33 MHz.
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Functional Description Secondary Ethernet Channel
The Harrier PCI I/O buffers operate at +3.3 V output levels and are +5 V tolerant allowing the
PCI interface to operate at either voltage level. VIO is connected to +3.3 V on the planned
standard product, but may be connected to +5 V by means of a build option. If VIO is connected
to +5 V then 66 MHz PCI operation is prohibited and disabled by means of a build option.
The following special function processor PMC pins, as defined by the Processor PMC Standard
VITA 32-2003, are implemented on the CPCI-6020 as described in the following table:
Table 4-1 Special Function Processor PMC Pins
PrPMC Signal Pin Number Support
PRESENT# J11-7 The PRESENT# signal from the slot is used in conjunction with
MONARCH# J12-64 The CPCI-6020 leaves the MONARCH# pin floating, causing any
IDSELB J12-34 IDSELB is connected to PCI Bus B AD[17].
REQB# J12-52 REQB# is routed to the PCI Bus B arbiter.
GNTB# J12-54 GNTB# is routed to the PCI Bus B arbiter.
M66EN J12-47 The CPCI-6020 has a weak pull-up on this signal. If the signal is
RESETOUT_L J12-60 The CPCI-6020 does not make any connection to RESETOUT_L.
EREADY J12-58 The EREADY signal (driven by the PMC) is connected to the Harrier
M66EN to detect the presence of a 66 MHz capable PMC. The state
of this bit is readable in the external register set on Harrier A Xport
channel 2.
installed processor PMC to operate as a slave module. Processor
PMC monarch mode is not supported.
grounded, as it will be on 33 MHz PMCs, the PCI Bus B will be
configured to run at 33 MHz upon power-up. If this line is left floating,
as it will be on 66 MHz capable PMCs, and it is qualified by assertion
of PRESENT#, then PCI Bus B will be configured to run at 66 MHz
upon power-up (as a side effect the secondary ethernet controller
on PCI Bus B will be disabled). A jumper is provided on the CPCI6020 to ground and thereby defeat the 66 MHz enable signal.
B EREADY pin and may be read in the XCSR.MCSR.EREADY
register of Harrier B. A pull-up is provided on board.
4.4.2 Secondary Ethernet Channel
The CPCI-6020 uses the Intel GD82551IT Ethernet controller to implement a secondary
10BaseT/100 BaseTx Ethernet channel on PCI Bus B. The GD82551IT consists of both the
Media Access Controller (MAC) and the physical layer (PHY) in a single integrated package.
The secondary Ethernet provides only rear I/O by routing the Ethernet transmit and receive
signal pairs to J5 connector.
The GD82551IT82551IT is limited to a maximum of 33 MHz PCI Bus operation. If the PMC slot
is populated with a 66 MHz capable PMC, the PCI Bus B will run at 66 MHz and this Ethernet
controller will be disabled by keeping it in reset.
The 82551IT interfaces to an AT93C46 serial EEPROM device which provides power up
configuration information for the 82551IT. This is a 1 kilobit device organized as 64, 16-bit
words.
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Processor Bus Resources Functional Description
4.5 Processor Bus Resources
Devices resident on the processor bus of the CPCI-6020 are a single processor, two Harriers
(denoted Harrier A and Harrier B) and a Mictor debug connector. The bus is the standard 60x
interface running at 100 MHz. Processor address and data bus parity generation and checking
is supported in conjunction with the Harrier ASICs. The MPX Bus extension, which the
MCP7410 is capable of, is not supported.
The MCP7410 processor uses a +2.5 V signalling level and is not +3.3 V tolerant. Care should
be taken that probe boards attached to the Mictor debug connector do not pull up or drive
signals in violation of this. The JTAG port is tolerant of +3.3 V signals.
4.5.1 Processor
The CPCI-6020 has the 360-pin CBGA foot print that supports the MPC7410 family of
processors. The CPCI-6020 supports an external processor bus speed of 100 MHz. The
common processor configuration will support variable core voltages between 0.8V and +3.3 V
and I/O voltages of either +2.5 V or +3.3 V.
4.5.2 L2 Cache
The CPCI-6020 uses a back-side L2 cache structure via the MPC7410 processor chip families.
The L2 cache is implemented with an on-chip, 2-way set-associative tag memory and external
direct-mapped synchronous SRAMs for data storage. The external SRAMs are accessed
through a dedicated 72-bit wide (64 bits of data and 8 bits of parity) L2 cache port. The
MPC7410 processor can support up to 2 MB. The L2 cache can operate in copyback or writethrough modes and supports system cache coherency through snooping. Data parity
generation and checking can be disabled by programming the processor L2 cache control
registers accordingly. The MPC7410 processor also supports direct mapping of the SRAM
memory, in conjunction with normal L2 cache operation. In this mode, a portion of the SRAM
memory space may be mapped to appear as a private memory space in the memory map.
Refer to the processor data sheet for additional information.
The L2 cache data SRAM for the CPCI-6020 is implemented using two 128 KB x 36-bit or 256
KB x 36-bit synchronous pipelined burst SRAMs providing a total 2 MB of L2 cache. Either
memory size is able to support a minimum L2 bus speed of 200 MHz. The common SRAM
footprint supports only+ 3.3 V core voltages and either +2.5 V or +3.3 V I/O voltages.
4.6 Harrier System Memory Controller and PCI Host Bridge ASIC
The Harrier ASIC provides the bridge function between the PPC60X Bus, the system memory
and the PCI Local Bus. The Harrier ASIC provides the following key features:
z 100 MHz PowerPC Bus interface
z SDRAM interface supporting up to eight banks of 256 MB each, with ECC
z 32/64-bit Rev 2.1 compliant PCI Bus interface capable of running up to 66 MHz
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Functional Description Dual Harrier Assignments
z Single channel DMA controller
z Message passing unit supporting I2O and generic functions
z Two internal 16550-type UARTs
z Two I
z MPIC compliant interrupt controller
z Four Xport channels for interfacing to flash or other external registers/devices
2
C Bus master interfaces
Refer to the Harrier Application Specific Integrated Circuit (ASIC) Programmer’s Reference
Guide (ASICHRA1/PG) for additional information and programming details.
4.6.1 Dual Harrier Assignments
The CPCI-6020 employs dual Harrier ASICs identified as Harrier A and Harrier B. Harrier A is
used for access to part of system memory, access to all of flash memory, NVRAM, RTC,
external registers, UARTs, onboard I2C, bridging to PCI Bus A and for top level control of all
interrupts. Harrier B is used for access to part of system memory, bridging to PCI Bus B and for
controlling some interrupts.
4.6.2 Harrier Power-Up Configuration
The Harrier ASIC XAD30-XAD0 pins provide configuration information for Harrier at power-up
reset time. The following table lists the default power-up reset state of these pins for the CPCI-
6020. The Select Option column indicates whether the power up setting can be changed by
build option resistor or by jumper, or if the setting is fixed and cannot be changed. The default
power-up setting column indicates the default values of the standard CPCI-6020 product.
Default settings for jumper options indicate power up value with jumper not installed.
Table 4-2 Harrier Power-Up Configuration Settings
Harrier
XAD Bus
Signal
XAD[30] Resistor 0 XCSR.XPGC.HDM Xports not Hawk Data Mode compatible.
XAD[29] Fixed 0 XCSR.UCTL.UCOS Select external clock source for UART.
XAD[28] Resistor 0 XCSR.BPCS.CSH Other PCI masters may access Harrier
XAD[27] Resistor 0 XCSR.BPCS.CSM All of Harrier’s PCI configuration
XAD[26] Resistor 0 XCSR.BXCS.P0HO
XAD[25] Fixed 1 XCSR.SDTC.SDER There are external buffers in series with
XAD[24] Resistor A = 1
Select
Option
Power Up
Default Register Bit(s)
/P1HO
XCSR.GCSR.AOAOHarrier A will respond to unmapped
B = 0
Meaning of Power-Up
Default State
configuration space.
registers are visible from PCI space.
Disable processor hold off at power up.
the BAx, RAx, WE, RAS or CAS signals.
address only cycles, Harrier B will not.
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Harrier Power-Up Configuration Functional Description
Table 4-2 Harrier Power-Up Configuration Settings (continued)
Harrier
XAD Bus
Signal
XAD
[23:20]
XAD[19] Resistor 0 State of bit can be
XAD[18] Resistor 1 XCSR.PARB.ENA Enable internal PCI arbiter
XAD[17] Fixed A=1
XAD
[16:15]
XAD
[14-12]
XAD
[11:10]
XAD[9] Jumper
XAD
[8:7]
XAD[6] Fixed A=1
XAD
[5:4]
XAD[3] Fixed 0 XCSR.XPAT2.RVEN Disable Xport channel 2 as Reset Vector
XAD
[2:1]
XAD[0] Fixed 0 XCSR.XPAT3.RVEN Disable Xport channel 3 as Reset Vector
Select
Option
Jumpers 1111 XCSR.GCSR.PUST
Fixed A=00
On board
logic sets
ratio
Fixed A=01
on board
Resistor A=01
Fixed A=00
Fixed xx XCSR.XPAT2.DW Xport Channel 3 Data Width
Power Up
Default Register Bit(s)
[3:0]
inferred:
XCSR.CLAS
(XCSR+$308)
XCSR.XARB.ENA Harrier A, enable internal PPC arbiter
B=0
XCSR Register
B=01
000 XCSR.GCSR.RAT Reserved
001 PPC-to-PCI clock ratio 3:2
010 PPC-to-PCI clock ratio 2:1
011 PPC-to-PCI clock ratio 5:2
100 PPC-to-PCI clock ratio 1:1
101 Reserved
110 PPC-to-PCI clock ratio 3:1
111 Reserved
B=XX
A=1
B=0
B=xx
B=0
B=xx
Group Base
Address
XCSR.XPAT0.DW Harrier A, Flash Bank A 16-bits wide
XCSR.XPAT0.RVEN Harrier A, Flash Bank A is Reset Vector.
XCSR.XPAT1.DW Harrier A, Flash Bank B to 16-bit width
XCSR.XPAT1.RVEN Harrier A, Flash Bank B is Reset Vector
XCSR.XPAT2.DW Harrier A, Xport Ch. 2 8-bit width.
Meaning of Power-Up
Default State
Generic Power Up Status Bits
(Software readable header)
Set PCI Configuration register CLAS to
present class code for “bridge device”.
Harrier B, disable internal PPC arbiter
Harrier A XCSR base addr. $FEFF0000
Harrier B XCSR base addr. $FEFF1000
Harrier B, Flash Bank A not used.
Harrier B has no flash.
Harrier B, Flash Bank B not used.
if and only if Bank A is not Reset Vector.
Harrier B has no flash.
Harrier B, Xport Ch. 2 not used.
Unused.
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Functional Description Debug Connector
Except where noted, Harrier A and Harrier B have the same default power-up setting.
4.6.3 Debug Connector
One 190-pin Mictor connector with center row of power and ground pins is used to provide
access to the processor bus and some miscellaneous signals. When the CPCI-6020 is
populated with an MPC7410 processor this bus is not tolerant of +3.3 V or +5 V signals. Boards
attached to this connector should not drive or pull signals up to intolerable levels.
4.6.4 PPC Bus Arbitration
The Harrier ASIC contains arbiters for the PPC Bus and the PCI Bus. The Harrier A PPC arbiter
is used to arbitrate between the processor, the Harrier A and the Harrier B PPC Bus masters
for ownership of the PPC Bus. The processor is connected to the Harrier A arbiter
CPU0_REQ/CPU0_GNT signal pair (XARB3/XARB0) and Harrier B is connected to the Harrier
A arbiter EXTL_REQ/EXTL_GNT signal pair (XARB5/XARB2). For more information on PPC
Bus arbitration refer to the CPCI-6020 CompactPCI Single Board Computer Programmer’s
Reference Guide and the Harrier Application Specific Integrated Circuit (ASIC) Programmer’s
Reference Guide.
4.7 ECC Memory Bus Resources
The CPCI-6020 supports 2 GB of memory via four RAM500 mezzanine modules populated in
the two memory connectors J7 and J28. There is no onboard memory. The ECC protected
memory mezzanines are distributed as separate sets, one attached to each Harrier. The CPCI6020 supports a total of 1 GB using currently available 256 MB SDRAMs, (evenly divided
between the two Harriers) and supports 2 GB when 512 MB SDRAMs become available.
4.7.1 Harrier A Memory Bus
Harrier A memory bus is routed to a connector on which a RAM500 mezzanine may be
mounted. The RAM500 mezzanine is capable of stacking so a total of two mezzanines may be
attached to the Harrier A memory bus. The mezzanines appear as Banks C and E to the Harrier.
Each mezzanine has a storage capacity of 256 MB of ECC protected memory using available
256 megabit SDRAMs, and a capacity of 512 MB when 512 megabit SDRAMs are available.
2
C SPD serial ROMs on these mezzanines are connected to Harrier A’s I2C port 0.
The I
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Harrier B Memory Bus Functional Description
4.7.2 Harrier B Memory Bus
Harrier B memory bus is also routed to a RAM500 compatible connector and has capabilities
and characteristics identical to the Harrier A memory bus. The ECC protected memory banks
on this memory bus appear as Banks C and E to Harrier B.
4.7.3 RAM500 Memory Mezzanine
Each RAM500 mezzanine carries nine SDRAM parts in a x8 configuration, a buffer for certain
control signals and a single +3.3 V, 256 x 8, SPD serial ROM. Each lower RAM500 attached to
the host board has its SPD addressable at $AA from the Harrier to which it is attached, the
upper at $AC.
The following are the expansion mezzanine size options for a single board. Boards of any size
can be stacked.
Table 4-3 Expansion SDRAM Memory Mezzanine Size Options
SDRAM Memory
Size (Banks) Device Size
32 MB 64 megabit 4 MB X 16 1 5
64 MB 64 megabit 8 MB X 8 1 9
128 MB 128 megabit 16 MB X 8 1 9
256 MB 256 megabit 32 MB X 8 1 9
512 MB 512 megabit 64 MB X 8 1 9
Device Organization
(depth x width-in-bits)
4.8 Harrier Xport Resources
The Xport is a bridge that interfaces the 60x bus to an expansion bus named Xport Bus. Each
of the two Harriers on CPCI-6020 has a separate Xport Bus. The Xport Bus is the set of signals
Harrier uses to control devices that have a simple, static RAM style interface. Such devices
include flash, NVRAM, RTC and external registers. A 60x bus slave and an Xport Bus master
constitute the most significant blocks that make up Xport within Harrier. The 60x bus slave has
four address response ranges. The Xport Bus master has four corresponding chip selects. An
address range with its corresponding chip select is referred to as a channel (0 through 3). Each
channel employs a combination of control registers and input signal pins to configure its
address range and attributes. Refer to the Harrier Engineering Specification for additional
details.
Number
of Banks
Number of
Devices
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Functional Description Harrier A, Channel 0 - Onboard Bank A Flash
4.8.1 Harrier A, Channel 0 - Onboard Bank A Flash
The CPCI-6020 contains one bank of flash memory soldered onboard. Bank A consists of a
single Intel Strata Flash P30 16-bit flash, providing 32 MB of memory. The following table
defines the flash type and size. The device support spage-read mode operations with an 4-word
page size. Flash Bank A is not ECC protected.
Table 4-4 Bank A Flash Options
Bank A Flash Size Intel Part Device Size Device Width
32 MB 1.8 Volt StrataFlash Memory 256 megabit 16 bits
4.8.2 Harrier A, Channel 1 - Socketed Bank B Flash
The CPCI-6020 contains two 32-pin PLCC sockets connected to Harrier A Xport channel 1,
which can be populated with 1 MB of flash memory using AMD AM29LV040B or equivalent
devices. This flash memory appears as flash Bank B to the Harrier A chip. Xport channel 1 is
configured to operate in normal address and data mode where the data alternates every byte
instead of every fourth byte (Hawk data mode). Only 8-bit writes are supported for this bank.
The reset vector may be sourced by either Bank A or Bank B depending on the state of Harrier
Xport 0 reset vector control bit RVEN0. When the RVEN0 bit is cleared, address range
FFF00000-FFFFFFFF maps to Bank B. When RVEN0 bit is set, it maps to Bank A. The default
state uses Bank A for the reset vector. Bank B may be selected by connecting the
BANKB_SEL_L pin to GND. Flash Bank B is not ECC protected.
4.8.3 Harrier A, Channel 2 - NVRAM, RTC, External Register Set
The Harrier A Xport 2 interface consists of the STMicroelectronics M48T37V. This device
provides 32 KB of nonvolatile static RAM, a real-time clock and a watchdog function. Refer to
the M48T37V Data Sheets for programming information. The M48T37V consists of two parts:
z A 44-pin 330mil SO device which contains the RTC, the oscillator, the power fail detection,
the watchdog timer logic, 32 KB of SRAM and gold-plated sockets for the SNAPHAT
battery.
z A SNAPHAT that houses the battery and/or the crystal
The output of the watchdog timer is logically ORed onboard to provide a hard reset. This signal
is routed to PLD ORing logic so that this feature may be disabled. Xport 2 is configured to
operate in Harrier 8-bit data mode.
4.8.4 Harrier A, Channel 3
The Xport interface is not used.
4.8.5 Harrier B, Channel 0, 1, 2 and 3
None of the Harrier B Xport Channels are used.
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Other Harrier Resources Functional Description
4.9 Other Harrier Resources
The following subsections discussion other resources that are available through the Harrier
ASIC.
4.9.1 I2C Bus Resources - Serial EEPROM
The CPCI-6020 contains two 8 KB Serial EEPROM devices onboard and provisions for four
256-byte Serial EEPROM devices on memory mezzanines.
z One 8 KB Serial EEPROM provides for Vital Product Data (VPD) storage of the module
hardware configuration
z One 8 KB device for storage of user configuration data.
The contents of the 8 KB devices are accessed by providing a two-byte address with the same
device ID, instead of the standard one-byte address as used in the 256-byte devices. The 256byte devices provide for Serial Presence Detect (SPD) memory configuration information. The
Serial EEPROMs for VPD, user data and memory attached to Harrier A are accessed through
I2C port 0 in the Harrier A ASIC.
The Serial EEPROM’s for memory attached to Harrier B are accessed through I2C port 0 in the
Harrier B ASIC. Refer to the CPCI-6020 CompactPCI Single Board Computer Programmer’s
Reference Guide for SROM device address assignments.
4.9.2 Asynchronous Serial Ports
The CPCI-6020 provides two asynchronous serial interfaces. UART0 and UART1 in the Harrier
A provide the 16550 compatible UART controllers. The UART0 port signals are wired to an RS232 transceiver which interfaces to the front panel RJ-45 connector. The UART0 port may
optionally be wired to the backplane via J5 instead. The UART1 port is wired to the J5 connector
only. An onboard 1.8432 MHz oscillator provides the baud rate clock for the UARTs. Refer to
the Harrier Application Specific Integrated Circuit Programmer’s Reference Guide for additional
UART information.
4.9.3 32-Bit Timers
Four 32-bit timers are provided by each Harrier (MPIC) that may be used for system timing or
to generate periodic interrupts. Each timer is driven by a divide-by-eight prescaler which is
synchronized to the PPC processor clock. For a 100 MHz processor bus, the timer frequency
would be 12.5 MHz. Refer to the Harrier Engineering Specification for additional information
and programming details on these timers.
4.9.4 Watchdog Timers
Both Harrier ASICs contains two Watchdog Timers, WDT1 and WDT2. Each timer is
functionally equivalent but independent. These timers will continuously decrement until they
reach a count of 0 or are reloaded by software. The time-out period is programmable from 1
microsecond up to 32 minutes. If the timer count reaches 0, a timer output signal will be
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Functional Description Other Board Resources
asserted. The output of Harrier A Watchdog Timer 1 is routed to a Harrier A MPIC interrupt. The
output of Harrier A Watchdog Timer 2 may be optionally routed by means of a build option to a
Harrier A MPIC interrupt or to provide a board hard reset. The standard CPCI-6020 product will
be built to provide hard reset.
The output of Harrier B Watchdog Timer 1 and 2 are routed to a Harrier B MPIC interrupt.
Following a Harrier device reset, WDT1 is enabled with a default time-out of 8 seconds and
WDT 2 is enabled with a default time-out of 16 seconds. Each timer must be disabled or
reloaded by software to prevent a time-out. Software may reload a new timer value or force the
timer to reload a previously loaded value. To disable or load/reload a timer requires a two step
process. Refer to the Harrier specification for additional timer details
4.10 Other Board Resources
The following subsections describe other resources that are available on the CPCI-6020.
4.10.1 Miscellaneous Control and Status
The Harrier ASIC contains a Miscellaneous Control and Status register that provides the CPCI6020 with the board fail LED control, PrPMC EREADY pin status, board reset control, and
processor timebase enable control. Refer to the Harrier Application Specific Integrated Circuit
(ASIC) Programmer’s Reference Guide for additional details.
4.10.2 Clock Generator
The CPCI-6020 clock generator uses an MPC9772 PLL clock driver in conjunction with an
MPC93R52 zero delay buffer to provide the clocks for the processor, both Harrier ASICs, the
SDRAMs and all PCI devices. The PPC-to-PCI clock ratios which are support by the CPCI-6020
are shown in the table below. The PCI Bus A runs at a fixed speed of 33 MHz. On board logic
uses the state of the PMC M66EN pin to determine if the PCI Bus B clock frequency will be 33
MHz or 66 MHz. The maximum PPC Bus frequency (66 MHz or 100 MHz) is determined at
board assembly time by populating the appropriate select resistors. The 100 MHz bus mode will
be the standard configuration.
Table 4-5 PPC to PCI Clock Ratios
PPC Clock Frequency
(MHz)
100 33.33 3:1 12
66.67 33.33 2:1 8
PCI Clock Frequency
(MHz) Ratio (PPC:PCI)
66.67 3:2 6
66.67 1:1 4
Harrier PCI Clock
Divisor (N)
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Onboard Power Supplies Functional Description
4.10.3 Onboard Power Supplies
The CPCI-6020 requires +5 V, +3.3 V, +1.8 V and +/-12 V (optional) input voltages. The
processor core voltage and +2.5 V for the Harrier core are generated on board from the +5 V
input by switching regulators. The processor core voltage regulator has a variable output which
is set using feedback resistors. In addition to the Harrier core voltage, the +2.5 V supply will
provide the processor, Harriers and L2 cache I/O voltage when the MPC7410 processor is
used. Power resistors installed during assembly will select either +3.3 V or +2.5 V to supply the
I/O voltage for the processor, Harriers and the L2 cache. +1.8 V is generated using an onboard
regulator through +3.3 V.
4.10.4 Board Reset Logic
A block diagram of the CPCI-6020 board reset logic is shown below. The board reset logic is
implemented in a programmable logic device (PLD) in order to provide maximum flexibility of
the circuit design.
There are several potential sources of reset on the CPCI-6020. They are:
z Power-on/under voltage reset
z Front panel reset switch
z CompactPCI PRST#
z Watchdog Timer reset via Harrier A WDT2
z CompactPCI FAL# signal
z Software generated hard reset via the Harrier RSTOUT bit
z Software generated hard reset via the Port 92 Register in the PBC
z CompactPCI Bus reset via the 21154 Bridge Control Register
z Processor RISCWatch JTAG emulator interface HRESET# signal (open collector)
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Functional Description Board Reset Logic
There is an optional build configuration for reset from the RISCWatch JTAG interface. In Option
2, the RISCWatch CPURST_L will reset the Harrier ASIC in addition to the processor. This
option may be used in cases where the state of the Harrier logic must be guaranteed when a
RISCWatch CPURST_L is issued. However, implementing this option will prevent the use of the
RISCWatch probe Reset and Run from RAM mode since the Harrier SDRAM configuration
settings will be lost when the reset occurs. The Option 2 connection will not be implemented in
the standard board configuration.
Figure 4-2 Reset Block Diagram
Reset to rest of board
FAL_L
PRST_L
OR
OR RST_ HRST0_
Power-up
Reset
Switch
OPT 2
PURST_
RSTSW_
XCSR.MCSR.RSTOUT
AUXUST_
Harrier A
Internal
Logic
XPMI.PINT.P0
XCSR.WT2C
OR
RSTOUT_
SRST0_
WDT2TO_
OPT 1
RW_HRST_
RW_SRST_
RW_TRST_
OR
OR
OR
CPU
HRST_
SRST_
TRST_
The RST_ and PURST_ inputs of Harrier B are tied to those of Harrier A, respectively. The
AUXRST_ and RSTSW_ inputs of Harrier B are held inactive. The RSTOUT_, HRST0_ and
SRST0_ outputs of Harrier B are not connected. The watchdog timers of Harrier B do not
generate reset.
The following table shows which devices are affected by various reset sources:
Table 4-6 Reset Sources and Devices Affected
Local
CompactPCI
Bus
Device Affected
Software Hard Reset
(Harrier RSTOUT,
PBC Port 92)
Software Hard Reset
(Harrier RSTOUT,
PBC Port 92)
ProcessorHarrier
ASIC
PCI
Devices
ISA
Devices
¸¸ ¸ ¸ ¸
¸¸ ¸ ¸ ¸
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Soft Reset Functional Description
Table 4-6 Reset Sources and Devices Affected (continued)
Device Affected
Software Hard Reset
(Harrier RSTOUT,
PBC Port 92)
Software Hard Reset
(Harrier RSTOUT,
PBC Port 92)
Software Hard Reset
(Harrier RSTOUT,
PBC Port 92)
Software Hard Reset
(Harrier RSTOUT,
PBC Port 92)
CompactPCI Reset
(21154 Bridge Control
Register)
Processor
RISCWatch JTAG
HRESET# Signal
1. Available as a build option (not enabled in standard configuration).
4.10.5 Soft Reset
ProcessorHarrier
¸¸ ¸ ¸ ¸
¸¸ ¸ ¸ ¸
¸¸ ¸ ¸ ¸
¸¸ ¸ ¸ ¸
¸(¸)
ASIC
1
1
PCI
Devices
ISA
Devices
Local
CompactPCI
Bus
¸
Software can assert the SRESET# pin of the processor by programming the P0 bit in the
Processor Init Register of the Harrier MPIC appropriately.
4.10.6 Front Panel Resources
The CPCI-6020 front panel provides access to recessed Abort and Reset push-button
switches, Board Fail, CPU Bus Activity and Hot Swap Status LEDs, an RJ-45 Ethernet
connector, an RJ-45 serial port connector, two USB connectors and the PMC front panel.
4.10.7 ABORT# and RESET# Switches
Two push-button switches provide ABORT# and RESET# inputs to the CPCI-6020. Both
switches are recessed to reduce the likelihood of accidental activation. The ABORT# signal is
connected to the Harrier Abort Switch (ABTSW_L) input and generates an MPIC internal
interrupt. The RESET# signal is connected to the Harrier Reset Switch (RSTSW_L) input which
will generate a Harrier Reset Out, which is ORed with the board reset logic. Each signal is
debounced in the Harrier ASIC.
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Functional Description On-Board LEDs
4.10.8 On-Board LEDs
The CPCI-6020 provides two LEDs visible on the front panel for status of CPU and Board Fail
(BDFL).
z The green CPU LED is lit when the DBB# signal of processor bus is active (hardware
controlled).
z The yellow FAIL LED is lit when the Harrier BDFL bit in the Miscellaneous Control and
Status register is active (software controlled).
Refer to the Harrier Application Specific Integrated Circuit (ASIC) Programmer’s Reference
Guide for details of the BDFL bit.
4.10.9 Harrier Power Up Configuration Header
An 8-pin header provides the means to change some of the Harrier power up configuration
settings. Refer to Chapter 3, Controls, LEDs, and Connectors for configuration settings
controlled by this header. A shunt must be installed to change a setting. The default
configuration setting (with the shunt not installed) is also given in that chapter.
4.11 Hot Swap Support
The CPCI-6020 provides hardware to support the physical connection process and the
hardware connection process of the full hot swap system model defined in the CompactPCI Hot
Swap Specification. This hardware supports the hot swap of peripheral boards in standardized
(non-high availability) chassis. Hot swapping of the CPCI-6020, the system controller, itself is
not defined in the CompactPCI specifications. A description of CPCI-6020 support for system
slot hot swapping is in the following high availability support section.
4.12 High Availability Support
The CPCI-6020 includes support for system slot hot swap in Motorola’s chassis. This includes
high availability (HA) features defined in the CompactPCI Hot Swap Specification as well as
Motorola’s added extensions.
Standardized features include implementation of the BD_SEL#, HEALTHY# and PCI_RST#
signals. Motorola extensions are described in the following sections.
4.12.1 HSC Bridge Board Interface
The CPCI-6020 interfaces with a local bridge card which resides on the remote CompactPCI
Bus. The bridge card is named local because it bridges down, in a hierarchical sense, from this
CPCI-6020 local domain to the remote bus. Similarly there is a remote CPU card with a remote
bridge card which bridges down to, and resides on, this local CompactPCI Bus.
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Local CompactPCI Bus Interface Functional Description
The PCI Bus routed to the J4 connector provides the communication path to the local bridge
card. There are also four signals in the J3 connector which comprise the communication with
the remote bridge card. When the CPCI-6020 is in control of the local CompactPCI Bus, these
signals allow the HSC on the remote bridge card to force the CPCI-6020 to quiesce the local
CompactPCI Bus and tri-state its 21154. This allows that HSC to then activate its own 21154
and assume control of the local CompactPCI Bus.
4.12.2 Local CompactPCI Bus Interface
Backplane communication is accomplished through the Intel 21154 transparent PCI-to-PCI
bridge. This device is not intended to support hot swap circuitry which has been added to the
CPCI-6020 to adapt the 21154 to this purpose and is described in the following sections.
4.12.3 Secondary Bus Arbitration
The 21154 internal secondary bus arbiter is not used on the CPCI-6020 because special HA
features are required. An external arbiter is used instead.
The external arbiter includes an interface to the Hot Swap Controller (HSC) located on the
remote bridge board. Through this interface the HSC may cause the arbiter to refuse to grant
the local CompactPCI Bus to any of the peripheral slot boards. In this manner the bus may be
made quiescent in preparation for a transfer of control from the CPCI-6020 to the bridge board
that bridges the remote domain down to the local CompactPCI Bus.
4.12.4 Secondary Bus Tri-Stating
When the CPCI-6020 is taken offline by the bridge board from the remote domain, its 21154
must be disabled to prevent it from responding to backplane transactions. The 21154 is
designed to drive its secondary bus signals to an inactive state when in reset. This would
prevent the remote bridge from assuming control of this bus. To overcome this there is a device
on the CPCI-6020 which can use the JTAG interface on the 21154 to put it into a high
impedance mode. That device is controlled by the remote bridge card.
4.12.5 System Slot Hot Swap
The CPCI-6020 may be safely inserted and extracted from the system chassis while power is
applied. Hot swap circuitry protects the board from electrical damage.
In systems that support high availability, the CompactPCI Bus may be active while the CPCI6020 is inserted and/or removed without disturbing the bus traffic. This is accomplished by pinstaged CompactPCI Bus connections, a switched pre-charged voltage level applied to bussed
pins and tri-stating of PCI-to-PCI bridge signals during insertion and removal.
The BD_SEL# signal from CompactPCI Bus J1 pin D15 must be driven true (low) for the back
end power supplies to switch on. When BD_SEL# is not asserted only a small portion of the
CPCI-6020 circuitry is powered.
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Functional Description EIDE Interface
The HLTY# signal is driven true (low) to the CompactPCI bus J1 pin B4 when the +5.0VDC,
+3.3VDC, +12VDC, and -12VDC and the J18 jumper is not installed. When the J18 jumper is
installed, only +5.0VDC and +3.3VDC are included in the HLTY# status and input power
supplies are all within tolerance. This can be used as a status indicator.
4.13 EIDE Interface
The CPCI-6020 supports primary EIDE onboard and the secondary EIDE channel which is
routed to the J5 User I/O connector. The CPCI-6020-MCPTM-01 contains the secondary EIDE
interface which supports a removable external EIDE device. The header of this EIDE is not
accessible through the rear panel. A cable must be used to connect an external EIDE device to
the header.
4.14 Ethernet Interface
The CPCI-6020 provides two 10BaseT/100BaseTX autoselect Ethernet interfaces. The first
Ethernet interface is routed to a RJ-45 connector located at the front panel of the board and
also to the J5 connector for Ethernet connection on the CPCI-6020-MCPTM-01. The transition
board option is selectable through option resistors during CPCI-6020 board assembly time. The
standard board route is to the front panel only. Contact your sales representative for more
information on the transition board option). The second Ethernet interface is routed only to the
J5 connector for Ethernet connection on the CPCI-6020-MCPTM-01.
The Ethernet Station Addresses are determined by the CPCI-6020 and are not affected by the
CPCI-6020-MCPTM-01.
4.15 Hot Swap Support
The CPCI-6020-MCPTM-01 is considered to be part of the CPCI-6020. Therefore, the CPCI6020-MCPTM-01 cannot be swapped without first removing or powering down the CPCI-6020.
All power for the CPCI-6020-MCPTM-01 is provided from the CPCI-6020 through pins on the
J3/J5 I/O connectors.
4.16 PMC Interface Module (PIM)
A single PMC Interface Module (PIM) site is supported on the CPCI-6020-MCPTM-01 in line
with the PMC module supported on the CPCI-6020. The CPCI-6020 provides two 64-pin EIAE700 AAAB connectors to interface to a 32/64-bit IEEE P1386.1 PMC. One of the two
connectors is dedicated to user I/O. The CPCI-6020 maps the PMC user I/O pins onto the
CompactPCI J3 and J5 connectors. The CPCI-6020-MCPTM-01 reverses the mapping and
brings the signals to a 64-pin EIA-E700 AAAB connector to interface with its PIM site. This
causes a one-to-one correspondence in the pinout between the PMC on the CPCI-6020 and
the PIM site on the CPCI-6020-MCPTM-01. Refer to the section titled PMC Slot on page 85 in
this chapter for a detailed description of the CPCI-6020’s PMC site.
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