Before using this product, read the operating instructions for safe usage contained in the
Product Safety and RF Exposure booklet enclosed with your radio.
C a u t i o n
ATTENTION!
This radio is restricted to occupational use only to satisfy FCC RF energy exposure requirements.
Before using this product, read the RF energy awareness information and operating instructions in the
Product Safety and RF Exposure booklet enclosed with your radio (Motorola Publication part numbe r
68P81095C98) to ensure compliance with RF energy exposure limits.
For a list of Motorola-approved antennas, batteries, and other accessories, visit the following web site which
lists approved accessories: http://www.motorola.com/cgiss/index.shtml.
Computer Software Copyrights
The Motorola products described in this manu al may include copyrigh ted Motorola compu ter programs stored
in semiconductor memories or other media. Laws in the United States and other countries preserve for
Motorola certain exclusive rights for co pyrighted computer programs, including, but not limited to, the
exclusive right to copy or reproduce in any form the copyrighted computer program. Accordingly, any
copyrighted Motorola computer programs contained in the Motorola products described in this manual may
not be copied, reproduced, modified, reverse-engineered, or distributed in any manner without the express
written permission of Motorola. Furthermore, the purchase of Motorola products shall not be deemed to grant
either directly or by implication, estoppel, or otherwise, any license under the copyrights, patents or patent
applications of Motorola, except for the normal non-exclusive license to use that arises by opera tion of law in
the sale of a product.
Document Copyrights
No duplication or distribution of this document or any portion thereof shall take place without the express
written permission of Motorola. No part of this manual may be reproduced, distributed, or transmitted in any
form or by any means, electronic or mechanical, for any purpose without the express written permission of
Motorola.
Disclaimer
The information in this document is carefully examined, and is believed to be entirely reliable. However, no
responsibility is assumed for inaccuracies. Furthermore, Motorola reserves the right to make changes to any
products herein to improve readability, function, or design. Motorola does not assume any liability arising out
of the applications or use of any product or circuit described herein; nor does it cover any license under its
patent rights nor the rights of others.
Page 3
Table of Contents
Foreword
Product Safety and RF Exposure Compliance.......................................................................... inside cover
List of Figures...........................................................................................................................................viii
List of Tables..............................................................................................................................................xi
Related Publications...................................................................................................................................xi
Chapter 1Test Equipment, Service Aids, and Service Tools.......... 1-1
Without RMS audio voltmeter or
With RMS audio voltmeter
Frequency/deviation meter and
signal generator for wide-range
troubleshooting and alignment
Digital voltmeter is recommended for AC/DC voltage and
current measurements
meter for RF voltage measurements.
Audio voltage measurements
Waveform measurements
RF level measurements
Receiver sensitivity measurements
Page 16
1-2Test Equipment, Service Aids, and Service Tools: Service Aids
1.2Service Aids
Table 1-2 lists service aids recommended for working on the CP150/CP200 Radios. While all of these
items are available from Motorola, most are standard shop equipment items, and any equivalent item
capable of the same performance may be substituted for the item listed.
Table 1-2. Service Aids
Motorola Part
No.
RLN4460Por table Test SetEnables connection to the audio/accessory jack.
RLN4510Battery InterfaceRegulates DC current and voltage between radio and
RVN4191Customer Programming Soft-
ware and Global Tuner Software
on CD Rom
AAPMKN4004Programming Test CableConnects radio to RIB (PLN4008).
AAPMKN4003Radio-to-Radio Cloning Cable
RLN4008Radio Interface BoxEnables communications between the radio and the
5886564Z01RF AdaptorAdapts radio’s antenna port to BNC cabling of test
0180305K08Shop Battery EliminatorInterconnects radio to power supply.
HSN9412Wall-Mounted Power SupplyUsed to supply power to the RIB (120 VAC).
DescriptionApplication
Allows switching for radio testing.
power supply.
Program customer option and channel data.
Allows a radio to be duplicated from a master radio by
transferring programmed data from the master radio to
the other.
computer’s serial communications adapter.
equipment.
3080369B71 or
3080369B72
6686533Z01Knob Remover/Chassis OpenerUsed to remove the front cover assembly.
HKN9216IBM Computer Interface CableConnection from computer to RIB.
8180384N65Housing EliminatorAllows testing of the radio outside of the housing.
Motorola Part
No.
RSX4043ATORX screwdriverTighten and remove chassis screws
6680387A70T6 TORX bitRemovable TORX screwdriver bit
R1453ADigital readout solder stationDigitally controlled soldering iron
RLN4062AHot air workstation, 120 VTool for hot air soldering/desoldering of surface
Computer Interface CableUse B72 for the IBM PC AT or newer (9-pin serial
port). Use B71 for older models (25-pin serial port).
Connects the computer’s serial communications
adapter to the RIB (PLN4008).
Table 1-3. Recommended Service Tools
DescriptionApplication
mounted integrated circuits
June, 20056880309N62-C
Page 17
Test Equipment, Service Aids, and Service Tools: Service Aids1-3
Table 1-3. Recommended Service Tools (Continued)
Motorola Part
No.
DescriptionApplication
0180386A78Illuminated magnifying glass with
lens attachment
Illumination and magnification of components
0180302E51Master lens system
0180386A82Anti-static grounding kitUsed during all radio assembly and disassembly pro-
cedures
6684253C72Straight prober
6680384A98Brush
1010041A86Solder (RMA type), 63/67,
0.5mm diameter, 1 lb. spool
0180303E45SMD tool kit (included with
R1319A)
R1319AChipMaster (110 V)Surface mount removal and assembly of surface
R1321AChipMaster (220 V)
mounted integrated circuits and/or rework station
shields. Includes 5 nozzles.
ChipMaster Nozzles:
6680332E83PLCC-28* nozzle
6680332E82PLCC-44* nozzle
6680332E94PLCC-52 nozzle
6680332E96PLCC-84 nozzle
6680334E67QFP-160 nozzle
6680333E46SOL-18 nozzle
6680332E84SOIC-20 nozzle
6680332E87SOL-20J nozzle
6680333E45SOL-24 nozzle
6680333E55TSOP-64 nozzle
* Included with ChipMaster packages
Soldering and Un-soldering IC’s
6880309N62-CJune, 2005
Page 18
1-4Test Equipment, Service Aids, and Service Tools: Service Aids
Programming/Test Cable
3.5mm mono
2.5mm stereo
Figure 1-1. Programming/Test Cable
P1
2.5mm stereo and
3.5mm
3.5mm Tip
(Speaker +)
3.5mm
Sleeve
2.5mm Tip
(Microphone)
2.5mm
2.5mm
Center
1
2
5
3
4
25 POSITION
MALE CONNECTOR
P2P3
36.0”
CABLE
P1
Orange
1
Blue
2
White
25 POSITION
FEMALE CONNECTOR
36.0”
CABLE
ohm
5
1UF,16V 5%
Spiral
3
Yellow
4
25 pin Male D Connector
P2
Components molded inside
1
5
47
24
7
33K
20
8
+
15
16
9
P3
25 pin Female
D Connector
1
15
4
11
To Test Box
To Test Box
Figure 1-2. Wiring of the Connectors
June, 20056880309N62-C
Page 19
Chapter 2DC Power Distribution
2.1DC Regulation and Distribution
A block diagram of the DC power distribution throughout the radio is shown in Figure 2-1.
Audio
Power
Amplifier
Accessories
20 pin Connector
Keypad/Option Board
7.5V
Battery
5V
5V
Vdda
Vddd
LCD
Driver
RF AMP, IF AMP,
ASFIC_CMP
RX/TX Buffers
IFIC
FRACTN
VCOBIC
UNSWB+
Fuse
3.3V
Reg.
LI Ion
PA, Driver
PCIC(ALC)
MECH.
SWB+
Low Battery
Detect
Control
On/Off
Switch
SWB+
Antenna
Switch
Vdda
Regulator
Vddd
Regulator
Tx
Led
MCU, ROM
and EEPROM
Regulator
Figure 2-1. DC Power Distribution Block Diagram
Battery voltage enters at connector J301 and is routed through fuse F301 to become USWB+.
VR301 protects against ESD, and D301 provides reverse polarity protection. This voltage is routed
to:
• FET switch Q170 in the TX power control circuit (turned on during transmit)
• TX power amplifier module U110 (via R150)
• input pins of regulators U310, U320 and U330
• FET switch Q493 (turned on whenever the radio is on)
• on-off switch S444 (part of on-off-volume control) to become SWB+
Page 20
2-2DC Power Distribution: DC Regulation and Distribution
When the radio is turned on, SWB+ is present and is applied to:
• transistor switch Q494 (pins 1 and 6) which turns on Q4 93
• RX audio power amplifier U490
• voltage divider R420/R421 and port PE0, a microprocessor A/D input which measures battery
voltage and radio on/off status
The output of FET switch Q493 is applied to the control pins of regulators U310, U320 and U330,
turning them on. The following regulators are used:
Table 2-1. Voltage Regulators
Reference No.DescriptionType
U3105 V RegulatorTK71750S
U320Digital 3.3 V RegulatorLP2986
U3303 V RegulatorTK71730S
The 5 V source is applied to:
• RX back end circuitry
• synthesizer super filter input and charge pump supply
• RED/GRN LEDs
• RX audio buffer U510
• portions of ASFIC U451
The 5 V source is also applied to FET switches Q311 and Q312. Q311 is turned on by Q313 when
RX_ENA (from U401 pin 49) is high, and supplies the "5R" source to the RF front end stages Q21Q22, and the VCO RX injection buffer Q280. Q312 is turned on by Q313 when TX_ENA (from U40 1
pin 50) is high, and supplies the "5T" source to the first transmitter stage Q100.
The digital 3.3 volt source from U320 (D_3.3 V) is applied to:
• microprocessor U401
• EEPROM U402
• flash ROM U404
The 3 V regulated source from U330 is applied to:
• synthesizer IC U201
• VCO/buffer IC U251
• portions of ASFIC U451
• microphone bias circuitry
While the radio is turned on, port PH3 (U401 pin 44) is he ld high. When the radio is turn ed off, SWB+
is removed and port PE0 (U401 pin 67) goes low, initiating a power-down routine. Port PH3 (pin 44)
remains high, keeping the voltage regulators on via Q493 and Q494, until the operating state of the
radio has been stored in EEPROM and other turn-off data functions have been completed. PH3 then
goes low, turning off Q494 and Q493, and all regulated voltages are removed.
June, 20056880309N62-C
Page 21
Chapter 3Controller Theory of Operation
3.1Controller
The controller provides the following functions:
• interface with controls and indicators
• serial bus control of major radio circuit blocks
• encoding and/or decoding of selective signaling formats such as PL, DPL , MDC1200 a nd QuikCall II
• interface to CPS programming via the microphone connector
• storage of customer-specific information such as channel frequencies, scan lists, and signaling
codes
• storage of factory tuning parame ters such as tra nsmitter powe r and de viation, r eceiver squelch
sensitivity, and audio level adjustments
• power-up, power-down and reset routines
Figure 7-3 (VHF) shows the interconnection between the controller and the various other radio
blocks. Figure 7-9 show the connections between the following circuit areas which comprise the
controller block:
• microprocessor circuitry
• audio circuitry
• DC regulation circuitry (refer to Chapter 2, DC Regulations and Distribution.)
• rotary and pushbutton controls and switches
• option board interface
The majority of the circuitry described below is contained in the (VHF) Mi croprocessor Circuitry
schematic diagrams (Figure 7-10). Portions are also found in the Audio and DC Regulation
schematics (Figures 7-11 and 7-12).
3.1.1Microprocessor Circuitry
The microprocessor circuitry includes microprocessor (U401) and associated EEPROM, S-RAM (not
used in PR400 models), and Flash ROM memories. The following memory IC's are used:
Table 3-1. Radio Memory Requirements
Reference No.DescriptionTypeSize
U402Serial EEPROMAT2512816K x 8
U403Static RAM(not used)
U404Flash ROMAT49LV001N_70 V128K x 8
Page 22
3-2Controller Theory of Operation: Controller
3.1.1.1 Memory Usage
Radio operation is controlled by software that is stored in external Flash ROM memory (U404).
Radio parameters and customer specific information is stored in external EEPROM (U402). The
operating status of the radio is maintained in RAM located within th e microprocessor . When the radio
is turned off, the operating status of the radio is written to EEPROM before operating voltage is
removed from the micropro cessor. See section “3.1.1.7 Microprocessor Power-Up, Power-Down and
Reset Routine” on page 3-3 for a discussion of the power-down routine.
Parallel communication with U403 and U404 is via:
• address lines A(0)-A(16), from U401 port F ADDR0-ADDR13 and port G XA14-XA16
• data lines D(0)-D(7), from U401 port C DATA0-DATA7
• chip-select for U403, from PH6 (U401 pin 41)
• chip-enable for U404, from PH7 (U401 pin 38)
• output enable for U404, from PA7 (U401 pin 86)
• write-enable for both U403 and U404, from PG7_R/W (U401 pin 4)
Serial communication with U402 is via:
• the SPI bus (see section “3.1.1.3 Serial Bus Control of Circuit Blocks” on page 3-2)
• chip-select for U402, from PD6 (U401 pin 3)
3.1.1.2 Control and Indicator Interface
Ports PI3 and PI4 are outputs which control the top-mounted LED indicator. When PI3 is high, the
indicator is red. When PI4 is high, the indicator is green. When both are high, the indicator is amber.
When both are low, the indicator is off.
Pressing the side-mounted PTT button (S441) provides a lo w to port PJ0 (U401 pin 71), which
indicates PTT is asserted. Side-mounted option buttons 1 and 2 (S442 and S443) are connected to
Ports PJ6 (pin 77) and PJ7 (pin 78), respectively.
3.1.1.3 Serial Bus Control of Circuit Blocks
The microprocessor communicates with other circuit blocks via a SPI (serial peripheral interface) bus
using ports PD2 (data into uP), PD3 (data out of uP) and PD4 (clock). The signal names and
microprocessor ports are defined in Table 3-2.
Table 3-2. SPI Bus Signal Definitions
Signal NameMicroprocessor PortMicroprocessor Pin
SPI-DATA_INPD2-MISOU401 Pin 99
SPI_DATA_OUTPD3-MOSIU401 pin 100
SPI_CLKPD4-SCKU401 pin 1
These signals are routed to:
• the audio filter IC (U451) to control internal functions such as gain change betwee n 25 kHz and
12.5 kHz channels, transmit or receive mode, volume adjustment, etc.
• the synthesizer IC U201 to load receive and transmit channel frequencies
• option board connector J460-1 for internal option configuration and control
• serial EEPROM U402 (both SPI_DATA_IN and SPI_DATA_OUT are used).
June, 20056880309N62-C
Page 23
Controller Theory of Operation: Controller3-3
In order for each circuit block to respond only to the data intended for it, each peripheral has its o wn
chip select (or chip enable) line. The device will only respond to data when its enable line is pulled
low by one of the microprocessor ports, as follows:
• port PD5 (U401 pin 2) for the audio filter IC
• port PH0 (U401 pin 47) for the synthesizer IC
• port PD6 (U401 pin 3) for the serial EEPROM.
3.1.1.4 Interface to RSS Programming
The radio can be programmed, or the programmed information can be read, using a computer with
CPS (Customer Programming Software) connected to the radio via a RIB (radio interface box) or
with the RIB-less cable. Connection to the radio is made via the microphone connector (part of
accessory connector J471). The SCI line connects the programming contact (J471 pin 6) to ports
PD0_RXD (data into uP, pin 97) and PD1_TXD (data out of uP, pin 98). Transistor Q410 isolates the
input and output functions by allowing PD1 to pull the line low , but does not af fect incoming data from
being read by port PD0. This isolation allows high-speed 2-wire pr ogramm ing via TP401 and TP402
for factory programming and tuning.
3.1.1.5 S t orage of Customer-Specific Information
Information that has been programmed using CPS, such as channel frequencies or selective
signaling codes, are stored in the external EEPROM, where it is retained permanently (unless
reprogrammed) without needing DC power applied to the microprocessor.
3.1.1.6 Sensing of Externally-Connected Accessories
Port PJ1 is used to detect the presence of externally connecte d accessor ies. Port PJ1 (U401 pin 72)
is normally low, unless accessories (lapel speaker microphone, lightweight headset, etc.) are used
with the radio. This port is used to detect an accessory PTT or auto sensing of a VOX accessory.
If VOX is programmed into the radio channe l codeplug information, and PJ1 is high during power-u p,
the radio will activate VOX operation. If a low is present at port PJ1 during power-up, the radio will
use this port as an external PTT indicator.
3.1.1.7 Microprocessor Power-Up, Power-Down and Reset Routine
On power-up, the microprocessor is held in reset until the digital 3.3 V regulator (U320 pin 5)
provides a stable supply voltage. Once the dig ital supply reaches steady st ate and releases the re set
line (U320 pin 7), the microprocessor begins to start up. The ASFIC_CMP (U451) has already
started running and is providing the startup clock to the microprocessor. After reset release by all
circuits, the software within the microprocessor begins executing port assignments, RAM checking,
and initialization. A fixed delay of 100 ms is added to allow the audio circuitry to settle. Next, an alert
beep is generated and the steady state software begins to execute (buttons are read, radio circuits
are controlled).
When the radio is turned off, SWB+ is removed and port PE0 (U401 pin 67) goes low, initiating a
power-down routine. Port PH3 (pin 44) remains high, keeping the voltage regulators on via Q493
and Q494, until the operating state of the radio has been stored in EEPROM. PH3 then goes low,
and all regulated voltages are removed.
6880309N62-CJune, 2005
Page 24
3-4Controller Theory of Operation: Controller
The microprocessor reset line (pin 94) can be controlled directly by the digital 3.3 V regulator (U320
pin 7), the microphone jack (part of accessory connector J471) via Q472 and Q471, and the
microprocessor itself. U320 pulls the reset line low if the digital 3.3 V source loses regulation. This
prevents possible MOS latch-up or overwriting of registers in the microprocessor because the reset
line is higher in voltage than the microprocessor VDD ports (U401 pins 12, 39, 59, 88). The
microprocessor can drive the reset line low if it detects a fault condition such as an expired watchdog
timer, software attempting to execute an infinite loop, unplanned hardware inputs, static discharge,
etc. Finally, the Q471 can pull the reset line low during use of the programming cable and CPS by
the application of a sufficiently negative voltage to the microphone connector tip contact (J471 pin 4),
however this reset method is not utilized.
3.1.1.8 Boot Mode Control
When power-up reset occurs, the microprocessor will boot into either normal or flash mode
depending on the logic level of ports MODA (U401 pin 58) a nd MODB (pin 57). T he Flash Adapter is
a programming accessory which provides negative 9 volts dc via a 1K resistor to microphone
connector J471 pin 4. This turns on Q471 and Q472 via D471 and VR472, pulling MODA and MODB
low and allowing booting in the flash mode by cycling power to reset the radio. Software upgrades
can then performed by loading the new software code into Flash ROM U404.
3.1.1.9 Microprocessor 7.3975 MHz Clock
The 7.3975 MHz clock signal (uP_CLK) is provided from the ASFIC_CMP (U451 pin 28). Upon
startup the 16.8MHz crystal provides the signal to the ASFIC_CMP, which sends out the uP_CLK at
3.8MHz until a steady-state condition is reached and the clock is increased to 7.3975MHz for the
microprocessor.
3.1.1.10 Battery Gauge
Various battery types are available having different capacities. The different battery types contain
internal resistors connected from the BATT_CHARGE contact to ground (which is routed to the
microprocessor as BATT_DETECT). A voltage divider is formed with R255 pro ducing a different DC
voltage for each battery type, which is read by microprocessor port PE2 (pin 65). This allows the
software to recognize the battery chemistry being used and adjust the battery gauge fo r best
accuracy.
3.1.2Audio Circuitry
3.1.2.1 Transmit and Receive Low-Level Audio Circuitry
The majority of RX and TX audio processing is performed by U451, the Audio Filter IC
(ASFIC_CMP), which provides the following functions:
• Tone PL/Digital PL encode and decode filtering
• Tone PL/Digital PL rejection filter in RX audio path
The parameters of U451 that are programmable are selected by the microprocessor via the CLOCK
(U451 pin 21), DATA (U451 pin 22) and chip enable (U451 pin 20) lines.
RX audio buffer U510 amplifies the audio level from the DEMOD output of the IFIC before being
applied to the audio filter IC input (DISC, U451 p in 2). The buffer is DC coupled to avoid corruption of
low-frequency data waveforms such as DPL. Because such waveforms are polarity sensitive, this
buffer is configured as a single-stage inverting amplifier (U510-1 only) for VHF models where highside first injection is used, or is configured as a two-stage non-inver ting amplifie r (U510-1 and -2 ) for
UHF models using low-side first injection. The gain of the buffer is 1.5 times or 3.5 dB.
U480 and associated components are not used. Stage U480-1 is bypassed by jumper R487.
Volume adjustment is performed by a digital attenuator within U451. The volume control (10KO, part
of S444) is connected to D_3.3 V and ground via R506 and R507. When the volume control is
rotated, it varies the dc volt age applie d to micr oprocessor A/D input por t PE1 (U4 01 pin 66) between
approximately 0 volts dc at minimum volume to 3.3 volts dc at maximum volume. Depending on this
voltage, the appropriate setting of the digital volume attenuator is selected. This technique is less
susceptible to noise than a conventional analog volume control.
3.1.2.2 Audio Power Amplifier
The audio power amplifier IC U490 amplifies receiver audio from U451 pin 41 to a level sufficient to
drive a loudspeaker. U490 is a bridge amplifier delivering 3.46 volts rms between pins 5 and 8
without distortion, which is sufficient to develop 500 milliwatts of audio power into the internal 24 ohm
speaker or an external 24 ohm load. The audio power amplifier is muted whenever speaker audio is
not required to reduce current drain. The audio amp is muted when U451 pin 14 is low. When U451
pin 14 is high, U490 pin 1 is pulled low by Q490, enabling the audio amplifier.
Because the power amplifier is a bridge-type, neither speaker terminal is gro unded. Care should be
taken that any test equipment used to measure the speaker audio voltage does not ground either
speaker output terminal, otherwise damage to the audio power amplifier IC may result. When a 24ohm load resistor is used it should be connected between the tip and the sleeve of accessory jack
J471 (3.5mm port), never to ground. External SPKR plug insertion mechanically disconnects the
internal speaker. Volta ge measurements using test equipment that is not isolated from ground may
be made from one side of the speaker or load r esistor (either the tip or the sle eve of J471) to chassis
ground, in which case the voltage indicated will be one half of the voltage applied to the speaker or
load resistor . The Motorola RLN44 60 Port able Test Set and AAPMKN4004 Programming T est Cable
provide the proper interface between the radio's ungrounded audio output and ground-referenced
test equipment.
3.1.2.3 Internal Microphone Audio Voice Path
Microphone audio from internal microphone is routed from J470-1 via C475, L471, and C470 to the
ASFIC_CMP mic audio input (MICINT, U451 pin 46). During transmit, Q470 is turned on by a low at
U451 pin 35, providing dc bias for the internal MIC via R478. External MIC plug insertion
mechanically disconnects the internal microphone. External MIC audio is coupled through L4 71 and
C470 to the mic audio input. An input level of 10 mV at J471 pin 4 produces 200 mV at the output of
U451 pin 40, which corresponds to 60% deviation.
6880309N62-CJune, 2005
Page 26
3-6Controller Theory of Operation: Controller
3.1.2.4 PTT Circuits
The internal side-mounted PTT switch (S441) is sensed directly by microprocessor port PJ0 (U401
pin 71). External mic PTT is sensed by measuring the current drawn through the accessory
connector (J471-4) by the mic cartridge (which is in series with the accessory PTT switch). This
current is drawn through the base (pin 5) and emitter (pin 4) of a transistor in Q470, causing its
collector (pin 3) to supply a logic-high to microprocessor port PJ1 (pin 72).
3.1.2.5 VOX Operation
VOX audio accessories do not have a PTT switch. Instead, the mic cartridge is wired directly from
J471-4 to ground. If the radio has been programmed for VOX operation an d the VOX accessory is
plugged in prior to turning the radio on, the current drawn by the cartridge will turn on Q470 (pins 34-5) and a logic high will be seen at port PJ1 at turn-on. The microprocessor then assumes VOX
operation, with PTT controlled by the presence of audio at the mic cartridge. A dc voltage
proportional to the audio level at the input of the ASFIC_CMP (U451 pin 46) is fed to a n A/D in put of
microprocessor U401 (pin 62). During VOX operation, PT T is activate d whe n the dc leve l exceeds a
preset threshold.
3.1.2.6 Battery Charging Through Microphone Jack
A wall-type charging power supply may be connected to the 2.5 mm microphone jack (p art of
accessory connector J451). The voltage present at the tip contact (pin 4) is app lied to the center
charging contact of the battery via diode D470. Another diode, internal to the battery, applies this
voltage to the (+) battery terminal. Only the recommended charger and battery type should be
charged in this manner.
Different battery types contain internal resistors connected from the BATT_CHARGE contact to
ground, which is routed to the microprocessor as BATT_DETECT. A voltage divider is formed with
R255 producing a DC voltage which is read by microprocessor port PE2 (pin 65). This allows the
software to recognize the battery chemistry being used and adjust the battery gauge fo r best
accuracy. The value of R255 is chosen so that the voltage at the BATT_CHARGE node (cathode of
D470) is never low enough to turn on the EXT_MIC_PTT sense transistor (part of Q470).
3.1.2.7 Programming and Flashing Through Microphone Jack
The ring contact on the 2.5 mm microphone jack is used for reading, pr ogramming or re-flashing the
radio using CPS. This contact (J471 pin 6) is routed to port s PD0_RXD (data into uP, pin 97) and
PD1_TXD (data out of uP, pin 98). Transistor Q410 isolates the input and output functions by
allowing PD1 to pull the line low, but does not affect incoming data from being read by port PD0.
To re-flash the radio (ov erw rit e th e software in the F lash ROM wi th ne w so ftware), the ra dio mu st
power up in the boot mode. This is accomplished by using a flash adapter acce ssory, which provides
SCI communication with the programming ring contact (J471 pin 6) and also allows a negative
voltage (negative 9 volts dc via a 1K resistor) to be applied to the tip contact (J471 pin 4). This
voltage is sufficient to turn on the base-emitter junction (pins 1 and 2) of Q472 via L471, D471,
VR472 and R471. Pin 6 of Q472 goes high, turning on Q471 (pins 3 and 4) and pulling the
BOOT_ENA line (ports MODA and MODB of the microprocessor) low. Cycling power generates a
reset which causes the radio to boot in the flash mode.
June, 20056880309N62-C
Page 27
Chapter 4136-162 MHz VHF Theory Of Operation
4.1Introduction
This chapter provides a detailed theory of operation for the radio components. Schematic diagrams
for the circuits described in the following paragraphs are located in Chapter 7 of this manual.
4.2VHF Receiver
The VHF receiver covers the range of 136-162 MHz and provides switchable IF bandwidth for use
with 12.5 kHz or 20/25 kHz channel spacing systems. The receiver is divided into two major blocks as
shown in Figure 4-1.
•Front End
• Back End
Preselector
RX from
Antenna Switch
from Synthesizer
4.2.1Receiver Front-End
Incoming RF signals from the antenna are first routed throug h the harmonic filter and ante nna switch,
part of the transmitter circuitry, before being applied to the receiver front end. The receiver front end
consists of a preselector filter, RF amplifier, an interstage filter, and a double-balanced first mixer.
The preselector filter is a fixed-tuned 4-pole design using discrete elements (L1-L4 and C1-C9) in a
series/shunt resonator configuration. It has a 3 dB bandwidth of 43 MHz, an in sertion loss of 2 dB and
image attenuation of 37 dB at 226 MHz, with increasing attenuation at higher frequencies. Diode CR1
protects the RF amplifier by limiting excessive RF levels.
The output of the filter is matched to the base of RF amplifier Q21, which provides 18 dB of gain and
a noise figure of 2 dB. Operating voltage is obtained from the 5R source, which is turned off during
transmit to reduce dissipation in Q21. Current mirror Q22 maintains the operating current of Q21
RF
Filter
First LO
Recovered Audio
Figure 4-1. VHF Receiver Block Diagram
Amp
RSSI
Interstage
Filter
Inj Filter
Ceramic
Resonator
1st Mixer
Demodulator
Crystal
Filter
6G
Switching
6E
IF
Amp
BW_SEL
Cer Fltr
4E
Page 28
4-2136-162 MHz VHF Theory Of Operation: VHF Receiver
constant at 6.2 mA regardless of device and temperature variations, for optimum dynamic range and
noise figure.
The output of the RF amplifier is applied to the interstage filter, a fixed-tuned 3-pole series-coupled
resonator design having a 3 dB bandwidth of 54 MHz and insertion loss of 1.8 dB. This filter has an
image rejection of 40 dB at 226 MHz, with increasing attenuation at higher frequencies.
The output of the interstage filter is connected to the passive double-balanced mixer consisting of
components T41, T42, and CR41. This mixer has a conversion loss of 7 dB. High-side injection from
the frequency synthesizer is filtered by L40-L41 and C40-C44 to remove second harmonic energy
that may degrade half-IF spurious rejection performance. The injection filter has a 3 dB bandwidth of
52 MHz and an insertion loss of 1.5 dB. The filtered injection signal is applied to T42 at a level of +6
dBm.
The mixer output is applied to a diplexer network (L51-L52, C51, R51) which ma tches the 44 .85 MHz
IF signal to crystal filter FL51, and terminates the mixer into 50Ω at all other frequencies
4.2.2Receiver Back-End
The receiver back end is a dual conversion design. High IF selectivity is provided by FL51, a 4-pole
fundamental mode 44.85 MHz crystal filter with a minimum 3 dB bandwidth of + 6.7 kHz, a maximum
20 dB bandwidth of ±12.5 kHz, and a maximum insertion loss of 3.5 dB. The output is matched to IF
amplifier stage Q51 by L53 and C93. Q5 1 provides 16 dB of gain and a noise figure of 1.8 dB. The dc
operating current is 1 mA. The output of Q51 is applied to the input of the receiver IFIC U51. Diode
CR51 limits the maximum RF level applied to the IFIC.
The IFIC is a low-voltage monolithic FM IF system incorporating a mixer/oscillator, two limiting IF
amplifiers, quadrature detector, logarithmic received signal strength indicator (RSSI), voltage
regulator and audio and RSSI op amps. The second LO frequency, 44.395 MHz, is determined by
Y51. The second mixer converts the 44.85 MHz high IF frequency to 455 kHz.
Additional IF selectivity is provided by two ceramic filters, FL52 (between the second mixer and IF
amp) and FL53 or FL54 (between the IF amp and the limiter input). The wider filter FL53 is used for
20/25 kHz channel spacing, and the narrower filter FL54 is used for 12.5 kHz channels. When the
BW_SEL line is high, the two upper diodes in packages D51 and D52 are forward biased, selecting
FL53 for 20/25 kHz channels. When the BW_SEL line is low, the two lower diodes in packages D51
and D52 are forward biased, selecting FL54 for 12.5 kHz channels.
FL52FL53FL54
Number of Elements:466
Insertion Loss:4 dB4 dB4 dB
6 dB Bandwidth:15 kHz15 kHz9 kHz
50 dB Bandwidth:30 kHz30 kHz22 kHz
Stopband Rejection:27 dB47 dB47 dB
Ceramic resonator Y70 provides phase vs. frequency characteristic required by the quadrature
detector, with 90 degree phase shift occurring at 455 kHz. Buffer Q70 provides a lower driving
impedance from the limiter to the resonator, improving the IF waveform and lowering the distortion of
the recovered audio signal. The recovered audio level at the DEMOD output is 120 mV rms (25 kHz
channel, 3 kHz deviation) or 60 mV rms (12.5 kHz chan n el, 1. 5 kHz devia tio n) . An ad dit ion a l RSSI
output provides a DC voltage level that is proportio nal to RF signal level. This volt age is measured by
an A/D converter contained in the microprocessor (PE4_AN4, U401 pin 63).
June, 20056880309N62-C
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136-162 MHz VHF Theory Of Operation: VHF Transmitter4-3
4.3VHF Tr ansmitter
The VHF transmitter covers the range of 136-162 MH z. Depen ding on mo del, the output po wer of the
transmitter is either switchable on a per-channel basis between high power (5 watts) and low power
(1 watt), or is factory preset to 2 watts. The transmitter is divided into four major blocks as shown in
Figure 4-2.
• Power Amplifier
• Harmonic Filter
• Antenna Matching Network
• Power Control
USWB+
TX_INJ
(From VCO)
TX_ENA
PWR_SET
5T
Q100
Power Control
VGG
Power Amplifier Module U110
Figure 4-2. VHF Transmitter Block Diagram
4.3.1Transmit Power Amplifier
The transmitter power amplifier has three stages of amplification. The first stage, Q100, operates in
Class AB from the 5T source. It provides 13 dB of gain and an output of 20 mW. The current drain is
typically 25mA. Components C105-C107 and L103 match the output of Q100 to the 50Ω input of the
module U110.
U110 is a two stage Silicon MOS FET power amplifier module. Drain voltage is obtained from UNSW
B+ after being routed through current-sense resistor R150 in the power control circuit. The output
power of the module is controlled by varying the DC gate bias on U110 pin 2 (VGG).
4.3.2Antenna Switch
VDD
RX_IN
(To Receiver)
Antenna
Switch
Harmonic Filter
Antenna
Matching
Network
J140 Antenna
Jack
Antenna
The antenna switch consists of two pin diodes, D120 and D121. In the rece ive mode, both diodes are
off. Signals applied at the antenna or at jack J140 are routed, via the harmonic filter, through network
C122-C124 and L121, to the receiver input. In the transmit mode, Q170 is on and TXB+ is present,
forward-biasing both diodes into conduction. The diode current is 50 mA, set by R120-R122. The
transmitter RF from U110 is routed through D120, and via the harmonic filter to the antenna jack.
D121 conducts, shunting RF power and preventing it from reaching the receiver. L121 is selected to
appear as a 1/4 wave at VHF, so that the low impedance of D121 appears as a high impedance at the
junction of D120 and the harmonic filter input. This provides a high series impedance and low shunt
impedance divider between the power amplifier output and receiver input.
4.3.3Harmonic Filter
The harmonic filter consists of components C130- C136 and L130-L132. The harmonic filter is a
seven-pole elliptical low-pass configuration, optimized for low insertion loss, with a 3 dB frequency of
approximately 180 MHz and typically less than 0.8 dB insertion loss in the passband.
6880309N62-CJune, 2005
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4-4136-162 MHz VHF Theory Of Operation: VHF Frequency Generation Circuitry
4.3.4Antenna Matching Network
The harmonic filter presents a 50 Ω impedance to antenna jack J140. A matching network, made up
of C140-C141 and L140, is used to match the antenna impedance to the harmonic filter. This
optimizes the performance of the transmitter and receiver into the impedance presented by the
antenna, significantly improving the antenna's efficiency.
4.3.5Power Control
The power control circuit is a dc-coupled amplifier whose output is the dc gate bias voltage (VGG)
applied to the two stages of the RF power amplifier U110.
The output power of the transmitter is adjusted by varying the setting of the power-set DAC cont ained
in the ASFICcmp IC (DACG, U451 pin 6). This PWR_SET voltage is applied to U150 pin 3.
Stage U150-2 compares the voltage drop across current sense resistor R150 to the voltage drop
across resistor R151 caused by current flow through Q150, and adjusts its output (pin 7) to maintain
equal voltages at pins 5 and 6. Thus the current flow through Q150, and hence its emitter voltage, is
proportional to the current drawn by stage U110, which is in turn proportional to the transmitter output
power. The emitter voltage of Q150 is applied to U150 pin 2, where it is compared to the power set
voltage PWR_SET at pin 3.
The output of U150 pin 1 is divided by R110 and R111 and applied as a gate voltage to the power
amplifier U110. By varying this gate voltage as needed to keep the voltages at U150 pins 2 and 3
equal, power is maintained at the desired setting. Excessive final current, for example due to antenna
mismatch, causes a lowering of the voltage at U150 pin 6, an increased voltage at pin 2, and a
lowering of the voltage at pin 1 and of the gate voltage VGG. This prevents damage to the final stage
due to excessive current.
4.4VHF Frequency Generation Circuitry
The frequency generation system, shown in Figure 4-3, is composed of two circuit blocks, the
Fractional-N synthesizer IC U201, the VCO/Buffer IC U251, and associated circuitry. Figure 4-4
shows the peripheral interconnect and support circuitry used in the synthesizer block, and Figure 4-5
details the internal circuitry of the VCOBIC and its interconnections to the surrounding components.
Refer to the schematic to identify reference designators.
The Fractional-N synthesizer is powered by regulated 5 V and 3 V provided by U310 and U330
respectively. 5 V is applied to U201 pins 13 and 30, and 3 V is applied to pins 5, 20, 34 and 36. The
synthesizer in turn generates a super-filtered 4.5 V supply (VSF, from pin 28) to power U251. In
addition to the VCO, the synthesizer also interfaces with the logic and ASFICcmp circuits.
Programming for the synthesizer is accomplished through the microprocessor SPI_DATA_OUT,
SPI_CLK, and SYNTH_CS (chip select) lines (U409 pins 100, 1 and 47 respectively). A logic high
(3 V) from U201 pin 4 indicates to the microprocessor that the synthesizer is locked.
June, 20056880309N62-C
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136-162 MHz VHF Theory Of Operation: VHF Frequency Generation Circuitry4-5
Transmit modulation from the ASFICcmp (U451 pin 40) is applied to U201 pin 10 (MOD_IN). An
electronic attenuator in the ASFICcmp adjusts overall transmitter deviation by varying the audio level
applied to the synthesizer IC. Internally the audio is digitized by the Fractional-N synthesizer and
applied to the loop divider to provide the low-port modulation. The audio is also routed through an
internal attenuator for the purpose of balancing the low port and high port modulation and reducing
the deviation by 6 dB for 12.5 kHz channels, and is available at U201 pin 41 (VCO_MOD). This audio
signal is routed to the VCO's modulator.
Voltage
Multiplier
VCP
Vmult1
Vmult2
Synthesizer
Aux3
U201
16.8 MHz
Ref. Osc.
MOD Out
Modulating
Signal
Figure 4-3. VHF Frequency Generation Unit Block Diagram
4.4.1Fractional-N Synthesizer
The Fractional-N synthesizer, shown in Figure 4-4, uses a 16.8 MHz crystal (Y201) to provide the
reference frequency for the system. External components C201-C203, R202 and D201 are also part
of the temperature-compensated oscillator circuit. The dc voltage applied to varactor D201 from U201
pin 25 is determined by a temperature-compensation algorithm within U201, and is specific to each
crystal Y201, based on a unique code assigned to the crystal that identifies its temperature
characteristics. Stability is better than 2.5 ppm over temperatures of -30 to 60 °C. Softwareprogrammable electronic frequency adjustment is achieved by an internal DAC which provides a
frequency adjustment voltage from U201 pin 25 to varact or D201.
The synthesizer IC U201 further divides the 16.8 MHz signal to 2.1 MHz, 2.225 MHz, or 2.4 MHz for
use as reference frequencies. It also provides a buffered 16.8 MHz signal at U201 pin 19 for use by
the ASFICcmp.
To achieve fast locking of the synthesizer, an internal adapt charge pump provides higher current at
U201 pin 45 to quickly force the synthesizer within lock range. The required frequency is then locked
by the normal mode charge pump at pin 43. A lo op filter (C243 -C245 and R243 -R245) removes noise
and spurs from the steering voltage applied to the VCO varactors, with additional filtering located in
the VCO circuit.
Both the normal and adapt charge pumps get their supply from the capa citive volt age multiplie r made
up of C221-C224 and D220-D221. Two 3 V square waves from U201 pins 14-15 provide the drive
signals for the voltage multiplier, which generates 12.1 V at U201 pin 47. This voltage is filtered by
C225-C228.
Loop
Filter
TRB
Rx VCO
Circuit
Tx VCO
Circuit
VCOBIC
U251
Rx Out
Tx Out
Buffer
Q280
To Mixer
To PA Driver
6880309N62-CJune, 2005
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4-6136-162 MHz VHF Theory Of Operation: VHF Frequency Generation Circuitry
One of the auxiliary outputs of the synthesizer IC (AUX3, U201 pin 2) provides the TRB signal which
determines the operating mode of the VCO, either receive or transmit.
13,30
10
23
25
32
47
7
8
9
DATA
CLK
CEX
MODIN
V
, 5V
CC
, 3V
V
DD
XTAL1
WARP
PREIN
VCP
VMULT2
U201
Low Voltage
Fractional-N
Synthesizer
VMULT1
14
15
Prescaler In
DATA (U401 Pin 100)
CLOCK (U401 Pin 1)
SYNTH_CS (U401 Pin 47)
MOD IN (U451 Pin 40)
+5V (U310 Pin 5)
+3V (U330 Pin 5)
Reference
Oscillator
Voltage
Multiplier
5,20,34,36
Figure 4-4. VHF Synthesizer Block Diagram
4.4.2Voltage Controlled Oscillator (VCO)
The VCOBIC (U251), shown in Figure 4-5, in conjunction with the Fractional-N synthesizer (U201)
generates RF in both the receive and the transmit modes of operation. The TRB line (U251 pin 19)
determines which oscillator and buffer are enabled. A sample of the RF signal from the enabled
oscillator is routed from U251 pin 12 through a low pass filter, to the prescaler input of the synthesizer
IC (U201 pin 32). After frequency comparison in the synthesizer, a resultant DC control voltage is
used to steer the VCO frequency. When the PLL is locked on frequency, this voltage can vary
between 3 V and 9 V. L251 and C251 further attenuate noise and spurs on the steering line voltage.
In the receive mode, the TRB line (U251 pin 19) is low. This activates the receive VCO and the
receive buffer of U251, which o perate within the ra nge of 180 .85 to 20 6.85 MHz. The VCO frequen cy
is determined by tank inductor L254, C253 -C257, and varactor D251. The buf fered RF signal at U251
pin 8 is further amplified by Q280 and applied as RX_INJ to the low-p ass injection filter in the receiver
front end circuit.
In the transmit mode, U251-19 is driven high by U201 pin 2, enabling the transmit VCO and buffer.
The 136-162 MHz RF signal from U251 pin 10 is applied as TX_INJ to the input of the transmitter
circuit via matching network C290-C291 and L291. TX VCO frequency is deter mined by L264, C263-
LOCK
FREFOUT
GND
IOUT
IADAPT
MODOUT
AUX3
SFOUT
BIAS1
BIAS2
4
19
6,22,23,24
43
45
41
2
28
40
39
LOCK (U401 Pin 56)
FREF (U451 Pin 34)
2-Pole
Loop Filter
VCO
TRB
Filtered 5V
Mod
Steering
Line
LO RF
Injection
Voltage
Controlled
Oscillator
TX RF
Injection
(First Stage of PA)
June, 20056880309N62-C
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136-162 MHz VHF Theory Of Operation: VHF Frequency Generation Circuitry4-7
C267, and varactor D261. High-port audio modulation from the synthesizer IC is applied as
VCO_MOD to varactor D262 which modulates the transmit VCO.
AUX3 (U201 Pin 2)
TRB_IN
Steer Line
Voltage
(V_STEER)
NC
NC
V_SF (U201 Pin 28)
RX VCO
RX
TX
Circuit
TX VCO
Circuit
Tank
Tank
Pin 7
Pin 13
Pin 3
Pin 4
Pin 5
Pin 6
Pin 16
Pin 15
Pin 18
Vcc-Logic
Pin 20
Vcc-Superfilter
Collector/RF in
RX
TX
Vsens
Circuit
TX/RX/BS
Switching Network
U251
VCOBIC
Rx Active
Bias
Tx Active
Bias
Pin 2
Rx-I adjust
Pin 19
Pin 1
Tx-I adjust
Pin 12
Presc
Pin 8
RX
Pin 14
Pin 10
TX
Pins 9,11,17
Prescaler Out
Buffer
Q280
VCC Buffers
U201 Pin 32
RX INJ
3V (U330 Pin 5)
Matching
Network
TX INJ
3V
(U330 Pin 5)
(U201 Pin 28)
Figure 4-5. VHF VCO Block Diagram
V_SF
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4-8136-162 MHz VHF Theory Of Operation: VHF Frequency Generation Circuitry
Notes:
June, 20056880309N62-C
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Chapter 5146-174 MHz VHF Theory Of Operation
5.1Introduction
This chapter provides a detailed theory of operation for the radio components. Schematic diagrams
for the circuits described in the following paragraphs are located in Chapter 7 of this manual.
5.2VHF Receiver
The VHF receiver covers the range of 146-174 MHz and provides switchable IF bandwidth for use
with 12.5 kHz or 20/25 kHz channel spacing systems. The receiver is divided into two major blocks as
shown in Figure 5-1.
•Front End
• Back End
Preselector
RX from
Antenna Switch
from Synthesizer
5.2.1Receiver Front-End
Incoming RF signals from the antenna are first routed throug h the harmonic filter and ante nna switch,
part of the transmitter circuitry, before being applied to the receiver front end. The receiver front end
consists of a preselector filter, RF amplifier, an interstage filter, and a double-balanced first mixer.
The preselector filter is a fixed-tuned 4-pole design using discrete elements (L1-L4 and C1-C9) in a
series/shunt resonator configuration. It has a 3 dB bandwidth of 44 MHz, an in sertion loss of 2 dB and
image attenuation of 40 dB at 235 MHz, with increasing attenuation at higher frequencies. Diode CR1
protects the RF amplifier by limiting excessive RF levels.
The output of the filter is matched to the base of RF amplifier Q21, which provides 18 dB of gain and
a noise figure of 2 dB. Operating voltage is obtained from the 5R source, which is turned off during
transmit to reduce dissipation in Q21. Current mirror Q22 maintains the operating current of Q21
RF
Filter
First LO
Recovered Audio
Figure 5-1. VHF Receiver Block Diagram
Amp
RSSI
Interstage
Filter
Inj Filter
Ceramic
Resonator
1st Mixer
Demodulator
Crystal
Filter
6G
Switching
6E
IF
Amp
BW_SEL
Cer Fltr
4E
Page 36
5-2146-174 MHz VHF Theory Of Operation: VHF Receiver
constant at 6.2 mA regardless of device and temperature variations, for optimum dynamic range and
noise figure.
The output of the RF amplifier is applied to the interstage filter, a fixed-tuned 3-pole series-coupled
resonator design having a 3 dB bandwidth of 58 MHz and insertion loss of 1.8 dB. This filter has an
image rejection of 42 dB at 235 MHz, with increasing attenuation at higher frequencies.
The output of the interstage filter is connected to the passive double-balanced mixer consisting of
components T41, T42, and CR41. This mixer has a conversion loss of 7 dB. High-side injection from
the frequency synthesizer is filtered by L40-L41 and C40-C44 to remove second harmonic energy
that may degrade half-IF spurious rejection performance. The injection filter has a 3 dB bandwidth of
52 MHz and an insertion loss of 1.5 dB. The filtered injection signal is applied to T42 at a level of +6
dBm.
The mixer output is applied to a diplexer network (L51-L52, C51, R51) which ma tches the 44 .85 MHz
IF signal to crystal filter FL51, and terminates the mixer into 50Ω at all other frequencies
5.2.2Receiver Back-End
The receiver back end is a dual conversion design. High IF selectivity is provided by FL51, a 4-pole
fundamental mode 44.85 MHz crystal filter with a minimum 3 dB bandwidth of + 6.7 kHz, a maximum
20 dB bandwidth of ±12.5 kHz, and a maximum insertion loss of 3.5 dB. The output is matched to IF
amplifier stage Q51 by L53 and C93. Q5 1 provides 16 dB of gain and a noise figure of 1.8 dB. The dc
operating current is 1 mA. The output of Q51 is applied to the input of the receiver IFIC U51. Diode
CR51 limits the maximum RF level applied to the IFIC.
The IFIC is a low-voltage monolithic FM IF system incorporating a mixer/oscillator, two limiting IF
amplifiers, quadrature detector, logarithmic received signal strength indicator (RSSI), voltage
regulator and audio and RSSI op amps. The second LO frequency, 44.395 MHz, is determined by
Y51. The second mixer converts the 44.85 MHz high IF frequency to 455 kHz.
Additional IF selectivity is provided by two ceramic filters, FL52 (between the second mixer and IF
amp) and FL53 or FL54 (between the IF amp and the limiter input). The wider filter FL53 is used for
20/25 kHz channel spacing, and the narrower filter FL54 is used for 12.5 kHz channels. When the
BW_SEL line is high, the two upper diodes in packages D51 and D52 are forward biased, selecting
FL53 for 20/25 kHz channels. When the BW_SEL line is low, the two lower diodes in packages D51
and D52 are forward biased, selecting FL54 for 12.5 kHz channels.
FL52FL53FL54
Number of Elements:466
Insertion Loss:4 dB4 dB4 dB
6 dB Bandwidth:15 kHz15 kHz9 kHz
50 dB Bandwidth:30 kHz30 kHz22 kHz
Stopband Rejection:27 dB47 dB47 dB
Ceramic resonator Y70 provides phase vs. frequency characteristic required by the quadrature
detector, with 90 degree phase shift occurring at 455 kHz. Buffer Q70 provides a lower driving
impedance from the limiter to the resonator, improving the IF waveform and lowering the distortion of
the recovered audio signal. The recovered audio level at the DEMOD output is 120 mV rms (25 kHz
channel, 3 kHz deviation) or 60 mV rms (12.5 kHz chan n el, 1. 5 kHz devia tio n) . An ad dit ion a l RSSI
output provides a DC voltage level that is proportio nal to RF signal level. This volt age is measured by
an A/D converter contained in the microprocessor (PE4_AN4, U401 pin 63).
June, 20056880309N62-C
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146-174 MHz VHF Theory Of Operation: VHF Transmitter5-3
5.3VHF Tr ansmitter
The VHF transmitter covers the range of 146-174 MH z. Depen ding on mo del, the output po wer of the
transmitter is either switchable on a per-channel basis between high power (5 watts) and low power
(1 watt), or is factory preset to 2 watts. The transmitter is divided into four major blocks as shown in
Figure 5-2.
• Power Amplifier
• Harmonic Filter
• Antenna Matching Network
• Power Control
USWB+
TX_INJ
(From VCO)
TX_ENA
PWR_SET
5T
Q100
Power Control
VGG
Power Amplifier Module U110
Figure 5-2. VHF Transmitter Block Diagram
5.3.1Transmit Power Amplifier
The transmitter power amplifier has three stages of amplification. The first stage, Q100, operates in
Class AB from the 5T source. It provides 13 dB of gain and an output of 20 mW. The current drain is
typically 25mA. Components C105-C107 and L103 match the output of Q100 to the 50Ω input of the
module U110.
U110 is a two stage Silicon MOS FET power amplifier module. Drain voltage is obtained from UNSW
B+ after being routed through current-sense resistor R150 in the power control circuit. The output
power of the module is controlled by varying the DC gate bias on U110 pin 2 (VGG).
5.3.2Antenna Switch
VDD
RX_IN
(To Receiver)
Antenna
Switch
Harmonic Filter
Antenna
Matching
Network
J140 Antenna
Jack
Antenna
The antenna switch consists of two pin diodes, D120 and D121. In the rece ive mode, both diodes are
off. Signals applied at the antenna or at jack J140 are routed, via the harmonic filter, through network
C122-C124 and L121, to the receiver input. In the transmit mode, Q170 is on and TXB+ is present,
forward-biasing both diodes into conduction. The diode current is 50 mA, set by R120-R122. The
transmitter RF from U110 is routed through D120, and via the harmonic filter to the antenna jack.
D121 conducts, shunting RF power and preventing it from reaching the receiver. L121 is selected to
appear as a 1/4 wave at VHF, so that the low impedance of D121 appears as a high impedance at the
junction of D120 and the harmonic filter input. This provides a high series impedance and low shunt
impedance divider between the power amplifier output and receiver input.
5.3.3Harmonic Filter
The harmonic filter consists of components C130- C136 and L130-L132. The harmonic filter is a
seven-pole elliptical low-pass configuration, optimized for low insertion loss, with a 3 dB frequency of
approximately 210 MHz and typically less than 0.8 dB insertion loss in the passband.
6880309N62-CJune, 2005
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5-4146-174 MHz VHF Theory Of Operation: VHF Frequency Generation Circuitry
5.3.4Antenna Matching Network
The harmonic filter presents a 50 Ω impedance to antenna jack J140. A matching network, made up
of C140-C141 and L140, is used to match the antenna impedance to the harmonic filter. This
optimizes the performance of the transmitter and receiver into the impedance presented by the
antenna, significantly improving the antenna's efficiency.
5.3.5Power Control
The power control circuit is a dc-coupled amplifier whose output is the dc gate bias voltage (VGG)
applied to the two stages of the RF power amplifier U110.
The output power of the transmitter is adjusted by varying the setting of the power-set DAC cont ained
in the ASFICcmp IC (DACG, U451 pin 6). This PWR_SET voltage is applied to U150 pin 3.
Stage U150-2 compares the voltage drop across current sense resistor R150 to the voltage drop
across resistor R151 caused by current flow through Q150, and adjusts its output (pin 7) to maintain
equal voltages at pins 5 and 6. Thus the current flow through Q150, and hence its emitter voltage, is
proportional to the current drawn by stage U110, which is in turn proportional to the transmitter output
power. The emitter voltage of Q150 is applied to U150 pin 2, where it is compared to the power set
voltage PWR_SET at pin 3.
The output of U150 pin 1 is divided by R110 and R111 and applied as a gate voltage to the power
amplifier U110. By varying this gate voltage as needed to keep the voltages at U150 pins 2 and 3
equal, power is maintained at the desired setting. Excessive final current, for example due to antenna
mismatch, causes a lowering of the voltage at U150 pin 6, an increased voltage at pin 2, and a
lowering of the voltage at pin 1 and of the gate voltage VGG. This prevents damage to the final stage
due to excessive current.
5.4VHF Frequency Generation Circuitry
The frequency generation system, shown in Figure 5-3, is composed of two circuit blocks, the
Fractional-N synthesizer IC U201, the VCO/Buffer IC U251, and associated circuitry. Figure 5-4
shows the peripheral interconnect and support circuitry used in the synthesizer block, and Figure 5-5
details the internal circuitry of the VCOBIC and its interconnections to the surrounding components.
Refer to the schematic to identify reference designators.
The Fractional-N synthesizer is powered by regulated 5 V and 3 V provided by U310 and U330
respectively. 5 V is applied to U201 pins 13 and 30, and 3 V is applied to pins 5, 20, 34 and 36. The
synthesizer in turn generates a super-filtered 4.5 V supply (VSF, from pin 28) to power U251. In
addition to the VCO, the synthesizer also interfaces with the logic and ASFICcmp circuits.
Programming for the synthesizer is accomplished through the microprocessor SPI_DATA_OUT,
SPI_CLK, and SYNTH_CS (chip select) lines (U409 pins 100, 1 and 47 respectively). A logic high
(3 V) from U201 pin 4 indicates to the microprocessor that the synthesizer is locked.
June, 20056880309N62-C
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146-174 MHz VHF Theory Of Operation: VHF Frequency Generation Circuitry5-5
Transmit modulation from the ASFICcmp (U451 pin 40) is applied to U201 pin 10 (MOD_IN). An
electronic attenuator in the ASFICcmp adjusts overall transmitter deviation by varying the audio level
applied to the synthesizer IC. Internally the audio is digitized by the Fractional-N synthesizer and
applied to the loop divider to provide the low-port modulation. The audio is also routed through an
internal attenuator for the purpose of balancing the low port and high port modulation and reducing
the deviation by 6 dB for 12.5 kHz channels, and is available at U201 pin 41 (VCO_MOD). This audio
signal is routed to the VCO's modulator.
Voltage
Multiplier
VCP
Vmult1
Vmult2
Synthesizer
Aux3
U201
16.8 MHz
Ref. Osc.
MOD Out
Modulating
Signal
Figure 5-3. VHF Frequency Generation Unit Block Diagram
5.4.1Fractional-N Synthesizer
The Fractional-N synthesizer, shown in Figure 5-4, uses a 16.8 MHz crystal (Y201) to provide the
reference frequency for the system. External components C201-C203, R202 and D201 are also part
of the temperature-compensated oscillator circuit. The dc voltage applied to varactor D201 from U201
pin 25 is determined by a temperature-compensation algorithm within U201, and is specific to each
crystal Y201, based on a unique code assigned to the crystal that identifies its temperature
characteristics. Stability is better than 2.5 ppm over temperatures of -30 to 60 °C. Softwareprogrammable electronic frequency adjustment is achieved by an internal DAC which provides a
frequency adjustment voltage from U201 pin 25 to varact or D201.
The synthesizer IC U201 further divides the 16.8 MHz signal to 2.1 MHz, 2.225 MHz, or 2.4 MHz for
use as reference frequencies. It also provides a buffered 16.8 MHz signal at U201 pin 19 for use by
the ASFICcmp.
To achieve fast locking of the synthesizer, an internal adapt charge pump provides higher current at
U201 pin 45 to quickly force the synthesizer within lock range. The required frequency is then locked
by the normal mode charge pump at pin 43. A lo op filter (C243 -C245 and R243 -R245) removes noise
and spurs from the steering voltage applied to the VCO varactors, with additional filtering located in
the VCO circuit.
Both the normal and adapt charge pumps get their supply from the capa citive volt age multiplie r made
up of C221-C224 and D220-D221. Two 3 V square waves from U201 pins 14-15 provide the drive
signals for the voltage multiplier, which generates 12.1 V at U201 pin 47. This voltage is filtered by
C225-C228.
Loop
Filter
TRB
Rx VCO
Circuit
Tx VCO
Circuit
VCOBIC
U251
Rx Out
Tx Out
Buffer
Q280
To Mixer
To PA Driver
6880309N62-CJune, 2005
Page 40
5-6146-174 MHz VHF Theory Of Operation: VHF Frequency Generation Circuitry
One of the auxiliary outputs of the synthesizer IC (AUX3, U201 pin 2) provides the TRB signal which
determines the operating mode of the VCO, either receive or transmit.
13,30
10
23
25
32
47
7
8
9
DATA
CLK
CEX
MODIN
V
, 5V
CC
, 3V
V
DD
XTAL1
WARP
PREIN
VCP
VMULT2
U201
Low Voltage
Fractional-N
Synthesizer
VMULT1
14
15
Prescaler In
DATA (U401 Pin 100)
CLOCK (U401 Pin 1)
SYNTH_CS (U401 Pin 47)
MOD IN (U451 Pin 40)
+5V (U310 Pin 5)
+3V (U330 Pin 5)
Reference
Oscillator
Voltage
Multiplier
5,20,34,36
Figure 5-4. VHF Synthesizer Block Diagram
5.4.2Voltage Controlled Oscillator (VCO)
The VCOBIC (U251), shown in Figure 5-5, in conjunction with the Fractional-N synthesizer (U201)
generates RF in both the receive and the transmit modes of operation. The TRB line (U251 pin 19)
determines which oscillator and buffer are enabled. A sample of the RF signal from the enabled
oscillator is routed from U251 pin 12 through a low pass filter, to the prescaler input of the synthesizer
IC (U201 pin 32). After frequency comparison in the synthesizer, a resultant DC control voltage is
used to steer the VCO frequency. When the PLL is locked on frequency, this voltage can vary
between 3 V and 9 V. L251 and C251 further attenuate noise and spurs on the steering line voltage.
In the receive mode, the TRB line (U251 pin 19) is low. This activates the receive VCO and the
receive buffer of U251, which o perate within the ra nge of 190 .85 to 21 8.85 MHz. The VCO frequen cy
is determined by tank inductor L254, C253 -C257, and varactor D251. The buf fered RF signal at U251
pin 8 is further amplified by Q280 and applied as RX_INJ to the low-p ass injection filter in the receiver
front end circuit.
In the transmit mode, U251-19 is driven high by U201 pin 2, enabling the transmit VCO and buffer.
The 146-174 MHz RF signal from U251 pin 10 is applied as TX_INJ to the input of the transmitter
circuit via matching network C290-C291 and L291. TX VCO frequency is deter mined by L264, C263-
LOCK
FREFOUT
GND
IOUT
IADAPT
MODOUT
AUX3
SFOUT
BIAS1
BIAS2
4
19
6,22,23,24
43
45
41
2
28
40
39
LOCK (U401 Pin 56)
FREF (U451 Pin 34)
2-Pole
Loop Filter
VCO
TRB
Filtered 5V
Mod
Steering
Line
LO RF
Injection
Voltage
Controlled
Oscillator
TX RF
Injection
(First Stage of PA)
June, 20056880309N62-C
Page 41
146-174 MHz VHF Theory Of Operation: VHF Frequency Generation Circuitry5-7
C267, and varactor D261. High-port audio modulation from the synthesizer IC is applied as
VCO_MOD to varactor D262 which modulates the transmit VCO.
AUX3 (U201 Pin 2)
TRB_IN
Steer Line
Voltage
(V_STEER)
NC
NC
V_SF (U201 Pin 28)
RX VCO
RX
TX
Circuit
TX VCO
Circuit
Tank
Tank
Pin 7
Pin 13
Pin 3
Pin 4
Pin 5
Pin 6
Pin 16
Pin 15
Pin 18
Vcc-Logic
Pin 20
Vcc-Superfilter
Collector/RF in
RX
TX
Vsens
Circuit
TX/RX/BS
Switching Network
U251
VCOBIC
Rx Active
Bias
Tx Active
Bias
Pin 2
Rx-I adjust
Pin 19
Pin 1
Tx-I adjust
Pin 12
Presc
Pin 8
RX
Pin 14
Pin 10
TX
Pins 9,11,17
Prescaler Out
Buffer
Q280
VCC Buffers
U201 Pin 32
RX INJ
3V (U330 Pin 5)
Matching
Network
TX INJ
3V
(U330 Pin 5)
(U201 Pin 28)
Figure 5-5. VHF VCO Block Diagram
V_SF
6880309N62-CJune, 2005
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5-8146-174 MHz VHF Theory Of Operation: VHF Frequency Generation Circuitry
Notes:
June, 20056880309N62-C
Page 43
Chapter 6VHF Troubleshooting Tables
6.1Troubleshooting Table for Receiver
Table 6-1. Troubleshooting Table for Receiver
SymptomPossible CausesProcedureCorrective Action
Radio Dead (no
turn-on beep, no
LED indication)
1. Battery dead or defective.
2. Defective battery contacts.
3. Blown fuseCheck voltage on each side of fuse.
4. DC switching faultVerify battery voltage present at
5. Microprocessor not
starting up.
6. Regulator faultVerify U310-5 is 5 V dc, U320-5 is
Substitute known good battery or
battery eliminator.
Inspect battery contacts for corrosion
or bent terminals.
If blown, 0 VDC after fuse.
S444 pin 5 when radio is on.
Verify Q494-1 is at least 1 V dc,
Q494-6 is ~0.1 V dc, Q493-3 is at
Vbatt.
Verify clock input to U401-90
(EXTAL) is 7.3975 MHz using high
impedance probe. If clock is 3.8
MHz, check for shorts on U401 pins.
Connect RIB to verify communication via CPS.
Verify U401-94 (RESET) is high.
3.3 V dc, U330-5 is 3 V dc.
Charge or replace battery.
Clean/repair/replace J301.
Check for short on output,
check D301, VR301, troubleshoot/repair as needed, replace
fuse.
Check/replace on-off-volume
control S444.
Troubleshoot/replace Q493/4.
Verify 16.8 MHz signal at U451-
34. If OK, troubleshoot/replace
U451. If not present, troubleshoot U201 Synthesizer. Reprogram/reflash as needed.
If RESET is Low, troubleshoot
regulator U320. Check for
shorts at U401 pins. Replace
U401 (depot only). Reprogram/
reflash as needed.
Check for shorts on outputs,
troubleshoot/repair as needed,
replace faulty regulator.
Page 44
6-2VHF Troubleshooting Tables: Troubleshooting Table for Receiver
Table 6-1. Troubleshooting Table for Receiver (Continued)
SymptomPossible CausesProcedureCorrective Action
No Audio
No Receive
(squelch noise
present)
1. Synthesizer out of lock Verify U201-4 is at 3 V dc.Troubleshoot synthesizer/VCO
circuits.
2. Defective IFICVeri fy audio is present at U51-8.Check Q70, Y70, U51.
3. RX audio buffer faultVerify audio is present at U451-2.Check U510 and associated
parts.
4. ASFIC faultVerify audio is present at U451-41.
Verify U451-14 is high.
5. Audio PA faultVerify U490-1 is <0.2 V dc.
Verify audio is present at U490-5
and 8.
6. Defective speakerVerify audio is present at speaker
terminals.
1. No first injectionCheck that RF level at T42-6 is
approx +6 dBm.
Check that RF level at U251-8 is at
1VDD for analog circuits3.00
2DISC audio input1.34From U510
3Ground for analog circuitsGND
4DACU output0
5DACR output0
6DACG output2.38 (typ)Power set (TX mode)
7VOX peak detector output2.91
8PLCAP for DC integrator0.40
9SQIN0.01
10Universal audio input/output0
11VDD for DACs4.95
12SQCAP0
13GCB2 general purpose output0Audio PA_EN (unsquelched)
June, 20056880309N62-C
Page 57
VHF Troubleshooting Tables: Troubleshooting Table for Board and IC Signals6-15
Table 6-4. Troubleshooting Table for Board and IC Signals (Continued)
IC DesignatorPinPin FunctionDC VoltageComments (Condition)
U451
ASFIC_CMP
14GCB1 general purpose output0
15GCB0 general purpose output3.00BW select (25 kHz mode)
16Squelch channel activity output0To U401-84
17Squelch detect digital output0To U401-83
18PL/low speed data I/O1.50
19High speed data I/O3.00
20Chip select3.23From U401-2
21Serial clock input0
22Serial data input3.23
23Ground for clock synthesizerGND
24Loop filter cap for clock syn0.74
25PLCAP2 for LS integrator1.17
26Not used0
27Vdd for clock synthesizer3.00
28Clock synthesizer output1.70
291200 Hz ref for MDC decode3.00
30GNDDOGND
31Ground for digital circuitsGND
32Vdd for analog switches4.96
33Vdd for digital circuits3.00
3416.8 MHz master clock input1.54
35GCB3 general purpose output3.00Internal MIC enable
36TX audio return from option0
37GCB4 general purpose output0
38GCB5 general purpose output0
39RX audio send to option1.48
40Modulation output1.50To U201-10
41RX audio out to power amp1.51
42Flat TX audio return from option0.20
43RX audio return to option1.50
44Flat TX audio send to option1.50
45Vdd for audio path I/O filters3.00
46Mic audio input1.50
47Ground for audio path I/O filtersGND
48Ext mic audio input (not used)0
6880309N62-CJune, 2005
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6-16VHF Troubleshooting Tables: Troubleshooting Table for Board and IC Signals
Notes:
Table 6-4. Troubleshooting Table for Board and IC Signals (Continued)
IC DesignatorPinPin FunctionDC VoltageComments (Condition)
U480
Dual Opamp
U490
Audio Power Amp
U510
Dual Opamp
1Unit 1 output2.48
2Unit 1 (-) input2.48
3Unit 1 (+) input2.46
4GroundGND
5Unit 2 (+) input0.28
6Unit 2 (-) input0.29
7Unit 2 output0
8Vcc4.96
1Enable/shutdown0.12(Unsquelched)
2Bias reference3.26(Unsquelched)
3(+) input3.26(Unsquelched)
4(-) input3.27(Unsquelched)
5(-) output3.25(Unsquelched)
6Vcc7.48(Unsquelched)
7GroundGND
8(+) output3.29(Unsquelched)
1Unit 1 output1.75
2Unit 1 (-) input1.56
3Unit 1 (+) input1.55
4GroundGND
5Unit 2 (+) input1.55
6Unit 2 (-) input1.56
7Unit 2 output1.38
8Vcc4.96
1. All voltages are measured with a high-impedance digital voltmeter and expressed in volts DC relative to ground (0 V).
2. Voltages are measured with a DC input voltage of 7.50 + .02 volts DC applied to the battery connector (J301).
3. All voltages are measured in the squelched receive mode, unless otherwise indicated.
4. Voltages are identical for VHF and UHF models unless otherwise indicated.
June, 20056880309N62-C
Page 59
VHF (136-162 MHz) Schematic Diagrams, Overlays, and Parts Lists (8486769Z02-A)7-5
Chapter 7VHF (136-162 MHz) Schematic Diagrams, Overlays, and Parts Lists (8486769Z02-A)
SH4012686420Z01shield, comp side, memory
T412580541Z02transformer, balun
T422580541Z02transformer, balun
U515186144B01receiver system (IFIC), SA616
U525109522E10triple inverter, TC7W04F
U1100186438Z01transmitter PA module,
U1505113818A01dual op amp, LM2904
U1512484657R01bead, 57R01
U201*5185963A27frequency synthesizer, 63A27
U2515105750U54VCO/buffer, 50U54
U3105102478J015 V voltage regulator,
U3205185963A55adjustable voltage regulator w/
U3305102479J013 V voltage regulator,
U403Not_PlacedSRM2B256
U4255162852A09LOW PWR OP AMP W/RAIL
U4515185130C53audio filter (ASFIC.cmp),
U480Not_PlacedLM2904
U4905108858K99audio power amplifier,
U5105113818A01dual op amp, LM2904
U5114802245J54dual digital NPN, UMG5
U401*5102226J56microprocessor,