MX27C4100/27C4096
4M-BIT [512K x 8/256K x 16] CMOS EPROM
FEATURES
•256K x 16 organization(MX27C4096, JEDEC pin out)
•512K x 8 or 256K x 16 organization(MX27C4100, ROM pin out compatible)
•+12.5V programming voltage
•Fast access time: 100/120/150 ns
•Totally static operation
•Completely TTL compatible
•Operating current: 60mA
•Standby current: 100uA
•Package type:
-40 pin plastic DIP
-44 pin PLCC
-40 pin SOP
GENERAL DESCRIPTION
The MX27C4100/4096 is a 5V only, 4M-bit, One Time Programmable Read Only Memory. It is organized as 256K words by 16 bits per word(MX27C4096), 512K x 8 or 256K x 16(MX27C4100), operates from a single + 5 volt supply, has a static standby mode, and features fast single address location programming. All programming signals are TTL levels, requiring a single pulse. For programming outside from the system, existing EPROM
programmers may be used. The MX27C4100/4096 supports a intelligent fast programming algorithm which can result in programming time of less than two minutes.
This EPROM is packaged in industry standard 40 pin dual-in-line packages, 40 lead SOP, and 44 lead PLCC packages.
PIN CONFIGURATIONS
SOP/PDIP(MX27C4100)
A17 |
1 |
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40 |
A8 |
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A7 |
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A9 |
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A6 |
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A10 |
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A5 |
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A11 |
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A4 |
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36 |
A12 |
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A3 |
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35 |
A13 |
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A2 |
7 |
MX27C4100 |
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A14 |
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A1 |
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33 |
A15 |
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A0 |
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A16 |
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31 |
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CE |
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BYTE/VPP |
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GND |
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30 |
GND |
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29 |
Q15/A-1 |
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Q0 |
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Q7 |
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Q8 |
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Q14 |
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Q1 |
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Q6 |
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Q9 |
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25 |
Q13 |
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Q2 |
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24 |
Q5 |
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Q10 |
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Q12 |
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Q3 |
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Q4 |
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Q11 |
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VCC |
BLOCK DIAGRAM (MX27C4100)
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Q0~Q14 |
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LOGIC |
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BUFFERS |
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Q15/A-1 |
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Y-DECODER |
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Y-SELECT |
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A0~A17 |
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4M BIT |
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ADDRESS |
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X-DECODER |
CELL |
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INPUTS |
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MAXTRIX |
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VCC
GND
P/N: PM0197 |
REV. 3.4, AUG. 22, 2001 |
1
MX27C4100/27C4096
PIN CONFIGURATIONS
PLCC(MX27C4096)
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Q13 |
Q14 |
Q15 |
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CE |
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VPP |
NC |
VCC |
A17 |
A16 |
A15 |
A14 |
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Q12 |
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1 |
44 |
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40 |
A13 |
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Q11 |
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A12 |
Q10 |
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A11 |
Q9 |
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A10 |
Q8 |
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MX27C4096 |
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A9 |
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GND |
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34 |
GND |
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NC |
Q7 |
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A8 |
Q6 |
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A7 |
Q5 |
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A6 |
Q4 |
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23 |
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29 |
A5 |
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18 |
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28 |
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Q3 |
Q2 |
Q1 |
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Q0 |
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OE |
NC |
A0 |
A1 |
A2 |
A3 |
A4 |
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PIN CONFIGURATIONS
PDIP(MX27C4096)
VPP |
1 |
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CE |
2 |
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Q15 |
3 |
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Q14 |
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Q13 |
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Q12 |
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Q11 |
7 |
MX27C4096 |
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Q10 |
8 |
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Q9 |
9 |
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Q8 |
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GND |
11 |
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Q7 |
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Q6 |
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Q5 |
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Q4 |
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Q3 |
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Q2 |
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Q1 |
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Q0 |
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OE |
20 |
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40 VCC
39 A17
38 A16
37 A15
36 A14
35 A13
34 A12
33 A11
32 A10
31 A9
30 GND
29 A8
28 A7
27 A6
26 A5
25 A4
24 A3
23 A2
22 A1
21 A0
BLOCK DIAGRAM (MX27C4096)
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CE |
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CONTROL |
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OUTPUT |
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Q0~Q15 |
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LOGIC |
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BUFFERS |
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OE |
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Y-DECODER |
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Y-SELECT |
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A0~A17 |
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4M BIT |
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ADDRESS |
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X-DECODER |
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CELL |
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INPUTS |
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MAXTRIX |
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VCC |
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VPP |
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GND |
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P/N: PM0197 |
REV. 3.4, AUG. 22, 2001 |
2
MX27C4100/27C4096
PIN DESCRIPTION(MX27C4100)
SYMBOL |
PIN NAME |
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A0~A17 |
Address Input |
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Q0~Q14 |
Data Input/Output |
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CE |
Chip Enable Input |
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OE |
Output Enable Input |
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BYTE/VPP |
Word/Byte Selection/Program Supply Voltage |
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Q15/A-1 |
Q15(Word mode)/LSB addr. (Byte mode) |
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VCC |
Power Supply Pin (+5V) |
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GND |
Ground Pin |
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PIN DESCRIPTION(MX27C4096)
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SYMBOL |
PIN NAME |
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A0~A17 |
Address Input |
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Q0~Q15 |
Data Input/Output |
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Chip Enable Input |
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CE |
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Output Enable Input |
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OE |
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VPP |
Program Supply Voltage |
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VCC |
Power Supply Pin (+5V) |
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GND |
Ground Pin |
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TRUTH TABLE OF BYTE FUNCTION(MX27C4100)
BYTE MODE(BYTE = GND)
CE |
OE |
Q15/A-1 |
MODE |
Q0-Q7 |
SUPPLY CURRENT |
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H |
X |
X |
Non selected |
High Z |
Standby(ICC2) |
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L |
H |
X |
Non selected |
High Z |
Operating(ICC1) |
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L |
L |
A-1 input |
Selected |
DOUT |
Operating(ICC1) |
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WORD MODE(BYTE = VCC)
CE |
OE |
Q15/A-1 |
MODE |
Q0-Q14 |
SUPPLY CURRENT |
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H |
X |
High Z |
Non selected |
High Z |
Standby(ICC2) |
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L |
H |
High Z |
Non selected |
High Z |
Operating(ICC1) |
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L |
L |
DOUT |
Selected |
DOUT |
Operating(ICC1) |
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NOTE : X = H or L |
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P/N: PM0197 |
REV. 3.4, AUG. 22, 2001 |
3
MX27C4100/27C4096
FUNCTIONAL DESCRIPTION
THE PROGRAMMING OF THE MX27C4100/4096
When the MX27C4100/4096 is delivered, or it is erased, the chip has all 4M bits in the "ONE" or HIGH state. "ZEROs" are loaded into the MX27C4100/4096 through the procedure of programming.
For programming, the data to be programmed is applied with 16 bits in parallel to the data pins.
VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP. When programming an MXIC EPROM, a 0.1uF capacitor is required across VPP and ground to suppress spurious voltage transients which may damage the device.
FAST PROGRAMMING
The device is set up in the fast programming mode when the programming voltage VPP = 12.75V is applied, with VCC = 6.25 V and OE = VIH (Algorithm is shown in Figure 1). The programming is achieved by applying a single TTL low level 100us pulse to the CE input after addresses and data line are stable. If the data is not verified, an additional pulse is applied for a maximum of 25 pulses. This process is repeated while sequencing through each address of the device. When the programming mode is completed, the data in all address is verified at VCC = VPP = 5V ± 10%.
PROGRAM INHIBIT MODE
Programming of multiple MX27C4100/4096's in parallel with different data is also easily accomplished by using the Program Inhibit Mode. Except for CE and OE, all like inputs of the parallel MX27C4100/4096 may be common. A TTL low-level program pulse applied to an MX27C4100/4096 CE input with VPP = 12.5 ± 0.5 V will program the MX27C4100/4096. A high-level CE input inhibits the other MX27C4100/4096s from being programmed.
PROGRAM VERIFY MODE
Verification should be performed on the programmed bits to determine that they were correctly programmed.
The verification should be performed with OE and CE at
VIL(for MX27C4096), OE at VIL and CE at VIH(for MX27C4100) and VPP at its programming voltage.
AUTO IDENTIFY MODE
The auto identify mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and device type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C± 5°C ambient temperature range that is required when programming the MX27C4100/4096.
To activate this mode, the programming equipment must force 12.0 ±0.5 V on address line A9 of the device. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during auto identify mode.
Byte 0 ( A0 = VIL) represents the manufacturer code, and byte 1 (A0 = VIH), the device identifier code. For the MX27C4100/4096, these two identifier bytes are given in the Mode Select Table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (Q15) defined as the parity bit.
READ MODE
The MX27C4100/4096 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE's, assuming that CE has been LOW and addresses have been stable for at least tACC - t OE.
WORD-WIDE MODE
With BYTE/VPP at VCC ± 0.2V outputs Q0-7 present data Q0-7 and outputs Q8-15 present data Q8-15, after CE and OE are appropriately enabled.
P/N: PM0197 |
REV. 3.4, AUG. 22, 2001 |
4
MX27C4100/27C4096
BYTE-WIDE MODE
With BYTE/VPP at GND ± 0.2V, outputs Q8-15 are tristated. If Q15/A-1 = VIH, outputs Q0-7 present data bits Q8-15. If Q15/A-1 = VIL, outputs Q0-7 present data bits Q0-7.
STANDBY MODE
The MX27C4100/4096 has a CMOS standby mode which reduces the maximum VCC current to 100 uA. It is placed in CMOS standby when CE is at VCC ± 0.3 V. The MX27C4100/4096 also has a TTL-standby mode which reduces the maximum VCC current to 1.5 mA. It is placed in TTL-standby when CE is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input.
TWO-LINE OUTPUT CONTROL FUNCTION
To accommodate multiple memory connections, a twoline control function is provided to allow for:
1.Low memory power dissipation,
2.Assurance that output bus contention will not occur.
It is recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device.
SYSTEM CONSIDERATIONS
During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1 uF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between Vcc and GND to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7 uF bulk electrolytic capacitor should be
used between VCC and GND for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array.
P/N: PM0197 |
REV. 3.4, AUG. 22, 2001 |
5
MX27C4100/27C4096
MODE SELECT TABLE (MX27C4096)
PINS
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MODE |
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CE |
OE |
A0 |
A9 |
VPP |
OUTPUTS |
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Read |
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VIL |
VIL |
X |
X |
VCC |
DOUT |
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Output Disable |
VIL |
VIH |
X |
X |
VCC |
High Z |
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Standby (TTL) |
VIH |
X |
X |
X |
VCC |
High Z |
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Standby (CMOS) |
VCC±0.3V |
X |
X |
X |
VCC |
High Z |
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Program |
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VIL |
VIH |
X |
X |
VPP |
DIN |
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Program Verify |
VIH |
VIL |
X |
X |
VPP |
DOUT |
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Program Inhibit |
VIH |
VIH |
X |
X |
VPP |
High Z |
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Manufacturer Code(3) |
VIL |
VIL |
VIL |
VH |
VCC |
00C2H |
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Device Code(3) |
VIL |
VIL |
VIH |
VH |
VCC |
0151H |
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NOTES: 1. |
VH |
= 12.0 V ± 0.5 V |
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3. A1 - A8 = A10 - A17 = |
VIL(For auto select) |
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2. |
X = |
Either VIH or VIL |
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4. See DC Programming Characteristics for VPP voltage during |
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programming. |
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MODE SELECT TABLE (MX27C4100)
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BYTE/ |
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MODE |
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A9 |
A0 |
Q15/A-1 |
VPP(5) |
Q8-14 |
Q0-7 |
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CE |
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OE |
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Read (Word) |
VIL |
VIL |
X |
X |
Q15 Out |
VCC |
Q8-14 Out |
Q0-7 Out |
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Read (Upper Byte) |
VIL |
VIL |
X |
X |
VIH |
GND |
High Z |
Q8-15 Out |
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Read (Lower Byte) |
VIL |
VIL |
X |
X |
VIL |
GND |
High Z |
Q0-7 Out |
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Output Disable |
VIL |
VIH |
X |
X |
High Z |
X |
High Z |
High Z |
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Standby |
VIH |
X |
X |
X |
High Z |
X |
High Z |
High Z |
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Program |
VIL |
VIH |
X |
X |
Q15 In |
VPP |
Q8-14 In |
Q0-7 In |
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Program Verify |
VIH |
VIL |
X |
X |
Q15 Out |
VPP |
Q8-14 Out |
Q0-7 Out |
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Program Inhibit |
VIH |
VIH |
X |
X |
High Z |
VPP |
High Z |
High Z |
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Manufacturer Code(3) |
VIL |
VIL |
VH |
VIL |
0B |
VCC |
00H |
C2H |
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Device Code(3) |
VIL |
VIL |
VH |
VIH |
1B |
VCC |
38H |
00H |
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NOTES: 1. |
VH = 12.0V ± 0.5V |
4. |
See DC Programming Characteristics for VPP voltages. |
2. |
X = Either VIH or VIL |
5. |
BYTE/VPP is intended for operation under DC Voltage conditions |
3. A1 - A8, A10 - A17 = VIL(for auto select) |
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only. |
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6. |
Manufacture code = 00C2H |
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Device code = B800H |
P/N: PM0197 |
REV. 3.4, AUG. 22, 2001 |
6