High Efficiency Maintained Over Wide Current Range
■
Current Mode Operation for Excellent Line and Load
Transient Response
■
Very Low Dropout Operation: 100% Duty Cycle
■
Short-Circuit Protection
■
Synchronous FET Switching for High Efficiency
■
Adaptive Non-Overlap Gate Drives
■
Available in SSOP and SO Packages
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APPLICATIO S
■
Step-Down and Inverting Regulators
■
Notebook and Palmtop Computers
■
Portable Instruments
■
Battery-Operated Digital Devices
■
Industrial Power Distribution
■
Avionics Systems
■
Telecom Power Supplies
LTC1159
LTC1159-3.3/LTC1159- 5
High Efficiency Synchronous
Step-Down Switching Regulators
U
DESCRIPTIO
The LTC®1159 series is a family of synchronous step-down
switching regulator controllers featuring automatic Burst
ModeTM operation to maintain high efficiencies at low
output currents. These devices drive external complementary power MOSFETs at switching frequencies up to 250kHz
using a constant off-time current-mode architecture.
A separate pin and on-board switch allow the MOSFET
driver power to be derived from the regulated output
voltage providing significant efficiency improvement when
operating at high input voltages. The constant off-time
current-mode architecture maintains constant ripple current in the inductor and provides excellent line and load
transient response. The output current level is user programmable via an external current sense resistor.
The LTC1159 automatically switches to power saving
Burst Mode operation when load current drops below
approximately 15% of maximum current. Standby current
is only 300µA while still regulating the output and shut-
down current is a low 20µA.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a trademark of Linear Technology Corporation.
TYPICAL APPLICATIO
V
IN
+
3.3µF
0V = NORMAL
>2V = SHUTDOWN
3300pF
1k
C
T
300pF
CAP
V
CC
V
CC
SHDN1
SHDN2
I
TH
C
T
S-GND
0.15µF
Figure 1. High Efficiency Step-Down Regulator
P-GATE
P-DRIVE
EXTV
LTC1159-5
SENSE
SENSE
N-GATE
P-GND
U
V
IN
+
C
R
SENSE
0.05Ω
IN
100µF
100V
21
4
+
V
OUT
5V/2A
C
OUT
220µF
100
FIGURE 1 CIRCUIT
90
80
EFFICIENCY (%)
70
60
0.02
LTC1159-5 Efficiency
VIN = 10V
VIN = 20V
0.22
LOAD CURRENT (A)
LTC1159 • TA01
1N4148
Si9435DY
0.1µF
CC
+
–
D1
MBRS140T3
0.01µF
LTC1159 • F01
L*
33µH
3
Si9410DY
*COILTRONICS CTX33-4-MP
1
LTC1159
LTC1159-3.3/LTC1159-5
A
W
O
LUTEXI TIS
S
A
WUW
U
ARB
G
(Note 1)
Input Supply Voltage (Pin 2) ..................... –15V to 60V
VCC Output Current (Pin 3) .................................. 50mA
–Current Sense Threshold VoltageLow Threshold (Forced)25mV
High Threshold (Forced)125150175mV
SHDN2 Threshold0.81.42V
Off-Time (Note 5)CT = 390pF, I
= 700mA, VIN = 10V3.556.5µs
LOAD
Note 3: On LTC1159 versions which have a SHDN1 pin, it must be at
ground potential for testing.
is calculated from the ambient temperature TA and power
J
according to the following formulas:
D
= TA + (PD • 135°C/W)
J
= TA + (PD • 80°C/W)
J
= TA + (PD • 110°C/W)
J
Note 4: The LTC1159 V
MOSFET driver currents. When V
, the input current increases by (I
EXTV
CC
and EXTVCC current measurements exclude
IN
power is derived from the output via
CC
• Duty Cycle)/(Efficiency).
GATECHG
See Typical Performance Characteristics and Applications Information.
Note 5: In applications where R
is placed at ground potential, the off-
SENSE
time increases approximately 40%.
3
LTC1159
LOAD CURRENT (A)
0
–100
∆V
OUT
(mV)
–80
–60
–40
–20
0
20
0.51.01.52.0
LTC1159 • TPC03
2.5
FIGURE 1 CIRCUIT
V
IN
= 24V
LTC1159-3.3/LTC1159-5
LECTRICAL CCHARA TERIST
E
ICS
Note 6: The LTC1159C, LTC1159C-3.3, and LTC1159C-5 are not tested
and not quality assurance sampled at –40°C and 85°C. These
specifications are guaranteed by design and/or correlation. The LTC1159I,
LTC1159I-3.3 and LTC1159I-5 are guaranteed and tested over the –40°C
Note 7: The logic-level power MOSFETs shown in Figure 1 are rated for
V
= 30V. For operation at VIN > 30V, use standard threshold
DS(MAX)
MOSFETs with EXTV
Information.
to 85°C operating temperature range.
UW
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Input Voltage
100
FIGURE 1 CIRCUIT
I
= 1A
LOAD
95
90
EFFICIENCY (%)
85
80
0
5101520
INPUT VOLTAGE (V)
NOTE 6
25 30 35 40
LTC1159 • TPC01
Line Regulation
60
FIGURE 1 CIRCUIT
= 1A
I
LOAD
40
20
(mV)
0
OUT
∆V
–20
–40
–60
0
515
1020
INPUT VOLTAGE (V)
30
25
NOTE 6
35
LT1159 • TPC02
powered from a 12V supply. See Applications
CC
Load Regulation
40
Operating Frequency
EXTVCC Pin Current
10
FIGURE 1 CIRCUIT
8
I
= 1A
LOAD
6
CURRENT (mA)
4
CC
I
= 100mA
EXTV
2
0
0
510
LOAD
I
= 0
LOAD
20
152540
INPUT VOLTAGE (V)
NOTE 6
30 35
LTC1159 • TPC04
VIN Pin Current
500
FIGURE 1 CIRCUIT
400
300
200
SUPPLY CURRENT (µA)
100
0
0
510
INPUT VOLTAGE (V)
NORMAL
V
= 2V
SHDN2
20
152540
NOTE 6
30 35
LTC1159 • TPC05
vs (VIN – V
2.0
V
= 5V
OUT
1.5
1.0
0.5
NORMALIZED FREQUENCY
0
0
5
(VIN – V
OUT
10
OUT
)
T = 0°C
T = 70°C
15
) VOLTAGE (V)
T = 25°C
20
25
LTC1159 • TPC06
4
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC1159
LTC1159-3.3/LTC1159- 5
EXTVCC Switch DropCurrent Sense Threshold Voltage
600
500
400
(mV)
CC
300
– V
CC
200
EXTV
100
0
0
5101520
SWITCH CURRENT (mA)
LTC1159 • TPC07
U
UU
Off-Time vs V
80
70
60
50
40
30
OFF-TIME (µs)
20
10
0
0
OUT
LTC1159-3.3
1
2
OUTPUT VOLTAGE (V)
LTC1159-5
34
LTC1159 • TPC08
5
160
140
120
100
80
60
SENSE VOLTAGE (mV)
40
20
0
0
20
MAXIMUM
THRESHOLD
THRESHOLD
6080
40
TEMPERATURE (°C)
PI FU CTIO S
VIN: Main Supply Input Pin.
SGND: Small-Signal Ground. Must be routed separately
from other grounds to the (–) terminal of C
OUT
.
PGND: Driver Power Grounds. Connect to source of Nchannel MOSFET and the (–) terminal of CIN.
VCC: Outputs of internal 4.5V linear regulator, EXTV
switch, and supply inputs for driver and control circuits.
The driver and control circuits are powered from the higher
of the 4.5V regulator or EXTVCC voltage. Must be closely
decoupled to power ground.
SENSE+: The (+) Input for the Current Comparator. A builtin offset between the SENSE+ and SENSE– pins, in conjunction with R
, sets the current trip threshold.
SENSE
N-Gate: High Current Drive for the Bottom N-Channel
MOSFET. The N-Gate pin swings from ground to VCC.
P-Gate: Level-Shifted Gate Drive Signal for the Top
CC
P-Channel MOSFET. The voltage swing at the P-gate pin is
from VIN to VIN – VCC.
P-Drive: High Current Gate Drive for the Top P-Channel
MOSFET. The P-drive pin(s) swing(s) from VCC to ground.
MINIMUM
100
LTC1159 • TPC09
CT: External capacitor CT from this pin to ground sets the
operating frequency. (The frequency is also dependent on
the ratio V
OUT/VIN
.)
ITH: Gain Amplifier Decoupling Point. The current comparator threshold increases with the I
pin voltage.
TH
VFB: For the LTC1159 adjustable version, the VFB pin
receives the feedback voltage from an external resistive
divider used to set the output voltage.
SENSE–: Connects to internal resistive divider which sets
the output voltage in fixed output versions. The SENSE– pin
is also the (–) input of the current comparator.
CAP: Charge Compensation Pin. A capacitor to VCC pro-
vides charge required by the P-gate level-shift capacitor
during supply transitions.
pacitor must be larger than the gate drive capacitor
SHDN1: This pin shuts down the control circuitry only (V
The charge compensation ca-
.
CC
is not affected). Taking SHDN1 pin high turns off the
control circuitry and holds both MOSFETs off. This pin
must be at ground potential for normal operation.
SHDN2: Master Shutdown Pin. Taking SHDN2 high shuts
down VCC and all control circuitry.
5
LTC1159
LTC1159-3.3/LTC1159-5
U
U
W
FU CTIO AL DIAGRA
V
IN
SHDN2
EXTV
LOW DROPOUT
4.5V REGULATOR
CC
LOW DROP SWITCH
SLEEP
+
S
V
–
TH2
CAP
V
CC
V
C
T
Internal divider broken at VFB for adjustable versions.
550k
PGND
–
V
+
25mV TO 150mV
13k
SGND
TH
TH1
Q
–
T
+
OFF-TIME
CONTROL
R
S
–
SENSE
–
C
+
I
V
CC
G
550k
–
+
1.25V
REFERENCE
SENSE
P-GATE
P-DRIVE
N-GATE
+
V
OS
SHDN1
–
SENSE
100k
LTC1159 • FD
V
FB
U
OPERATIO
The LTC1159 uses a current mode, constant off-time
architecture to synchronously switch an external pair of
complementary power MOSFETs. Operating frequency is
set by an external capacitor at the CT pin.
The output voltage is sensed either by an internal voltage
divider connected to the SENSE– pin (LTC1159-3.3 and
LTC1159-5) or an external divider returned to the VFB pin
(LTC1159). A voltage comparator V, and a gain block G,
compare the divided output voltage with a reference voltage of 1.25V. To optimize efficiency, the LTC1159 automatically switches between two modes of operation, burst
and continuous.
A low dropout 4.5V regulator provides the operating voltage VCC for the MOSFET drivers and control circuitry during
start-up. During normal operation, the LTC1159 family
powers the drivers and control from the output via the
EXTVCC pin to improve efficiency. The N-GATE pin is
referenced to ground and drives the N-channel MOSFET
gate directly. The P-channel gate drive must be referenced
to the main supply input VIN, which is accomplished by
(Refer to Functional Diagram)
level-shifting the P-drive signal via an internal 550k resistor
and external capacitor.
During the switch “ON” cycle in continuous mode, current
comparator C monitors the voltage between the SENSE
+
and SENSE– pins connected across an external shunt in
series with the inductor. When the voltage across the shunt
reaches its threshold value, the P-gate output is switched
to VIN, turning off the P-channel MOSFET. The timing
capacitor CT is now allowed to discharge at a rate determined by the off-time controller. The discharge current is
made proportional to the output voltage to model the
inductor current, which decays at a rate which is also
proportional to the output voltage. While the timing
capacitor is discharging, the N-gate output is high, turning
on the N-channel MOSFET.
When the voltage on CT has discharged past V
, compara-
TH1
tor T trips, setting the flip-flop. This causes the N-gate output
to go low (turning off the N-channel MOSFET) and the Pgate output to also go low (turning the P-channel MOSFET
back on). The cycle then repeats. As the load current
6
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