Page 1
Application Note 124
775 Nanovolt Noise Measurement for A Low Noise
Voltage Reference
Quantifying Silence
Jim Williams
July 2009
Introduction
Frequently, voltage reference stability and noise defi ne
measurement limits in instrumentation systems. In particular, reference noise often sets stable resolution limits.
Reference voltages have decreased with the continuing
drop in system power supply voltages, making reference
noise increasingly important. The compressed signal
processing range mandates a commensurate reduction
in reference noise to maintain resolution. Noise ultimately
translates into quantization uncertainty in A to D converters,
introducing jitter in applications such as scales, inertial
navigation systems, infrared thermography, DVMs and
medical imaging apparatus. A new low voltage reference,
the LTC6655, has only 0.3ppm (775nV) noise at 2.5V
OUT
.
Figure 1 lists salient specifi cations in tabular form. Accuracy and temperature coeffi cient are characteristic of
high grade, low voltage references. 0.1Hz to 10Hz noise,
particularly noteworthy, is unequalled by any low voltage
electronic reference.
Noise Measurement
Special techniques are required to verify the LTC6655’s extremely low noise. Figure 2’s approach appears innocently
straightforward but practical implementation represents a
high order diffi culty measurement. This 0.1Hz to 10Hz noise
testing scheme includes a low noise pre-amplifi er, fi lters
and a peak-to-peak noise detector. The pre-amplifi ers 160nV
noise fl oor, enabling accurate measurement, requires
special design and layout techniques. A forward gain of
6
permits readout by conventional instruments.
10
Figure 3’s detailed schematic reveals some considerations
required to achieve the 160nV noise fl oor. The references
DC potential is stripped by the 1300μF, 1.2k resistor
combination; AC content is fed to Q1. Q1-Q2, extraordinarily low noise J-FET’s, are DC stabilized by A1, with A2
providing a single-ended output. Resistive feedback from
A2 stabilizes the confi guration at a gain of 10,000. A2’s
output is routed to amplifi er-fi lter A3-A4 which provides
0.1Hz to 10Hz response at a gain of 100. A5-A8 comprise
a peak-to-peak noise detector read out by a DVM at a
scale factor of 1 volt/microvolt. The peak-to-peak noise
detector provides high accuracy measurement, eliminating
tedious interpretation of an oscilloscope display. Instantaneous noise value is supplied by the indicated output to a
monitoring oscilloscope. The 74C221 one-shot, triggered
by the oscilloscope sweep gate, resets the peak-to-peak
noise detector at the end of each oscilloscope 10-second
sweep.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
LTC6655 Reference Tabular Specifi cations
SPECIFICATION LIMITS
Output Voltages 1.250, 2.048, 2.500, 3.000, 3.300, 4.096, 5.000
Initial Accuracy 0.025%, 0.05%
Temperature Coeffi cient 2ppm/°C, 5ppm/°C
0.1Hz to 10Hz Noise 0.775μV at V
Additional Characteristics 5ppm/Volt Line Regulation, 500mV Dropout, Shutdown Pin, I
Figure 1. LTC6655 Accuracy and Temperature Coeffi cient Are Characteristic of High Grade, Low Voltage References.
0.1Hz to 10Hz Noise, Particularly Noteworthy, Is Unequalled by Any Low Voltage Electronic Reference
I
OUT(SINK/SOURCE)
= 2.500V, Peak-to-Peak Noise is within this Figure in 90% of 1000 Ten Second Measurement Intervals
OUT
= ±5mA, I
Circuit = 15mA.
SHORT
= 5mA, VIN = VO + 0.5V to 13.2V
SUPPLY
,
MAX
AN124-1
an124f
Page 2
Application Note 124
A = 10
6
LTC6655
2.5V REFERENCE
, 0.1Hz TO 10Hz = 160nV
E
N
≈700nV
NOISE
0.1Hz TO 10Hz
LOW NOISE
AC PRE-AMP
A = 10,000
VERTICAL
INPUT
0.1Hz TO 10Hz FILTER AND
PEAK TO PEAK NOISE DETECTOR
0μV TO 1μV = 0V TO 1V, A = 100
OUTPUT
OSCILLOSCOPE
RESET
AN124 F02
SWEEP
GATE OUT
DC OUT
0V TO 1V = 0μV
AT INPUT
1μV
P-P
P-P
TO
Figure 2. Conceptual 0.1Hz to 10Hz Noise Testing Scheme Includes Low Noise Pre-Amplifi er, Filter and Peak to Peak Noise
Detector. Pre-Amplifi er’s 160nV Noise Floor, Enabling Accurate Measurement, Requires Special Design and Layout Techniques
Numerous details contribute to the circuit’s performance.
The 1300μF capacitor, a highly specialized type, is selected
for leakage in accordance with the procedure given in
Appendix B. Further, it, and its associated low noise 1.2k
resistor, are fully shielded against pick-up. FETs Q1 and
Q2 differentially feed A2, forming a simple low noise op
amp. Feedback, provided by the 100k - 10Ω pair, sets
closed loop gain at 10,000. Although Q1 and Q2 have
extraordinarily low noise characteristics, their offset and
afforded by conventional diodes. Diodes at the FET gates
clamp reverse voltage, further minimizing leakage.
storage capacitors highly asymmetric charge-discharge
profi le necessitates the low dielectric absorption polypro-
3
pelene capacitors specifi ed.
Oscilloscope connections via
galvanically isolated links prevent ground loop induced
corruption. The oscilloscope input signal is supplied by an
isolated probe; the sweep gate output is interfaced with an
isolation pulse transformer. Details appear in Appendix C.
drift are uncontrolled. A1 corrects these defi ciencies by
adjusting Q1’s channel current via Q3 to minimize the
Q1-Q2 input difference. Q1’s skewed drain values ensure
that A1 is able to capture the offset. A1 and Q3 supply
whatever current is required into Q1’s channel to force
offset within about 30μV. The FETs’ V
can vary over
GS
a 4:1 range. Because of this, they must be selected for
10% V
matching. This matching allows A1 to capture
GS
the offset without introducing signifi cant noise. Q1 and
Noise Measurement Circuit Performance
Circuit performance must be characterized prior to measuring LTC6655 noise. The pre-amplifi er stage is verifi ed
for >10Hz bandwidth by applying a 1μV step at its input
(reference disconnected) and monitoring A2’s output.
Figure 4’s 10ms risetime indicates 35Hz response, insuring
the entire 0.1Hz to 10Hz noise spectrum is supplied to the
succeeding fi lter stage.
Q2 are thermally mated and lagged in epoxy at a time
constant much greater than A1’s DC stabilizing loop rolloff, preventing offset instability and hunting. The entire
A1-Q1-Q2-A2 assembly and the reference under test are
1
completely enclosed within a shielded can.
The reference
is powered by a 9V battery to minimize noise and insure
freedom from ground loops.
Peak-to-peak detector design considerations include J-FET’s
used as peak trapping diodes to obtain lower leakage than
Note 1. The pre-amplifi er structure must be carefully prepared. See
Appendix A, “Mechanical and Layout Considerations”, for detail on preamplifi er construction.
Note 2. Diode connected J-FET’s superior leakage derives from their
extremely small area gate-channel junction. In general, J-FET’s leak a few
picoamperes (25°C) while common signal diodes (e.g. 1N4148) are about
1,000X worse (units of nanoamperes at 25°C).
Note 3. Tefl on and polystyrene dielectrics are even better but the Real
World intrudes. Tefl on is expensive and excessively large at 1μF. Analog
types mourn the imminent passing of the polystyrene era as the sole
manufacturer of polystyrene fi lm has ceased production.
2
The peak
an124f
AN124-2
Page 3
Application Note 124
+
+
16V
10k*
330μF
16V
100Ω*330Ω*
10k
ROOT-SUM-SQUARE
+
IN OUT
330μF
SEE TEXT
CORRECTION
+
16V
16V
330μF
GENERATOR
+15
RESET PULSE
10k
0.22μF
+15
BAT-85
RC2
C2
RST = Q2
+15
BAT-85
B2
+V
74C221
10k
A2
CLR2
+15
VIA ISOLATION
SWEEP GATE OUTPUT
FROM OSCILLOSCOPE
PULSE TRANSFORMER
Q1, Q2 = THERMALLY MATED
< 5nA
LEAK
T
= TANTALUM,WET SLUG
I
SEE TEXT/APPENDIX B
10%)
GS
OR LSK389 DUAL
THERMALLY LAG
SEE TEXT
2SK369 (MATCH V
P
= POLYPROPELENE
330μF
A4
LT1012
–
+
0.1μF
0.1μF
A = 100 AND
0.1Hz TO 10Hz FILTER
0.1μF
124k* 124k*
1M*
A3
LT1012
+
–
2k
1μF
AN124 F03
AT 25°C
DC
A4 330μF OUTPUT CAPACITORS = <200nA LEAKAGE
AT 1V
10V
1N4697
0.15μF
15V
SWEEP = 1s/DIV
1V/DIV = 1μV/DIV,
REFERRED TO INPUT,
VIA ISOLATED PROBE,
100k*
10Ω*
0.022μF
5
A2
LT1097
–
+
900Ω*
15V
200Ω*
1k*
450Ω*
–15V
Q3
10k
2N2907
1μF
A1
+
1μF
LT1012
–15V
–
4
A = 10
LOW NOISE
PRE-AMP
100k100k
SHIELD
T
1300μF
– INPUT
Q2
Q1
750Ω*
**1.2k
+
F
S
1μF
SHIELDED CAN
–15V
AC LINE GROUND
PEAK TO PEAK
NOISE DETECTOR
4.7k
+
–
A7
1/4 LT1058
+ PEAK
A5
1/4 LT1058
P
1μF
TO OSCILLOSCOPE INPUT
1k
+
–
+
O TO 1V =
O TO 1μV
–
DVM
0.1μF
0.005μF
100k
1k
+
– PEAK
4.7k
* = 1% METAL FILM
** = 1% WIREWOUND, ULTRONIX105A
A8
1/4 LT1058
= 1N4148
–
–
A6
1/4 LT1058
100k
P
1μF
= 2N4393
+
= 1/4 LTC202
SEE APPENDIX C FOR POWER, SHIELDING
AND GROUNDING SCHEME
. Peak to Peak Noise Detector, Reset by Monitoring Oscilloscope Sweep Gate, Supplies DVM Output
6
0.005μF
LTC6655
9V
IN
2.5V
REFERENCE
SD
UNDER TEST
RST
10k
–15
RST
10k
Figure 3. Detailed Noise Test Circuitry. Thermally Lagged Q1-Q2 Low Noise J-FET Pair Is DC Stabilized by A1-Q3; A2 Delivers A = 10,000 Pre-Amplifi er Output. A3-A4 form 0.1Hz to
15
10Hz ,A = 100, Bandpass Filter; Total Gain Referred to Pre-Amplifi er Input Is 10
an124f
AN124-3
Page 4
Application Note 124
Figure 5 describes peak-to-peak noise detector operation.
Waveforms include A3’s input noise signal (Trace A), A7
(Trace B) positive/A8 (Trace C) negative peak detector
outputs and DVM differential input (Trace D). Trace E’s
oscilloscope supplied reset pulse has been lengthened
for photographic clarity.
Circuit noise fl oor is measured by replacing the LTC6655
with a 3V battery stack. Dielectric absorption effects in
the large input capacitor require a 24-hour settling period
before measurement. Figure 6, taken at the circuit’s oscilloscope output, shows 160nV 0.1Hz to 10Hz noise in a
10 second sample window. Because noise adds in rootsum-square fashion, this represents about a 2% error in
2mV/DIV
10ms/DIV
Figure 4. Pre-Amplifi er Rise Time Measures 10ms; Indicated
35Hz Bandwidth Ensures Entire 0.1Hz to 10Hz Noise Spectrum Is
Supplied to Succeeding Filter Stage
A = 5mV/DIV
B = 0.5V/DIV
C = 0.5V/DIV
D = 1V/DIV
E = 20V/DIV
1s/DIV
Figure 5. Waveforms for Peak to Peak Noise Detector Include
A3 Input Noise Signal (Trace A), A7 (Trace B) Positive/A8
(Trace C) Negative Peak Detector Outputs and DVM Differential
Input (Trace D). Trace E’s Oscilloscope Supplied Reset Pulse
Lengthened for Photographic Clarity
AN124 F04
AN124 F05
100nV/DIV
1s/DIV
Figure 6. Low Noise Circuit/Layout Techniques Yield 160nV
0.1Hz to 10Hz Noise Floor, Ensuring Accurate Measurement.
Photograph Taken at Figure 3’s Oscilloscope Output with 3V
Battery Replacing LTC6655 Reference. Noise Floor Adds ≈2%
Error to Expected LTC6655 Noise Figure Due to Root-Sum-Square
Noise Addition Characteristic; Correction is Implemented at
Figure 3’s A3
AN124 F06
the LTC 6655’s expected 775nV noise fi gure. This term is
accounted for by placing Figure 3’s “root-sum-square correction” switch in the appropriate position during reference
testing. The resultant 2% gain attenuation fi rst order corrects LTC6655 output noise reading for the circuit’s 160nV
noise fl oor contribution. Figure 7, a strip-chart recording
of the peak-to-peak noise detector output over 6 minutes,
4
shows less than 160nV test circuit noise.
Resets occur
every 10 seconds. A 3V battery biases the input capacitor,
replacing the LTC6655 for this test.
Figure 8 is LTC6655 noise after the indicated 24-hour
dielectric absorption soak time. Noise is within 775nV
peak-to-peak in this 10 second sample window with
the root-sum-square correction enabled. The verifi ed,
extremely low circuit noise fl oor makes it highly likely
this data is valid. In closing, it is worth mention that the
approach taken is applicable to measuring any 0.1Hz to
10Hz noise source, although the root-sum-square error
correction coeffi cient should be re-established for any
given noise level.
Note 4. That’s right, a strip-chart recording. Stubborn, locally based
aberrants persist in their use of such archaic devices, forsaking more
modern alternatives. Technical advantage could account for this choice,
although deeply seated cultural bias may be indicated.
AN124-4
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Page 5
Application Note 124
100nV
AMPLITUDE
0V
1 MIN
Figure 7. Peak to Peak Noise Detector Output Observed Over
6 Minutes Shows <160nV Test Circuit Noise. Resets Occur
Every 10 seconds. 3V Battery Biases Input Capacitor, Replacing
LTC6655 for This Test
TIME
AN124 F07
REFERENCES
1. Morrison, Ralph, “Grounding and Shielding Techniques
in Instrumentation,” Wiley-Interscience, 1986.
2. Ott, Henry W., “Noise Reduction Techniques in Electronic Systems,” Wiley-Interscience, 1976.
3. LSK-389 Data Sheet, Linear Integrated Systems.
4. 2SK-369 Data Sheet, Toshiba.
5. LTC6655 Data Sheet, Linear Technology Corporation.
6. LT1533 Data Sheet, Linear Technology Corporation.
7. Williams, Jim, “Practical Circuitry for Measurement
and Control Problems,” Linear Technology Corporation, Application Note 61, August 1994.
8. Williams, Jim, “A Monolithic Switching Regulator with
100μV Output Noise,” Linear Technology Corporation,
Application Note 70, October 1997.
9. Williams, Jim and Owen, Todd, “Performance Verifi cation of Low Noise, Low Dropout Regulators,” Linear
Technology Corporation, Application Note 83, March
2000.
500nV/DIV
1s/DIV
Figure 8. LTC6655 0.1Hz to 10Hz Noise Measures 775nV in
10 Second Sample Time
AN124 F08
10. Williams, Jim, “Low Noise Varactor Biasing with
Switching Regulators,” Linear Technology Corporation,
Application Note 85, August 2000, pages 4-6.
11. Williams, Jim, “Minimizing Switching Regulator Residue in Linear Regulator Outputs,” Linear Technology
Corporation, Application Note 101, July 2005.
12. Williams, Jim, “Power Conversion, Measurement
and Pulse Circuits,” Linear Technology Corporation,
Application Note 113, August 2007.
13. Williams, Jim, “High Voltage, Low Noise, DC-DC Converters,” Linear Technology Corporation, Application
Note 118, March 2008.
14. Tektronix, Inc., “Type 1A7 Plug-In Unit Operating and
Service Manual,” Tektronix, Inc., 1965.
15. Tektronix, Inc., “Type 1A7A Differential Amplifi er Operating and Service Manual,” Tektronix, Inc. 1968.
16. Tektronix, Inc. “Type 7A22 Differential Amplifi er Operating and Service Manual,” Tektronix, Inc., 1969.
17. Tektronix, Inc., “AM502 Differential Amplifi er Operating
and Service Manual,” Tektronix, Inc., 1973.
an124f
AN124-5
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Application Note 124
APPENDIX A
Mechanical and Layout Considerations
The low noise X10,000 preamplifi er, crucial to the noise
measurement, must be quite carefully prepared. Figure
A1 shows board layout. The board is enclosed within
a shielded can, visible in A1A. Additional shielding is
provided to the input capacitor and resistor (A1A left);
the resistor’s wirewound construction has low noise but
is particularly susceptible to stray fi elds. A1A also shows
the socketed LTC6655 reference under test (below the
large input capacitor shield) and the JFET input amplifi er
associated components. Q3 (A1A upper right), a heat
source, is located away from the JFET printed circuit lands,
preventing convection currents from introducing noise.
Additionally, the JFET’s are contained within an epoxy fi lled
plastic cup (Figure A1B center), promoting thermal mating
1
and lag.
This thermal management of the FETs prevents
offset instability and hunting in A1’s stabilizing loop from
masquerading as low frequency noise. ±15V power enters
the enclosure via banana jacks; the reference is supplied
by a 9V battery (both visible in A1A). The A = 100 fi lter
and peak-peak detector circuitry occupies a separate board
outside the shielded can. No special commentary applies to
this section although board leakage to the peak detecting
capacitors should be minimized with guard rings or fl ying
lead/Tefl on stand-off construction.
Note 1. The plastic cup, supplied by Martinelli and Company, also
includes, at no charge, 10 ounces of apple juice.
Figure A1A. Figure A1B.
Figure A1. Preamplifi er Board Top (Figure A1A) and Bottom (A1B) Views. Board Top Includes Shielded Input Capacitor (Upper Left)
and Input Resistor (Upper Center Left). Stabilized JFET Input Amplifi er Occupies Board Upper Center Right; Output Stage Adjoins
BNC Fitting. Reference Under Test Resides in Socket Below Input Capacitor. ±15 Power Enters Shielded Enclosure Via Banana Jacks
(Extreme Right). 9V Battery (Lower) Supplies Reference Under Test. Board Bottom’s Epoxy Filled Plastic Cup (A1B Center) Contains
JFETs, Provides Thermal Mating and Lag
AN124-6
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Application Note 124
APPENDIX B
Input Capacitor Selection Procedure
The input capacitor, a highly specialized type, must be
selected for leakage. If this is not done, resultant errors
can saturate the input pre-amplifi er or introduce noise.
The highest grade wet slug 200°C rated tantalum capacitors are utilized. The capacitor operates at a small fraction of its rated voltage at room temperature, resulting
in much lower leakage than its specifi cation indicates.
VISHAY
XTV138M030P0A
WET SLUG TANTALUM
3V
AA
CELLS
1.5V
1.5V
+
1300μF/30V
TEST SEQUENCE
1. TURN OFF MICROVOLT METER
2. CONNECT 3V BATTERY STACK
3. WAIT 24 HOURS
4. TURN ON MICROVOLT METER
5. READ CAPACITOR LEAKAGE, 1nA = 1μV
–
1k
The capacitor’s dielectric absorption requires a 24-hour
charge time to insure meaningful measurement. Capacitor
leakage is determined by following the 5-step procedure
given in the fi gure. Yield to required 5-nanoampere leakage exceeds 90%.
Note 1. This high yield is most welcome because the specifi ed capacitors
are spectacularly priced at almost $400.00. There may be a more palatable
alternative. Selected commercial grade aluminum electrolytics can
approach the required DC leakage although their aperiodic noise bursts
(mechanism not understood; reader comments invited) are a concern.
HP-419A MICROVOLT METER
hp
+
–
1
AN124 FB01
Figure B1. Pre-Amplifi er Input Capacitor Selected for <5nA Leakage to Minimize DC Error and Capacitor
Introduced Noise. Capacitor Dielectric Absorption Requires 24 Hour Charge Time to Insure Meaningful
Measurement. Highest Grade Wet Slug Tantalum Capacitors are Required to Pass This Test
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Application Note 124
APPENDIX C
Power, Grounding and Shielding Considerations
Figure 3’s circuit requires great care in power distribution,
grounding and shielding to achieve the reported results.
Figure C1 depicts an appropriate scheme. A low shunt capacitance line isolation transformer powers an instrument
grade ±15V supply, furnishing clean, low noise power. The
pre-amplifi er’s shielded can is tied to the 110V AC ground
terminal, directing pick-up to earth ground. Filter/peak-topeak detector oscilloscope connections are made via an
isolated probe and a pulse isolation transformer, precluding
1
error inducing ground loops.
The indicated loop, included
to verify no current fl ow between circuit common and earth
ground, is monitored with a current probe. Figures C2 and
C3, both optional, show battery powered supplies which
replace the line isolation transformer and instrumentation
grade power supplies. C2 uses linear regulators to furnish low noise ±15V. Because the batteries fl oat, positive
regulators suffi ce for both positive and negative rails. In
C3, a single battery stack supplies an extremely low noise
DC-DC converter to furnish positive and negative rails via
2
low noise discrete linear regulators.
Both of these battery
supplied approaches are economical compared to the AC
line powered version but require battery maintenance.
The indicated commercial products accompanying
Figure C1’s blocks represent typical applicable units which
have been found to satisfy requirements. Other types
may be employed but should be verifi ed for necessary
performance.
Note 1. An acceptable alternative to the isolated probe is monitoring
Figure 3’s A4 output current into a grounded 1k resistor with a DC
stabilized current probe (e.g. Tektronix P6042, AM503). The resultant
isolated 1V/μV oscilloscope presentation requires 10Hz lowpass fi ltering
(see Appendix D) due to inherent current probe noise.
Note 2. References 6 and 8 detail the specialized DC-DC converter used.
OSCILLOSCOPE
VERTICAL
9V
BATTERY
SHIELDED CAN
= AC LINE GROUND
= CIRCUIT COMMON
REFERENCE
UNDER TEST
TEKTRONIX A6909,
TEKTRONIX A6902B,
SIGNAL ACQUISITION
TECHNOLOGIES SL-10
A = 10,000
PRE-AMP
RF
FEEDTHROUGHS
HEWLETT PACKARD,
6111A,
PHILBRICK RESEARCHES
6033, PR-300
PEAK TO PEAK
+15
–15
INSTRUMENT
GRADE ±15V
POWER SUPPLY
INPUT
ISOLATED
PROBE
A = 100
FILTER AND
DETECTOR
CIRCUIT
COMMON
SWEEP RESET
PEAK TO PEAK
RESET
+
DVM
–
CAPACITANCE ISOLATION
FROM SHIELDED CAN)
CURRENT
MONITOR
PULSE ISOLATION
TRANSFORMER/
COAXIAL CAPACITOR
TOPAZ, 0111T35S
LOW SHUNT
TRANSFORMER
(LOCATE ≥3 FEET
LOOP
DEERFIELD LAB 185,
HEWLETT PACKARD
10240B
110VAC
LINE INPUT
AN124 FC1
Figure C1. Power/Grounding/Shielding Scheme for Low Noise Measurement Minimizes AC Line Originated Interference
and Mixing of Circuit Return and AC Line Ground Current. No Current Should Flow in Current Monitor Loop
AN124-8
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Application Note 124
12 Size D
ALKALINE
1.5V CELLS
EACH PACK
+18
+
SD
IN OUT
SD
IN OUT
+
10μF
* = 1% METAL FILM RESISTOR
B
LT1761
FB
B
LT1761
FB
0.1μF
13.7k*
1.21k*
0.1μF
13.7k*
1.21k*
AN124 FC2
+15
+
10μF10μF
–15
10μF
+
Figure C2. LT1761 Regulators form ±15V, Low Noise Power Supply. Isolated Battery Packs Permit Positive
Regulator to Supply Negative Output and Eliminate Possible AC Line Referred Ground Loops
an124f
AN124-9
Page 10
Application Note 124
4.99k*
–
1/2 LT1013
+
5k
19V UNREGULATED
10k*
LT1010
LT 1 0 1 0
8
47μF
0.1μF
47μF
0.1μF
L1
25μH
+ +
15V
OUT
OUT
COMMON
–15V
OUT
OUT
IN
10k*
10V
L2
25μH
LT 1 0 2 1
AN124 FC3
6V BATTERY
4x 1.5V
ALKALINE
D CELL
6V
+
4.7μF
14 13 12
V
IN
GND FB
43k
5V
L1: 22nH INDUCTOR. COILCRAFT B-07T TYPICAL,
PC TRACE, OR FERRITE BEAD
L2, L3: PULSE ENGINEERING. PE92100
T1: COILTRONICS CTX-02-13664-X1
: 1N4148
* = 1% METAL FILM
R
LT1533
3300pF
10k
15k
15k
32
R
VSL
C
T
5
DUTY
CSL
R
PGND
T
6
L1
18k
COL A
COL B
10k*
1μF
6V
+
4.7μF
151689
12
T1
2
3
10
4
9
5
7
100μF
+
–19V UNREGULATED
4
–
1/2 LT1013
+
100μF
+
Figure C3. A Low Noise, Bipolar, Floating Output Converter. Grounding LT1533 “DUTY” Pin and Biasing FB Puts Regulator into 50%
Duty Cycle Mode. LT1533’s Controlled Transition Times Permit <100μV Broadband Output Noise; Discrete Linear Regulators Maintain
Low Noise, Provide Regulation
AN124-10
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Page 11
Application Note 124
APPENDIX D
are single-pole types resulting in somewhat pessimistic
bandwidth cut-offs. Additionally, the amplifi ers listed do
High Sensitivity, Low Noise Amplifi ers
Figure D1 lists some useful low level amplifi ers for setting
up and troubleshooting the texts’ circuit. The table lists
both oscilloscope plug-in amplifi ers and stand-alone types.
Two major restrictions apply. The fi lters in these units
INSTRUMENT
TYPE MANUFACTURER
Differential Amplifi er Tektronix 1A7/1A7A 1MHz 10μV/DIV Secondary Market Requires 500 Series Mainframe,
Differential Amplifi er Tektronix 7A22 1MHz 10μV/DIV Secondary Market Requires 7000 Series Mainframe,
Differential Amplifi er Tektronix 5A22 1MHz 10μV/DIV Secondary Market Requires 5000 Series Mainframe,
Differential Amplifi er Tektronix ADA-400A 1MHz 10μV/DIV Current Production Stand-Alone with Optional Power
Differential Amplifi er Preamble 1822 10MHz Gain = 1000 Current Production Stand-Alone, Settable Bandstops
Differential Amplifi er Stanford
Research
Systems
Differential Amplifi er Tektronix AM-502 1MHz Gain = 100000 Secondary Market Requires TM-500 Series Power
MODEL
NUMBER
SR-560 1MHz Gain = 50000 Current Production Stand-Alone, Settable Bandstops,
–3dB
BANDWIDTH
not include 10Hz lowpass frequency fi lters, although
they are easily modifi ed to provide this capability. Figure
D2 lists four amplifi ers with the necessary modifi cation
information.
Note 1. See References 14-17.
MAXIMUM
SENSITIVITY/GAIN AVAILABILITY COMMENTS
1
Settable Bandstops
Settable Bandstops
Settable Bandstops
Supply, Settable Bandstops
Battery or Line Operation
Supply, Settable Bandstops
Figure D1. Some Useful High Sensitivity, Low Noise Amplifi ers. Trade-Offs Include Bandwidth, Sensitivity and Availability
MANUFACTURER MODEL NUMBER MODIFICATION
Tektronix 1A7 Parallel C370A with 1μF
Tektronix 1A7A Parallel C445A with 1μF
Tektronix 7A22 Parallel C426H with 3μF
Tektronix AM502 Parallel C449 with 3μF
Figure D2. Modifi cation Information for Various Tektronix Low
Level Oscilloscope Plug-In’s and Amplifi ers Permits 10Hz High
Frequency Filter Operation in 100Hz Panel Switch Position. All
Cases Utilize 100V, Mylar Capacitors
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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AN124-11
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Application Note 124
500nV/DIV
1s/DIV
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Linear Technology Corporation
AN124-12
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
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LT 0709 • PRINTED IN USA
© LINEAR TECHNOLOGY CORPORATION 2009
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