LED LCD TV
SERVICE MANUAL
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
CHASSIS : LB12D
MODEL : 47LW9800 47LW9800-TA
North/Latin America http://aic.lgservice.com
Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com
Internal Use Only
Printed in Korea P/NO : MFL67007028 (1108-REV00)
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LGE Internal Use Only Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
CONTENTS
CONTENTS .............................................................................................. 2
PRODUCT SAFETY ................................................................................. 3
SPECIFICATION ....................................................................................... 4
ADJUSTMENT INSTRUCTION ................................................................ 8
EXPLODED VIEW .................................................................................. 16
SCHEMATIC CIRCUIT DIAGRAM ..............................................................
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LGE Internal Use Only Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
SAFETY PRECAUTIONS
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
General Guidance
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC
power line. Use a transformer of adequate power rating as this
protects the technician from accidents resulting in personal injury
from electrical shocks.
It will also protect the receiver and it's components from being
damaged by accidental shorts of the circuitry that may be
inadvertently introduced during the service operation.
If any fuse (or Fusible Resistor) in this TV receiver is blown,
replace it with the specified.
When replacing a high wattage resistor (Oxide Metal Film Resistor,
over 1 W), keep the resistor 10 mm away from PCB.
Keep wires away from high voltage or high temperature parts.
Before returning the receiver to the customer,
always perform an AC leakage current check on the exposed
metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.
Leakage Current Cold Check(Antenna Cold Check)
With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩ and 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.
Leakage Current Hot Check (See below Figure)
Plug the AC cord directly into the AC outlet.
Do not use a line Isolation Transformer during this check.
Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
between a known good earth ground (Water Pipe, Conduit, etc.)
and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
Reverse plug the AC cord into the AC outlet and repeat AC voltage
measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
0.5 mA.
In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.
Leakage Current Hot Check circuit
1.5 Kohm/10W
To Instrument's
exposed
METALLIC PARTS
Good Earth Ground
such as WATER PIPE,
CONDUIT etc.
AC Volt-meter
When 25A is impressed between Earth and 2nd Ground
for 1 second, Resistance must be less than 0.1
*Base on Adjustment standard
IMPORTANT SAFETY NOTICE
0.15 uF
Ω
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LGE Internal Use Only Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement
.
1. Application range
This specification is applied to the LCD TV used LB12D
chassis.
2. Requirement for Test
Each part is tested as below without special appointment.
1) Temperature: 25 ºC ± 5 ºC(77 ºF ± 9 ºF), CST: 40 ºC ± 5 ºC
2) Relative Humidity: 65 % ± 10 %
3) Power Voltage
: Standard input voltage (AC 100-240 V~, 50/60 Hz)
* Standard Voltage of each products is marked by models.
4) Specification and performance of each parts are followed
each drawing and specification by part number in
accordance with BOM.
5) The receiver must be operated for about 5 minutes prior to
the adjustment.
3. Test method
1) Performance: LGE TV test method followed
2) Demanded other specification
- Safety : CE, IEC specification
- EMC : CE, IEC
4. Model General Specification
No. Item Specification Remarks
1. Market ASIA, Oceania, Africa, DTV & Analog
Middle East(PAL/DVB Market) * DTV Region : Australia/New Zealand(AU), Singapore(SG), Indonesia(ID),
Malaysia(MY), Vietnam(VN), South Africa(ZA), Iran(IR)
2. Broadcasting system 1) PAL-B/G * Australia/India : only PAL
2) PAL-D/K
3) PAL-I/I’
3) SECAM-DK, BG, I
4) DVB-T
3. Receiving system Analog : Upper Heterodyne G DVB-T
Digital : COFDM, QAM - Guard Interval(Bitrate_Mbit/s)
1/4, 1/8, 1/16, 1/32
- Modulation : Code Rate
QPSK : 1/2, 2/3, 3/4, 5/6, 7/8
16-QAM : 1/2, 2/3, 3/4, 5/6, 7/8
64-QAM : 1/2, 2/3, 3/4, 5/6, 7/8
4. Video Input RCA (2EA) PAL, SECAM, NTSC 4 System : PAL, SECAM, NTSC, PAL60
Rear 1EA, AV gender jack 1EA
5. Head phone out Antena, AV1, AV2, Component1,
Component2, RGB, HDMI1, HDMI2,
HDMI3, HDMI4, USB1, USB2
6. Component Input (2EA) Y/Cb/Cr, Y/Pb/Pr Rear 1EA, Gender 1EA
7. RGB Input (1EA) RGB-PC Analog(D-SUB 15PIN)
8. HDMI Input (4EA) HDMI1-ARC PC(HDMI version 1.3) Support HDCP
HDMI2
HDMI3
HDMI4
9. Audio Input (5EA) RGB/DVI Audio L/R Input
Component1,2
AV1,2
10. SDPIF out (1EA) SPDIF out
11. USB (2EA) EMF, DivX HD, For SVC(download) JPEG, MP3, DivX HD Plus
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LGE Internal Use Only Copyright © 2011 LG Electronics. Inc. All rights reserved.
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5. Component Video Input (Y, CB/P B, C R/P R)
No.
Specification
Remark
Resolution H-freq(kHz) V-freq(Hz)
1. 720x480 15.73 60.00 SDTV,DVD 480i
2. 720x480 15.63 59.94 SDTV,DVD 480i
3. 720x480 31.47 59.94 480p
4. 720x480 31.50 60.00 480p
5. 720x576 15.625 50.00 SDTV,DVD 625 Line
6. 720x576 31.25 50.00 HDTV 576p
7. 1280x720 45.00 50.00 HDTV 720p
8. 1280x720 44.96 59.94 HDTV 720p
9. 1280x720 45.00 60.00 HDTV 720p
10. 1920x1080 31.25 50.00 HDTV 1080i
11. 1920x1080 33.75 60.00 HDTV 1080i
12. 1920x1080 33.72 59.94 HDTV 1080i
13. 1920x1080 56.250 50 HDTV 1080p
14. 1920x1080 67.5 60 HDTV 1080p
No.
Specification
Proposed Remarks
Resolution H-freq(kHz) V-freq(Hz) Pixel Clock(MHz)
1. 720*400 31.468 70.08 28.321 For only DOS mode
2. 640*480 31.469 59.94 25.17 VESA Input 848*480 60 Hz, 852*480 60 Hz
-> 640*480 60 Hz Display
3. 800*600 37.879 60.31 40.00 VESA
4. 1024*768 48.363 60.00 65.00 VESA(XGA)
5. 1360*768 47.72 59.8 84.75 WXGA
6. 1920*1080 66.587 59.93 138.625 WUXGA FHD model
6. RGB (PC)
7. HDMI Input
(1) DTV Mode
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark
1. 720*480 31.469 / 31.5 59.94 / 60 27.00 / 27.03 SDTV 480P
2. 720*576 31.25 50 54 SDTV 576P
3. 1280*720 37.500 50 74.25 HDTV 720P
4. 1280*720 44.96 / 45 59.94 / 60 74.17 / 74.25 HDTV 720P
5. 1920*1080 33.72 / 33.75 59.94 / 60 74.17 / 74.25 HDTV 1080I
6. 1920*1080 28.125 50.00 74.25 HDTV 1080I
7. 1920*1080 26.97 / 27 23.97 / 24 74.17 / 74.25 HDTV 1080P
8. 1920*1080 33.716 / 33.75 29.976 / 30.00 74.25 HDTV 1080P
9. 1920*1080 56.250 50 148.5 HDTV 1080P
10. 1920*1080 67.43 / 67.5 59.94 / 60 148.35 / 148.50 HDTV 1080P
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LGE Internal Use Only Copyright © 2011 LG Electronics. Inc. All rights reserved.
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No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark
1 720*400 31.468 70.08 28.321 HDCP
2 640*480 31.469 59.94 25.17 VESA HDCP
3 800*600 37.879 60.31 40.00 VESA HDCP
4 1024*768 48.363 60.00 65.00 VESA(XGA) HDCP
5 1360*768 47.72 59.8 84.75 WXGA HDCP
6 1280*1024 63.981 60.02 108 SXGA HDCP
7 1920*1080 67.5 60.00 138.625 WUXGA HDCP / FHD model
(2) PC Mode
8. 3D Mode - HDMI & USB
(1) HDMI Input (V1.4a)
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed 3D input proposed mode
1 1920*1080 53.95 / 54 23.98 / 24 148.35/148.5 HDTV 1080P Frame packing
2 1280*720 89.9 / 90 59.94/60 148.35/148.5 HDTV 720P Frame packing
3 1280*720 75 50 148.5 HDTV 720P Frame packing
4 1920*1080 67.5 60 148.5 HDTV 1080P Side by Side(half), Top and bottom
5 1920*1080 56.3 50 148.5 HDTV 1080P Side by Side(half), Top and bottom
6 1280*720 45 60 74.25 HDTV 720P Side by Side(half), Top and Bottom
7 1280*720 37.5 50 74.25 HDTV 720P Side by Side(half), Top and Bottom
8 1920*1080 33.7 60 74.25 HDTV 1080i Side by Side(half), Top and Bottom
9 1920*1080 28.1 50 74.25 HDTV 1080i Side by Side(half), Top and Bottom
10 1920*1080 27 24 74.25 HDTV 1080P Side by Side(half), Top and Bottom
11 1920*1080 33.7 30 89.1 HDTV 1080P Side by Side(half), Top and Bottom
(2) HDMI Input(1.3)
No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed 3D input proposed mode
1 1280*720 45.00 60.00 74.25 HDTV 720P Side by Side, Top & Bottom
2 1280*720 37.500 50 74.25 HDTV 720P Side by Side, Top & Bottom
3 1920*1080 33.75 60.00 74.25 HDTV 1080I Side by Side, Top & Bottom
4 1920*1080 28.125 50.00 74.25 HDTV 1080I Side by Side, Top & Bottom
5 1920*1080 27.00 24.00 74.25 HDTV 1080P Side by Side, Top & Bottom, Checkerboard
6 1920*1080 33.75 30.00 74.25 HDTV 1080P Side by Side, Top & Bottom, Checkerboard
7 1920*1080 67.50 60.00 148.5 HDTV 1080P Side by Side, Top & Bottom, Checkerboard
Single Frame Sequential
8 1920*1080 56.250 50 148.5 HDTV 1080P Side by Side, Top & Bottom, Checkerboard
Single Frame Sequential
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LGE Internal Use Only Copyright © 2011 LG Electronics. Inc. All rights reserved.
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No. Side by Side Top & Bottom Checkerboard Single Frame Sequential Frame Packing 2D to 3D
1
(6) USB Input
(3) RF 3D Input(DTV)
(8) 3D Input mode
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed 3D input proposed mode
1 1280*720 37.500 50 74.25 HDTV 720P Side by Side, Top & Bottom
2 1920*1080 28.125 50 74.25 HDTV 1080I Side by Side, Top & Bottom
(4) RGB-PC Input
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed 3D input proposed mode
1 1920*1080 67.5 60 148.5 HDTV 1080P Side by Side, Top & Bottom
(5) DLNA
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed 3D input proposed mode
1 1920*1080 33.75 30 74.25 HDTV 1080P Side by Side, Top & Bottom,
Checkerboard
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode Proposed
1 1920*1080 33.75 30.000 74.25 Side by Side HDTV 1080P
Top & Bottom
Checkerboard
(7) DVR
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode Proposed
1 ALL - - - Side by Side
Top & Bottom
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LGE Internal Use Only Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
ADJUSTMENT INSTRUCTION
1. Application Range
This specification sheet is applied to all of the LED LCD TV
with LB12D chassis.
2. Designation
1) Because this is not a hot chassis, it is not necessary to use
an isolation transformer. However, the use of isolation
transformer will help protect test instrument.
2) Adjustment must be done in the correct order.
3) The adjustment must be performed in the circumstance of
25 ºC ± 5 ºC of temperature and 65 % ± 10 % of relative
humidity if there is no specific designation.
4) The input voltage of the receiver must keep AC 100-240
V~, 50/60 Hz.
5) The receiver must be operated for about 5 minutes prior to
the adjustment when module is in the circumstance of over
15.
In case of keeping module is in the circumstance of 0 °C, it
should be placed in the circumstance of above 15 °C for 2
hours.
In case of keeping module is in the circumstance of below 20 °C, it should be placed in the circumstance of above 15
°C for 3 hours.
[Caution]
When still image is displayed for a period of 20 minutes or
longer (especially where W/B scale is strong. Digital pattern
13ch and/or Cross hatch pattern 09ch), there can some
afterimage in the black level area.
3. Automatic Adjustment
3.1. ADC Adjustment
(1) Overview
ADC adjustment is needed to find the optimum black level
and gain in Analog-to-Digital device and to compensate
RGB deviation.
(2) Equipment & Condition
1) Jig (RS-232C protocol)
2) MSPG-925 Series Pattern Generator(MSPG-925FA,
pattern - 65)
- Resolution : 480i Comp1
1080P Comp1
1920*1080 RGB
- Pattern : Horizontal 100% Color Bar Pattern
- Pattern level : 0.7±0.1 Vp-p
- Image
(3) Adjustment
1) Adjustment method
- Using RS-232, adjust items in the other shown in
“3.1.(3).3)”
2) Adj. protocol
Ref.) ADC Adj. RS232C Protocol_Ver1.0
3) Adj. order
- aa 00 00 [Enter ADC adj. mode]
- xb 00 04 [Change input source to Component1 (480i&
1080p)]
- ad 00 10 [Adjust 480i&1080p Comp1]
- xb 00 06 [Change input source to RGB(1024*768)]
- ad 00 10 [Adjust 1920*1080 RGB]
- ad 00 90 End adj.
3.2. MAC Address
(1) Equipment & Condition
- Play file: Serial.exe
- MAC Address edit
- Input Start / End MAC address
(2) Download method
1) Communication Prot connection
Connect: PCBA Jig-> RS-232C Port== PC-> RS-232C Port
Protocol Command Set ACK
Enter adj. mode aa 00 00 a 00 OK00x
Source change xb 00 40 b 00 OK40x (Adjust 480i, 1080p Comp1 )
xb 00 60 b 00 OK60x (Adjust 1920*1080 RGB)
Begin adj. ad 00 10
Return adj. result OKx (Case of Success)
NGx (Case of Fail)
Read adj. data (main) (main)
ad 00 20 000000000000000000000000007c007b006dx
(sub) (Sub)
ad 00 21 000000070000000000000000007c00830077x
Confirm adj. ad 00 99 NG 03 00x (Fail)
NG 03 01x (Fail)
NG 03 02x (Fail)
OK 03 03x (Success)
End adj. aa 00 90 a 00 OK90x
PCBA
PC(RS-232C)
RS-232C Po rt
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2) MAC Address Download, Whidevine Download
- Com 1,2,3,4 and 115200(Baud rate)
3.3. LAN
(1) Equipment & Condition
A Each other connection to LAN Port of IP Hub and Jig
(2) LAN inspection solution
A LAN Port connection with PCB
A Network setting at MENU Mode of TV
A Setting automatic IP
A Setting state confirmation
-> If automatic setting is finished, you confirm IP and
MAC Address.
(3) WIDEVINE key Inspection
- Confirm key input data at the “IN START” MENU Mode.
3.4. LAN PORT INSPECTION(PING TEST)
Connect SET -> LAN port == PC -> LAN Port
(1) Equipment setting
1) Play the LAN Port Test PROGRAM.
2) Input IP set up for an inspection to Test Program.
*IP Number : 12.12.2.2
(2) LAN PORT inspection (PING TEST)
1) Play the LAN Port Test Program.
2) Connect each other LAN Port Jack.
3) Play Test (F9) button and confirm OK Message.
4) Remove LAN cable.
3.5. Model name & Serial number Download
(1) Model name & Serial number D/L
A Press “Power on” key of service remote control.
(Baud rate : 115200 bps)
A Connect RS232 Signal Cable to RS-232 Jack.
A Write Serial number by use RS-232.
A Must check the serial number at Instart menu.
(2) Method & notice
A. Serial number D/L is using of scan equipment.
B. Setting of scan equipment operated by Manufacturing
Technology Group.
C. Serial number D/L must be conformed when it is
produced in production line, because serial number D/L
is mandatory by D-book 4.0
SET PC
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LGE Internal Use Only Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
* Manual Download (Model Name and Serial Number)
If the TV set is downloaded by OTA or service man, sometimes
model name or serial number is initialized.(Not always)
It is impossible to download by bar code scan, so It need
Manual download.
a. Press the ‘instart’ key of ADJ remote control.
b. Go to the menu ‘6.Model Number D/L’ like below photo.
c. Input the Factory model name(ex 42LD450-TA) or Serial
number like photo.
d. Check the model name Instart menu -> Factory name
displayed (ex 42LE7500-TA)
e. Check the Diagnostics(DTV country only) -> Buyer model
displayed (ex 42LE7500-TA)
3.6. WIFI MAC ADDRESS CHECK
a. Using RS232
b. Check the menu on in-start
4. Manual Adjustment
4.1. ADC Adjustment
4.1.1. Overview
ADC adjustment is needed to find the optimum black level and
gain in Analog-to-Digital device and to compensate RGB
deviation.
4.1.2. Equipment & Condition
(1) Adjustment Remote control
(2) 801GF(802B, 802F, 802R) or MSPG925FA Pattern Generator
- Resolution :
480i, 720*480(MSPG-925FA -> Model: 209, Pattern: 65) 480i
1080p, 1920*1080(MSPG-925FA -> Model: 225, Pattern:
65) - 1080p
- Pattern : Horizontal 100 % Color Bar Pattern
- Pattern level: 0.7 ± 0.1 Vp-p
- Image
(3) Must use standard cable.
4.1.3. Adjust method
(1) ADC 480i, 1080p Comp1
1) Check connected condition of Component 1 cable to the
equipment.
2) Give a 480i, 1080p Mode, Horizontal 100% Color Bar
Pattern to Component 1.
(MSPG-925FA -> Model: 209, Pattern: 65) - 480i
(MSPG-925FA -> Model: 225, Pattern: 65) - 1080p
3) Change input mode as Component1 and picture mode
as “Standard”.
4) Press the “In-start” key on the Adjustment remote control
after at least 1 min of signal reception. Then, select 7.
External ADC -> 1. COMP 1080p on the menu. Press
“Enter” key. The adjustment will start automatically.
5) If ADC calibration is successful, “ADC RGB Success” is
displayed. If ADC calibration is failure, “ADC RGB Fail”
is displayed.
6) If ADC calibration is failure, after recheck ADC pattern or
condition retry calibration. Error message refer to 5).
(2) ADC 1920*1080 RGB
1) Check connected condition of Component & RGB cable
to the equipment
2) Give a 1920*1080 Mode, 100 % Horizontal Color Bar
Pattern to RGB port.
(MSPG-925 Series -> model: 225, pattern: 65 )
3) Change input mode as RGB and picture mode as “Standard”.
4) Press the In-start key on the ADJ remote control after at
least 1 min of signal reception. Then, select 7. External
ADC -> 1. COMP 1080p on the menu. Press enter key.
The adjustment will start automatically.
5) If ADC calibration is successful, “ADC RGB Success” is
displayed. If ADC calibration is failure, “ADC RGB Fail”
is displayed.
6) If ADC calibration is failure, after recheck ADC pattern or
condition retry calibration. Error message refer to 5).
H-freq(kHz) V-freq.(Hz)
Transmission [A][I][][Set ID][][20][Cr] [O][K][X] or [NG]
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4.2. EDID(The Extended Display Identification
Data)/DDC(Display Data Channel) download
(1) Overview
It is a VESA regulation. A PC or a MNT will display an
optimal resolution through information sharing without any
necessity of user input. It is a realization of “Plug and Play”.
(2) Equipment
- Adjustment remote control
- Since embedded EDID data is used, EDID download JIG,
HDMI cable and D-sub cable are not need.
(3)Download method
1) Press “ADJ” key on the Adjustment remote control then
select “10.EDID D/L”, By pressing “Enter” key, enter
EDID D/L menu.
2) Select “Start” key by pressing “Enter” key, HDMI1/
HDMI2/ HDMI3/ HDMI4/ RGB are Writing and display
OK or NG.
(4) EDID DATA
A RGB
A HDMI(FHD 3D, HDMI 1.4a, 3D)
* Physical Add & Checksum(HDMI1/2/3/4)
4.3. White Balance Adjustment
4.3.1. Overview
A W/B adj. Objective & How-it-works
(1) Objective: To reduce each Panel’s W/B deviation
(2) How-it-works : When R/G/B gain in the OSD is at 192, it
means the panel is at its Full Dynamic Range. In order to
prevent saturation of Full Dynamic range and data, one of
R/G/B is fixed at 192, and the other two is lowered to find
the desired value.
(3) Adjustment condition : normal temperature
1) Surrounding Temperature : 25 ºC ± 5 ºC
2) Warm-up time: About 5 Min
3) Surrounding Humidity : 20 % ~ 80 %
4.3.2. Equipment
1) Color Analyzer: CA-210 (LED Module : CH 14)
2) Adjustment Computer(During auto adj., RS-232C protocol is
needed)
3) Adjustment Remote control
4) Video Signal Generator MSPG-925F 720p/216-Gray
(Model: 217, Pattern: 78)
-> Only when internal pattern is not available
A Color Analyzer Matrix should be calibrated using CS-1000.
4.3.3. Equipment connection MAP
4.3.4. Adj. Command (Protocol)
<Command Format>
- LEN: Number of Data Byte to be sent
- CMD: Command
- VAL: FOS Data value
- CS: Checksum of sent data
- A: Acknowledge
Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX]
D-sub to D-sub DVI-D to HDMI or HDMI to HDMI
For HDMI EDID For Analog EDID
0123456789ABCDEF
0 00FFFFFFFFFFFF001E6D01 00 010101 01
10 01 15 01 03 80 10 09 78 0A EE 91 A3 54 4C 99 26
20 0F 50 54 A1 08 00 71 40 81 C0 81 00 81 80 95 00
30 90 40 A9 C0 B3 00 02 3A 80 18 71 38 2D 40 58 2C
40 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30
50 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 39
60 3F 1F 52 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 7F
80 02 03 37 F1 4E 10 1F 84 13 05 14 03 02 12 20 21
90 22 15 01 26 15 07 50 09 57 07 78 03 0C 00 XX XX
A0 B8 2D 20 C0 0E 01 40 0A 3C 08 10 18 10 98 10 58
B0 10 38 10 E3 05 03 01 01 1D 80 18 71 1C 16 20 58
C0 2C 25 00 A0 5A 00 00 00 9E 01 1D 00 80 51 D0 1A
D0 20 6E 88 55 00 A0 5A 00 00 00 1A 02 3A 80 18 71
E0 38 2D 40 58 2C 45 00 A0 5A 00 00 00 1E 00 00 00
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 XX
0123456789ABCDEF
0 00FFFFFFFFFFFF001E6D01 00 010101 01
10 01 15 01 03 68 10 09 78 0A EE 91 A3 54 4C 99 26
20 0F 50 54 A1 08 00 71 40 81 C0 81 00 81 80 95 00
30 90 40 A9 C0 B3 00 02 3A 80 18 71 38 2D 40 58 2C
40 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30
50 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 3A
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 00 98
INPUT 9Eh/9Fh(Physical Add) FFh(Checksum)
HDMI 1 10 00 CB
HDMI 2 20 00 BB
HDMI 3 30 00 AB
HDMI 4 40 00 9B
Color Analyzer
Comp uter
Pattern Generator
RS- 232C
RS-232C
RS-232C
Probe
Signal Source
* If TV internal pattern is used, not needed
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LGE Internal Use Only Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
A RS-232C Command used during auto-adjustment.
Ex) wb 00 00 -> Begin white balance auto-adj.
wb 00 10 -> Gain adj.
ja 00 ff -> Adj. data
jb 00 c0
...
...
wb 00 1f -> Gain adj. completed
*(wb 00 20(Start), wb 00 2f(end)) -> Off-set adj.
wb 00 ff -> End white balance auto-adj.
A Adj. Map
4.3.5. Adj. method
(1) Auto adj. method
1) Set TV in adj. mode using POWER ON key.
2) Zero calibrate probe then place it on the center of the
Display.
3) Connect Cable (RS-232C)
4) Select mode in adj. Program and begin adjustment.
5) When adj. is complete (OK Sign), check adj. status pre
mode. (Warm, Medium, Cool)
6) Remove probe and RS-232C cable to complete adj.
A W/B Adj. must begin as start command “wb 00 00” , and
finish as end command “wb 00 ff”, and Adj. offset if need.
(2) Manual adj. method
1) Set TV in Adj. mode using POWER ON.
2) Zero Calibrate the probe of Color Analyzer, then place it
on the center of LCD module within 10 cm of the surface.
3) Press ADJ key -> EZ adjust using adj. R/C -> 7. WhiteBalance then press the cursor to the right (key
G).
(When Key(G ) is pressed 216 Gray internal pattern will
be displayed)
4) One of R Gain / G Gain / B Gain should be fixed at 192,
and the rest will be lowered to meet the desired value.
5) Adj. is performed in COOL, MEDIUM, WARM 3 modes
of color temperature.
A If internal pattern is not available, use RF input. In EZ
Adj. menu 7.White Balance, you can select one of 2
Test-pattern: ON, OFF. Default is inner(ON). By selecting
OFF, you can adjust using RF signal in 216 Gray pattern.
A Adj. condition and cautionary items
1) Lighting condition in surrounding area
Surrounding lighting should be lower 10 lux. Try to
isolate adj. area into dark surrounding.
2) Probe location
: Color Analyzer(CA-210) probe should be within 10 cm
and perpendicular of the module surface (80º ~ 100º)
3) Aging time
- After Aging Start, Keep the Power ON status during
5 Minutes.
- In case of LCD, Back-light on should be checked
using no signal or Full-white pattern.
4.3.6. Reference (White Balance Adj. coordinate and
color temperature)
A Luminance : 204 Gray
A Standard color coordinate and temperature using CS-1000
(over 26 inch)
A
Standard color coordinate and temperature using CA-210(CH 9)
ITEM Command Data Range(Hex.) Default
Cmd 1 Cmd 2 Min Max (Decimal)
Cool R-Gain j g 00 C0
G-Gain j h 00 C0
B-Gain j i 00 C0
R-Cut
G-Cut
B-Cut
Medium R-Gain j a 00 C0
G-Gain j b 00 C0
B-Gain j c 00 C0
R-Cut
G-Cut
B-Cut
Warm R-Gain j d 00 C0
G-Gain j e 00 C0
B-Gain j f 00 C0
R-Cut
G-Cut
RS-232C COMMAND
Explanation
[CMD ID DATA]
wb 00 00 Begin White Balance adj.
wb 00 10 Gain adj.(internal white pattern)
wb 00 1f Gain adj. completed
wb 00 20 Offset adj.(internal white pattern)
wb 00 2f Offset adj. completed
wb 00 ff End White Balance adj.(Internal pattern disappears)
Mode Color Coordination Temp ∆UV
xy
COOL 0.269 ± 0.002 0.273 ± 0.002 13000 K 0.0000
MEDIUM 0.285 ± 0.002 0.293 ± 0.002 9300 K 0.0000
WARM 0.313 ± 0.002 0.329 ± 0.002 6500 K 0.0000
Mode Color Coordination Temp ∆UV
xy
COOL 0.269 0.273 13000 K 0.0000
MEDIUM 0.285 0.293 9300 K 0.0000
WARM 0.313 0.329 6500 K 0.0000
- 13 -
LGE Internal Use Only Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
4.3.7. ALELF & EDGE LED White balance table
- ALELF&EDGE LED module change color coordinate
because of aging time.
- Apply under the color coordinate table, for compensated
aging time.
- ALEF - LGD Only
4.4. Wireless function check
Step 1) Connect set and Dongle of Wireless to Cable of HDMI
& TTA 20Pin.
Step 2) At OSD of SET, check the message like Fig 3.
Step 3) Detach Cable of Wireless Dongle.
4.5. EYE-Q function check
Step 1) Turn on TV.
Step 2) Press EYE key of Adjustment remote control.
Step 3) Cover the Eye Q II sensor on the front of the using
your hand and wait for 6 seconds.
Step 4) Confirm that R/G/B value is lower than 10 of the “Raw
Data (Sensor data, Back light)”. If after 6 seconds,
R/G/B value is not lower than 10, replace Eye Q II
sensor.
Step 5) Remove your hand from the Eye Q II sensor and wait
for 6 seconds.
Step 6) Confirm that “ok” pop up. If change is not seen,
replace Eye Q II sensor.
4.6. Local Dimming Function Check
Step 1) Turn on TV.
Step 2) At the Local Dimming mode, module Edge Backlight
moving right to left Back light of IOP module moving.
Step 3) Confirm the Local Dimming mode.
Step 4) Press “exit” key.
4.7. Magic Motion Remote control test
- Equipment : RF Remote control for test, IR-KEY-Code
Remote control for test
- You must confirm the battery power of RF-Remote control
before test(recommend that change the battery per every lot)
- Sequence (test)
1) if you select the ‘start(Mute)’ key on the Adjustment
remote control, you can pairing with the TV SET.
2) You can check the cursor on the TV Screen, when select
the ‘OK’ key on the Adjustment remote control.
3) You must remove the pairing with the TV Set by select
‘OK’ key + ‘Mute’ key on the Adjustment remote control
for 5 seconds.
Aging Time Cool Medium Warm
GP3 (Min.) X Y X Y X Y
269 273 285 293 313 329
1 0-2 285 297 301 317 321 340
2 3-5 284 296 300 316 320 339
3 6-9 283 294 299 314 319 337
4 10-19 282 292 298 312 318 335
5 20-35 279 287 295 307 315 330
6 36-49 275 281 291 301 311 324
7 50-79 273 278 289 298 309 322
8 80-149 271 275 287 295 307 318
9 Over 150 269 273 286 293 305 316
Fig.1
Fig.3 Connect the Dongle
Fig.2
Connect
Local Dimming Demo (Edge LED Model)
Local Dimming Demo (IOP & ALEF Model)
- 14 -
LGE Internal Use Only Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
4.8. 3D function test
(Pattern Generator MSHG-600, MSPG-6100[Support HDMI1.4])
* HDMI mode NO. 872 , pattern No.83
1) Please input 3D test pattern like below (HDMI mode No.
872 , pattern No.83)
2) When 3D OSD appear automatically , then select OK key.
3) Don’t wear a 3D Glasses, Check the picture like below .
4.8.1. IR emitter inspection
1) Start 3D pattern inspection.
2) If IR emitter signal is correctly received to IR receiver, the
lamp of IR tester turn on.
4.9. Option selection per country
(1) Overview
- Option selection is only done for models in NON-AU/-ID/SG/-MY/-VN/-IL/-ZA/-IR
- Applied model: LB12C/D/E Chassis applied Asia/MEA
model.
(2) Method
1) Press ADJ key on the Adjustment remote control, then
select Country Group Menu.
2) Depending on destination, select Country Group Code
12 or Country Group A-ASIA.
3) Press ADJ key on the Adjustment remote control, then
select Area Option.
4) Depending on Area code number, select Default Lang.,
Wi-Fi Frequency, Lang Gr., Teletext Lang Gr., I II Save,
HDEV, MONO, Location.
4.10. Tool Option selection
- Method : Press Adj. key on the Adj. Remote Control, then
select Tool option.
4.11. Ship-out mode check(In-stop)
After final inspection, press IN-STOP key of the Adjustment
remote control and check that the unit goes to Stand-by
mode.
4.12. GND and Internal Pressure check
(1) Method
1) GND & Internal Pressure auto-check preparation
- Check that Power Cord is fully inserted to the SET.
(If loose, re-insert)
2) Perform GND & Internal Pressure auto-check
- Unit fully inserted Power cord, Antenna cable and A/V
arrive to the auto-check process.
- Connect D-terminal to AV JACK TESTER
- Auto CONTROLLER(GWS103-4) ON
- Perform GND TEST
- If NG, Buzzer will sound to inform the operator.
- If OK, changeover to I/P check automatically.
(Remove CORD, A/V form AV JACK BOX.)
- Perform I/P test
- If NG, Buzzer will sound to inform the operator.
- If OK, Good lamp will lit up and the stopper will allow
the pallet to move on to next process.
(2) Checkpoint
• TEST voltage
- GND: 1.5 KV / min at 100 mA
- SIGNAL: 3 KV / min at 100 mA
• TEST time: 1 second
• TEST POINT
- GND TEST = POWER CORD GND & SIGNAL CABLE
METAL GND
- Internal Pressure TEST = POWER CORD GND & LIVE
& NEUTRAL
• LEAKAGE CURRENT: At 0.5 mArms
<IR Tester Lamp turned off(NG)>
<IR Emitter inspection>
<IR Tester Lamp turned on(OK)>
- 15 -
LGE Internal Use Only Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
5. Audio
Measurement condition:
1. RF input: Mono, 1 KHz sine wave signal, 100 % Modulation
2. CVBS, Component: 1 KHz sine wave signal 0.5 Vrms
3. RGB PC: 1 KHz sine wave signal 0.7 Vrms
6. USB S/W download(Service only)
1) Put the USB Stick to the USB socket.
2) Automatically detecting update file in USB Stick.
- If your downloaded program version in USB Stick is Low,
it didn’t work. But your downloaded version is High, USB
data is automatically detecting.
3) Show the message “Copying files from memory”.
4) Updating is starting.
5) Updating Completed, The TV will restart automatically.
6) If your TV is turned on, check your updated version and
Tool option. (explain the Tool option, next stage)
* If downloading version is more high than your TV have, TV
can lost all channel data. In this case, you have to channel
recover. if all channel data is cleared, you didn’t have a
DTV/ATV test on production line.
* After downloading, have to adjust TOOL OPTION again.
1) Push “IN-START” key in service remote control.
2) Select “Tool Option 1” and push “OK” key.
3) Punch in the number. (Each model has their number.)
No. Item Min. Typ. Max. Unit
1. Audio practical max 9.0 10.0 12.0 W EQ Off
Output, L/R AVL Off
(Distortion=10 % 8.5 8.9 9.8 Vrms Clear Voice Off
max Output)
2. Speaker (8 Ω 10.0 15.0 W EQ On
Impedance) AVL On
Clear Voice On
- 16 -
LGE Internal Use Only Copyright LG Electronics. Inc. All rights reserved.
Only for training and service purposes
300
200
121
LV1
521
530
540
400
900
910
920
810
710
220
230
231
221
210
700
120
560
511
570
510
A10
A5
A2
AG1
A23
A22
EXPLODED VIEW
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
IMPORTANT SAFETY NOTICE
NAND FLASH MEMORY 8Gbit
Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
+3.3V_Normal
NC_1
1
NC_2
2
NC_3
3
NC_4
4
NC_5
5
NC_6
6
RY/BY
7
RE
8
CE
9
NC_7
0
LGE35230(BCM35230KFSBG)
B5
C5
A4
B4
A3
B3
A2
B2
W2
V4
W4
V3
V2
D13
E6
R106
3K
10
NC_8
11
VCC_1
12
VSS_1
13
NC_9
14
NC_10
15
CLE
16
ALE
17
WE
18
WP
19
NC_11
20
NC_12
21
NC_13
22
NC_14
23
NC_15
24
IC101
NON_BCM_CAP
HDMI0_CLKN
HDMI0_CLKP
HDMI0_D0N
HDMI0_D0P
HDMI0_D1N
HDMI0_D1P
HDMI0_D2N
HDMI0_D2P
CEC
DDC0_SCL
DDC0_SDA
HDMI0_HTPLG_IN
HDMI0_HTPLG_OUT
HDMI0_ARC
HDMI0_RESREF
LT0VCAL_MONITOR
NAND_RBb
NAND_REb
NAND_CEb
NAND_CEb2
NAND_CLE
NAND_ALE
R101
4.7K
FLASH_WP
R105
4.7K
NAND_WEb
R104
4.7K
R195
4.7K
Write Protection
- High : Normal Operation
- Low : Write Protection
+3.3V_Normal
R107 2.7K
R148
+3.3V_Normal
R103
4.7K
HDMI_CLKHDMI_CLK+
HDMI_RX0HDMI_RX0+
HDMI_RX1HDMI_RX1+
HDMI_RX2HDMI_RX2+
HDMI_ARC
16Gbit
R149 0
16Gbit
C102
4700pF
C101
0.1uF
OPT
IC102
TC58DVG3S0ETA00
NAND_8Gbit
TXOUT0_L0N
TXOUT0_L0P
TXOUT0_L1N
TXOUT0_L1P
TXOUT0_L2N
TXOUT0_L2P
TXCLK_LN
TXCLK_LP
TXOUT0_L3N
TXOUT0_L3P
TXOUT0_L4N
TXOUT0_L4P
TXOUT0_U0N
TXOUT0_U0P
TXOUT0_U1N
TXOUT0_U1P
TXOUT0_U2N
TXOUT0_U2P
TXCLK_UN
TXCLK_UP
TXOUT0_U3N
TXOUT0_U3P
TXOUT0_U4N
TXOUT0_U4P
TXOUT1_L0N
TXOUT1_L0P
TXOUT1_L1N
TXOUT1_L1P
TXOUT1_L2N
TXOUT1_L2P
TXCLK1_LN
TXCLK1_LP
TXOUT1_L3N
TXOUT1_L3P
TXOUT1_L4N
TXOUT1_L4P
TXOUT1_U0N
TXOUT1_U0P
TXOUT1_U1N
TXOUT1_U1P
TXOUT1_U2N
TXOUT1_U2P
TXCLK1_UN
TXCLK1_UP
TXOUT1_U3N
TXOUT1_U3P
TXOUT1_U4N
TXOUT1_U4P
GPIO_BL_ON
BL_PWM/GPIO
AE27
AE28
AF27
AF28
AG27
AG28
AE26
AF26
AH27
AG26
AF25
AE25
AH26
AG25
AE24
AD24
AH25
AF24
AE23
AD23
AG24
AF23
AC22
AD22
AG23
AH23
AE22
AE21
AF22
AH22
AG22
AF21
AG21
AF20
AD21
AC21
AG20
AH20
AD19
AE19
AF19
AH19
AE18
AD18
AG19
AF18
AG18
AF17
AC18
AH16
AG16
16Gbit
IC102-*1
TH58DVG4S0ETA20
SDA0_3.3V
SCL0_3.3V
SCL2_3.3V
SDA2_3.3V
R199 22
R197 22
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC_26
NC_25
NC_24
NC_23
I/O8
I/O7
I/O6
I/O5
NC_22
PSL
NC_21
VCC_2
VSS_2
NC_20
NC_19
NC_18
I/O4
I/O3
I/O2
I/O1
NC_17
NC_16
NC_15
NC_14
+3.3V_Normal
NC_1
1
NC_28
48
NC_27
47
NC_26
46
NC_25
45
I/O8
NAND_DATA[7]
44
I/O7
NAND_DATA[6]
43
I/O6
42
NAND_DATA[5]
I/O5
41
NAND_DATA[4]
NC_24
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
PSL
NC_23
VCC_2
VSS_2
NC_22
NC_21
NC_20
I/O4
I/O3
I/O2
I/O1
NC_19
NC_18
NC_17
NC_16
16Gbit
R151
+3.3V_Normal
C104 10uF
NAND_DATA[3]
NAND_DATA[2]
NAND_DATA[1]
NAND_DATA[0]
TXB4P
TXB4N
TXB3P
TXB3N
TXBCLKP
TXBCLKN
TXB2P
TXB2N
TXB1P
TXB1N
TXB0P
TXB0N
TXA4P
TXA4N
TXA3P
TXA3N
TXACLKP
TXACLKN
TXA2P
TXA2N
TXA1P
TXA1N
TXA0P
TXA0N
TXD4P
TXD4N
TXD3P
TXD3N
TXDCLKP
TXDCLKN
TXD2P
TXD2N
TXD1P
TXD1N
TXD0P
TXD0N
TXC4P
TXC4N
TXC3P
TXC3N
TXCCLKP
TXCCLKN
TXC2P
TXC2N
TXC1P
TXC1N
TXC0P
TXC0N
+3.3V_Normal
0
C103
0.1uF
10V
R194
2.7K
R108 10K
NAND_DATA[0-7]
RGB_DDC_SDA
RGB_DDC_SCL
BBS CONNECT
P101
TJC2508-4A
VCC
1
SCL
2
SDA
3
GND
4
C105
2.2uF
10V
Q101
BSS83
Q102
BSS83
+3.3V_Normal
A_DIM
RY/BY2
RY/BY1
VCC_1
VSS_1
NC_10
NC_11
NC_12
NC_13
SBD
G
SBD
G
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
CE1
CE2
CLE
ALE
RE
WE
WP
C106
4.7uF
DEV_NAND_16Gbit
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
+3.3V_Normal
R196
10K
C118
0.1uF
16V
+3.3V_Normal
R198
10K
C119
0.1uF
16V
R110
R109
1.5K
1.5K
DVB_S Option: apply EU Satellite model
FOR HDMI STANDARD
APPLY ONLY WHEN CONNECT TO PULL-UP GPIO
Boot ROM Device Select - (FA4,FAD7,FAD2,FAD1)
+3.3V_Normal
R113
10K
R114
10K
OPT
R117
10K
OPT
R118
10K
R122
10K
R123
10K
OPT
R127
10K
OPT
R128
10K
CI_ADDR[4]
NAND_DATA[7]
NAND_DATA[2]
NAND_DATA[1]
NAND ECC (FA3, FA2, FALE)
+3.3V_Normal
R119
R115
R111
10K
OPT
R112
10K
10K
R116
10K
OPT
10K
OPT
R120
10K
CI_ADDR[3]
CI_ADDR[2]
NAND_ALE
DUAL COMPONENT
IC102 1ST : EAN61000101 2ND : T-TH58DVG4S0ETA20
IC102-*1
LGE35230(BCM35230KFSBG)
AG6
AF6
V5
AB4
Y4
AA4
Y5
AB2
AB5
U3
U2
Y2
Y1
33
AA3
AA2
H3
H2
H4
H5
F25
W5
OPT
U5
U4
OPT
OPT
W3
W1
OPT
AB6
R139 0
Y6
Y3
G24
J6
W6
F7
E7
R140
560
1%
BCM REFRENCE is 562ohm
R121
1.2K
C107
33pF
50V
DVB_S
+3.3V_Normal
+3.3V_Normal
R124
1K
OPT
R125
1K
R126
1.2K
C108
33pF
50V
DVB_S
R129
1.2K
C109
33pF
50V
5V_HDMI_3
R130
OPT
2K
R132 4.7K
+3.3V_Normal
C111 0.01uF
C112 0.1uF
54MHz_XTAL_P
54MHz_XTAL_N
R131
1.2K
C110
33pF
50V
PCM_5V_CTL
5V_HDMI_1
5V_HDMI_2
5V_HDMI_4
SOC_RESET
LNB_INT
SC_ID
BCM_RX
BCM_TX
R135
R136 33
+3.3V_Normal
R141 4.7K
R142 22
R143 22
R144 22
R145 22
SRST
0000: ST Micro M25P or compatible Serial Flash
0010: 8-bit 512Mbit 512B page SLC NAND Flash devices
0100: 8-bit 128, 256Mbit 512B page SLC NAND Flash devices
0110: 8-bit 1Gbit 2KB page SLC NAND Flash devices
1000: 8-bit 2Gbit, 4Gbit, 8Gbit 2KB page SLC NAND Flash devices
1010: 8-bit 16Gbit, 32Gbit 4KB page SLC NAND Flash devices (O)
0001: 8-bit 8/16/32Gbit 2KB page MLC NAND Flash devices
0011: 8-bit 16/32Gbit 4KB page MLC NAND Flash devices
0101: 8-bit 32Gbit 8KB page MLC NAND Flash devices
0111: 3B dual IO Serial Flash
1001: BB dual IO Serial Flash
1011: fast Serail Flash > 50Mhz
1100: OneNAND Flash (always 16-bit)
1110: Reserved
1101, 1111: Reserved
000 = ECC disabled
001 = ECC 1-bit repair
010 = ECC 4-bit BCH (O)
011 = ECC 8-bit BCH, 27 byte spare
100 = ECC 12-bit BCH, 27 byte spare
101 = ECC 8-bit BCH, 16 byte spare
110, 111 = Reservedd
IC101
NON_BCM_CAP
TVM_XTALIN
TVM_XTALOUT
IRRXDA
FP_IN0
FP_IN1
SPARE_ADC1
SPARE_ADC2
FS_IN1
FS_IN2
VGA_SDA
VGA_SCL
RDA
TDA
BSCDATAA
BSCCLKA
RDB/GPIO
TDB/GPIO
BSC_S_SCL
BSC_S_SDA
NMIB
POWER_CTRL
AON_HSYNC
AON_VSYNC
AON_GPIO_36
AON_GPIO_37
AON_RESETOUTB
TVM_BYPASS
RESETB
RESETOUTB
TMODE
TESTEN
VDAC_VREG
VDAC_RBIAS
AVS_NDRIVE_1
AVS_PDRIVE_1
FAD_7
FAD_6
FAD_5
FAD_4
FAD_3
FAD_2
FAD_1
FAD_0
FALE
FCEB_0
FCEB_1
FCEB_2
FCEB_3
NFWPB
FRDYB
FA_0
FA_1
FA_2
FA_3
FA_4
FA_5
FA_6
FA_7
FA_8
FA_9
FA_10
FA_11
FA_12
FA_13
FA_14
FA_15
TRSTB
TDI/GPIO
TMS/GPIO
TCK/GPIO
DINT/GPIO
AVS_VFB
AVS_VSENSE
AVS_RESETB
VDAC_1
VDAC_2
AB1
NAND_DATA[7]
AB3
NAND_DATA[6]
AC1
NAND_DATA[5]
AC2
NAND_DATA[4]
AC3
NAND_DATA[3]
AD2
NAND_DATA[2]
AD3
NAND_DATA[1]
AE2
NAND_DATA[0]
AG1
AF1
AC5
AE6
AG5
AF3
AG2
FWE
AE3
FRD
AA5
AF2
AE1
AC4
AD5
AD4
AE4
AE5
AD6
AH3
AF4
AH4
AG4
AF5
AG3
AH2
AH5
AD15
AF14
AH14
TDO
AD14
AG14
AC16
AH7
AG7
AD7
AF7
AH8
C6
D7
NAND_ALE
NAND_CEb
NAND_CEb2
/CI_CE1
/CI_CE2
FLASH_WP
NAND_WEb
NAND_REb
/PCM_WAIT
NAND_CLE
NAND_RBb
CI_ADDR[2]
CI_ADDR[3]
CI_ADDR[4]
CI_ADDR[5]
CI_ADDR[6]
CI_ADDR[7]
CI_ADDR[8]
CI_ADDR[9]
CI_ADDR[10]
CI_ADDR[11]
CI_ADDR[12]
CI_ADDR[13]
CI_ADDR[14]
R146 10K
NAND_DATA[0-7]
R147
1K
DTV/MNT_V_OUT
Strap Setting
CI_ADDR[2-14]
+3.3V_Normal
R150
R153
1K
R156
1K
1K
For L/R sync GPIO
SRST
+3.3V_Normal
R157
R160
R154
10K
10K
OPT
OPT
R158
R155
10K
10K
NAND_DATA[0]:
0: System is LITTLE endian (O)
1: System is BIG endian
CI_ADDR[7]:
0: Disable EDID automatic Downloading from Flash (O)
1: Enable EDID automatic Downloading from Flash
NAND_DATA[6] :
0: Disable OSC clock output on chip Pin (O)
1: Enable OSC clock output on chip pin.
CI_ADDR[6]:
0: Host MIPS run at 500 MHz (O)
1: Host MIPS run at 250 MHz
NAND_CLE:
0: Differential Oscillators TVM not bypassed (O)
1: Differential Oscillators TVM bypassed
NAND_DATA[4]:
0: 27MHz TVM Crystal Frequency
1: 54MHz TVM Crystal Frequency (O)
R162
R159
1K
L/R_SYNC_DINT
L/R_SYNC_DINT
R166
1K
1K
R163
1K
10K
OPT
R161
10K
R164
10K
OPT
R165
10K
R167
10K
OPT
R168
10K
R175
10K
OPT
R176
10K
R177
10K
R178
10K
OPT
R170
10K
R171
10K
OPT
CI_ADDR[9],CI_ADDR[11],CI_ADDR[12],CI_ADDR[13]
TVM Crystal oscillator bias/gain control
0000: 210uA
0001: 390uA
0010: 570uA
0011: 730uA
0100: 890uA (O)
0111: 1290uA
1000: 1416uA
1111: 2196uA
0101, 0110, 1001, 1010, 1011, 1100, 1101, 1110: Reserved
CI_ADDR[8]:
0: RESETOUTb (in On/Off only) stay asserted until software releases them.
1: Fix amount of delay for de-assertion on RESETOUTb (in On/IOff only)
at end of RESETb pulse (O)
NAND_DATA[3]:
0: MIPS will boot from external flash (O)
1: MIPS will boot from ROM
NAND_DATA[5]:
0: FLASH MODE (O)
1: BSC_SLAVE(BBS) MODE
R179
10K
OPT
R180
10K
R181
10K
OPT
R182
10K
R183
10K
R184
10K
OPT
R187
10K
OPT
R188
10K
NVRAM
+3.3V_Normal
R169
0
R173
R172
4.7K
4.7K
OPT
R174
4.7K
BCM_NVM_1M
IC103
M24M01-HRMN6TP
OPT
NC
1
E1
2
A8’h
E2
3
VSS
4
+3.3V_Normal
VCC
8
WP
7
SCL
6
SDA
5
R190 33
R191 33
54MHz X-TAL
C113
12pF
50V
3
X-TAL_2
4
GND_2
54MHz
X101
CRYSTAL_BCM_Sunny
C114
12pF
EAW58812611
50V
SUNNY ELECTRONICS CORPORATION
2
1
GND_1
X-TAL_1
R185 0
R186 0
R189
1M
OPT
54MHz_XTAL_N
54MHz_XTAL_P
R192
10K
OPT
NAND_DATA[0]
CI_ADDR[7]
NAND_DATA[6]
CI_ADDR[6]
NAND_CLE
NAND_DATA[4]
CI_ADDR[9]
CI_ADDR[11]
CI_ADDR[12]
CI_ADDR[13]
CI_ADDR[8]
NAND_DATA[3]
NAND_DATA[5]
R193
10K
BCM_NVM_256K
IC103-*1
AT24C256C-SSHL-T
A0
1
A1
2
A2
3
GND
4
Write Protection
- Low : Normal Operation
- High : Write Protection
X101-*2
54MHz
X-TAL_1
1
GND_1
2
CRYSTAL_BCM_KDS
EAW58239604
DAISHINKU CORPORATION.
X101-*1
54MHz
X-TAL_1
1
GND_1
2
CRYSTAL_BCM_Lihom
EAW60763703
LIHOM CO., LTD.
VCC
8
WP
7
SCL
6
SDA
5
SCL3_3.3V
SDA3_3.3V
GND_2
4
X-TAL_2
3
GND_2
4
X-TAL_2
3
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
BCM35230
MAIN & NAND FLASH
2010.09.18
1
+3.3V_Normal
Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
FHD
R252
1K
HD
R262
1K
PHM
OLED
LCD
BCM
internal
FRC
0 0 1 1
1 1 0 0
HIGH
Support
FE_TS_DATA[0-7]
CHBO_TS_CLK
CHBO_TS_SERIAL
CHBO_TS_SYNC
CHBO_TS_VAL_ERR
R251
1K
1K
1K
BCM_FRC/URSA5
R261
1K
NO_FRC/FRC2
R250
FRC2/URSA5
R260
NO_FRC/BCM_FRC
MODEL OPTION
MODEL_OPT_0
MODEL_OPT_1
MODEL_OPT_2
MODEL_OPT_3
MODEL_OPT_4
MODEL_OPT_5
MODEL_OPT_6
MODEL_OPT_7 Enable Disable
NO_FRC
DDR speed
T2 Tuner
S Tuner
R253
R263
1K
1K
R254
1K
OPT
R264
1K
LG FRC2
LOW
HD FHD
LCD OLED
1600 1333
Not Support
Not Support Support
R255
1K
T2_TUNER
R265
1K
NO_T2_TUNER
external
URSA5
SIDE_USB_OCD1
SIDE_USB_OCD2
PCM_TS_DATA[0-7]
R201 0
F/NIM_EU_CN
PCM_MDI[0-7]
OPT
R202
0
R256
1K
S_TUNER
R266
1K
NO_S_TUNNER
+3.3V_Normal
R286
10K
WIFI
TU_TS_CLK
FE_TS_DATA[0]
FE_TS_DATA[1]
FE_TS_DATA[2]
FE_TS_DATA[3]
FE_TS_DATA[4]
FE_TS_DATA[5]
FE_TS_DATA[6]
FE_TS_DATA[7]
PHM
NO_PHM
R287
10K
WIFI
R257
1K
R267
1K
R203 0
R204 0
R205 0
R206 0
R207 0
R208 0
R209 0
C201
100pF
OPT
F/NIM_EU_CN
F/NIM_EU_CN
F/NIM_EU_CN
PCM_MDI[0]
PCM_MDI[1]
PCM_MDI[2]
PCM_MDI[3]
PCM_MDI[4]
PCM_MDI[5]
PCM_MDI[6]
PCM_MDI[7]
R211
6.04K
EPHY_TDP
EPHY_TDN
EPHY_RDP
EPHY_RDN
R210
4.87K
1%
SIDE_USB_DM
SIDE_USB_DP
SIDE_USB_CTL1
WIFI_DM
WIFI_DP
SIDE_USB_CTL2
PCM_TS_CLK
PCM_TS_DATA[0]
PCM_TS_DATA[1]
PCM_TS_DATA[2]
PCM_TS_DATA[3]
PCM_TS_DATA[4]
PCM_TS_DATA[5]
PCM_TS_DATA[6]
PCM_TS_DATA[7]
PCM_TS_SYNC
PCM_TS_VAL
F/NIM_EU_CN
F/NIM_EU_CN
F/NIM_EU_CN
F/NIM_EU_CN
TU_TS_SYNC
TS_VAL_ERR
PCM_MCLKI
PCM_MISTRT
PCM_MIVAL_ERR
/PCM_IRQA
MODEL_OPT_0
MODEL_OPT_1
MODEL_OPT_2
MODEL_OPT_3
MODEL_OPT_4
MODEL_OPT_5
MODEL_OPT_6
MODEL_OPT_7
LGE35230(BCM35230KFSBG)
F26
D26
F27
F28
E27
E26
F5
E5
C2
D1
E1
D2
B1
C1
C3
C4
M4
L5
M5
L6
N3
N1
N2
M3
M2
L4
N4
K6
J4
K5
J2
J3
K2
K1
K3
L1
L3
L2
P4
T2
R3
R2
P3
P2
P1
R6
N5
T4
P5
R4
U1
T3
T1
T5
IC101
NON_BCM_CAP
EPHY_VREF
EPHY_RDAC
EPHY_TDP
EPHY_TDN
EPHY_RDP
EPHY_RDN
USB_MONCDR
USB_RREF
USB_PORT1DN
USB_PORT1DP
USB_PWRFLT_1/GPIO
USB_PWRON_1/GPIO
USB_PORT2DN
USB_PORT2DP
USB_PWRFLT_2/GPIO
USB_PWRON_2/GPIO
TCLKA/GPIO
TDATA_0/GPIO
TDATA_1/GPIO
TDATA_2/GPIO
TDATA_3/GPIO
TDATA_4/GPIO
TDATA_5/GPIO
TDATA_6/GPIO
TDATA_7/GPIO
TSTRTA/GPIO
TVLDA/GPIO
TCLKD/GPIO
TDATD_0/GPIO
TDATD_1/GPIO
TDATD_2/GPIO
TDATD_3/GPIO
TDATD_4/GPIO
TDATD_5/GPIO
TDATD_6/GPIO
TDATD_7/GPIO
TSTRTD/GPIO
TVLDD/GPIO
MPEG_CLK/GPIO
MPEG_D_0/GPIO
MPEG_D_1/GPIO
MPEG_D_2/GPIO
MPEG_D_3/GPIO
MPEG_D_4/GPIO
MPEG_D_5/GPIO
MPEG_D_6/GPIO
MPEG_D_7/GPIO
MPEG_SYNC/GPIO
MPEG_DATA_EN/GPIO
MCIF_RESET/GPIO
MCIF_SCLK/GPIO
MCIF_SCTL/GPIO
MCIF_SDI/GPIO
MCIF_SDO/GPIO
PCI_DEVSELB/GPIO
PCI_FRAMEB/GPIO
C225
0.22uF
6.3V
VI_IFP0
VI_IFM0
VDDR_AGC
AGC_SDM_2
AGC_SDM_1
GPIO_0
GPIO_1
GPIO_2
GPIO_3
PCI_VIO_0
PCI_VIO_1
PCI_VIO_2
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_70
GPIO_71
GPIO_72
GPIO_73
GPIO_74
GPIO_75
GPIO_76
GPIO_77
GPIO_78
GPIO_79
PCI_AD05
PCI_AD06
PCI_AD07
PCI_AD08
PCI_AD09/GPIO
PCI_AD10/GPIO
PCI_AD11/GPIO
PCI_AD12/GPIO
PCI_AD13/GPIO
PCI_AD14/GPIO
PCI_AD15/GPIO
PCI_AD16/GPIO
PCI_AD17/GPIO
PCI_AD18/GPIO
PCI_AD19/GPIO
PCI_AD20/GPIO
PCI_AD21/GPIO
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_CBE00
PCI_CBE01/GPIO
PCI_CBE02/GPIO
PCI_CBE03
PCI_IRDYB/GPIO
PCI_PAR/GPIO
PCI_PERRB/GPIO
PCI_REQ1B
PCI_SERRB/GPIO
PCI_STOPB/GPIO
PCI_TRDYB/GPIO
+0.9V_CORE
C221
0.1uF
C17
B17
D15
B16
A16
A15
C16
G28
G26
+3.3V_Normal
W14
W15
W13
J5
R5
V6
H6
AE15
AF15
AG15
AF16
AD16
AE16
AG17
AH17
AE17
AD17
AB13
AC15
AB12
AB11
AE14
AG13
AH13
AF13
AE13
AD12
AF12
AG10
AF10
AE10
AD10
AE9
AE8
AC10
AC11
AC8
AB8
AC14
AG12
AH10
AB7
AG11
AD11
AE11
AD13
AE12
AC12
AC13
AH11
AF11
C223
0.01uF
C203
10uF
10V
close to soc
Non_CHB
R212
1K
closed to soc
R213 2K
C216 0.01uF
R280
22
R214 22
R215 22
R281 22
R282 22
R216 22
R218 22
R220 22
R221 22
R222 22
R283
22
R223 22
R284 22
R224 22
R235
R225 0
R226 22
R285 22
R227 22
C205
C207
10uF
4.7uF
10V
10V
C217
16V
100
0.1uF
R241
C218
100
0.1uF
R242
16V
M_REMOTE_RX
CI_DET
M_RFModule_RESET
EPHY_ACTIVITY
EPHY_LINK
DTV_ATV_SELECT
RF_SWITCH_CTL_2
INSTANT_MODE
BCM_L/DIM
BCM_L/DIM
100
OPT
NFM18PS105R0J
C233
6.3V
GND
C232
4.7uF
10V
C209
4.7uF
10V
IF_P
IF_N
IF_AGC
3D_SYNC
MODEL_OPT_0
MODEL_OPT_1
MODEL_OPT_2
MODEL_OPT_3
SC_DET/COMP2_DET
CHB_RESET
TW9910_RESET
AV2_CVBS_DET
RF_BOOSTER_CTL
DSUB_DET
PCM_RST
MODEL_OPT_4
DC_MREMOTE
DD_MREMOTE
COMP1_DET
MODEL_OPT_5
3D_GPIO_0
MODEL_OPT_6
MODEL_OPT_7
ERROR_OUT
RF_SWITCH_CTL
3D_GPIO_1
3D_GPIO_2
OUT IN
C234
0.1uF
C211
0.1uF
+3.3V_Normal
+3.3V_Normal
R228 22
R230 22
BCM_L/DIM
R231 100
L/DIM0_MOSI
L/DIM0_SCLK
NFM18PS105R0J
C204
6.3V
OUT IN
GND
C236
0.1uF
C213
0.1uF
BLM18PG121SN1D
C229
0.1uF
R240
2.7K
+3.3V_Normal
R231-*1 0
FRC2_RESET
URSA_RESET
NFM18PS105R0J
C238
4.7uF
10V
C215
0.01uF
L201
NON_NTP
PWM_DIM
L/DIM0_VS
4.7K
C244
6.3V
GND
C220
0.1uF
+3.3V_Normal
4.7K
R232
URSA_RESET
+0.9V_CORE
+3.3V_Normal
OUT IN
+1.5V_DDR
C222
0.01uF
R233
1.2K
C227
33pF
50V
R232-*1
FRC2_RESET
R234
1.2K
C231
33pF
50V
C247
22uF
C248
10uF
10V
NON_NTP
FRC_RESET
SDA1_3.3V
SCL1_3.3V
POWER 2.5V
+2.5V_BCM35230
+2.5V_BCM35230
Place Cap
Very close to R22 Ball
L202
BLM18PG121SN1D
C249
10uF
10V
L203
BLM18PG121SN1D
C251
0.1uF
16V
+2.5V_BCM35230
BLM18PG121SN1D
C250
4.7uF
10V
+1.5V_DDR
Place Cap
Very close to R22 Ball
C242
0.1uF
+3.3V_Normal
C253
10uF
10V
EPHY_VDD25
C252
4.7uF
10V
L204
C254
4.7uF
MLG1005S22NJT
C224
L220
1uF
25V
OPT
+0.9V_CORE
AADC_AVDD25
C256
0.1uF
C255
0.1uF
VAFE3_VDD25
C257
0.1uF
+0.9V_CORE
C226
0.1uF
16V
OPT
+3.3V_Normal
+2.5V_BCM35230
L205
BLM18PG121SN1D
C258
0.1uF
+2.5V_BCM35230
C259
C260
10uF
4.7uF
10V
+2.5V_BCM35230
+2.5V_BCM35230
NON_BCM_CAP
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32
VDDC_33
VDDC_34
VDDC_35
VDDC_36
VDDC_37
VDDC_38
VDDC_39
VDDC_40
VDDC_41
VDDC_42
POR_VDD
VDDR1_1
VDDR1_2
VDDR1_3
VDDR1_4
VDDR1_5
VDDR1_6
VDDR1_7
VDDR1_8
VDDR1_9
VDDR1_10
VDDR1_11
VDDR1_12
DDR_LDO_VDDO
VDDR3_1
VDDR3_2
VDDR3_3
VDDR3_4
VDDR3_5
VDDR3_6
VDDR3_7
VDDR3_8
VDDR3_9
VDDR3_10
VDDR3_11
AON_VDDC_1
AON_VDDC_2
AON_POR_VDD
AON_VDDR3
AON_VDDR10_1
AON_VDDR10_2
IC101
LGE35230(BCM35230KFSBG)
V12
V7
M10
N10
P10
R10
T10
U10
V10
W10
V13
L11
M11
N11
P11
R11
T11
U11
V11
W11
V14
L18
M18
N18
P18
R18
T18
U18
V18
W18
V15
L19
M19
N19
P19
R19
T19
U19
V19
W19
V16
V17
L10
L22
AA28
V28
R28
M28
J28
K23
M22
T22
T23
U22
Y22
R22
G15
H22
G23
AB9
K7
AB15
L7
AB14
M7
N6
P6
AA6
AA7
Y7
U7
T7
T6
C261
10uF
10V
C262
10uF
L206
BLM18PG121SN1D
L207
BLM18PG121SN1D
K10
VSS_1
K11
VSS_2
K12
VSS_3
L12
VSS_4
M12
VSS_5
N12
VSS_6
P12
VSS_7
R12
VSS_8
T12
VSS_9
U12
VSS_10
W12
VSS_11
K13
VSS_12
L13
VSS_13
M13
VSS_14
N13
VSS_15
P13
VSS_16
R13
VSS_17
T13
VSS_18
U13
VSS_19
W16
VSS_20
K14
VSS_21
L14
VSS_22
M14
VSS_23
N14
VSS_24
P14
VSS_25
R14
VSS_26
T14
VSS_27
U14
VSS_28
K15
VSS_29
L15
VSS_30
M15
VSS_31
N15
VSS_32
P15
VSS_33
R15
VSS_34
T15
VSS_35
U15
VSS_36
K16
VSS_37
L16
VSS_38
M16
VSS_39
N16
VSS_40
P16
VSS_41
R16
VSS_42
T16
VSS_43
U16
VSS_44
K17
VSS_45
L17
VSS_46
M17
VSS_47
N17
VSS_48
P17
VSS_49
R17
VSS_50
T17
VSS_51
U17
VSS_52
W17
VSS_53
K18
VSS_54
K19
VSS_55
H7
VSS_56
G14
VSS_57
AB16
VSS_58
R7
VSS_59
M6
VSS_60
AB23
VSS_61
P7
VSS_62
W7
VSS_63
J7
VSS_64
N7
VSS_65
AB10
VSS_66
AC23
VSS_67
AC6
VSS_68
G19
VSS_69
AA22
VSS_70
J23
VSS_71
J22
VSS_72
K22
VSS_73
J25
VSS_74
N22
VSS_75
N23
VSS_76
M25
VSS_77
P22
VSS_78
R25
VSS_79
V22
VSS_80
W22
VSS_81
W23
VSS_82
V25
VSS_83
AA25
VSS_84
ADAC_AVDD25
C271
C267
C263
4.7uF
C265
4.7uF
PLL_VAFE_AVDD25
C264
4.7uF
0.01uF
0.1uF
C272
C270
C266
4.7uF C277
VAFE2_VDD25
0.1uF
C269
0.1uF
C268
0.1uF
0.01uF
CORE 0.9V
+0.9V_CORE
L209
BLM18PG121SN1D
C274
22uF
+0.9V_CORE
L210
BLM18PG121SN1D
+0.9V_CORE
L211
BLM18PG121SN1D
POWER 3.3V
+3.3V_Normal
Place as close as possible to the pad
use only for A0/B0 chip
C210-*1
220pF
50V
BCM_A0/B0
PLL_VAFE_AVDD25
+0.9V_CORE
Place as close as possible to the pad
C281
0.1uF
C282
0.1uF
L212
VAFE2_DVDD
VAFE3_DVDD
C208
390pF
50V
C206
390pF
50V
+0.9V_CORE
+0.9V_CORE
USB_AVDD33
C283
0.1uF
+3.3V_Normal
+2.5V_BCM35230
+2.5V_BCM35230
VDAC_AVDD33
BCM_C0
PLL_MIPS_AVDD
C273
0.1uF
BLM18PG121SN1D
C284
22uF
BLM18PG121SN1D
L213
BLM18PG121SN1D
ADAC_AVDD25
EPHY_VDD25
HDMI_AVDD33
C275
0.1uF
OPT
USB_AVDD33
C212
390pF
50V
C210
390pF
50V
PLL_MAIN_AVDD
C276
0.01uF
OPT
HDMI_AVDD
C280
0.1uF
PLL_AUD_AVDD
4.7uF
PLL_VAFE_AVDD
C279
4.7uF
BLM18PG121SN1D
VAFE2_VDD25
VAFE3_VDD25
Place as close as possible to the pad
PLL_VAFE_AVDD
C202
390pF
50V
L214
C285
4.7uF
L215
+3.3V_Normal
AADC_AVDD25
HDMI_AVDD
USB_AVDD
C214
390pF
50V
PLL_AUD_AVDD
+3.3V_Normal
USB_AVDD
VAFE3_DVDD
C287
4.7uF
VDAC_AVDD33
C286
4.7uF
C288
0.1uF
C290
0.1uF
L216
BLM18PG121SN1D
C289
0.1uF
+0.9V_CORE
+0.9V_CORE
+0.9V_CORE
HDMI_AVDD33
C291
4.7uF
LGE35230(BCM35230KFSBG)
AADC_AVDD25
ADACA_AVDD25
ADACC_AVDD25
ADACD_AVDD25
EPHY_BVDD25
EPHY_AVDD25
D5
HDMI0_AVDD
D4
HDMI0_AVDD33
LT0VDD25_1
LT0VDD25_2
LT0VDD25_3
LT0VDD25_4
SPDIF_IN_AVDD25
E4
USB_AVDD
D3
USB_AVDD33
D6
VDAC_AVDD33
VAFE2_DVDD
VAFE2_AVDD25_1
VAFE2_AVDD25_2
VAFE2_DVDD25
D9
VAFE3_DVDD
D8
VAFE3_AVDD25_1
E8
VAFE3_AVDD25_2
F9
VAFE3_AVDD25_3
E9
VAFE3_DVDD25
F8
POR_VDD25
PLL_AUD_AVDD
K4
PLL_MAIN_AVDD
PLL_MIPS_AVDD
PLL_VAFE_AVDD
PLL_VAFE_AVDD25
TVM_OSC_AVDD
U6
AUX_AVDD33
NON_BCM_CAP
C278
0.1uF
AE20
AD20
AC20
AB20
AD25
F19
D25
D24
E24
F24
E25
D14
D18
E17
D16
D17
G25
D11
D12
AE7
L219
BLM18PG121SN1D
C292
22uF
L217
BLM18PG121SN1D
L218
BLM18PG121SN1D
C293
0.1uF
IC101
AADC_AVSS
ADACA_AVSS
ADACC_AVSS
ADACD_AVSS
EPHY_AVSS
HDMI0_AVSS_1
HDMI0_AVSS_2
LT0VSS_1
LT0VSS_2
LT0VSS_3
LT0VSS_4
LT0VSS_5
LT0VSS_6
LT0VSS_7
SPDIF_IN_AVSS
USB_AVSS_1
USB_AVSS_2
VDAC_AVSS
VAFE2_VSS_1
VAFE2_VSS_2
VAFE2_VSS_3
VAFE2_VSS_4
VAFE2_VSS_5
VAFE2_VSS_6
VAFE2_VSS_7
VAFE3_VSS_1
VAFE3_VSS_2
VAFE3_VSS_3
VAFE3_VSS_4
VAFE3_VSS_5
VAFE3_VSS_6
PLL_MIPS_AVSS
TVM_OSC_AVSS
VAFE2_DVDD
C299
C296
0.1uF
4.7uF
PLL_MAIN_AVDD
C297
C294
0.1uF
4.7uF
PLL_MIPS_AVDD
C298
C295
0.1uF
4.7uF
F20
G22
G21
F22
F23
F6
G6
AB22
AB21
AB19
AC19
AB18
AB17
AC17
F15
G7
G8
G9
G20
E18
G18
G17
F18
G16
F16
G13
G12
F12
G11
G10
F10
AD26
AC7
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
BCM35230
MAIN POWER
2
50
DSUB_R+
Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
INCM_R
DSUB_G+
INCM_G
DSUB_B+
INCM_B
COMP1_Y
COMP1_Pr
COMP1_Pb
INCM_VID_SC/COMP2
AV2_CVBS_IN
INCM_VID_AV2
C320 0.1uF
C321 0.1uF
R311
36
C327 0.1uF
C328 0.1uF
R317
36
C322 0.1uF
C323 0.1uF
R312
36
INCM_VID_COMP1
SC_R/COMP2_Pr
SC_G/COMP2_Y
SC_B/COMP2_Pb
C303 0.1uF
C304 0.1uF
R303
36
TU_CVBS
AV1_CVBS_IN
INCM_VID_AV1
TU_SIF
R310
0
R318
0
EU
R325-*1
10
C317 0.1uF
C318 0.1uF
R304
36
SC_CVBS_IN
INCM_VID_SC
NON_EU
R325 0
INCM_TUNER
R306
75
1%
OPT
+2.5V_BCM35230
C319 0.1uF
R305
240
OPT
INCM_SIF
C325 0.1uF
C326 0.1uF
R316
36
R313
10K
+2.5V_BCM35230
R314
12K
C324 0.1uF
R315
120
OPT
DSUB_HSYNC
DSUB_VSYNC
C329 0.1uF
C330 0.1uF
C331 0.1uF
C332 0.1uF
C333 0.1uF
C334 0.1uF
C335 0.1uF
C336 0.1uF
SC_FB
R319
10K
OPT
R320
12K
OPT
LGE35230(BCM35230KFSBG)
B6
A6
C7
A7
B7
C8
C13
A13
C9
A9
B9
B8
C11
A10
B10
C10
D10
F13
A12
C12
B12
B11
E12
E14
E15
F17
E16
F14
E11
C18
B18
A18
C19
A19
B19
C20
B20
E19
D19
E10
F11
IC101
NON_BCM_CAP
VI_R
VI_INCM_R
VI_G
VI_INCM_G
VI_B
VI_INCM_B
HSYNC_IN
VSYNC_IN
VI_Y1
VI_PR1
VI_PB1
VI_INCM_COMP1
VI_SC_R1
VI_SC_G1
VI_SC_B1
VI_INCM_SC1
VI_FB_1/GPIO
VI_FS1
VI_SC_R2
VI_SC_G2
VI_SC_B2
VI_INCM_SC2
VI_FB_2/GPIO
VI_FS2
VI_L1
VI_C1_1
VI_INCM_LC1_1
VI_C1_2
VI_INCM_LC1_2
VI_CVBS1
VI_INCM_CVBS1
VI_CVBS2
VI_INCM_CVBS2
VI_CVBS3
VI_INCM_CVBS3
VI_CVBS4
VI_INCM_CVBS4
VI_SIF1_1
VI_INCM_SIF1_1
VI_SIF1_2
VI_INCM_SIF1_2
Near
Near
Near
Near
Near
Near
Near
Near
P801
P801
P801
JK1101
JK1104
TU2101/2
TU2201/2/3
JK1102
JK1103
JK2501
VIDEO INCM
Run Along DSUB_R Trace
Run Along DSUB_G Trace
Run Along DSUB_B Trace
Run Along COMP_Y_IN,COMP_Pr_IN,COMP_Pb_IN Trace
Run Along AV2_CVBS Trace
Run Along TUNER_CVBS_IF_P Trace
Run Along AV1_CVBS Trace
Run Along COMP_Y_IN,COMP_Pr_IN,COMP_Pb_IN/SC R,G,B Trace
INCM_R
INCM_G
INCM_B
INCM_VID_COMP1
INCM_VID_AV2
INCM_TUNER
INCM_VID_AV1
INCM_VID_SC/COMP2
BCM35230_with_CAP_220pF
IC101-*1
LGE35230
B6
BCM_CAP
VI_R
A6
VI_INCM_R
C7
VI_G
A7
VI_INCM_G
B7
VI_B
C8
VI_INCM_B
C13
HSYNC_IN
A13
VSYNC_IN
C9
VI_Y1
A9
VI_PR1
B9
VI_PB1
B8
VI_INCM_COMP1
C11
VI_SC_R1
A10
VI_SC_G1
B10
VI_SC_B1
C10
VI_INCM_SC1
D10
VI_FB_1/GPIO
F13
VI_FS1
A12
VI_SC_R2
C12
VI_SC_G2
B12
VI_SC_B2
B11
VI_INCM_SC2
E12
VI_FB_2/GPIO
E14
VI_FS2
E15
VI_L1
F17
VI_C1_1
E16
VI_INCM_LC1_1
F14
VI_C1_2
E11
VI_INCM_LC1_2
C18
VI_CVBS1
B18
VI_INCM_CVBS1
A18
VI_CVBS2
C19
VI_INCM_CVBS2
A19
VI_CVBS3
B19
VI_INCM_CVBS3
C20
VI_CVBS4
B20
VI_INCM_CVBS4
E19
VI_SIF1_1
D19
VI_INCM_SIF1_1
E10
VI_SIF1_2
F11
VI_INCM_SIF1_2
SCL3_3.3V
SDA3_3.3V
+3.3V_Normal
R302
R301
1.2K
1.2K
C301
C302
33pF
33pF
50V
50V
PHONE JACK
INCM_AUD_SC/COMP2
M_REMOTE_TX
PC_L_IN
PC_R_IN
AV1_L_IN
AV1_R_IN
INCM_AUD_AV1
AV2_L_IN
AV2_R_IN
INCM_AUD_AV2
SC/COMP2_L_IN
SC/COMP2_R_IN
C305 1uF10V
C306 1uF10V
C307 1uF10V
C308 1uF10V
C309 1uF10V
C310 1uF10V
C311 1uF10V
C312 1uF10V
C313 1uF10V
C314 1uF10V
C315 1uF10V
C316 1uF10V
NON_BCM_CAP
SPDIF_INC_P
SPDIF_INC_N
SPDIF_IND_P
SPDIF_IND_N
I2SSCK_IN/GPIO
I2SWS_IN
I2SSD_IN/GPIO
AADC_LINE_L1
AADC_LINE_R1
AADC_INCM1
AADC_LINE_L2
AADC_LINE_R2
AADC_INCM2
AADC_LINE_L3
AADC_LINE_R3
AADC_INCM3
AADC_LINE_L4
AADC_LINE_R4
AADC_INCM4
AADC_LINE_L5
AADC_LINE_R5
AADC_INCM5
AADC_LINE_L6
AADC_LINE_R6
AADC_INCM6
AADC_LINE_L7
AADC_LINE_R7
AADC_INCM7
IC101
I2SSCK_OUTA/GPIO
I2SWS_OUTA/GPIO
I2SSD_OUTA0/GPIO
I2SSOSCK_OUTA/GPIO
I2SSD_OUTA1/GPIO
I2SSD_OUTA2/GPIO
I2SSCK_OUTC/GPIO
I2SWS_OUTC/GPIO
I2SSD_OUTC/GPIO
I2SSOSCK_OUTC/GPIO
I2SSCK_OUTD/GPIO
I2SWS_OUTD/GPIO
I2SSD_OUTD/GPIO
I2SSOSCK_OUTD/GPIO
SPDIF_OUTA/GPIO
LGE35230(BCM35230KFSBG)
B15
C15
C14
B14
G4
F4
G5
C25
B24
A24
E22
E23
D23
C24
C23
B23
E21
D21
D22
B22
C22
A22
F21
D20
E20
A21
C21
B21
AUDMUTE_0/GPIO
AUDMUTE_1
ADAC_AL_N
ADAC_AL_P
ADAC_AR_N
ADAC_AR_P
ADAC_CL_N
ADAC_CL_P
ADAC_CR_N
ADAC_CR_P
ADAC_DL_N
ADAC_DL_P
ADAC_DR_N
ADAC_DR_P
AF8
AF9
AG9
AC9
AD8
AD9
E2
F2
E3
F3
G2
G3
G1
H1
B13
AG8
E13
C28
C27
D28
D27
C26
A27
B27
B28
B25
A25
A26
B26
R326 100
R327 100
R328 100
R329 100
TU_RESET_SUB
HP_DET
AV1_CVBS_DET
TU_RESET
SC_RE1
SC_RE2 INCM_AUD_PC
/RST_HUB
S2_RESET
SPDIF_OUT
HP_LOUT_N
HP_LOUT_P
HP_ROUT_N
HP_ROUT_P
SCART1_Lout_N
SCART1_Lout_P
SCART1_Rout_N
SCART1_Rout_P
C337
22pF
OPT
C338
22pF
OPT
C339
22pF
OPT
C340
33pF
OPT
AUD_SCK
AUD_LRCK
AUD_LRCH
AUD_MASTER_CLK
Near
Near
Near
Near
Near
JK1102
JK1103
JK2501
JK1104
JK801
TU2101/2
TU2201/2/3
R321 0
R322 0
R323 0
R324 0
AUDIO INCM
Route Between AV1_L_IN & AV1_R_IN Trace
Route Between SC/COMP2_L_IN & SC/COMP2_R_IN Trace
Route Between AV2_L_IN & AV2_R_IN Trace
Route Between PC_L_IN & PC_R_IN Trace
Route Along With TUNER_SIF_IF_N
INCM_AUD_AV1
INCM_AUD_SC/COMP2
INCM_AUD_AV2
INCM_AUD_PC
INCM_SIF
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
BCM35230
MAIN AUDIO/VIDEO
3
50
DDR STRAP
Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
R401
4.7K
DDR_1333
R403
4.7K
R405
4.7K
DDR_1333
R407
4.7K
DDR_DQ[0]
DDR_DQ[1]
DDR_DQ[2]
DDR_DQ[3]
DDR_DQ[4]
JEDEC Types : DDR_DQ[0:4]
R409
00001 : DDR3-1333H (CasL=9)
4.7K
10101 : DDR3-1600K (CasL=11) (O)
OPT
DUAL COMPONENT
IC401,IC402 1ST : EAN61667501, 2ND : EAN61570701
IC401-*1
IC402-*1
1ST : T-K4B2G1646B_HCK0, 2ND : T-H5TQ2G63BFR-PBC
+1.5V_DDR
OUT IN
GND
C403
2.2uF
C405
10uF
C407
2.2uF
NFM18PS105R0J
C410
6.3V
C417
470pF
C421
2.2uF
C423
10uF
C425
10uF
NFM18PS105R0J
C432
6.3V
OUT IN
GND
+1.5V_DDR
DDR_DQ[10]
DDR_DQ[9]
DDR_DQ[7]
DDR_DQ[8]
DDR_DQ[6]
DDR_DQ[5]
R408
4.7K
IC101
NON_BCM_CAP
DDR_ADA_ALT_4
DDR_ADA_ALT_5
DDR_ADA_ALT_6
DDR_CKA01_P
DDR_CKA01_N
DDR_CKA23_P
DDR_CKA23_N
R410
4.7K
OPT
DDR_ADA_0
DDR_ADA_1
DDR_ADA_2
DDR_ADA_3
DDR_ADA_4
DDR_ADA_5
DDR_ADA_6
DDR_ADA_7
DDR_ADA_8
DDR_ADA_9
DDR_ADA_10
DDR_ADA_11
DDR_ADA_12
DDR_ADA_13
DDR_ADA_14
DDR_BAA_0
DDR_BAA_1
DDR_BAA_2
DDR_RASA_N
DDR_CASA_N
DDR_WEA_N
DDR_CKEA
DDR_VREFA
DDR_RST_N
DDR_ZQ
V23
AB27
Y23
Y26
AB26
Y24
AC26
AB24
AC25
AC24
AB25
AD28
Y25
AA27
AC27
AA26
AA24
AD27
Y27
AB28
W24
V24
W25
V26
U24
W27
W28
N28
N27
U23
AA23
W26
IC401-*2
NT5CB128M16BP-CG
DDR_1333_NANYA
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12
T3
NC_6
M7
NC_5
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE
L2
CS
K1
ODT
J3
RAS
K3
CAS
L3
WE
T2
RESET
F3
DQSL
G3
DQSL
C7
DQSU
B7
DQSU
E7
DML
D3
DMU
E3
DQL0
F7
DQL1
F2
DQL2
F8
DQL3
H3
DQL4
H8
DQL5
G2
DQL6
H7
DQL7
D7
DQU0
C3
DQU1
C8
DQU2
C2
DQU3
A7
DQU4
A2
DQU5
B8
DQU6
A3
DQU7
Bus Width : DDR_DQ[10]
0 - 16b
1 - 32b (O)
Chip Width : DDR_DQ[8]
0 - 8b
1 - 16b (O)
Chip Size : DDR_DQ[6:5]
00 - 4Gbit
01 - 2Gbit (O)
10 - 1Gbit
11 - 512Mbit
DDR_AA0
DDR_AA1
DDR_AA2
DDR_AA3
DDR01_AA4
DDR01_AA5
DDR01_AA6
DDR23_AA4
DDR23_AA5
DDR23_AA6
DDR_AA7
DDR_AA8
DDR_AA9
DDR_AA10
DDR_AA11
DDR_AA12
DDR_AA13
DDR_AA14
DDR_BAA0
DDR_BAA1
DDR_BAA2
DDR_RASb
DDR_CASb
DDR_WEb
DDR_CKE
DDR01_CLK
DDR01_CLKb
DDR23_CLK
DDR23_CLKb
DDR_VREFA
DDR_RESETb
R411 240
1%
M8
VREFCA
H1
VREFDQ
L8
ZQ
B2
VDD_1
D9
VDD_2
G7
VDD_3
K2
VDD_4
K8
VDD_5
N1
VDD_6
N9
VDD_7
R1
VDD_8
R9
VDD_9
A1
VDDQ_1
A8
VDDQ_2
C1
VDDQ_3
C9
VDDQ_4
D2
VDDQ_5
E9
VDDQ_6
F1
VDDQ_7
H2
VDDQ_8
H9
VDDQ_9
J1
NC_1
J9
NC_2
L1
NC_3
L9
NC_4
T7
NC_7
A9
VSS_1
B3
VSS_2
E1
VSS_3
G8
VSS_4
J2
VSS_5
J8
VSS_6
M1
VSS_7
M9
VSS_8
P1
VSS_9
P9
VSS_10
T1
VSS_11
T9
VSS_12
B1
VSSQ_1
B9
VSSQ_2
D1
VSSQ_3
D8
VSSQ_4
E2
VSSQ_5
E8
VSSQ_6
F9
VSSQ_7
G1
VSSQ_8
G9
VSSQ_9
IC402-*2
NT5CB128M16BP-CG
DDR_1333_NANYA
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12
T3
NC_6
M7
NC_5
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE
L2
CS
K1
ODT
J3
RAS
K3
CAS
L3
WE
T2
RESET
F3
DQSL
G3
DQSL
C7
DQSU
B7
DQSU
E7
DML
D3
DMU
E3
DQL0
F7
DQL1
F2
DQL2
F8
DQL3
H3
DQL4
H8
DQL5
G2
DQL6
H7
DQL7
D7
DQU0
C3
DQU1
C8
DQU2
C2
DQU3
A7
DQU4
A2
DQU5
B8
DQU6
A3
DQU7
C453
1uF
6.3V
DDR01_CLK
DDR01_CLKb
R412
56
1%
C401
1000pF
DDR_DQ[0-7]
DDR_DQ[8-15]
IC401-*3
NT5CB128M16BP-DI
DDR_1600_NANYA
M8
VREFCA
H1
VREFDQ
L8
ZQ
B2
VDD_1
D9
VDD_2
G7
VDD_3
K2
VDD_4
K8
VDD_5
N1
VDD_6
N9
VDD_7
R1
VDD_8
R9
VDD_9
A1
VDDQ_1
A8
VDDQ_2
C1
VDDQ_3
C9
VDDQ_4
D2
VDDQ_5
E9
VDDQ_6
F1
VDDQ_7
H2
VDDQ_8
H9
VDDQ_9
J1
NC_1
J9
NC_2
L1
NC_3
L9
NC_4
T7
NC_7
A9
VSS_1
B3
VSS_2
E1
VSS_3
G8
VSS_4
J2
VSS_5
J8
VSS_6
M1
VSS_7
M9
VSS_8
P1
VSS_9
P9
VSS_10
T1
VSS_11
T9
VSS_12
B1
VSSQ_1
B9
VSSQ_2
D1
VSSQ_3
D8
VSSQ_4
E2
VSSQ_5
E8
VSSQ_6
F9
VSSQ_7
G1
VSSQ_8
G9
VSSQ_9
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12
T3
NC_6
M7
NC_5
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE
L2
CS
K1
ODT
J3
RAS
K3
CAS
L3
WE
T2
RESET
F3
DQSL
G3
DQSL
C7
DQSU
B7
DQSU
E7
DML
D3
DMU
E3
DQL0
F7
DQL1
F2
DQL2
F8
DQL3
H3
DQL4
H8
DQL5
G2
DQL6
H7
DQL7
D7
DQU0
C3
DQU1
C8
DQU2
C2
DQU3
A7
DQU4
A2
DQU5
B8
DQU6
A3
DQU7
M8
VREFCA
H1
VREFDQ
L8
ZQ
B2
VDD_1
D9
VDD_2
G7
VDD_3
K2
VDD_4
K8
VDD_5
N1
VDD_6
N9
VDD_7
R1
VDD_8
R9
VDD_9
A1
VDDQ_1
A8
VDDQ_2
C1
VDDQ_3
C9
VDDQ_4
D2
VDDQ_5
E9
VDDQ_6
F1
VDDQ_7
H2
VDDQ_8
H9
VDDQ_9
J1
NC_1
J9
NC_2
L1
NC_3
L9
NC_4
T7
NC_7
A9
VSS_1
B3
VSS_2
E1
VSS_3
G8
VSS_4
J2
VSS_5
J8
VSS_6
M1
VSS_7
M9
VSS_8
P1
VSS_9
P9
VSS_10
T1
VSS_11
T9
VSS_12
B1
VSSQ_1
B9
VSSQ_2
D1
VSSQ_3
D8
VSSQ_4
E2
VSSQ_5
E8
VSSQ_6
F9
VSSQ_7
G1
VSSQ_8
G9
VSSQ_9
IC402-*3
NT5CB128M16BP-DI
DDR_1600_NANYA
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12
T3
NC_6
M7
NC_5
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE
L2
CS
K1
ODT
J3
RAS
K3
CAS
L3
WE
T2
RESET
F3
DQSL
G3
DQSL
C7
DQSU
B7
DQSU
E7
DML
D3
DMU
E3
DQL0
F7
DQL1
F2
DQL2
F8
DQL3
H3
DQL4
H8
DQL5
G2
DQL6
H7
DQL7
D7
DQU0
C3
DQU1
C8
DQU2
C2
DQU3
A7
DQU4
A2
DQU5
B8
DQU6
A3
DQU7
OPT
R432
4.7K
R404
4.7K
OPT
4.7K
OPT
R402
4.7K
OPT
R406
LGE35230(BCM35230KFSBG)
DDR_DQ[0-7]
DDR_DQ[0]
DDR_DQ[1]
DDR_DQ[2]
DDR_DQ[3]
DDR_DQ[4]
DDR_DQ[5]
DDR_DQ[24]
DDR_DQ[25]
DDR_DQ[26]
DDR_DQ[27]
DDR_DQ[28]
DDR_DQ[29]
DDR_DQ[30]
DDR_DQ[31]
DDR_DM[0]
DDR_DM[1]
DDR_DM[2]
DDR_DM[3]
DDR_QS0
DDR_QS0b
DDR_QS1
DDR_QS1b
DDR_QS2
DDR_QS2b
DDR_QS3
DDR_QS3b
DDR_DQ[6]
DDR_DQ[7]
DDR_DQ[8]
DDR_DQ[9]
DDR_DQ[10]
DDR_DQ[11]
DDR_DQ[12]
DDR_DQ[13]
DDR_DQ[14]
DDR_DQ[15]
DDR_DQ[16]
DDR_DQ[17]
DDR_DQ[18]
DDR_DQ[19]
DDR_DQ[20]
DDR_DQ[21]
DDR_DQ[22]
DDR_DQ[23]
DDR_DQ[8-15]
DDR_DQ[16-23]
DDR_DQ[24-31]
DDR_DM[0-3] DDR_QS3
U26
R26
U27
R27
V27
P26
U25
P27
R24
N24
T25
M23
R23
N25
T24
N26
L26
H27
L27
J26
M27
G27
M26
H26
L23
H25
L24
J24
M24
H23
L25
H24
T26
P25
J27
K24
T27
T28
P24
P23
K27
K28
K25
K26
DDR_DQA_0
DDR_DQA_1
DDR_DQA_2
DDR_DQA_3
DDR_DQA_4
DDR_DQA_5
DDR_DQA_6
DDR_DQA_7
DDR_DQA_8
DDR_DQA_9
DDR_DQA_10
DDR_DQA_11
DDR_DQA_12
DDR_DQA_13
DDR_DQA_14
DDR_DQA_15
DDR_DQA_16
DDR_DQA_17
DDR_DQA_18
DDR_DQA_19
DDR_DQA_20
DDR_DQA_21
DDR_DQA_22
DDR_DQA_23
DDR_DQA_24
DDR_DQA_25
DDR_DQA_26
DDR_DQA_27
DDR_DQA_28
DDR_DQA_29
DDR_DQA_30
DDR_DQA_31
DDR_DMA_0
DDR_DMA_1
DDR_DMA_2
DDR_DMA_3
DDR_DQSA_P_0
DDR_DQSA_N_0
DDR_DQSA_P_1
DDR_DQSA_N_1
DDR_DQSA_P_2
DDR_DQSA_N_2
DDR_DQSA_P_3
DDR_DQSA_N_3
R413
56
1%
+1.5V_DDR
C455
C454
1uF
1uF
6.3V
6.3V
DDR_AA0
DDR_AA1
DDR_AA2
DDR_AA3
DDR01_AA4
DDR01_AA5
DDR01_AA6
DDR_AA7
DDR_AA8
DDR_AA9
DDR_AA10
DDR_AA11
DDR_AA12
DDR_AA13
DDR_BAA0
DDR_BAA1
DDR_BAA2
DDR_CKE
+1.5V_DDR
R414 10K
DDR_RASb
DDR_CASb
DDR_WEb
DDR_RESETb
DDR_QS0
DDR_QS0b
DDR_QS1
DDR_QS1b
DDR_DM[0]
DDR_DM[1]
DDR_DQ[0]
DDR_DQ[1]
DDR_DQ[2]
DDR_DQ[3]
DDR_DQ[4]
DDR_DQ[5]
DDR_DQ[6]
DDR_DQ[7]
DDR_DQ[8]
DDR_DQ[14]
DDR_DQ[13]
DDR_DQ[12]
DDR_DQ[9]
DDR_DQ[10]
DDR_DQ[15]
DDR_DQ[11]
M8
VREFCA
H1
VREFDQ
L8
ZQ
B2
VDD_1
D9
VDD_2
G7
VDD_3
K2
VDD_4
K8
VDD_5
N1
VDD_6
N9
VDD_7
R1
VDD_8
R9
VDD_9
A1
VDDQ_1
A8
VDDQ_2
C1
VDDQ_3
C9
VDDQ_4
D2
VDDQ_5
E9
VDDQ_6
F1
VDDQ_7
H2
VDDQ_8
H9
VDDQ_9
J1
NC_1
J9
NC_2
L1
NC_3
L9
NC_4
T7
NC_7
A9
VSS_1
B3
VSS_2
E1
VSS_3
G8
VSS_4
J2
VSS_5
J8
VSS_6
M1
VSS_7
M9
VSS_8
P1
VSS_9
P9
VSS_10
T1
VSS_11
T9
VSS_12
B1
VSSQ_1
B9
VSSQ_2
D1
VSSQ_3
D8
VSSQ_4
E2
VSSQ_5
E8
VSSQ_6
F9
VSSQ_7
G1
VSSQ_8
G9
VSSQ_9
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
M2
N8
M3
J7
K7
K9
L2
K1
J3
K3
L3
T2
F3
G3
C7
B7
E7
D3
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
NFM18PS105R0J
K4B2G1646C
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
NC_5
BA0
BA1
BA2
CK
CK
CKE
CS
ODT
RAS
CAS
WE
RESET
DQSL
DQSL
DQSU
DQSU
DML
DMU
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
C402
6.3V
OUT IN
GND
IC401
DDR_1333_SS
VREFCA
VREFDQ
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
NC_1
NC_2
NC_3
NC_4
NC_6
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
C412
1uF
ZQ
M8
H1
L8
R415 240
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
J1
J9
L1
L9
T7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
+1.5V_DDR
C415
0.01uF
C416
0.01uF
1%
+1.5V_DDR
DDR_AA14
R416
4.99K
1%
R417
4.99K
1%
DDR_VREFA
+1.5V_DDR
DDR23_CLK
DDR23_CLKb
DDR_DQ[16-23]
DDR_DQ[24-31]
R418
DDR23_AA4
DDR23_AA5
DDR23_AA6
R419
56
56
1%
1%
C419
1000pF
+1.5V_DDR
DDR_RESETb
DDR_DM[2]
DDR_DM[3]
DDR_DQ[24]
DDR_DQ[30]
DDR_DQ[29]
DDR_DQ[28]
DDR_DQ[25]
DDR_DQ[26]
DDR_DQ[31]
DDR_DQ[27]
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
DDR_AA0
DDR_AA1
DDR_AA2
DDR_AA3
DDR_AA7
DDR_AA8
DDR_AA9
DDR_AA10
DDR_AA11
DDR_AA12
DDR_AA13
DDR_BAA0
DDR_BAA1
DDR_BAA2
DDR_CKE
R420 10K
DDR_RASb
DDR_CASb
DDR_WEb
DDR_QS2
DDR_QS2b
DDR_QS3b
DDR_DQ[16]
DDR_DQ[17]
DDR_DQ[18]
DDR_DQ[19]
DDR_DQ[20]
DDR_DQ[21]
DDR_DQ[22]
DDR_DQ[23]
NFM18PS105R0J
C433
6.3V
OUT IN
GND
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
M2
N8
M3
J7
K7
K9
L2
K1
J3
K3
L3
T2
F3
G3
C7
B7
E7
D3
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
K4B2G1646C
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
NC_5
BA0
BA1
BA2
CK
CK
CKE
CS
ODT
RAS
CAS
WE
RESET
DQSL
DQSL
DQSU
DQSU
DML
DMU
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
C426
1uF
IC402
DDR_1333_SS
VREFCA
VREFDQ
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
NC_1
NC_2
NC_3
NC_4
NC_6
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
ZQ
+1.5V_DDR
M8
H1
L8
R421 240
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
J1
J9
L1
L9
T7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
+1.5V_DDR
R422
4.99K
1%
R423
C435
4.99K
0.01uF
1%
DDR_VREFA
C436
0.01uF
+1.5V_DDR
1%
DDR_AA14
BCM35230
MAIN DDR
IC401-*1
K4B2G1646C-HCK0
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC
T3
A13
M7
NC_5
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE
L2
CS
K1
ODT
J3
RAS
K3
CAS
L3
WE
T2
RESET
F3
DQSL
G3
DQSL
C7
DQSU
B7
DQSU
E7
DML
D3
DMU
E3
DQL0
F7
DQL1
F2
DQL2
F8
DQL3
H3
DQL4
H8
DQL5
G2
DQL6
H7
DQL7
D7
DQU0
C3
DQU1
C8
DQU2
C2
DQU3
A7
DQU4
A2
DQU5
B8
DQU6
A3
DQU7
DDR_1600_SS
VREFCA
VREFDQ
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
NC_1
NC_2
NC_3
NC_4
NC_6
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
DDR23_AA6
DDR23_AA4
DDR23_AA5
DDR01_AA6
DDR01_AA4
DDR01_AA5
M8
H1
L8
ZQ
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
J1
J9
L1
L9
T7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
DDR_RESETb
DDR_CKE
DDR_AA13
DDR_AA14
DDR_AA2
DDR_AA11
DDR_AA3
DDR_AA7
DDR_AA9
DDR_AA8
DDR_AA0
DDR_AA1
DDR_BAA0
DDR_BAA2
DDR_BAA1
DDR_AA10
DDR_AA12
DDR_WEb
DDR_CASb
DDR_RASb
R428
82
R424 56
R425 56
AR401 56
AR402 56
AR403 56
AR404 56
AR405 56
AR406 56
R426 56
R427 56
IC402-*1
K4B2G1646C-HCK0
DDR_1600_SS
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC
T3
A13
M7
NC_5
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE
L2
CS
K1
ODT
J3
RAS
K3
CAS
L3
WE
T2
RESET
F3
DQSL
G3
DQSL
C7
DQSU
B7
DQSU
E7
DML
D3
DMU
E3
DQL0
F7
DQL1
F2
DQL2
F8
DQL3
H3
DQL4
H8
DQL5
G2
DQL6
H7
DQL7
D7
DQU0
C3
DQU1
C8
DQU2
C2
DQU3
A7
DQU4
A2
DQU5
B8
DQU6
A3
DQU7
+1.5V_DDR
R429
82
C437
100pF
OPT
C441 1uF
VREFCA
VREFDQ
ZQ
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
NC_1
NC_2
NC_3
NC_4
NC_6
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
4
M8
H1
L8
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
J1
J9
L1
L9
T7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
C438
C404
C406
C450
C408
C439
C409
C451
C411
C440
C452
R430
4.7K
OPT
C442
100pF
R431
4.7K
OPT
1uF
0.1uF
0.1uF
0.1uF
0.1uF
1uF
0.1uF
0.1uF
0.1uF
1uF
0.1uF
50
NEC MICOM
Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
For Debug
P601
12505WS-12A00
+3.5V_ST
1
2
3
4
5
6
7
8
9
10
11
12
13
R607
R610
+3.5V_ST
R606 10K
10K
10K
R61 5 22
R61 7 22
R62 1 22
EEPROM for Micom
IC601
M24C16-WMN6T
NC/E0
1
NC/E1
R60 1
47K
NC/E2
2
3
VSS
4
VCC
8
WC
7
SCL
6
SDA
5
MICOM MODEL OPTION
+3.5V_ST
PDP/3D
R613 10K
R611 10K
LCD/OLED
R612 10K
TOUCH_KEY
TACT_KEY
R614 10K
AMP_RESET_N
PANEL_CTL
INSTANT_MODE
R604 100
R605 100
R602 100
R603 100
R619
22
R616
22
I2C LED
R622 10K
PWM_LED
R623 10K
MICOM_RESET
NEC_ISP_Tx
NEC_ISP_Rx
OCD1A
OCD1B
FLMD0
NEC_ISP_Rx
NEC_ISP_Tx
R624 10K
10YEAR_TOOL
R625 10K
11YEAR_TOOL
+3.5V_ST
MODEL1_OPT_0
MODEL1_OPT_1
MODEL1_OPT_2
MODEL1_OPT_3
EEPROM_SCL
EEPROM_SDA
PIN NAME
MODEL_OPT_0
MODEL_OPT_1 I2C_LED
MODEL_OPT_2
MODEL_OPT_3
MODEL_OPT_3
MODEL_OPT_1
MODEL_OPT_2
MODEL OPTION
PIN NO.
HIGH
10YEAR_TOOL
8
(10 SENSOR)
11
30
TOUCH_KEY
31
PDP/3D
LCD
PDP
0 0
LOW
1
0 1 0
1 0
LOW
11YEAR_TOOL
(11 SENSOR)
PWM_LED
TACT_KEY
LCD/OLED
OLED 3D
TBD
0
GND
+3.5V_ST
C602
13pF
C603
50V
50V
13pF
X601
10MHz
47K
OPT
R637
10Mhz Crystal
+3.5V_ST
C604
0.1uF
+3.5V_ST
VDD
R626 4.7K
SCL2_3.3V
SDA2_3.3V
EEPROM_SCL
EEPROM_SDA
HDMI_CEC
POWER_ON/OFF2_1
AMP_MUTE
MODEL1_OPT_0
SOC_RESET
INV_CTL
MODEL1_OPT_1
OCD1B
S/T_SCL
+3.5V_ST
R628 4.7K
R629
R630
R631 22
R632 22
R633
22
OPT
R627
4.7K
22
22
P60/SCL0
P61/SDA0
P62/EXSCL0
P33/TI51/TO51/INTP4
P73/KR3
P72/KR2
P71/KR1
P70/KR0
P32/INTP3/OCD1B
P63
P75
P74
1
2
3
4
5
6
7
8
9
10
11
12
48
13
P31/INTP2/OCD1A
OPT
1
HIGH LOW_SMALL
1
1
+3.5V_ST
4.7K
R636
R63 8 22
S/T_SDA
OCD1A
FLMD0
R641
R639 10K
GND
C605 0.1uF
P122/X2/EXCLK/OCD0B
P121/X1/OCD0A
REGC
VSS
44
45
46
47
IC602
uPD78F0514
NEC_MICOM
14
15
16
17
P30/INTP1
P15/TOH0
P17/TI50/TO50
P16/TOH1/INTP5
10K
R64 0
IR
POWER_DET
LED_R/BUZZ
LED_B/LG_LOGO
0
15pF
C606
MICOM_DOWNLOAD
C607 15pF
X602
32.768KHz
R642
4.7M
OPT
P124/XT2/EXCLKS
P123/XT1
FLMD0
41
42
43
18
19
20
P14/RXD6
P13/TXD6
P12/SO10
NEC_ISP_Tx
NEC_ISP_Rx
POWER_ON/OFF2_2
WIRELESS_PWR_EN
WIRELESS_DET
C608
0.1uF
16V
R643 22
P120/INTP0/EXLVI
P41
P40
RESET
37
38
39
40
36
35
34
33
32
31
30
29
28
27
26
25
21
22
23
24
AVSS
AVREF
P11/SL10/RXD0
P10/SCK10/TXD0
NEC_TXD
NEC_RXD MICOM_RESET
+3.5V_ST
47K
OPT
270K
R647 20K
R646
20K
JTP-1127WEM
4 3
1/16W
1%
1/16W
1%
SW1
1 2
R644
R645
P140/PCL/INTP6
P00/TI000
P01/TI010/TO00
P130
P20/ANI0
ANI1/P21
ANI2/P22
ANI3/P23
ANI4/P24
ANI5/P25
ANI6/P26
ANI7/P27
+3.5V_ST
C609 1uF
R648 10K
R649 0
OPT
RL_ON
SCART_MUTE
C
Q601
B
2SC3052
E
EDID_WP
MODEL1_OPT_3
MODEL1_OPT_2
POWER_ON/OFF1
MICOM_DOWNLOAD
SIDE_HP_MUTE
KEY2
KEY1
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
BCM35230
MICOM
6
50
BODY_SHIELD
Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
20
EAG62611201
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HP_DET
5V
GND
DDC_DATA
DDC_CLK
ARC
CE_REMOTE
CK-
CK_GND
CK+
D0-
D0_GND
D0+
D1-
D1_GND
D1+
D2-
D2_GND
D2+
5V_HDMI_1
R730
3.6K
OPT
VR703
10V
OPT
CEC_REMOTE
CK-_HDMI1
CK+_HDMI1
D0-_HDMI1
D0+_HDMI1
D1-_HDMI1
D1+_HDMI1
D2-_HDMI1
D2+_HDMI1
R737
0
DUAL COMPONENT
D707,D708
D713
D710,D711
D713
R754
27K
BODY_SHIELD
HP_DET
5V
GND
DDC_DATA
DDC_CLK
NC
CE_REMOTE
CK-
CK_GND
CK+
D0-
D0_GND
D0+
D1-
D1_GND
D1+
D2-
D2_GND
D2+
5V_HDMI_4
R735
3.6K
OPT
VR707
10V
OPT
CEC_REMOTE
CK-_HDMI4
CK+_HDMI4
D0-_HDMI4
D0+_HDMI4
D1-_HDMI4
D1+_HDMI4
D2-_HDMI4
D2+_HDMI4
R727
0
OPT
C717
0.1uF
16V
OPT
DDC_SDA_4
DDC_SCL_4
VR708
10V
OPT
R729
1K
HDMI_HPD_4
OPT
* HDMI CEC
BAT54_SUZHO
CEC_REMOTE
GND
20
EAG62611201
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
R77 5
150
R77 6
63. 4
R728
1K
OPT
HDMI_HPD_1
HDMI_ARC
VR706
10V
OPT
C714
OPT
0.1uF
16V
OPT
DDC_SDA_1
DDC_SCL_1
ARC
C730
0.1uF
1ST : 0DD184009AA 2ND : 0DSIH00028A
1ST : T-BAT54_SUZHO, 2ND : 0DSON00138A
+3.5V_ST
G
SBD
Q710
BSS83
R741
120K
HDMI_CEC
+3.3V_Normal +3.3V_HDMI
L701
BLM18PG121SN1D
C720
0.1uF
16V
C718
10uF
C719
10uF
JK703
RSD-105156-100
BODY_SHIELD
20
19
18
17
16
15
14
13
12
11
10
EAG62611201
JK701
RSD-105156-100
BODY_SHIELD
20
EAG62611201
JK702
RSD-105156-100
9
8
7
6
5
4
3
2
1
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HP_DET
5V
GND
DDC_DATA
DDC_CLK
NC
CE_REMOTE
CK-
CK_GND
CK+
D0-
D0_GND
D0+
D1-
D1_GND
D1+
D2-
D2_GND
D2+
HP_DET
5V
GND
DDC_DATA
DDC_CLK
NC
CE_REMOTE
CK-
CK_GND
CK+
D0-
D0_GND
D0+
D1-
D1_GND
D1+
D2-
D2_GND
D2+
5V_HDMI_2
R740
3.6K
OPT
5V_HDMI_3
R739
3.6K
OPT
VR701
10V
OPT
VR702
10V
OPT
R725
0
R731
0
HDMI1
R736
1K
OPT
HDMI_HPD_2
CEC_REMOTE
CK-_HDMI2
CK+_HDMI2
D0-_HDMI2
D0+_HDMI2
D1-_HDMI2
D1+_HDMI2
D2-_HDMI2
D2+_HDMI2
VR704
10V
OPT
C715
OPT
0.1uF
16V
OPT
DDC_SDA_2
DDC_SCL_2
HDMI2
R726
1K
OPT
HDMI_HPD_3
CEC_REMOTE
CK-_HDMI3
CK+_HDMI3
D0-_HDMI3
D0+_HDMI3
D1-_HDMI3
D1+_HDMI3
D2-_HDMI3
D2+_HDMI3
VR705
10V
OPT
C716
OPT
0.1uF
16V
OPT
DDC_SDA_3
DDC_SCL_3
RSD-105156-100
JK704
+5V_Normal
D707
R713
4.7K
+5V_Normal
D708
R714
4.7K
5V_HDMI_1
A1CA2
5V_HDMI_3
A1CA2
R715
4.7K
R716
4.7K
HDMI3
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
DDC_SDA_1
DDC_SCL_1
DDC_SDA_3
DDC_SCL_3
HDMI4
+5V_Normal
5V_HDMI_2
A1CA2
D710
R723
R720
4.7K
4.7K
+5V_Normal
5V_HDMI_4
R721
4.7K
A1CA2
R724
4.7K
D711
EDID Pull-up
DDC_SDA_2
DDC_SCL_2
DDC_SDA_4
DDC_SCL_4
+3.3V_HDMI
C707
10uF
10V
HDMI2
CK-_HDMI2
CK+_HDMI2
D0-_HDMI2
D0+_HDMI2
D1-_HDMI2
D1+_HDMI2
D2-_HDMI2
D2+_HDMI2
HDMI3
CK-_HDMI3
CK+_HDMI3
D0-_HDMI3
D0+_HDMI3
D1-_HDMI3
D1+_HDMI3
D2-_HDMI3
D2+_HDMI3
C701
10uF
10V
C706
10uF
10V
C703
0.1uF
16V
C711
0.1uF
16V
C712
0.1uF
16V
C713
0.1uF
16V
R1XCN
R1XCP
R1X0N
R1X0P
R1X1N
R1X1P
R1X2N
R1X2P
VCC33_1
RSVD_1
R2XCN
R2XCP
R2X0N
R2X0P
R2X1N
R2X1P
R2X2N
R2X2P
HDMI1
D2-_HDMI1
D1+_HDMI1
D0-_HDMI1
D0+_HDMI1
D1-_HDMI1
D2+_HDMI1
R0X0N
R0X0P
R0X1N
R0X1P
R0X2N
R0X2P
[EP]GND
67
68
69
70
71
72
1
2
THERMAL
3
73
4
5
6
7
8
9
SII9287B
10
11
12
13
14
15
16
17
18
19
R3XCN20R3XCP21R3X0N22R3X0P23R3X1N24R3X1P25R3X2N26R3X2P
CK-_HDMI4
D0-_HDMI4
D0+_HDMI4
CK+_HDMI4
D1-_HDMI4
D1+_HDMI4
CK+_HDMI1
R0XCP
66
IC701
D2-_HDMI4
HDMI4
CK-_HDMI1
VCC33_3
R0XCN
64
65
27
VCC33_2
D2+_HDMI4
HDMI S/W OUTPUT
HDMI_RX0+
HDMI_CLK-
HDMI_RX0-
HDMI_CLK+
TX0P
TX0N
TXCP
TXCN
60
61
62
63
28
29
31
DSDA030DSCL0
RSVD_2
CBUS_HPD0
DDC_SCL_1
DDC_SDA_1
HDMI_HPD_1
HDMI_RX1-
HDMI_RX1+
TX2N
TX1P
TX1N
58
59
32
33
DSDA134DSCL1
R0PWR5V
DDC_SDA_2
HDMI_RX2+
HDMI_RX2-
+5V_Normal
C708
1uF
OPT
OPT
C710
1uF
10V
R780 33
R781 33
R778
33
R779
33
TPWR_CI2CA
TX2P
55
56
57
35
36
R1PWR5V
CBUS_HPD1
DDC_SCL_2
HDMI_HPD_2
CSCL
54
CSDA
53
INT
52
CEC_D
51
CEC_A
50
R4PWR5V
49
DSCL4
48
DSDA4
47
R3PWR5V
46
CBUS_HPD3
45
DSCL3
44
DSDA3
43
R2PWR5V
42
CBUS_HPD2
41
DSCL2
40
DSDA2
39
SBVCC
38
MICOM_VCC33
37
1uF
C704
C709
1uF
R708
10
R712
10
R777
4.7K
1/16W
R707
1K
1%
5V_HDMI_1
1/16W
R703
1K
1%
R706
0
5V_HDMI_2
BCM35230
HDMI 7
HDMI_HPD_4
DDC_SCL_4
DDC_SDA_4
HDMI_HPD_3
DDC_SCL_3
DDC_SDA_3
SCL1_3.3V
SDA1_3.3V
SCL3_3.3V
SDA3_3.3V
R717
10
C705
1uF
C702
1uF
1/16W
R711
1K
1%
5V_HDMI_4
5V_HDMI_3
R718
10
1/16W
R705
1K
1%
31
RGB/ PC AUDIO/ SPDIF/ EARPHONE/ RS232C
Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
RGB PC
DSUB_VSYNC
DSUB_HSYNC
R868
0
R869
0
DUAL COMPONENT
L804
BG2012B080TF
C828
0.22uF
10V
+3.3V_Normal
R842
4.7K
C
Q801
E
L805
BG2012B080TF
C829
0.22uF
10V
B
2SC3052
OPT
R843
0
R844
1K
HP_LOUT
SIDE_HP_MUTE
HP_ROUT
D811
5.6V
OPT
+5V_Normal
EDID_WP
RGB_DDC_SCL
RGB_DDC_SDA
+3.3V_Normal
R819
10K
D812
5.6V
ESD_COMMON
R820 1K
D812-*1
5.6V
ESD_CERADIODE
DSUB_DET
EARPHON JACK
+3.3V_Normal
R822
2.7K
HP_LOUT
HP_DET
R821 1K
HP_ROUT
EARPHONE AMP
HP_LOUT_N
HP_LOUT_P
HP_ROUT_P
HP_ROUT_N
R823
R824
4.7K
OPT
R825
R826 0
C816
1uF
10V
C817
1uF
10V
C818
1uF
10V
C819
1uF
10V
OPT
OPT
JK803
KJA-PH-0-0177
5 GND
4L
3 DETECT
1R
EAG61030001
0
OPT
R828
SPK_R+_HOTEL
SPK_R-_HOTEL
INL-
INL+
INR+
INR-
4.7K
R827
Close to the IC
SGND
OUTL
15
16
1
2
IC804
TPA6132A2
3
4
EAN60724701
6G07G18
5
OUTR
+3.3V_Normal
D810
KDS184
A2
C
A1
IC801
74F08D
D0A
1
D0B
R801
22
R802
22
R850 0
R851 0
2
Q0
3
D1A
4
OPT
D1B
5
OPT
Q1
6
GND
7
DSUB_B+
DSUB_G+
DSUB_R+
+5V_Normal
IC802
VCC
14
D3B
13
D3A
12
Q3
11
D2B
R852 0
10
OPT
D2A
R853 0
9
OPT
Q2
8
R807
10K
OPT
R808
10K
OPT
R812
75
R811
75
R813
75
D804
30V
D805
30V
C830
47pF
50V
C831
47pF
50V
C832
47pF
50V
AT24C02BN-SH-T
A0
1
A1
2
A2
3
GND
4
5.6V
D808-*1
ESD_CERADIODE
ESD_COMMON
5.6V
D806-*1
ESD_CERADIODE
ESD_COMMON
5.6V
D807-*1
ESD_CERADIODE
VCC
8
WP
7
SCL
6
SDA
5
C807
22pF
50V
C808
22pF
50V
BLM15BD121SN1
ESD_COMMON
D808
30V
BLM15BD121SN1
D806
30V
BLM15BD121SN1
D807
30V
Closed to JACK
L807
L808
L806
C809
18pF
R814
R815
2.7K
2.7K
R848 22
R847 22
C810
18pF
50V
50V
R817
10K
OPT
D809
5.6V
91010
5
15
D804,D805,D806
D807,D808,D813
D814
D810
Q801
IC805
L803
120-ohm
BLM18PG121SN1D
C822
10uF
10V
C821
1uF
10V
EN14VDD
13
12
11
10
9
HPVSS
C823
2.2uF
10V
HPVDD
CPP
PGND
CPN
C824
0.1uF
16V
1ST : EAH39491601, 2ND : EAH33945901
1ST : 0DD184009AA, 2ND : 0DSIH00028A
1ST : 0TRIY80001A, 2ND : 0TR387500AA
1ST : EAN61151201, 2ND : EAN61130001
LPF READEY
(For H/P Noise Improvement)
R837
C825
100K
2.2uF
OPT
10V
C826
2.2uF
10V
PC AUDIO
JK801
KJA-PH-0-0177
5 GND
4 L
3 DETECT
1 R
SPDIF OUT
SPDIF_OUT
R803
0
D801
AMOTECH
5.6V
ESD_COMMON
D802
AMOTECH
5.6V
ESD_COMMON
R804
470K
R805
470K
R806
2.7K
R866
22
C801
560pF
50V
R867
22
C802
560pF
50V
+3.3V_Normal
D803
30V
OPT
C803
0.1uF
16V
C804
560pF
50V
C805
560pF
50V
PC_L_IN
PC_R_IN
JK802
2F11TC1-EM52-4F
VIN
A
VCC
B
GND
C
Fiber Optic
4
SHIELD
111112121313141415
6677889
112233445
JK804
SLIM-15F-D-2
16
16
RS232C
10
5
JP809
9
8
7
6
SPG09-DB-009
JK805
R862
0
R863
0
R864
0
R865
0
4
3
2
1
BCM_RX
NEC_RXD
BCM_TX
NEC_TXD
0.1uF
C812 0.1uF
C813
C815 0.1uF
IR_OUT
100
+3.5V_ST
IC803
MAX3232CDR
C1+
1
V+
2
C1-
3
C2+
C814 0.1uF
4
C2-
5
V-
6
DOUT2
7
RIN2
8
EAN41348201
VCC
16
GND
15
DOUT1
14
RIN1
13
ROUT1
12
DIN1
11
DIN2
10
ROUT2
9
R833
100
R834
ESD_COMMON
D813-*1
D813
30V
5.6V
ESD_CERADIODE
+3.5V_ST
D814
30V
ESD_COMMON
5.6V
D814-*1
R860
4.7K
OPT
IR_OUT
ESD_CERADIODE
R861
4.7K
OPT
R838 0
JP810
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
BCM35230
2010.10.21
8 COMMON JACK
58
Q901,Q902,Q903
Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
Q904,Q905,Q906
D903,D904
D905,D906
DUAL COMPONENT
1ST : 0TRIY80001A 2ND : 0TR387500AA
1ST : EAH42720601, 2ND : EAH60994401
IR & KEY
IR
Q901
2SC3052
+3.5V_ST
R903
47K
R902
0
+3.5V_ST
KEY1
KEY2
3.5V
3.3V
S/T_SCL
ST_SDA
GND
GND
IR
GND
GND
IR_15P
P901
12507WR-15L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
.
IR_12P
P902
12507WR-12L
1
2
3
4
5
6
7
8
9
10
11
12
13
EEPROM_SCL
EEPROM_SDA
LED_B/LOGO
LED_R/BUZZ
C911
100pF
50V
R933
100
R934
100
R928 1.5K
D907
5.6V
AMOTECH
LED_R/BUZZ
D903
CDS3C05HDMI1
5.6V
D904
CDS3C05HDMI1
5.6V
D905
CDS3C05HDMI1
5.6V
D906
CDS3C05HDMI1
5.6V
R929
1.5K
LED_B/LG_LOGO
+3.3V_Normal
BLM18PG121SN1D
16V
EEPROM_SCL
EEPROM_SDA
L902
C913
0.1uF
ESD_ATSC
16V
R920
R919
10K
10K
1%
1%
R915
100
KEY1
R916
+3.5V_ST
R908
47K
COMMERCIAL_EU
Q903
2SC3052
COMMERCIAL_EU
WIRELESS
Q904
2SC3052
WIRELESS
+3.5V_ST
R909
3.3K
OPT
+3.5V_ST
R911
47K
C
B
E
COMMERCIAL_EU
COMMERCIAL_US
R910
0
+3.5V_ST
R912
47K
C
B
E
WIRELESS
R905
47K
R904
C
10K
B
E
OPT
Q902
2SC3052
C
B
E
COMMERCIAL
R906
COMMERCIAL
22
IR_OUT
WIRELESS
R907
WIRELESS
22
IR_PASS
KEY2
R913
10K
R914
10K
R917
COMMERCIAL
Q905
2SC3052
COMMERCIAL
R918
WIRELESS
Q906
2SC3052
WIRELESS
100
+3.5V_ST
47K
C
E
+3.5V_ST
47K
C
E
B
COMMERCIAL
B
WIRELESS
R921
47K
R922
47K
+3.5V_ST
C901
0.1uF
C902
0.1uF
OPT
BLM18PG121SN1D
16V
L901
S/T_SCL
S/T_SDA
C903
0.1uF
C904
0.1uF
D901
5.6V
AMOTECH
16V
OPT
Zener Diode is
close to wafer
C905
1000pF
50V
R935
100
R936
100
D902
5.6V
AMOTECH
ESD_ATSC
C912
0.1uF
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
BCM35230
IR/KEY
9
50
WIRELESS READY MODEL
Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
D1001,D1002
Q1001
Q1002
DUAL COMPONENT
1ST : EAH42720601 2ND : EAH60994401
1ST : EBK61012601, 2ND : 0TRDI80002A
1ST : EBK60752501, 2ND : EBK61011501
Wireless power
+24V
R1002
22K
WIRELESS
R1003
2.2K
WIRELESS
WIRELESS_PWR_EN
R1001
10K
WIRELESS
B
C1002
2.2uF
WIRELESS
Q1002
AO3407A
WIRELESS
C
Q1001
MMBT3904(NXP)
WIRELESS
E
JK1001
KJA-PH-3-0168
DETECT
INTERRUPT
GND_1
RESET
GND_2
I2C_SCL
I2C_SDA
GND_3
UART_RX
UART_TX
GND_4
GND_5
IR
WIRELESS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 GND_6
21
SHIELD
VCC(24V/20V/17V)_1
VCC(24V/20V/17V)_2
VCC(24V/20V/17V)_3
VCC(24V/20V/17V)_4
VCC(24V/20V/17V)_1
VCC(24V/20V/17V)_1
+3.3V_Normal
S
G
D
L1001
MLB-201209-0120P-N2
WIRELESS
C1004
10uF
35V
WIRELESS
WIRELESS_DET
WIRELESS_SCL
WIRELESS_SDA
IR_PASS
R1008
WIRELESS
R1007 1K
WIRELESS
D1001
CDS3C05HDMI1
WIRELESS
10K
5.6V
WIRELESS
D1002
5.6V
CDS3C05HDMI1
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Wireless I2C connection with I2C_1
Address : 0X20
WIRELESS_SCL
WIRELESS_SDA
R1005 33
WIRELESS
R1006 33
WIRELESS
SCL2_3.3V
SDA2_3.3V
BCM35230
10
50 WIRELESS
CVBS 1 PHONE JACK
Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
D1105
D1107
5.6V
5.6V
ZD1115
5.1V
ZD1116
5.1V
D1108
5.6V
R1110
JK1102
KJA-PH-1-0177
5 M5_GND
4 M4
3 M3_DETECT
1 M1
6 M6
COMPONENT 1 PHONE JACK
D1101
JK1101
KJA-PH-1-0177
5 M5_GND
4 M4
3 M3_DETECT
1 M1
6 M6
5.6V
ZD1117
5.1V
ZD1110
5.1V
ZD1111
5.1V
ZD1112
5.1V
ZD1113
5.1V
ZD1114
5.1V
R1109
75
1%
470K
R1111
470K
+3.3V_Normal
R1105
2.7K
R1106
75
1%
R1107
75
1%
R1108
75
1%
+3.3V_Normal
R1112
2.7K
C1106
47pF
50V
C1107
560pF
50V
C1108
560pF
50V
R1137
10
R1138
10
R1139
10
R1143
22
R1144
22
R1114
1K
C1102
47pF
50V
C1103
27pF
50V
C1104
27pF
50V
R1113
1K
R1136
10
L1110
CM2012FR10KT
L1111
CM2012FR27KT
L1112
CM2012FR27KT
FOR EMI
C1109
560pF
50V
C1110
560pF
50V
C1125
47pF
50V
C1126
27pF
50V
C1127
27pF
50V
COMP1_DET
COMP1_Y
COMP1_Pb
COMP1_Pr
AV1_CVBS_DET
AV1_CVBS_IN
AV1_L_IN
AV1_R_IN
JACK_PACK
JK1105
PPJ238-01
[RD1]E-LUG
6C
[RD1]O-SPRING
5C
[RD1]CONTACT
4C
[WH1]O-SPRING
5B
[YL1]CONTACT
4A
[YL1]O-SPRING
5A
[YL1]E-LUG
6A
[RD2]E-LUG
6H
[RD2]O-SPRING_2
5H
[RD2]CONTACT
4H
[WH2]O-SPRING
5G
[RD2]O-SPRING_1
5F
[RD2]E-LUG-S
7F
[BL2]O-SPRING
5E
[BL2]E-LUG-S
7E
[GN2]CONTACT
4D
[GN2]O-SPRING
5D
[GN2]E-LUG
6D
CVBS2 REAR JACK
JK1104
PPJ233-01
AV2_JACK
[RD]E-LUG
5C
[RD]O-SPRING
4C
[RD]CONTACT
3C
[WH]C-LUG
4B
[YL]CONTACT
3A
[YL]O-SPRING
4A
[YL]E-LUG
5A
COMP2 REAR JACK
COMP2
COMP2
COMP2
COMP2
COMP2
COMP2
ZD1103
5.1V
ZD1104
5.1V
ZD1105
5.1V
ZD1106
5.1V
ZD1107
5.1V
ZD1108
5.1V
AV2
R1141
22
D1109
AMOTECH
5.6V
AV2
D1110
AMOTECH
5.6V
AV2
ZD1101
AV2
5.1V
ZD1102
AV2
5.1V
D1111
AV2
5.6V
COMP2
R1119
0
COMP2
R1124
75
COMP2
R1120
0
COMP2
R1125
75
COMP2
R1121
0
COMP2
R1126
75
D1112
5.6V
COMP2
D1113
5.6V
COMP2
COMP2
D1114
5.6V
AV2
10
10
10
AV2
AV2
COMP2
COMP2
COMP2
R1116
470K
R1117
470K
R1118
75
R1133
R1134
R1135
+3.3V_Normal
+3.3V_Normal
R1128
2.7K
AV2
COMP2
R1122
470K
COMP2
R1123
470K
COMP2_Pr
COMP2_Pb
COMP2_Y
COMP2
R1127
2.7K
C1118
560pF
50V
AV2
C1119
560pF
50V
AV2
C1120
47pF
50V
AV2
BLM18PG121SN1D
C1113
560pF
50V
COMP2
BLM18PG121SN1D
COMP2
C1114
560pF
50V
COMP2_Pr
COMP2_Pb
COMP2_Y
COMP2
COMP2
COMP2
COMP_NON_EU
R1130 1K
R1142
22
R1129
1K
AV2
L1103
L1104
AV2
C1117-*1
47pF
50V
C1121
560pF
50V
COMP2
COMP2
C1122
560pF
50V
CM2012FR27KT
C1115
27pF
50V
CM2012FR27KT
C1116
27pF
50V
CM2012FR27KT
COMP_EU
C1117
27pF
50V
COMP_EU
L1109
L1108
L1107
FOR EMI
C1123
560pF
50V
AV2
C1124
560pF
50V
AV2
COMP2
R1131
22
COMP2
R1132
22
AV2
R1140
10
SC/COMP2_R_IN
SC/COMP2_L_IN
SC_R/COMP2_Pr
C1128
27pF
50V
SC_B/COMP2_Pb
C1129
27pF
50V
L1107-*1
CM2012FR10KT
COMP_NON_EU
SC_G/COMP2_Y
COMP_NON_EU
C1130
27pF
50V
COMP_EU
SC_DET/COMP2_DET
C1130-*1
47pF
50V
AV2_R_IN
AV2_L_IN
AV2_CVBS_IN
AV2_CVBS_DET
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
BCM35230
COMP/AV 11
50
USB_WIFI
Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
+3.3V_Normal
WIFI_DM
WIFI_DP
L1203
BLM18PG121SN1D
WIFI
+5V_USB
+3.3V_USB
L1202
MLB-201209-0120P-N2
C1234
WIFI
0.1uF
16V
For EMI
Close to BCM IC
R1232 0
WIFI
R1233 0
WIFI
CDS3C05HDMI1
WIFI
WIFI120-ohm
WIFI
D1201
5.6V
WIFI_ESD
WIFI
C1209
1uF
10V
WIFI
C1210
0.1uF
R1204
12K
1/16W 1%
WIFI
C1211
15pF
WIFI
R1205
1M
WIFI
X1201
24MHz
C1233
0.1uF
16V
WIFI
CDS3C05HDMI1
SIDE_USB_DP
WIFI
C1213
15pF
1%
C1232
100uF
16V
D1202
5.6V
WIFI_ESD
SIDE_USB_DM
R1206
WIFI
100K
VDD
DM
DP
GND
P1201
12507WR-04L
WIFI
1
2
3
4
5
.
+3.3V_USB
DUAL COMPONENT
D1201,D1202
D1203,D1204
D1205,D1206
1ST : EAH42720601 2ND : EAH60994401
USB / DVR Ready
L1205
MLB-201209-0120P-N2
120-ohm
C1220
C1231
10uF
100uF
10V
3AU04S-305-ZC-(LG)
JK1201
1 2 3 4
USB DO WN STREAM USB DO WN STREAM
5
16V
OPT
D1207
RCLAMP0502BA
D1203
CDS3C05HDMI1
5.6V
IC1204
NC
OUT_2
OUT_1
FLG
AP2191DSG
1
8
2
7
3
6
4
5
EAN61849601
D1205
CDS3C05HDMI1
5.6V
GND
IN_1
IN_2
EN
+3.3V_Normal
R1221
4.7K
OPT
USB_CTL1
R1230 0
R1231 0
NON_WIFI
R1224 0
R1225 0
NON_WIFI
NON_WIFI
NON_WIFI
R1223
2.7K
+5V_USB
C1224
0.1uF
/USB_OCD1
SIDE_USB_CTL1
SIDE_USB_OCD1
USB_DM1
USB_DP1
SIDE_USB_DM
SIDE_USB_DP
SUSP_IND/LOCAL_PWR/NON_REM[0]
VDDA33_3
USBDM_UP
USBDP_UP
XTALOUT
XTALIN/CLKIN
PLLFILT
RBIAS
VDD33_3
+3.3V_USB
C1204
1uF
10V
WIFI
C1205
0.1uF
WIFI
USB_DM1
USB_DP1
USB_DM2
USB_DP2
C1206
0.1uF
WIFI
C1207
0.1uF
WIFI
C1208
0.1uF
WIFI
USBDM_DN[1]
USBDP_DN[1]
USBDM_DN[2]
USBDP_DN[2]
VDDA33_1
NC_1
NC_2
NC_3
NC_4
[EP]VSS
36
1
THERMAL
2
3
4
5
6
7
8
9
10
VDDA33_2
32
33
34
35
37
IC1202
USB2512B-AEZG
WIFI
11
12
13
14
TEST
CRFILT
OCS_N[1]
WIFI
PRTPWR[1]/BC_EN[1]
C1212
USB_CTL1
/USB_OCD1
29
30
31
15
16
17
VDD33_1
OCS_N[2]
C1214
0.1uF
PRTPWR[2]/BC_EN[2]
1uF
10V
WIFI
USB_CTL2
/USB_OCD2
28
VBUS_DET
27
RESET_N
26
HS_IND/CFG_SEL[1]
25
SCL/SMBCLK/CFG_SEL[0]
24
VDD33_2
23
SDA/SMBDATA/NON_REM[1]
22
NC_8
21
NC_7
20
NC_6
19
18
NC_5
WIFI
R1207
100K
WIFI
C1216
0.1uF
C1215
0.1uF
WIFI
WIFI
R1208
100K
R1212
100K
R1213
WIFI
100K
R1209
OPT
100K
OPT
R1215 100K
R1214 100K
R1216 100K
+3.3V_USB
C1218
0.1uF
OPT
WIFI
C1217
4.7uF
OPT
OPT
OPT
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
+3.3V_USB
/RST_HUB
USB
3AU04S-305-ZC-(LG)
JK1202
1 2 3 4
5
L1204
MLB-201209-0120P-N2
120-ohm
C1230
C1219
100uF
10uF
16V
10V
OPT
D1208
RCLAMP0502BA
BCM35230
USB + WIFI
IC1203
AP2191DSG
NC
8
OUT_2
7
OUT_1
6
FLG
5
EAN61849601
D1204
CDS3C05HDMI1
5.6V
+3.3V_Normal
GND
1
IN_1
2
IN_2
3
EN
4
D1206
CDS3C05HDMI1
5.6V
R1220
4.7K
OPT
USB_CTL2
R1228 0
R1229 0
R1226 0
R1227 0
NON_WIFI
NON_WIFI
NON_WIFI
NON_WIFI
R1222
2.7K
SIDE_USB_CTL2
SIDE_USB_OCD2
USB_DM2
USB_DP2
WIFI_DM
WIFI_DP
12
+5V_USB
C1223
0.1uF
/USB_OCD2
TI solution M_REMOTE OPTION
Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
P1302
12507WR-12L
M_REMOTE
13
.
+3.3V_Normal
L1303
120-ohm
R1315
100
R1319
100
M_REMOTE
M_REMOTE
R1316
100
M_REMOTE
R1317
100
M_REMOTE
R1318
100
3D_M_REMOTE
R1320
22
3D_M_REMOTE
R1324
22
3D_M_REMOTE
R1325
22
3D_M_REMOTE
R1326
22
M_REMOTE_RX
M_REMOTE_TX
3D_GPIO_0
3D_GPIO_1
3D_GPIO_2
3D_SYNC_RF
R1321
2.7K
M_REMOTE
3.3V
1
GND
2
3
4
5
6
7
8
9
10
11
12
RX
TX
RESET
DC
DD
GND
GPIO_0
GPIO_1
GPIO_2
3D_SYNC
M_REMOTE
M_REMOTE
+3.3V_Normal
R1322
2.7K
M_REMOTE
R1323
2.7K
M_REMOTE
M_RFModule_RESET
DC_MREMOTE
DD_MREMOTE
ALL M_REMOTE OPTION
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
BCM35230
13
50 M_REMOCON
Ethernet Block
Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
JK1401
XRJH-01A-4-DA7-180-LG(B)
P1[CT]
1
P2[TD+]
2
P3[TD-]
3
P4[RD+]
4
P5[RD-]
5
P6[CT]
6
P7
7
P8
8
P9
9
P10[GND]
10
P11
11
YL_C
D1
YL_A
D2
GN_C
D3
GN_A
D4
12
SHIELD
R1401 240
R1402
+2.5V_BCM35230
+3.3V_Normal
240
L1401
MLB-201209-0120P-N2
C1401
0.1uF
16V
D1401
5.5V
LAN_ESD
D1405
D1403
5V
5V
LAN_ESD
LAN_ESD
D1402
5.5V
LAN_ESD
D1404
5.5V
LAN_ESD
D1401,D1402
D1403,D1404
D1405,D1406
D1406
5.5V
LAN_ESD
EPHY_ACTIVITY
EPHY_LINK
DUAL COMPONENT
1ST : EAH42720601 2ND : EAH60994401
EPHY_TDP
EPHY_TDN
EPHY_RDP
EPHY_RDN
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
BCM35230
14 ETHERNET
50
FHD120Hz LVDS output(51pin+41Pin)
Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
P1501
FI-RE51S-HFK-A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
R1504 33
R1506 33
R1507 33
R1508 33
R1516 33
FRC2
FRC2
FRC2
FRC2
OPT
C1501
10uF
25V
OPT
PANEL_VCC
C1502
1000pF
50V
3D_SYNC_RF
SDA2_3.3V
SCL2_3.3V
FRC_RESET
PANEL_CTL
TXA0N
TXA0P
TXA1N
TXA1P
TXA2N
TXA2P
TXACLKN
TXACLKP
TXA3N
TXA3P
TXA4N
TXA4P
TXB0N
TXB0P
TXB1N
TXB1P
TXB2N
TXB2P
TXBCLKN
TXBCLKP
TXB3N
TXB3P
TXB4N
TXB4P
L1501
MLB-201209-0120P-N2
NON_SHARP_60INCH
C1503
0.1uF
16V
LVDS_SEL
+3.3V_Normal
R1513
3.3K
LVDS_SEL_HIGH
R1514
10K
LVDS_SEL_LOW
BIT_SEL
R1512
10K
BIT_SEL_LOW
P1502
FI-RE41S-HFK-A
LVDS_41P
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
1
2
3
4
5
6
7
8
9
TXC0N
TXC0P
TXC1N
TXC1P
TXC2N
TXC2P
TXCCLKN
TXCCLKP
TXC3N
TXC3P
TXC4N
TXC4P
TXD0N
TXD0P
TXD1N
TXD1P
TXD2N
TXD2P
TXDCLKN
TXDCLKP
TXD3N
TXD3P
TXD4N
TXD4P
REVERSE MARK
LVDS_41P
C1504
2.2uF
50V
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
BCM35230
2010.11.03
50 15 LVDS