lenovo YOGA 3 Schematic

A

1 1

B

C

D

E

2 2

YOGA3-BDW M/B Schematics Document

INTEL Broadwell Mobile ULT Platform
INTEL BDW U-series CPU + DDR3L DIMM+ NV N16S-GT

2014-04-28

REV:1.0

3 3

4 4

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2014/01/11

2014/01/11

2014/01/11

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2013/11/08

2013/11/08

2013/11/08

Title

Cover Page

Cover Page

Cover Page

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Haydn

Haydn

Haydn

Monday, November 17, 2014

Monday, November 17, 2014

Monday, November 17, 2014

1 45

1 45

E

1 45

1.0

1.0

1.0

5

4

3

2

1

D D

VRAM DDR3L
1~2G 4psc

SINGLE

N15S/N16S-GT

Page 15-23

Micro HDMI Conn.

Page 25

eDP Conn.

SATA/SSHD

C C

SPK Conn.

(1W x 2)

Int. MIC Conn.

PCIe Mini Card
WIFI with BT support,

Codec CX20752

Page 24

Page 32

Page 30

HP&Mic Combo Conn.

iphone type

G-Sensor
BMA222E

B B

E-compass
G-sensor
BMC150

ALS
AL3010

Sensor Board

32.768KHz

Page 7

24MHz

Page 8

PCIE-Port5
GEN2

DDI-Port1

eDP-Port[0:1]

Intel CPU
Broadwell-U SDP 15W

SATA Gen3 Port 1

PCIe Port3

USB 2.0-Port4

HD Audio

I2C

Touch Pad Int.KBD LID

Page 31 Page 30

40x24x1.38 BGA

BGA 1168

Page 4~13

LPC BUS

EC
ITE IT8386 128VFBGA

LID PAD

USB 2.0 1x

USB 2.0 Port 5

Page 29

Memory BUS-ChannelB

1.35V DDR3L 1333/1600 MT/s

USB 2.0-Port0

USB 2.0-Port1

USB 3.0-Port2

USB 2.0-Port2

USB 3.0-Port1

USB 2.0-Port3

USB 2.0-Port6

USB 2.0-Port7

SPI BUS

32.768KHz

Page 29

Int. Camera

USB 3.0/2.0 Right

USB 3.0/2.0 Left

IO/CONN

Touch Screen

DC_IN Combo USB port

USB 2.0 Port 7

SPI ROM

(8MB)

Battery

SMBUS

Thermal Sensor
NCT7718W

USB Board

SO-DIMM DDR3L

UP TO 8G

Page 24

Page 32

Cardreader
Realtek RTS5170

Page 24

Page 7

Page 37

Page 31

Page 14

SD/MMC Conn.

Yoga3 BDW Refresh Block diagram

Sub-board

DMIC SUB

Sensor SUB

A A

USB SUB

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2014/01/11

2014/01/11

2014/01/11

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/11/08

2013/11/08

2013/11/08

Title

Block Diagram

Block Diagram

Block Diagram

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Haydn

Haydn

Haydn

Monday, November 17, 2014

Monday, November 17, 2014

Monday, November 17, 2014

2 45

2 45

1

2 45

1.0

1.0

1.0

5

4

3

2

1

PGOOD

PGOOD

+5VLP/ 100mA

+5VALW/5A

+3VLP/ 100mA

+3VALW/ 5A

+1.35V/8A

+0.68V/1A

+1.05VS/6A

CPU_CORE / 14A

+VGA_CORE/31A

+3VALW

ANPEC

APL5930KAI-TRG

EN

LDO

PAGE 42

+1.5VS/100mA

Silergy

D D

AC Adapter

20V/40W/65W

SYX196C1QNC

Converter

FOR SYSTEM

EN PGOOD

Silergy

SYX196BQNC

Converter

FOR SYSTEM

EN PGOOD

Silergy

TPS51716RUKR

Converter

FOR DDR3L

C C

Battery Charger

SMBus

TI

BQ24715RGRR

Switch Mode

IO Board / Page7

B+

EN PGOOD

PAGE 40

Silergy

SYX198DQNC

Converter

FOR CPU/PCH

EN

PAGE 41

Onsemi

NCP81108MNTXG

Switch Mode

FOR CPU IMVP7

Battery

Li-ion

B B

2S2P /46WH

EN PGOOD

PAGE 43

Onsemi

NCP81172MNTWG

VIDs

Switch Mode

EN

FOR GPU VDDC

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2014/01/11

2014/01/11

2014/01/11

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/11/08

2013/11/08

2013/11/08

Title

PWR_BLOCK DIAGRAM

PWR_BLOCK DIAGRAM

PWR_BLOCK DIAGRAM

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Yoga3-BDW

Yoga3-BDW

Yoga3-BDW

Monday, November 17, 2014

Monday, November 17, 2014

Monday, November 17, 2014

36 45

36 45

1

36 45

1.0

1.0

1.0

A

Voltage Rails

, X --> Means OFF )( O --> Means ON

Power Plane

B+

+3VL

+3VALW

State

1 1

+5VLP

+5VALW

+3VALW_PCH

+1.35V

B

+5VS

+3VS

+1.5VS

+1.05VS

+0.68VS

+CPU_CORE

+1.35V_CPU

C

BOM Structure Table

BOM Structure

DA8@

UMA@ UMA SKU part

DEBUG@ DEBUG CARD Part

ME@ ME part(connector, hole)

RF@

EMC@

CD@ COST DOWN Part

REV@ RESERVER Part

PCB

RF request

EMC request

BOM Structure

MIRROR@ EC Mirror-code enable

OPT@ Discrete GPU SKU part

N15SGT@ For N15S-GT GPU part

GC6@ GC62.0 support part

RANKA@ For VRAM RankA part

EC Mirror-code disableableUNMIRROR@

D

Board ID Table

DescriptionBoard ID

E

PCB Revision

S0

S3

DS3

S5 S4/AC Only

S5 S4
Battery only

S5 S4
AC & Battery

2 2

don't exist

STATE SLP_S3#SLP_S1#

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

DS3 (Suspend to RAM) ON OFF OFFLOW LOW HIGH LOW

S4 (Suspend to Disk) ON

S5 (Soft OFF)

SIGNAL

O

O O X

O O X X

O

LOW

LOW HIGH

LOW

LOW LOW

O O O

O

O

O

OO O X

X

O

X

XX

HIGH HIGH

LOW

LOW LOW

X

SLP_S4# +VS+V

+VALW

HIGHHIGHHIGH

ON

ON

ON

ON

ON

LOW OFF

ON

XX

X

+VALW_PCH

ONONON

ONONON

ON

OFF

X

X

Clock

ONON

ON

LOW

OFF OFF

OFF

OFF

OFF

OFF

O

O

BOM Configuration Table

SKU Description BOM Config

SKU1

X

SKU2

X

X

X

X76&VGA Configuration Table

SKU Description BOM Config

SMBUS Control Table

Thermal

GPU

X

X

X

V

X

V

+3VS

X

USB Port Table

0

EXHCI/XHCI

1
2
3
4
5
6
7

PCH

Sensor

X

X

X

X

V

V

+3VALW_PCH

+3VS

X

X

USB20 USB30

CAMERA

Right USB

Left USB

CARD READER

BT

Sensor

TOUCH PANEL

DC_IN combo USB2.0

B

1
2
3
4

charger

Left USB

Right USB

X

X

V

X

X

PCB And LOGO Config

X

PCB

ZZZ1

ZZZ3

DA8@

PCB 0YC NM-A381 REV0 M/B

I7@ ZZZ2

I5@ ZZZ9

LOGO

I3@

ZZZ4

HDMI@ ZZZ5

USB30@

CPU

BDW U2+2 Ci7

ZZZ6

HY2G@ ZZZ7

BDW U2+2 Ci5

MIC2G@ ZZZ8

BDW 2+2U 1.6G 1333 ES2

SAM2G@

HDMI LOGO

USB30 LOGO

VRAM

HYNIX 2G

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

MICRON 2G

2014/01/11

2014/01/11

2014/01/11

SAMSUNG 2G

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2013/11/08

2013/11/08

2013/11/08

Title

Title

Title

Notes List

Notes List

Notes List

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Haydn

Haydn

Haydn

Monday, November 17, 2014

Monday, November 17, 2014

Monday, November 17, 2014

3 45

3 45

E

3 45

1.0

1.0

1.0

+3VLP

touch sensor

V

X

X

X

SODIMMBATTALS

X

X X

X

X

DevicePort

X

X

WLAN

X

GPU

Sensor

SOURCE

3 3

EC_SMB_CLK1

EC_SMB_DAT1

EC_SMB_CLK3

EC_SMB_DAT3

EC_SMB_CLK0

EC_SMB_DAT0 +3VS

SMB_DATA

SM Bus address

Battery

EC1

Charger

4 4

Sensor

EC3

ALS

Thermal Sensor

EC0

PCH THM

TP

PCH

Device

IT8386

+3VALW_EC

IT8386

+3VS

IT8386

PCHSMB_CLK

+3VALW_PCH

address

0001 011X b

1001_100xb

X

X

V

V

+3VS

+3VS

X

X

X

X

PCIE PORT LIST

1
2
3
4
5

A

Haswell MCP (DDI,EDP)

5

4

3

2

+3VS

PCIECLKREQ5#

1

PCIECLKREQ5# 8

D D

@

UC1A

PCH_HDMI_TX2-25
PCH_HDMI_TX2+25
PCH_HDMI_TX1-25
PCH_HDMI_TX1+25
PCH_HDMI_TX0-25
PCH_HDMI_TX0+25
PCH_HDMI_CLK-25
PCH_HDMI_CLK+25

C C

B B

PCH_BKLT_CTRL24
PCH_BKLT_EN24,29
PCH_LCD_VDDEN24

GC6_FB_EN16
PXS_PWREN18
PCH_GPU_RST#16
PCH_GPU_EVENT#16

PCH_BKLT_CTRL
PCH_BKLT_EN
PCH_LCD_VDDEN

PCI_PIRQD#8

GC6_FB_EN
PXS_PWREN
PCH_GPU_RST#
PCH_GPU_EVENT#

Connect to GPU signal :
GC6_FB_EN
PCH_GPU_EVENT#
PCH_GPU_RST#
PCH_PLT_RST#
PXS_PWREN

TP4 @

1 2

RC39 1K_0402_5%OPT@

1 2

RC40 0_0402_5%OPT@

1

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

GPIO55

PXS_PWREN_R
PCH_GPU_RST#_R

C54

DDI1_TXN0

C55

DDI1_TXP0

B58

DDI1_TXN1

C58

DDI1_TXP1

B55

DDI1_TXN2

A55

DDI1_TXP2

A57

DDI1_TXN3

B57

DDI1_TXP3

C51

DDI2_TXN0

C50

DDI2_TXP0

C53

DDI2_TXN1

B54

DDI2_TXP1

C49

DDI2_TXN2

B50

DDI2_TXP2

A53

DDI2_TXN3

B53

DDI2_TXP3

HASWELL-ULT-DDR3L_BGA1168

UC1I

@

B8

EDP_BKLCTL

A9

EDP_BKLEN

C6

EDP_VDDEN

U6

PIRQA/GPIO77

P4

PIRQB/GPIO78

N4

PIRQC/GPIO79

N2

PIRQD/GPIO80

AD4

PME

U7

GPIO55

L1

GPIO52

L3

GPIO54

R5

GPIO51

L4

GPIO53

HASWELL-ULT-DDR3L_BGA1168

eDP SIDEBAND

PCIE

HSW_ULT_DDR3L

1 OF 19

HSW_ULT_DDR3L

9 OF 19

EDPDDI

DISPLAY

EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1

EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3

EDP_AUXN
EDP_AUXP

EDP_RCOMP

EDP_DISP_UTIL

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP

DDPB_HPD
DDPC_HPD

EDP_HPD

C45
B46
A47
B47

C47
C46
A49
B49

A45
B45

D20
A43

B9
C9
D9
D11

C5
B6
B5
A6

C8
A8
D6

EDP_COMP

PCH_EDP_TX0- 24
PCH_EDP_TX0+ 24
PCH_EDP_TX1- 24
PCH_EDP_TX1+ 24

PCH_EDP_AUX- 24
PCH_EDP_AUX+ 24

1 2

1

TP1 @

PCH_HDMI_DDC_CLK 25
PCH_HDMI_DDC_DAT 25

PCH_HDMI_HPD 25

PCH_EDP_HPD 24

RC5 24.9_0402_1%

+VCCIOA_OUT

EDP_COMP:

Trace Width:25mil
Space:25mil
Max length:100mil

RC41

1 2

10K_0402_5%

RPC2

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

1 2

UMA@

RC1 10K_0402_5%

1 2

RC2 10K_0402_5%

1 2

RC3 10K_0402_5%

1 2

@

RC4 10K_0402_5%

1 2

RC6 100K_0402_5%

1 2

RC7 100K_0402_5%

1 2

@

RC8 10K_0402_5%

1 2

RC9 100K_0402_5%

1 2

@

RC10 100K_0402_5%

1 2

@

RC11 10K_0402_5%

Port

DDI PROCESSOR Pin Names

Port 1

DDI1_TXN[0]
DDI1_TXP[0]
DDI1_TXN[1]
DDI1_TXP[1]
DDI1_TXN[2]
DDI1_TXP[2]
DDI1_TXN[3]
DDI1_TXP[3]
DDPB_HPD
DDPB_CTRLCLK
DDPB_CTRLDATA

DisplayPort* Disabling and Termination

Pin Name Recommendation
DDPC_AUXP No Connect
DDPC_AUXN No Connect
DDPC_HPD No Connect
DDI2_TXP[3:0] No Connect
DDI2_TXN[3:0] No Connect
DDPC_CTRLCLK No Connect
DDPC_CTRLDATA No Connect

GPIO55

PCI_PIRQA#
PCIECLKREQ5#
PCI_PIRQB#
PCI_PIRQC#

GC6_FB_EN

PCH_GPU_EVENT#

PXS_PWREN_R

PCH_GPU_RST#_R

PCH_BKLT_EN

PCH_LCD_VDDEN

GC6_FB_EN

PCH_GPU_RST#_R

PXS_PWREN_R

PCH_GPU_EVENT#

HDMI* Mapping
HDMIxC_TX2_DN
HDMIxC_TX2_DP
HDMIxC_TX1_DN
HDMIxC_TX1_DP
HDMIxC_TX0_DN
HDMIxC_TX0_DP
HDMIxC_CLK_DN
HDMIxC_CLK_DP
DDI1_HPD_Q
DDI1_CTRL_CK
DDI1_CTRL_DATA

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2014/01/11

2014/01/11

2014/01/11

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/11/08

2013/11/08

2013/11/08

Title

MCP (DDI,EDP)

MCP (DDI,EDP)

MCP (DDI,EDP)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Haydn

Haydn

Haydn

Monday, November 17, 2014

Monday, November 17, 2014

Monday, November 17, 2014

4 45

4 45

1

4 45

1.0

1.0

1.0

5

4

3

2

1

UC1B

+1.35V

D61

PROC_DETECT

K61

CATERR

N62

PECI

K63

PROCHOT

C61

PROCPWRGD

AU60

SM_RCOMP0

AV60

SM_RCOMP1

AU61

SM_RCOMP2

AV15

SM_DRAMRST

AV61

SM_PG_CNTL1

HASWELL-ULT-DDR3L_BGA1168

@

1 2

RC45

1K_0402_5%

SM_PG_CNTL1

2

B

1

TP2 @

1

TP3 @

D D

CPU_PROCHOT#29,37

DDRA_DRAMRST#14

C C

B B

1

2

1 2

RD55
0_0402_5%

CC14

.1U_0402_10V6-K

CPU_PROCHOT#

+1.35V_CPU

RC15

470_0402_5%

1 2

CPU_PECI_R29

1 2

RC13
56_0402_5%

RC14
10K_0402_5%

RC20 200_0402_1%
RC21 121_0402_1%
RC22 100_0402_1%

TP_SKTOCC#

CPU_PECI_R

CPU_PROCHOT#_R

12

CPU_PROCPWRGD

12

SM_RCOMP_0

12

SM_RCOMP_1

12

SM_RCOMP_2
DDRA_DRAMRST#_R
SM_PG_CNTL1

CATERR#

HSW_ULT_DDR3L

MISC

THERMAL

PWR

DDR3L

+3VALW

12

RC42
100K_0402_5%

C

QC14

E

3 1

MMBT3904WH_SOT323-3

PROC_TCK

JTAG

2 OF 19

PROC_TMS

PROC_TRST

PROC_TDI

PROC_TDO

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7

CPU_DRAMPG_CNTL 14,39

PRDY
PREQ

J62
K62
E60
E61
E59
F63
F62

J60
H60
H61
H62
K59
H63
K60
J61

RC43

10K_0402_5%

@

1 2

VR OD Output
Place CC9 Close to EC Side
RC23 Close to MCP
for Defensive Design

CPU_PROCHOT#

A A

5

+1.05VS

12

RC23
62_0402_1%

1

CC9

47P_0402_50V8J

2

CPU_PROCHOT#

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

2014/01/11

2014/01/11

2014/01/11

3

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2013/11/08

2013/11/08

2013/11/08

2

Title

MCP (MISC,THERMAL,JATG)

MCP (MISC,THERMAL,JATG)

MCP (MISC,THERMAL,JATG)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Monday, November 17, 2014

Monday, November 17, 2014

Date: Sheet of

Date: Sheet of

Date: Sheet of

Monday, November 17, 2014

Haydn

Haydn

Haydn

1

5 45

5 45

5 45

1.0

1.0

1.0

5

4

3

2

1

BDW-U

D D

DDRA_DQ0
DDRA_DQ1
DDRA_DQ2
DDRA_DQ3
DDRA_DQ4
DDRA_DQ5
DDRA_DQ6
DDRA_DQ7
DDRA_DQ8
DDRA_DQ9
DDRA_DQ10
DDRA_DQ11
DDRA_DQ12
DDRA_DQ13
DDRA_DQ14
DDRA_DQ15

DDRA_DQ16

C C

B B

DDRA_DQ17
DDRA_DQ18
DDRA_DQ19
DDRA_DQ20
DDRA_DQ21
DDRA_DQ22
DDRA_DQ23
DDRA_DQ24
DDRA_DQ25
DDRA_DQ26
DDRA_DQ27
DDRA_DQ28
DDRA_DQ29
DDRA_DQ30
DDRA_DQ31

UC1C

AH63

SA_DQ0

AH62

SA_DQ1

AK63

SA_DQ2

AK62

SA_DQ3

AH61

SA_DQ4

AH60

SA_DQ5

AK61

SA_DQ6

AK60

SA_DQ7

AM63

SA_DQ8

AM62

SA_DQ9

AP63

SA_DQ10

AP62

SA_DQ11

AM61

SA_DQ12

AM60

SA_DQ13

AP61

SA_DQ14

AP60

SA_DQ15

AP58

SA_DQ16

AR58

SA_DQ17

AM57

SA_DQ18

AK57

SA_DQ19

AL58

SA_DQ20

AK58

SA_DQ21

AR57

SA_DQ22

AN57

SA_DQ23

AP55

SA_DQ24

AR55

SA_DQ25

AM54

SA_DQ26

AK54

SA_DQ27

AL55

SA_DQ28

AK55

SA_DQ29

AR54

SA_DQ30

AN54

SA_DQ31

AY58

SA_DQ32

AW58

SA_DQ33

AY56

SA_DQ34

AW56

SA_DQ35

AV58

SA_DQ36

AU58

SA_DQ37

AV56

SA_DQ38

AU56

SA_DQ39

AY54

SA_DQ40

AW54

SA_DQ41

AY52

SA_DQ42

AW52

SA_DQ43

AV54

SA_DQ44

AU54

SA_DQ45

AV52

SA_DQ46

AU52

SA_DQ47

AK40

SA_DQ48

AK42

SA_DQ49

AM43

SA_DQ50

AM45

SA_DQ51

AK45

SA_DQ52

AK43

SA_DQ53

AM40

SA_DQ54

AM42

SA_DQ55

AM46

SA_DQ56

AK46

SA_DQ57

AM49

SA_DQ58

AK49

SA_DQ59

AM48

SA_DQ60

AK48

SA_DQ61

AM51

SA_DQ62

AK51

SA_DQ63

HASWELL-ULT-DDR3L_BGA1168

@

󱫹

HSW_ULT_DDR3L

DDR CHANNEL A

so-dimm󰯇,

3 OF 19

󱱎󱱿󲒪󱱕󱜸󰤿󰰀

SA_CLK#0

SA_CLK0

SA_CLK#1

SA_CLK1

SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3

SA_CS#0
SA_CS#1

SA_ODT0

SA_RAS

SA_WE

SA_CAS

SA_BA0
SA_BA1
SA_BA2

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8

SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15

SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7

SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7

SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1

AU37
AV37
AW36
AY36

AU43
AW43
AY42
AY43

AP33
AR32

AP32

AY34
AW34
AU34

AU35
AV35
AY41

AU36

DDRA_MA0

AY37

DDRA_MA1

AR38

DDRA_MA2

AP36

DDRA_MA3

AU39

DDRA_MA4

AR36

DDRA_MA5

AV40

DDRA_MA6

AW39

DDRA_MA7

AY39

DDRA_MA8

AU40

DDRA_MA9

AP35

DDRA_MA10

AW41

DDRA_MA11

AU41

DDRA_MA12

AR35

DDRA_MA13

AV42

DDRA_MA14

AU42

DDRA_MA15

AJ61

DDRA_DQS#0

AN62

DDRA_DQS#1

AM58
AM55
AV57

DDRA_DQS#2

AV53

DDRA_DQS#3

AL43
AL48

AJ62

DDRA_DQS0

AN61

DDRA_DQS1

AN58
AN55
AW57

DDRA_DQS2

AW53

DDRA_DQS3

AL42
AL49

AP49
AR51
AP51

SMVREF

WIDTH:20MIL
SPACING: 20MIL

1
1

1

TP19@
TP20@

TP21@

1

@

DDRA_CLK0# 14
DDRA_CLK0 14
DDRA_CLK1# 14
DDRA_CLK1 14

DDRA_CKE0 14
DDRA_CKE1 14

DDRA_CS0# 14
DDRA_CS1# 14

DDRA_RAS# 14

DDRA_WE# 14

DDRA_CAS# 14

DDRA_BS0# 14
DDRA_BS1# 14
DDRA_BS2# 14

DDR_SM_VREFCA 14
DDR_SA_VREFDQ 14

TP22

interleaved,

DDRA_DQ[63:0] 14

DDRA_MA[15:0] 14

DDRA_DQS[7:0] 14

DDRA_DQS#[7:0] 14

DDRA_DQ32
DDRA_DQ33
DDRA_DQ34
DDRA_DQ35
DDRA_DQ36
DDRA_DQ37
DDRA_DQ38
DDRA_DQ39
DDRA_DQ40
DDRA_DQ41
DDRA_DQ42
DDRA_DQ43
DDRA_DQ44
DDRA_DQ45
DDRA_DQ46
DDRA_DQ47

DDRA_DQ48
DDRA_DQ49
DDRA_DQ50
DDRA_DQ51
DDRA_DQ52
DDRA_DQ53
DDRA_DQ54
DDRA_DQ55
DDRA_DQ56
DDRA_DQ57
DDRA_DQ58
DDRA_DQ59
DDRA_DQ60
DDRA_DQ61
DDRA_DQ62
DDRA_DQ63

UC1D

AY31

SB_DQ0

AW31

SB_DQ1

AY29

SB_DQ2

AW29

SB_DQ3

AV31

SB_DQ4

AU31

SB_DQ5

AV29

SB_DQ6

AU29

SB_DQ7

AY27

SB_DQ8

AW27

SB_DQ9

AY25

SB_DQ10

AW25

SB_DQ11

AV27

SB_DQ12

AU27

SB_DQ13

AV25

SB_DQ14

AU25

SB_DQ15

AM29

SB_DQ16

AK29

SB_DQ17

AL28

SB_DQ18

AK28

SB_DQ19

AR29

SB_DQ20

AN29

SB_DQ21

AR28

SB_DQ22

AP28

SB_DQ23

AN26

SB_DQ24

AR26

SB_DQ25

AR25

SB_DQ26

AP25

SB_DQ27

AK26

SB_DQ28

AM26

SB_DQ29

AK25

SB_DQ30

AL25

SB_DQ31

AY23

SB_DQ32

AW23

SB_DQ33

AY21

SB_DQ34

AW21

SB_DQ35

AV23

SB_DQ36

AU23

SB_DQ37

AV21

SB_DQ38

AU21

SB_DQ39

AY19

SB_DQ40

AW19

SB_DQ41

AY17

SB_DQ42

AW17

SB_DQ43

AV19

SB_DQ44

AU19

SB_DQ45

AV17

SB_DQ46

AU17

SB_DQ47

AR21

SB_DQ48

AR22

SB_DQ49

AL21

SB_DQ50

AM22

SB_DQ51

AN22

SB_DQ52

AP21

SB_DQ53

AK21

SB_DQ54

AK22

SB_DQ55

AN20

SB_DQ56

AR20

SB_DQ57

AK18

SB_DQ58

AL18

SB_DQ59

AK20

SB_DQ60

AM20

SB_DQ61

AR18

SB_DQ62

AP18

SB_DQ63

HASWELL-ULT-DDR3L_BGA1168

@

HSW_ULT_DDR3L

4 OF 19

DDR CHANNEL B

SB_CK#0

SB_CK0

SB_CK#1

SB_CK1

SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3

SB_CS#0
SB_CS#1

SB_ODT0

SB_RAS

SB_WE

SB_CAS

SB_BA0
SB_BA1
SB_BA2

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8

SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15

SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7

SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7

AM38
AN38
AK38
AL38

AY49
AU50
AW49
AV50

AM32
AK32

AL32

AM35
AK35
AM33

AL35
AM36
AU49

AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46

AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18

AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18

DDRA_DQS#4
DDRA_DQS#5

DDRA_DQS#6
DDRA_DQS#7

DDRA_DQS4
DDRA_DQS5

DDRA_DQS6
DDRA_DQS7

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2014/01/11

2014/01/11

2014/01/11

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/11/08

2013/11/08

2013/11/08

Title

MCP (DDR3L)

MCP (DDR3L)

MCP (DDR3L)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Haydn

Haydn

Haydn

Monday, November 17, 2014

Monday, November 17, 2014

Monday, November 17, 2014

6 45

6 45

1

6 45

1.0

1.0

1.0

5

VCCRTC

1 2

RC24 20K_0402_1%

1 2

RC25 20K_0402_1%

JCMOS1

Place under RAM Door

D D

RTCRST#&SRTCRST#

Space 15Mil

VCCRTC

12

RC29 1M_0402_5%

12

RC32 330K_0402_5%

INTVRMEN

* PU to VccRTC via 330 k, Internal VRM EN
PD to GND via 330 k,Internal VRM Disable

12

RC36 10M_0402_5%

YC1

C C

CRYSTAL

1,Space 15MIL
2,No trace under crystal

B B

RTC COIN

RTC_VCC_R 20MIL
+3VL 20MIL
VCCRTC 20MIL
BAT_D 20MIL

+3VS

1 2

32.768KHZ_12.5PF_202740-PG14

1

CC7
15P_0402_50V8J

2

RTC_VCC_R

RC1491

1K_0402_5%

RTC_VCC

12

BAT_D

+3VL

1 2

J3

JUMP_43X39

@

SRTC_RST#

RTC_RST#

CC10

1U_0402_10V6K

CC11

1U_0402_10V6K

1

1

2

2

TP71 For clear CMOS.

SM_INTRUDER#

INTVRMEN

CC12

1U_0402_10V6K

1

@

2

2

CC8
18P_0402_50V8J

1

VCCRTC

DC1
RB751V-40_SOD323-2

DC37

12

RB751V-40_SOD323-2

2

112

1

TP71

@

RTC_X1

RTC_X2

CC17

1U_0402_10V6K

1

2

RTC_VCC_R

12

CC32

10P_0402_50V8J

PCH_HDA_BCLK27
PCH_HDA_SYNC27
PCH_HDA_RST#27
PCH_HDA_SDIN027

PCH_HDA_SDOUT27
PCH_ME_PROTECT29

PCH_SPI_CLK29
PCH_SPI_CS0#29

PCH_SPI_SI29

CC26

.1U_0402_10V6-K

2

1

PCH_SPI_SO29

@

RC26 33_0402_5%
RC27 33_0402_5%
RC28 33_0402_5%

RC30 33_0402_5%
RC31 0_0402_5%

PCH_SPI_CLK
PCH_SPI_CS0#

PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_WP#
PCH_SPI_HOLD#

4

RTC_RST#29

@

Place close to PCH.

1 2
1 2
1 2

1 2
1 2

LPC_AD029
LPC_AD129
LPC_AD229
LPC_AD329

LPC_FRAME#29

1 2

RC297 15_0402_5%

1 2

RC60 0_0402_5%

1 2

RC299 15_0402_5%

1 2

RC300 15_0402_5%

1 2

RC301 15_0402_5%@

1 2

RC302 15_0402_5%@

RTC_X1
RTC_X2
SM_INTRUDER#
INTVRMEN
SRTC_RST#
RTC_RST#

PCH_HDA_BCLK_R
PCH_HDA_SYNC_R
PCH_HDA_RST#_R

PCH_HDA_SDOUT_R

UC1E

AW5

RTCX1

AY5

RTCX2

AU6

INTRUDER

AV7

INTVRMEN

AV6

SRTCRST

AU7

RTCRST

AW8

HDA_BCLK/I2S0_SCLK

AV11

HDA_SYNC/I2S0_SFRM

AU8

HDA_RST/I2S_MCLK

AY10

HDA_SDI0/I2S0_RXD

AU12

HDA_SDI1/I2S1_RXD

AU11

HDA_SDO/I2S0_TXD

AW10

HDA_DOCK_EN/I2S1_TXD

AV10

HDA_DOCK_RST/I2S1_SFRM

AY8

I2S1_SCLK

AU62

PCH_TRST

AE62

PCH_TCK

AD61

PCH_TDI

AE61

PCH_TDO

AD62

PCH_TMS

AL11

RSVD1

AC4

RSVD2

AE63

JTAGX

AV2

RSVD0

HASWELL-ULT-DDR3L_BGA1168

@

PCH_SPI_CLK_R
PCH_SPI_CS0#_R

PCH_SPI_SI_R
PCH_SPI_SO_R
PCH_SPI_WP#_R
PCH_SPI_HOLD#_R

PCH_SPI_CS0#

PCH_SPI_SO

PCH_SPI_WP#

UC1G

AU14

LAD0

AW12

LAD1

AY12

LAD2

AW11

LAD3

AV12

LFRAME

AA3

SPI_CLK

Y7

SPI_CS0

Y4

SPI_CS1

AC2

SPI_CS2

AA2

SPI_MOSI

AA4

SPI_MISO

Y6

SPI_IO2

AF1

SPI_IO3

HASWELL-ULT-DDR3L_BGA1168

@

3

HSW_ULT_DDR3L

RTC

AUDIO SATA

JTAG

5 OF 19

HSW_ULT_DDR3L

LPC

SMBUS

C-LINKSPI

UC3

1

CS#

2

DO

3

WP#

4

GND

W25Q64FVSSIG_SO8

HOLD#

8

50mA

VCC

7

PCH_SPI_HOLD#

6

PCH_SPI_CLK

CLK

5

PCH_SPI_SI

DI

SATA_RN0/PERN6_L3

SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3

SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2

SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2

SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1

SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1

SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0

SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0

SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37

SATA_RCOMP

SMBALERT/GPIO11

SMBCLK

SMBDATA

SML0ALERT/GPIO60

SML0CLK

SML1ALERT/PCHHOT/GPIO73

SML0DATA

SML1CLK/GPIO75

SML1DATA/GPIO74

7 OF 19

2

.1U_0402_10V6-K

1

CL_CLK

CL_DATA

CL_RST

+3V_SPI

CC22

SATA_IREF

RSVD3
RSVD4

SATALED

AN2
AP2
AH1
AL2
AN1
AK1
AU4
AU3
AH3

AF2
AD2
AF4

J5
H5
B15
A15

J8
H8
A17
B17

J6
H6
B14
C15

F5
E5
C17
D17

V1

PCH_GPIO34

U1

SATA1GP

V6

SATA2GP

AC1

SATA3GP

A12
L11
K10
C12

SATACOMP

U3

SATALED#

SMB_ALERT#
PCH_SMB_CLK
PCH_SMB_DATA
SML0_ALERT#
SML0_CLK
SML0_DATA
SML1_ALERT#
PCH_SML1_CLK
PCH_SML1_DAT

RC33

3.01K_0402_1%

Space:12Mil
Length: 500Mil

1 2

@

RC35
10K_0402_5%

+3VALW_PCH

2

SATA_PRX_DTX_N1 32
SATA_PRX_DTX_P1 32
SATA_PTX_DRX_N1 32
SATA_PTX_DRX_P1 32

PCH_GPIO34 9

SATA1GP 9

+1.05VS_PSATA3PLL

12

IREF&RCOMPWidth: 12-15Mil

+3VS

SMB_ALERT# 9

SML0_ALERT# 9

SML1_ALERT# 9

MIRROR@

1 2

RC68 0_0402_5%

GPU_PCIE_CLKREQ#8,16

2N7002KDWH_SOT363-6

PCH_SMB_CLK

+3VS

PCH_SMB_DATA

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

PCH_SML1_CLK

+3VS

PCH_SML1_DAT

2N7002KDWH_SOT363-6

UNMIRROR@

1 2

RC69 0_0402_5%

QC2A

6 1

D

G

2

5

G

3 4

D

QC2B

QC5A

6 1

D

@

G

2

5

G

@

3 4

D

QC5B

1

14
23

14
23

14
23

+3VS

+3VALW_PCH

PCH_GPIO479
PCH_GPIO249
PCH_GPIO289

SATA2GP
SATA3GP

SML0_CLK
SML0_DATA

PCH_SMB_CLK
PCH_SMB_DATA

PCH_SML1_CLK
PCH_SML1_DAT

RPC3

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

RPC4

2.2K_0404_4P2R_5%
RPC5

2.2K_0404_4P2R_5%
RPC14

2.2K_0404_4P2R_5%

RPC7

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

SODIMM

S

S

S

S

+3VS+3V_SPI

PM_SMB_CLK 14,31

RPC18

14
23

2.2K_0404_4P2R_5%

PM_SMB_DAT 14,31

EC_SMB_CLK0 16,29,31

RPC26

14
23

2.2K_0404_4P2R_5%

EC_SMB_DAT0 16,29,31

+3VS

+3VS

1 2

@

RC1495 1K_0402_5%

PCH_ME_PROTECT

HDA_SDO This signal has a weak internal pull-down.
*L ME Protection Enable
H ME Protection Disable:

A A

can make ME flash be enable with ME locked
Must be PU with the same Power with HDA PWR, or
will make PWR leakage

EMI

1

CC1029
10P_0402_50V8J

2

EMC_NS@

PCH_HDA_SDOUT_R

PCH_HDA_SDIN0

5

+3V_SPI

1 2

RC37 1K_0402_5%

1 2

RC38 1K_0402_5%

4

PCH_SPI_WP#

PCH_SPI_HOLD#

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2014/01/11

2014/01/11

2014/01/11

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/11/08

2013/11/08

2013/11/08

Title

Title

Title

MCP (RTC&AUDIO&SATA&SMBUS)

MCP (RTC&AUDIO&SATA&SMBUS)

MCP (RTC&AUDIO&SATA&SMBUS)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Haydn

Haydn

Haydn

Monday, November 17, 2014

Monday, November 17, 2014

Monday, November 17, 2014

7 45

7 45

1

7 45

1.0

1.0

1.0

5

Haswell MCP (Clock,PM)

D D

PCH_ACIN

AO5804EL_SC89-6
QC11A

TP5 @

1 2
1 2
1 2

1 2

PCIECLKREQ0#

PCIECLKREQ1#

CLK_PCIE_WLAN#
CLK_PCIE_WLAN
WLAN_CLKREQ#

PCIECLKREQ3#

CLK_PCIE_GPU#
CLK_PCIE_GPU
GPU_PCIE_CLKREQ#

PCIECLKREQ5#

1

EC_SUSACK#_R
SYS_RESET#
SYS_PWROK
PCH_PWROK
APWROK
PCH_PLT_RST#

EC_SUSWARN#
EC_PBTN_OUT#_R
PCH_ACIN
PCH_GPIO72

PCIECLKREQ0#9

@

CLK_PCIE_WLAN#30
CLK_PCIE_WLAN30

WLAN_CLKREQ#30

CLK_PCIE_GPU#16
CLK_PCIE_GPU16

GPU_PCIE_CLKREQ#7,16

PCIECLKREQ5#4

0_0402_5%

+1.35V_CPU

VR_VDDQ_PWRGD

EC_SUS_VCCP

+1.05VS

VR_VCCST_PWRGD

EC_PCH_PWROK

VCCST_PWRGD

VR_CPU_PWROK

EC_SYS_PWROK

6

2

@

1

RC61 100_0402_5%
RC62 0_0402_5%
RC139 0_0402_5%

RC141 0_0402_5%

PCIE CLK2 WLAN

PCIE CLK4 GPU

C C

1 2

EC_PCH_ACIN29

EC_ACIN#29

B B

A A

RC65 0_0402_5%

1 2

RC64

EC_SYS_PWROK29
EC_PCH_PWROK10,29

PCH_PLT_RST#16,29,30

EC_RSMRST#29

EC_SUSWARN#29

EC_PBTN_OUT#29 PCH_SLP_S4# 29

5

4

UC1F

C43

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

U2

PCIECLKRQ0/GPIO18

B41

CLKOUT_PCIE_N1

A41

CLKOUT_PCIE_P1

Y5

PCIECLKRQ1/GPIO19

C41

CLKOUT_PCIE_N2

B42

CLKOUT_PCIE_P2

AD1

PCIECLKRQ2/GPIO20

B38

CLKOUT_PCIE_N3

C37

CLKOUT_PCIE_P3

N1

PCIECLKRQ3/GPIO21

A39

CLKOUT_PCIE_N4

B39

CLKOUT_PCIE_P4

U5

PCIECLKRQ4/GPIO22

B37

CLKOUT_PCIE_N5

A37

CLKOUT_PCIE_P5

T2

PCIECLKRQ5/GPIO23

HASWELL-ULT-DDR3L_BGA1168

@

UC1H

AK2

SUSACK

AC3

SYS_RESET

AG2

SYS_PWROK

AY7

PCH_PWROK

AB5

APWROK

AG7

PLTRST

AW6

RSMRST

AV4

SUSWARN/SUSPWRDNACK/GPIO30

AL7

PWRBTN

AJ8

ACPRESENT/GPIO31

AN4

BATLOW/GPIO72

AF3

SLP_S0

AM5

SLP_WLAN/GPIO29

HASWELL-ULT-DDR3L_BGA1168

@

4

HSW_ULT_DDR3L

CLOCK

SIGNALS

6 OF 19

HSW_ULT_DDR3L

SYSTEM POWER MANAGEMENT

8 OF 19

XTAL24_IN

XTAL24_OUT

RSVD5
RSVD6

DIFFCLK_BIASREF

TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8

CLKOUT_LPC_0
CLKOUT_LPC_1

CLKOUT_ITPXDP

CLKOUT_ITPXDP_P

DSWVRMEN

CLKRUN/GPIO32

SUS_STAT/GPIO61

SUSCLK/GPIO62

SLP_S5/GPIO63

DPWROK

WAKE

SLP_S4
SLP_S3

SLP_A
SLP_SUS
SLP_LAN

A25
B25

K21
M21
C26

C35
C34
AK8
AL8

AN15
AP15

B35
A35

3

XTAL24_IN

XTAL24_IN
XTAL24_OUT

MCP_TESTLOW1
MCP_TESTLOW2
MCP_TESTLOW3
MCP_TESTLOW4

PCH_PCI_CLK_R

RC770 1M_0402_5%

YC2

GND12OSC2

1

1

2

OSC1

24MHZ_6PF_7V24000032

CC23

3.3P_0402_50V8-B

12

RC71 3.01K_0402_1%

1 2

RC72 22_0402_5%

12

3

4

GND2

+1.05VS_PLPTCLKPLL

DIFFCLK_BIASREF

Width: 12-15Mil
Space:12Mil
Length: 500Mil

12

@

1

2

PCH_PCI_CLK 29

CC31
10P_0402_50V8J

CC24

3.3P_0402_50V8-B

2

XTAL24_OUT

Place close to PCH.

1 2

AW7

DSWODVREN

AV5

DPWROK

AJ5

PCIE_WAKE#

V5

PM_CLKRUN#

AG4

SUS_STAT#

AE6

SUSCLK

AP5

AJ6

PCH_SLP_S4#_R

AT4

PCH_SLP_S3#_R

AL5
AP4
AJ7

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

RC66 0_0402_5%

1

TP54@

1

TP53@

1 2

RC56 0_0402_5%

1 2

RC58 0_0402_5%

1

TP55@

2014/01/11

2014/01/11

2014/01/11

EC_RSMRST#

PCIE_WAKE# 30

SUSCLK 30

PCH_SLP_S3# 29

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

1

RPC6

WLAN_CLKREQ#
SYS_RESET#
PCIECLKREQ1#

PCIECLKREQ3#

PCI_PIRQD#4
PCH_GPIO339
PCH_GPIO769

07/22
change 10K to 1K for the HLH at RSMRST#

PCI_PIRQD#
PCH_GPIO33

MCP_TESTLOW1
MCP_TESTLOW2

MCP_TESTLOW3
MCP_TESTLOW4

PCH_PLT_RST#

SUSCLK

PCIE_WAKE#

PCH_ACIN

ACPRESENT

DSX_CFG-DEEP SX Configuration Register
*0 In DS-Sx config Mode, Internal 20K PD Enabled
In Non DS-Sx config Mode, Internal 20K PD Disabled
1 Internal 20K PD Disabled

PCH_GPIO72

BATLOW:

*PU To VCCDSW3_3 IN DEEP SX PLATFORM
PU TO VCCSUS3_3 IN NON DEEP SX PLATFORM

DSWODVREN

DSWVRMEN(PU to RTCVCC):

*1 Enable DSW 3.3V TO 1.05V Integrated
DSW On-die Voltage Regulator
0 Disable

EC_SUSWARN#

SUSWARN:

1, 10K PU to VCCSUS Follow CRB
2, No Need PU for Check List used as SUSWARN#
*3, Need PU for GPIO30 and not used

PM_CLKRUN#

18
27
36
45

10K_0804_8P4R_5%

RPC8

18
27
36
45

10K_0804_8P4R_5%

10K_0404_4P2R_5%

RPC10

1 4
2 3

10K_0404_4P2R_5%

RPC21

1 4
2 3

1 2

RC98 100K_0402_5%

12

RC147 1K_0402_5%@

1 2

RC89 10K_0402_5%

1 2

RC94 1K_0402_5%

1 2

RC86 10K_0402_5%

12

RC77 330K_0402_5%

1 2

RC95 10K_0402_5%

@

12

RC78 8.2K_0402_5%

Intel demand

Title

Title

2013/11/08

2013/11/08

2013/11/08

Title

MCP (Clock,PM)

MCP (Clock,PM)

MCP (Clock,PM)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Haydn

Haydn

Haydn

Monday, November 17, 2014

Monday, November 17, 2014

Monday, November 17, 2014

1

+3VS

+3VALW_PCH

+3VALW_PCH

+3VALW_PCH

VCCRTC

+3VALW_PCH

+3VS

8 45

8 45

8 45

1.0

1.0

1.0

Haswell MCP (GPIO,USB,PCIE)

5

4

3

2

1

+3VS

+3VALW_PCH

D D

+3VS

C C

B B

+3VS

+3VALW_PCH

A A

RPC9

10K_0804_8P4R_5%

RPC11

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

RPC12

10K_0804_8P4R_5%

RPC13

10K_0804_8P4R_5%

RPC20

18

SML1_ALERT#

27

PCH_GPIO8

36

USB_OC1#

45

USB_OC3#

10K_0804_8P4R_5%

RPC15

10K_0804_8P4R_5%

RPC16

10K_0804_8P4R_5%

RPC17

10K_0804_8P4R_5%

RPC19

10K_0804_8P4R_5%

RPC23

10K_0804_8P4R_5%

RPC24

10K_0804_8P4R_5%

RPC22

1 4
2 3

10K_0404_4P2R_5%

1 2

RC754 10K_0402_5%

@

1 2

RC753 10K_0402_5%

1 2

RC756 10K_0402_5%

1 2

RC773 10K_0402_5%

1 2

RC772 10K_0402_5%

RC97
0_0402_5%

1 2

1 2

RC764 10K_0402_5%

1 2

RC765 10K_0402_5%

1 2

@

RC766 10K_0402_5%

1 2

@

RC767 10K_0402_5%

18

PCH_GPIO45

27

PCH_GPIO56

36

PCH_GPIO58

45

PCH_GPIO59

PCH_GPIO26
SMB_ALERT#
PCH_GPIO57
PCH_GPIO13

18
27

PCH_GPIO9

36

SML0_ALERT#

45

USB_OC0#

18

PCH_GPIO10

27

USB_OC2#

36

PCH_GPIO46

45

PCH_GPIO14

SML1_ALERT# 7

18

PCH_GPIO93

27

PCH_GPIO91

36

PCH_GPIO3

45

PCH_GPIO1

18

PCH_GPIO34

27

PCIECLKREQ0#

36

SATA1GP

45

PCH_GPIO50

18

PCH_GPIO38

27

PCH_GPIO92

36

PCH_GPIO2

45

PCH_GPIO90

18

PCH_GPIO89

27

PCH_GPIO0

36

PCH_GPIO85

45

PCH_GPIO83

18

PCH_GPIO6

27

PCH_GPIO70

36

PCH_GPIO64

45

PCH_GPIO67

18

PCH_GPIO94

27

PCH_GPIO65

36

PCH_GPIO69

45

PCH_GPIO68

PCH_GPIO5
PCH_GPIO4

PCH_GPIO71

PCH_WLAN_OFF#

PCH_BT_OFF#

PCH_GPIO49

PCH_LCD_FPBACK

PCH_GPIO27

PCH_GPIO25

PCH_GPIO12

PCH_GPIO71

5

SMB_ALERT# 7

PCH_GPIO768

SML0_ALERT# 7

PCH_LCD_FPBACK24

PCH_GPIO34 7
PCIECLKREQ0# 8
SATA1GP 7

+1.05VS_PUSB3PLL

PCIE_RCOMP&PCIE_IREF (Shared with DMI)

Width 20Mil
Space 15Mil
Length 500Mil

PCH_GPIO247

PCH_GPIO287

PCH_GPIO477

PCH_GPIO338

PCH_BEEP27

PCIE_CRX_GTX_N[0..3]16

PCIE_CRX_GTX_P[0..3]16

PCIE_CTX_C_GRX_N[0..3]16

PCIE_CTX_C_GRX_P[0..3]16

PCIE_CTX_C_GRX_N0 PCIE_CTX_GRX_N0
PCIE_CTX_C_GRX_P0 PCIE_CTX_GRX_P0

PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_P1 PCIE_CTX_GRX_P1

PCIE5

PCIE_CTX_C_GRX_N2 PCIE_CTX_GRX_N2
PCIE_CTX_C_GRX_P2 PCIE_CTX_GRX_P2

PCIE_CTX_C_GRX_N3 PCIE_CTX_GRX_N3
PCIE_CTX_C_GRX_P3 PCIE_CTX_GRX_P3

PCIE_PRX_DTX_N330

PCIE_PRX_DTX_P330

PCIE_PTX_C_DRX_N330

PCIE_PTX_C_DRX_P330

RC113 3.01K_0402_1%

OPT@
OPT@

OPT@
OPT@

OPT@
OPT@

OPT@
OPT@

12

PCH_GPIO76
PCH_GPIO8
PCH_GPIO12
PCH_GPIO15
BOARD_ID0
BOARD_ID1
PCH_GPIO24
PCH_GPIO27
PCH_GPIO28
PCH_GPIO26

PCH_GPIO56
PCH_GPIO57
PCH_GPIO58
PCH_GPIO59
WIN8_BUTTON#_R
PCH_GPIO47
PCH_LCD_FPBACK
PCH_GPIO49
PCH_GPIO50
PCH_GPIO71
PCH_GPIO13
PCH_GPIO14
PCH_GPIO25
PCH_GPIO45
PCH_GPIO46

PCH_GPIO9
PCH_GPIO10
PCH_GPIO33
PCH_GPIO70
PCH_GPIO38
BOARD_ID2
PCH_BEEP

1 2
1 2

CC19.1U_0402_10V6-K
CC18.1U_0402_10V6-K

1 2
1 2

CC20.1U_0402_10V6-K
CC21.1U_0402_10V6-K

1 2
1 2

CC25.1U_0402_10V6-K
CC34.1U_0402_10V6-K

1 2
1 2

CC35.1U_0402_10V6-K
CC36.1U_0402_10V6-K

PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3

12

PCIE_PTX_DRX_N3

12

PCIE_PTX_DRX_P3

CC177 .1U_0402_10V6-K
CC188 .1U_0402_10V6-K

PCIE_CRX_GTX_N0
PCIE_CRX_GTX_P0

PCIE_CRX_GTX_N1
PCIE_CRX_GTX_P1

PCIE_CTX_GRX_N1

PCIE_CRX_GTX_N2
PCIE_CRX_GTX_P2

PCIE_CRX_GTX_N3
PCIE_CRX_GTX_P3

PCIE_RCOMP

4

UC1J

P1

BMBUSY/GPIO76

AU2

GPIO8

AM7

LAN_PHY_PWR_CTRL/GPIO12

AD6

GPIO15

Y1

GPIO16

T3

GPIO17

AD5

GPIO24

AN5

GPIO27

AD7

GPIO28

AN3

GPIO26

AG6

GPIO56

AP1

GPIO57

AL4

GPIO58

AT5

GPIO59

AK4

GPIO44

AB6

GPIO47

U4

GPIO48

Y3

GPIO49

P3

GPIO50

Y2

HSIOPC/GPIO71

AT3

GPIO13

AH4

GPIO14

AM4

GPIO25

AG5

GPIO45

AG3

GPIO46

AM3

GPIO9

AM2

GPIO10

P2

DEVSLP0/GPIO33

C4

SDIO_POWER_EN/GPIO70

L2

DEVSLP1/GPIO38

N5

DEVSLP2/GPIO39

V2

SPKR/GPIO81

HASWELL-ULT-DDR3L_BGA1168

@

UC1K

F10

PERN5_L0

E10

PERP5_L0

C23

PETN5_L0

C22

PETP5_L0

F8

PERN5_L1

E8

PERP5_L1

B23

PETN5_L1

A23

PETP5_L1

H10

PERN5_L2

G10

PERP5_L2

B21

PETN5_L2

C21

PETP5_L2

E6

PERN5_L3

F6

PERP5_L3

B22

PETN5_L3

A21

PETP5_L3

G11

PERN3

F11

PERP3

C29

PETN3

B30

PETP3

F13

PERN4

G13

PERP4

B29

PETN4

A29

PETP4

G17

PERN1/USB3RN3

F17

PERP1/USB3RP3

C30

PETN1/USB3TN3

C31

PETP1/USB3TP3

F15

PERN2/USB3RN4

G15

PERP2/USB3RP4

B31

PETN2/USB3TN4

A31

PETP2/USB3TP4

E15

RSVD9

E13

RSVD10

A27

PCIE_RCOMP

B27

PCIE_IREF

HASWELL-ULT-DDR3L_BGA1168

@

HSW_ULT_DDR3L

GPIO

SERIAL IO

10 OF 19

HSW_ULT_DDR3L

PCIE USB

11 OF 19

CPU/
MISC

THRMTRIP

RCIN/GPIO82

SERIRQ

PCH_OPI_RCOMP

RSVD7
RSVD8

GSPI0_CS/GPIO83

GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86

GSPI1_CS/GPIO87

GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89

GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS/GPIO93
UART0_CTS/GPIO94

UART1_RXD/GPIO0

UART1_TXD/GPIO1

UART1_RST/GPIO2

UART1_CTS/GPIO3

I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69

USB2N0
USB2P0

USB2N1
USB2P1

USB2N2
USB2P2

USB2N3
USB2P3

USB2N4
USB2P4

USB2N5
USB2P5

USB2N6
USB2P6

USB2N7
USB2P7

USB3RN1

USB3RP1

USB3TN1
USB3TP1

USB3RN2

USB3RP2

USB3TN2
USB3TP2

USBRBIAS
USBRBIAS

RSVD11
RSVD12

OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43

3

H_THRMTRIP#_R

.01U_0402_16V7-K

1

CC106

2

@

D60

H_THRMTRIP#_R

V4

EC_KBRST#_R

T4

SERIRQ

AW15

OPI_COMP

AF20
AB21

R6

PCH_GPIO83

L6

BOARD_ID3

N6

PCH_GPIO85

L8

PCH_GPIO86

R7

PCH_BT_OFF#

L5

PCH_WLAN_OFF#

N7

PCH_GPIO89

K2

PCH_GPIO90

J1

PCH_GPIO91

K3

PCH_GPIO92

J2

PCH_GPIO93

G1

PCH_GPIO94

K4

PCH_GPIO0

G2

PCH_GPIO1

J3

PCH_GPIO2

J4

PCH_GPIO3

F2

PCH_GPIO4

F3

PCH_GPIO5

G4

PCH_GPIO6

F1

PCH_GPIO7

E3

PCH_GPIO64

F4

PCH_GPIO65

D3

PCH_GPIO66

E4

PCH_GPIO67

C3

PCH_GPIO68

E2

PCH_GPIO69

AN8
AM8

AR7
AT7

AR8
AP8

AR10
AT10

AM15
AL15

AM13
AN13

AP11
AN11

AR13
AP13

G20
H20

C33
B34

E18
F18

B33
A33

AJ10

USBRBIAS

AJ11
AN10

USBRBIAS

AM10

Width: 20Mil Space:15Mil Length: 500Mil

AL3

USB_OC0#

AT1

USB_OC1#

AH2

USB_OC2#

AV3

USB_OC3#

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1 2

RC44 0_0402_5%

1 2

RC758 0_0402_5%@

1 2

RC759 0_0402_5%

RC104 49.9_0402_1%

OPI_RCOMP Width: 12-15Mil

1 2

RC761 0_0402_5%

USB20_N0 24
USB20_P0 24

USB20_N1 32
USB20_P1 32

USB20_N2 27
USB20_P2 27

USB20_N3 27
USB20_P3 27

USB20_N4 30
USB20_P4 30

USB20_N5 29
USB20_P5 29

USB20_N6 24
USB20_P6 24

USB20_N7 37
USB20_P7 37

USB30_RX_N1 27
USB30_RX_P1 27

USB30_TX_N1 27
USB30_TX_P1 27

USB30_RX_N2 32
USB30_RX_P2 32

USB30_TX_N2 32
USB30_TX_P2 32

RC112 22.6_0402_1%

USB_OC0# 32
USB_OC1# 27

USB_OC3# 37

@

@

12

Space:12Mil
Length: 500Mil

12

2014/01/11

2014/01/11

2014/01/11

+1.05VS

12

RC101
1K_0402_1%

H_THRMTRIP#

EC_KBRST# 29
EC_INT_SERIRQ 29

PCH_BT_OFF# 30
PCH_WLAN_OFF# 30

EC_SCI# 29

Camera _Conn

Right USB2.0

Left USB2.0

Card Reader

Mini Card BT

ECT8386 Sensor

Touch Panel

DC_IN combo USB2.0

Left USB3.0

Right USB3.0

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3

H_THRMTRIP# 16

WIN8_BUTTON#24,29

EC_LID_OUT#24,29

GPIO15, Internal PD
1: INTEL ME TLS W Confidentiality
*0: INTEL ME TLS WO Confidentiality

GPIO66, Internal 20K PD
1: Top-Block Swap Override EN
*0: Disable

GPIO81, No Reboot, Internal PD
1: Enabled No Reboot Mode
*0: Disable No Reboot Mode

GPIO86, Internal PD
1: LPC
*0: SPI ROM

2013/11/08

2013/11/08

2013/11/08

RC314
10K_0402_5%

@

1 2

RC566
10K_0402_5%

1 2

RC503
10K_0402_5%

OPT@

1 2

RC512
10K_0402_5%

UMA@

1 2

RC569
10K_0402_5%

1 2

RC372
10K_0402_5%

@

1 2

BOM Control :BOARD_ID1

BOARD_ID0 BOARD_ID1 Description

0 0

0 1

PCH_GPIO15

PCH_GPIO66

PCH_BEEP

PCH_GPIO86

Title

Title

Title

MCP (GPIO,USB,PCIE)

MCP (GPIO,USB,PCIE)

MCP (GPIO,USB,PCIE)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

UMA

DIS

+3VALW_PCH

1 2

RC763
0_0402_5%

@

@

1 2

RC762
0_0402_5%

1 2

@

RC540 1K_0402_5%

@

RC541 1K_0402_5%

@

RC544 1K_0402_5%

12

@

RC542 1K_0402_5%

12

@

RC543 1K_0402_5%

Haydn

Haydn

Haydn

Monday, November 17, 2014

Monday, November 17, 2014

Monday, November 17, 2014

RC567
10K_0402_5%

1 2

WIN8_BUTTON#_R

+3VALW_PCH

12

12

1

PCH_GPIO14

1 2

1 2

+3VS

+3VS

+3VS

RC584
10K_0402_5%

RC598
10K_0402_5%

@

9 45

9 45

9 45

1.0

1.0

1.0

Haswell MCP (Power)

5

+CPU_CORE(32A) 22 µF X23

1.35V_CPU(1.4A)

HW 4PCS 2.2UF CAP Mounted
HW 6PCS 10UF CAP Mounted
PWR 2PCS 470U Near VR Output

D D

4.7U_0603_6.3V6K

+VCCIOA_OUT

C C

VCC_SENSE

Length Match: No More Than 25Mil
Space: More Than 25Mil
GND Reference

SVID

1, Stripline Line, No More Than 6000Mil
2, Alert# Route Between CLK and Data
3, CLK Length<Data Length<CLK Length + 2000Mil
4, Space at least 18Mil

+VCCIO_OUT

1

CC65

2

@

+1.05VS

+1.05VS

VCC_SENSE

Length Match: <25Mil
Space: More Than 25Mil
GND Reference

CPU_VCC_SENSE43

CPU_VR_ON43

12

@

RC161 150_0402_1%

1 2

RC138 0_0402_5%

CC82

22U_0603_6.3V6-M

CD@

+1.05VS

VCCST(0.1A)

1

2

4

RC114

100_0402_1%

1 2

RC137 0_0402_5%

CPU_SVID_ALRT#_R
CPU_SVID_CLK_R
CPU_SVID_DAT_R
VCCST_PG_EC_R

CPU_VR_READY

TP36 @
TP44 @

RC1515 10K_0402_5%

+1.05V_VCCST

1

+CPU_CORE

CC81
.1U_0402_10V6-K

2

+CPU_CORE

1 2

1
1

+CPU_CORE

PWR_DEBUG

12

+1.35V_CPU

L59
J58

AH26

AJ31
AJ33

AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50

F59
N58

AC58

E63

AB23

A59

E20
AD23
AA23
AE59

L62

N63

L63

B59

F60

C59

D63

H59

P62

P60

P61

N59

N61

T59
AD60
AD59
AA59
AE60
AC59
AG58

U59

V59

AC22
AE22
AE23

AB57
AD57
AG57

C24

C28

C32

UC1L

RSVD13
RSVD14

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11

VCC1
RSVD15
RSVD16

VCC_SENSE
RSVD17
VCCIO_OUT
VCCIOA_OUT
RSVD18
RSVD19
RSVD20

VIDALERT
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY

VSS344
PWR_DEBUG
VSS345
RSVD_TP1
RSVD_TP2
RSVD_TP3
RSVD_TP4
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29

VCCST1
VCCST2
VCCST3

VCC2
VCC3
VCC4
VCC5
VCC6
VCC7

HASWELL-ULT-DDR3L_BGA1168

@

HSW_ULT_DDR3L

HSW ULT POWER

12 OF 19

3

+CPU_CORE

C36

VCC8

C40

VCC9

C44

VCC10

C48

VCC11

C52

VCC12

C56

VCC13

E23

VCC14

E25

VCC15

E27

VCC16

E29

VCC17

E31

VCC18

E33

VCC19

E35

VCC20

E37

VCC21

E39

VCC22

E41

VCC23

E43

VCC24

E45

VCC25

E47

VCC26

E49

VCC27

E51

VCC28

E53

VCC29

E55

VCC30

E57

VCC31

F24

VCC32

F28

VCC33

F32

VCC34

F36

VCC35

F40

VCC36

F44

VCC37

F48

VCC38

F52

VCC39

F56

VCC40

G23

VCC41

G25

VCC42

G27

VCC43

G29

VCC44

G31

VCC45

G33

VCC46

G35

VCC47

G37

VCC48

G39

VCC49

G41

VCC50

G43

VCC51

G45

VCC52

G47

VCC53

G49

VCC54

G51

VCC55

G53

VCC56

G55

VCC57

G57

VCC58

H23

VCC59

J23

VCC60

K23

VCC61

K57

VCC62

L22

VCC63

M23

VCC64

M57

VCC65

P57

VCC66

U57

VCC67

W57

VCC68

+1.35V_CPU

1

2

+1.35V_CPU

1

RF_NS@

2

1

CC27

2

CC37
10U_0603_6.3V6M

CC76

33P_0402_50V8J

2.2U_0603_6.3V6K

2

1

CC38
10U_0603_6.3V6M

2

1

2

1

2.2U_0603_6.3V6K

1

2

CD@

1

CC29

2

CC39
10U_0603_6.3V6M

+CPU_CORE

RF_NS@

2.2U_0603_6.3V6K

1

2

CC83

1

2

1

CC28

2

CD@

CC75

33P_0402_50V8J

RF_NS@

CC40
10U_0603_6.3V6M

33P_0402_50V8J

1

CC30

2.2U_0603_6.3V6K

2

CD@

1

CC41
10U_0603_6.3V6M

2

CC80

1

2

RF_NS@

1

CC42
10U_0603_6.3V6M

2

CD@

33P_0402_50V8J

12

+3VALW

1 2

RC123
130_0402_1%

CPU_SVID_ALRT#_R

RC1516

10K_0402_5%@

6

AO5804EL_SC89-6

@

AO5804EL_SC89-6
QC12A

1

RC546
75_0402_1%

1 2

CPU_SVID_ALERT#43

B B

A A

CPU_SVID_CLK43

CPU_SVID_DAT43

VR_CPU_PWROK29,43

RC83 0_0402_5%

@

5

12

12

RC121 43_0402_5%

1 2

RC122 0_0402_5%

1 2

RC124 0_0402_5%

2

CC54

0.01U_0402_16V7K

@

1

2

CPU_SVID_CLK_R

CPU_SVID_DAT_R

+1.05VS

@

QC12B

5

12

CC43
.1U_0402_10V6-K

@

RC1513
10K_0402_5%

1 2

3

@

4

12

RC84 0_0402_5%

@

4

+1.05VS

+3VALW

CPU_VR_ON VCCST_PG_EC_R

RC1514
10K_0402_5%

1 2

CPU_VR_READY

0_0402_5%

1 2

RC85

VR_CPU_PWROK

EC_PCH_PWROK8,29

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

12

RC80 0_0402_5%

@

@

1

2

2014/01/11

2014/01/11

2014/01/11

CC49

0.01U_0402_16V7K

RC1517

@

10K_0402_5%

1 2

6

AO5804EL_SC89-6

@

2

AO5804EL_SC89-6
QC13A

1

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

QC13B

5

2

1 2

3

@

4

RC1512
1K_0402_5%

2013/11/08

2013/11/08

2013/11/08

1 2

RC81 0_0402_5%

CC50

0.01U_0402_16V7K

1

2

Title

Title

Title

MCP (Power)

MCP (Power)

MCP (Power)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Monday, November 17, 2014

Monday, November 17, 2014

Monday, November 17, 2014

Date: Sheet of

Date: Sheet of

Date: Sheet of

VCCST_PG_EC 29

Haydn

Haydn

Haydn

1

10 45

10 45

10 45

1.0

1.0

1.0

Haswell MCP (Power2)

5

4

3

2

1

+1.05VS_VCCHSIO

D D

+1.05VS

C C

RC107 0_0402_5%

+1.05VS

CC78

33P_0402_50V8J

1

2

RF_NS@

LC1

1 2

2.2UH_CIG10W2R2MNC_20%

LC2

1 2

2.2UH_CIG10W2R2MNC_20%

LC4

1 2

2.2UH_CIG10W2R2MNC_20%

LC5

1 2

2.2UH_CIG10W2R2MNC_20%

1 2

CC6

22U_0603_6.3V6-M

1

2

1

2

1

2

1

2

1

@

2

CC2
22U_0603_6.3V6-M

CC4
22U_0603_6.3V6-M

CC118
47U_0805_6.3V6-M

CC121

22U_0603_6.3V6-M

22U_0603_6.3V6-M

1

CC13
22U_0603_6.3V6-M

2

CC128

1

@

22U_0603_6.3V6-M

2

+1.05VS_PUSB3PLL
41mA

1

CC3
22U_0603_6.3V6-M

2

+1.05VS_PSATA3PLL
42mA

1

CC5
22U_0603_6.3V6-M

2

+1.05VS_PLPTVCC1P05
185mA

1

CC130

CD@

CD@

2

+1.05VS_PLPTCLKPLL
31mA

1

CD@

CC127
47U_0805_6.3V6-M

2

+1.05VS_POPIPLL
57mA

CC129

1

@

@

22U_0603_6.3V6-M

2

1

22U_0603_6.3V6-M

2

CC131

1

22U_0603_6.3V6-M

2

+1.05VS_PUSB3PLL

1

CC107
1U_0402_10V6K

2

+1.05VS_PSATA3PLL

1

CC111
1U_0402_10V6K

2

+1.05VS_PLPTVCC1P05

1

CC132

2

+1.05VS_PLPTCLKPLL

1

CC119
1U_0402_10V6K

2

+1.05VS_POPIPLL

1

CC122
1U_0402_10V6K

2

1U_0402_10V6K
CC117

+1.05VS

CC112,CC101
Place Near K9,L10,M9

CC84
Place Near N8,P9

CC107
Place Near B18

CC111
Place Near B11

CC122
Place Near AA21,W21

CC103
Place Near J13

CC120
Place Near AH14

CC102
Place Near AH13

CC100
Place Near AC9,AA9,AE20,AE21

CC97
Place Near AH10

CC95
Place Near V8,W9

CC117
Place Near J18,K19

CC119
Place Near A20

CC98,CC99
Place Near J17,R21,T21

PJ11
JUMP_43X39

112

@

+1.05VS_VCCHSIO

2

VCC1_05[1:9]

1.741A

+3VALW_PCH

+3VS

VCCHSIO

1.838A

CD@

+1.05VS_PSATA3PLL

+1.05VS_POPIPLL

+1.05VS_PLPTCLKPLL

CD@

1 2

RC99 0_0402_5%

+3VALW_PCH

12

CC1121U_0402_10V6K

12

CC1011U_0402_10V6K

12

CC841U_0402_10V6K

12

CC1031U_0402_10V6K @

12

CC1201U_0402_10V6K

12

CC1021U_0402_10V6K @

12

CC10022U_0603_6.3V6-M

12

CC971U_0402_10V6K @

12

CC9522U_0603_6.3V6-M

12

CC991U_0402_10V6K

12

CC981U_0402_10V6K

+1.05VS_PUSB3PLL

+3VS

+3VALW_PCH

+3VALW_PCH

VCCSUS3_3[1:5]
65mA

VCCDSW3_3

+1.05VS_VCCHSIO

+1.05VS

1

TP42 @

+1.05VS_DCPSUS3

VCCHDA
11mA

VCCHDA

+1.05VS_DCPSUS2

VCCDSW
114mA

VCC3_3[1:4]
41mA

+1.05VS_PLPTVCC1P05

+1.05VS

1

TP47 @

1

TP48 @

UC1M

K9

VCCHSIO[1]

L10

VCCHSIO[2]

M9

VCCHSIO[3]

N8

VCC1_05[1]

P9

VCC1_05[2]

B18

VCCUSB3PLL

B11

VCCSATA3PLL

Y20

RSVD30

AA21

VCCAPLL[1]

W21

VCCAPLL[2]

J13

DCPSUS3

AH14

VCCHDA

AH13

DCPSUS2

AC9

VCCSUS3_3[1]

AA9

VCCSUS3_3[2]

AH10

VCCDSW3_3

V8

VCC3_3[1]

W9

VCC3_3[2]

J18

VCCCLK[1]

K19

VCCCLK[2]

A20

VCCACLKPLL

J17

VCCCLK[3]

R21

VCCCLK[4]

T21

VCCCLK[5]

K18

RSVD31

M20

RSVD32

V21

RSVD33

AE20

VCCSUS3_3[3]

AE21

VCCSUS3_3[4]

HASWELL-ULT-DDR3L_BGA1168

@

HSIO

USB3

HDA

VRM

GPIO/LPC

LPT LP POWER

HSW_ULT_DDR3L

OPI

13 OF 19

RTC

SPI

CORE

THERMAL SENSOR

SERIAL IO

SUS OSCILLATOR

USB2

VCCSUS3_3[5]

VCCRTC
DCPRTC

VCCSPI

VCCASW[1]
VCCASW[2]

VCC1_05[3]
VCC1_05[4]
VCC1_05[5]
VCC1_05[6]

VCC1_05[7]
DCPSUSBYP[1]
DCPSUSBYP[2]

VCCASW[3]

VCCASW[4]

VCCASW[5]

DCPSUS1[1]
DCPSUS1[2]

VCCTS1_5
VCC3_3[3]
VCC3_3[4]

VCCSDIO[1]
VCCSDIO[2]

DCPSUS4

RSVD34
VCC1_05[8]
VCC1_05[9]

+3VALW_PCH

CC125 1U_0402_10V6K

VCCRTC

+1.05VS

+1.05VS

+1.05VS

+1.5VS

+3VS

+3VS

+1.05VS

TP121@

CC85 1U_0402_10V6K
CC86 .1U_0402_10V6-K
CC87 .1U_0402_10V6-K
CC88 .1U_0402_10V6-K

CC90 .1U_0402_10V6-K

CC113 10U_0603_6.3V6M
CC124 1U_0402_10V6K
CC115 1U_0402_10V6K

CC123 1U_0402_10V6K

CC94 22U_0603_6.3V6-M@
CC126 1U_0402_10V6K

CC109

CC96 .1U_0402_10V6-K

CC105 1U_0402_10V6K

CC110

CC104 1U_0402_10V6K

AH11
AG10
AE7

+DCPRTC

Y8

VCCSPI

AG14
AG13

J11
H11
H15
AE8
AF22
AG19

+PCH_DCPSUSBYP

AG20
AE9
AF9
AG8
AD10
AD8

+1.05VS_DCPSUS1VCCDSW3_3

J15
K14
K16

U8
T9

0529
DEL CC108 for VCCSPI change

AB8

+1.05VS_DCPSUS4

1

AC20
AG16
AG17

1 2
1 2
1 2
1 2
1 2

1 2

1 2
1 2
1 2

1 2

1 2
1 2

1 2

1 2

1 2

CD@

1 2

1 2

CD@

@

1U_0402_10V6K@

1U_0402_10V6K@

VCCRTC
1mA

VCCSPI
18mA

VCCASW[1:5]
658mA

VCCTS1_5
3mA

VCCSDIO
17mA

CC1251
Place Near AH11

CC85,86,87
Place Near AG10

CC88
Place Near AE7

CC90
Place Near Y8

CC90
Place Near Y8

CC113,CC124,CC115
Place Near J11,H11,H15,AE8,AF22

CC123
Place Near AG19,Ag20

CC94,CC126
Place Near AE9,AF9,AG8

CC109
Place Near AD10,AD8

CC96
Place Near K14,K16

CC105
Place Near U8,T9

CC108
Place Near AB8

CC104
Place Near AG16,AG17

12

@

B B

A A

5

4

RC102 0_0402_5%

1 2

RC103 0_0402_5%

1 2

CC398 0.47U_0402_25V6K

0524
Add 0.47U for VCCDSW3_3 ramp up
slower than 100us

+3V_SPI

+3VS

RC105

1 2

12

RC106 0_0402_5%

@

+PCH_DCPSUSBYPVCCDSW3_3

0_0402_5%

VCCHDA

VCCSPI

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2014/01/11

2014/01/11

2014/01/11

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/11/08

2013/11/08

2013/11/08

Title

Title

Title

MCP (Power2)

MCP (Power2)

MCP (Power2)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Haydn

Haydn

Haydn

Monday, November 17, 2014

Monday, November 17, 2014

Monday, November 17, 2014

11 45

11 45

1

11 45

1.0

1.0

1.0

5

4

3

2

1

Haswell MCP (VSS)

HSW_ULT_DDR3L

UC1N

A11

VSS1

A14

VSS2

A18

VSS3

A24

VSS4

A28

VSS5

A32

D D

C C

B B

VSS6

A36

VSS7

A40

VSS8

A44

VSS9

A48

VSS10

A52

VSS11

A56

VSS12

AA1

VSS13

AA58

VSS14

AB10

VSS15

AB20

VSS16

AB22

VSS17

AB7

VSS18

AC61

VSS19

AD21

VSS20

AD3

VSS21

AD63

VSS22

AE10

VSS23

AE5

VSS24

AE58

VSS25

AF11

VSS26

AF12

VSS27

AF14

VSS28

AF15

VSS29

AF17

VSS30

AF18

VSS31

AG1

VSS32

AG11

VSS33

AG21

VSS34

AG23

VSS35

AG60

VSS36

AG61

VSS37

AG62

VSS38

AG63

VSS39

AH17

VSS40

AH19

VSS41

AH20

VSS42

AH22

VSS43

AH24

VSS44

AH28

VSS45

AH30

VSS46

AH32

VSS47

AH34

VSS48

AH36

VSS49

AH38

VSS50

AH40

VSS51

AH42

VSS52

AH44

VSS53

AH49

VSS54

AH51

VSS55

AH53

VSS56

AH55

VSS57

AH57

VSS58

AJ13

VSS59

AJ14

VSS60

AJ23

VSS61

AJ25

VSS62

AJ27

VSS63

AJ29

VSS64

HASWELL-ULT-DDR3L_BGA1168

@

14 OF 19

VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128

AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20

AP22
AP23
AP26
AP29

AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49

AR5
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63

AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14

AV16
AV20
AV24
AV28

AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55

HSW_ULT_DDR3L

UC1O

VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192

HASWELL-ULT-DDR3L_BGA1168

@

15 OF 19

VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256

AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31

UC1P

D33

VSS257

D34

VSS258

D35

VSS259

D37

VSS260

D38

VSS261

D39

VSS262

D41

VSS263

D42

VSS264

D43

VSS265

D45

VSS266

D46

VSS267

D47

VSS268

D49

VSS269

D5

VSS270

D50

VSS271

D51

VSS272

D53

VSS273

D54

VSS274

D55

VSS275

D57

VSS276

D59

VSS277

D62

VSS278

D8

VSS279

E11

VSS280

E17

VSS281

F20

VSS282

F26

VSS283

F30

VSS284

F34

VSS285

F38

VSS286

F42

VSS287

F46

VSS288

F50

VSS289

F54

VSS290

F58

VSS291

F61

VSS292

G18

VSS293

G22

VSS294

G3

VSS295

G5

VSS296

G6

VSS297

G8

VSS298

H13

VSS299

HASWELL-ULT-DDR3L_BGA1168

@

HSW_ULT_DDR3L

VSS_SENSE

16 OF 19

VSS_SENSE

Length Match: No More Than 25Mil
Space: More Than 25Mil
GND Reference

VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337

VSS338
VSS339
VSS340

VSS341

H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63

V58
AH46
V23
E62
AH16

RC131
0_0402_5%

RC132
100_0402_1%

1 2

1 2

CPU_VSS_SENSE 43

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

2014/01/11

2014/01/11

2014/01/11

3

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2013/11/08

2013/11/08

2013/11/08

2

Title

MCP (VSS)

MCP (VSS)

MCP (VSS)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Monday, November 17, 2014

Monday, November 17, 2014

Date: Sheet of

Date: Sheet of

Date: Sheet of

Monday, November 17, 2014

Haydn

Haydn

Haydn

1

12 45

12 45

12 45

1.0

1.0

1.0