Lenovo Y720-15ACZ Schematic

A

1 1

B

C

D

E

LCFC Confidential

Allsparks 5B Project M/B Schematics Document

2 2

AMD FP4 Carrizo SOC with DDRIIIL

AMD Exo Pro A10/FX

2015-04-23

3 3

4 4

REV:0.3

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

A

B

2014/10/22

2014/10/22

2014/10/22

C

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2014/10/22

2014/10/22

2014/10/22

D

Title

Cover Page

Cover Page

Cover Page

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Wednesday, April 29, 2015

Allsparks 5B

Allsparks 5B

Allsparks 5B

E

1 51

1 51

1 51

0.3

0.3

0.3

A

B

C

D

E

LCFC confidential

AMD Strato XT
M3 Package: 29mmX29mm

Page 18~24

1 1

VRAM 256*16

GDDR5*4/8 4GB/2GB

Page 14~22

PCI-Express
8x Gen3

PEG 0~7

Memory BUS (DDR3L)

1.35V DDR3L 1600 MT/s

DDR3L-SO-DIMM X2

Page 12,13

UP TO 8G x 2

HDMI Conn.

Page 26

eDP Conn

FHD

Page 25

Int. Camera

USB2.0 Port1

HDMI x4 Lane Port1

DP x2 Lane Port0

USB2.0 2x

AMD FP4 APU
Carrizo 35W

(Integrated FCH)

Int. Mic Conn

2 2

Page 23

USB 3.0 2x

USB 2.0 2x

USB2.0 1x

USB3.0 1x

SATA HDD

Page 33

SATA Port0

SATA Gen3

USB2.0 1x

USB Right

USB 2.0 Port5
USB 3.0 Port1

USB 2.0 Port6
USB 3.0 Port2

USB charger

TPS2546RTER

JUSB1

Page 32

JUSB2

USB Left

USB2.0 Port0

(Debug Port)

Cardreader Genesys
GL3215

USB3.0 Port0
USB2.0 Port4

JUSB3

SD/MMC SD4.0 Conn.

IO Board

BGA-968

SATA SSD

Page 30

RJ45 Conn.

3 3

Page 29

Subwoofer Conn

Page 27

Amplifiers

TPA3113D2PWPR

Page 27

LAN Realtek

RTL8111H-CG

Page 28

Realtek ALC3248

Page 34

SATA Port1

PCIe Port2/3

PCIe Port1

Codec

SATA Gen3

PCIe 2x

PCIe 1x

HD Audio

SPK Conn.

Page 34

Page 4~11

HP&Mic Combo Conn.

37mm*29mm

ITE IT8371-LQFP

Page 35

EC

USB 2.0 1x

PCIe 1x

SPI BUS

TPM
Z32H320TC

for reserve

Page 36

NGFF Card
WLAN&BT

Page 31

SPI ROM
8MB

Page 08

PCIe Port1
USB2.0 Port3

Sub-board

LED BOARD

IO Board

IO Board

4 4

A

B

Touch Pad Int.KBD

Page 36

Page 36

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

Thermal Sensor
F75303M

Page 31

LC Future Center Secret Data

LC Future Center Secret Data

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2014/10/22

2014/10/22

2014/10/22

Title

Title

Title

Block Diagram

Block Diagram

Block Diagram

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Wednesday, April 29, 2015

Allsparks 5B

Allsparks 5B

Allsparks 5B

E

2 51

2 51

2 51

0.3

0.3

0.3

A

B

C

D

E

Voltage Rails

power
plane

1 1

State

S0

S3

2 2

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

( O --> Means ON , X --> Means OFF )

B+
(+20VSB)

+3VL

+5VLP

O

O

O

O

X

+5VALW

+3VALW
(+3VALW_APU)

+1.8VALW

+0.95VALW

+0.775VALW

+1.35V
(+VSYSMEM_APU)

O

O

O

X

O

X X

X

X X X

+5VS

+3VS

+1.8VS

+1.5VS

+0.95VS

+0.675VS

+APU_CORE

+APU_CORE_NB

+APU_GFX

+VGA_CORE

+3VGS

+1.8VGS

+1.35VGS

+0.95VGS

OO

X

X

STATE

S0 (Full ON)

S1 (Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S3# SLP_S5# +VALW +V +VS Clock

HIGH HIGH

LOW

LOW LOW

USB Port Table for Carrzio

USB 3.0USB 2.0 Port

0

EHCI

xHCI

1
2
3
4
5
6
7

ON

ONONON ON

ON

HIGHHIGH

ON

HIGHLOW

LOW

3 External
USB Port

ON

ON

OFF

ON

OFF

LEFT USB (2.0) charge
Camera
N/A
Blue Tooth
Card Reader
Right USB (3.0)
Right USB (3.0)
N/A

ON

LOW

OFF

OFF

OFF

OFF

OFF

OFF

BOM Structure Table

PCIE PORT LIST

SMBUS Control Table

SOURCE

EC_SMB_CK1

EC_SMB_DA1

3 3

EC_SMB_CK2

EC_SMB_DA2

APU_SMB_CLK
APU_SMB_DATA

IT8371D

+3VALW

IT8371D

+3VS

APU

+3VS

EC SM Bus1 address

Device

Battery

Charger

GPU BATT SODIMM WLAN Thermal

X

V

+3VS_VGA

X

X X X X

X

X

V V

EC SM Bus2 address

Address

0X16 1001_100xb

0001 0010 b

Device

Thermal Sensor

GPU

APU Thermal Diode

Address

0x41(default)

TBU

Sensor

X

X

APUIT8371DX

Charger

XV

V

X

V

APU_SIC
APU_SID

1.8VS for CZ
3VS for CZL

TP

V

X

X

X

X

V

Port Device

0

GPP

1
2
3
0

GFX

1
2
3
4
5
6
7

LAN
WLAN

SSD

STRATO
GPU

VRAM

Board ID need to be update!

BOARD
Config.

@
ME@
EMC@
RF@
PX@
PSSD@
SSD@
CHA@
CHB@
DXMIRROR@
NOMIRROR@
8586@
NOBACO@
BACO@
CD@
REV@
TPM@
EMC_NS@
RF_NS@
AOAC@
HDT@
8371@

S2G@
M2G@
H2G@
S1G@
M1G@
H1G@

GPIOxx GPIOxx Function

0 0

BTO ItemBOM Structure

Not stuff

Connector

EMC Part

RF Part

Discrete GPU SKU part

PCIE BUS NGFF SSD

SATA BUS NGFF SSD

VRAM channel A

VRAM channel B

IT8371DX for MIRROR

IT8371/8586 for noMIRROR

IT8586

GPU WITHOUT BACO FUNCTION

GPU WITH BACO FUNCTION

COST DOWN PROPOSAL

RESERVE FOR DEBUG

RESERVE FOR TPM FUNCTION

EMC reserve Part

RF reserve Part

AOAC support part

HDT Debug part

IT8371

X76 SAMSUNG 2G

X76 MICRON 2G

X76 HYNIX 2G

X76 SAMSUNG 1G

X76 MICRON 1G

X76 HYNIX 2G

GPIOxx

0

APU SM Bus address

4 4

Device Address

DDR DIMMA

DDR DIMMB

WLAN

TP

1001 000Xb

1001 010Xb

RSVD

RSVD

A

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2014/10/22

2014/10/22

2014/10/22

Title

Title

Title

Notes List

Notes List

Notes List

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Wednesday, April 29, 2015

Allsparks 5B

Allsparks 5B

Allsparks 5B

E

3 51

3 51

3 51

0.3

0.3

0.3

5

D D

PCIE_PRX_DTX_P028

LAN

WLAN

C C

+0.95VS

GPU

B B

PCIE_PRX_DTX_N028

PCIE_PRX_DTX_P130
PCIE_PRX_DTX_N130

PCIE_PRX_DTX_P230
PCIE_PRX_DTX_N230

PCIE_PRX_DTX_P330
PCIE_PRX_DTX_N330

1 2

RC1 196_0402_1%

PCIE_CRX_GTX_P015
PCIE_CRX_GTX_N015

PCIE_CRX_GTX_P115
PCIE_CRX_GTX_N115

PCIE_CRX_GTX_P215
PCIE_CRX_GTX_N215

PCIE_CRX_GTX_P315
PCIE_CRX_GTX_N315

PCIE_CRX_GTX_P415
PCIE_CRX_GTX_N415

PCIE_CRX_GTX_P515
PCIE_CRX_GTX_N515

PCIE_CRX_GTX_P615
PCIE_CRX_GTX_N615

PCIE_CRX_GTX_P715
PCIE_CRX_GTX_N715

4

PCIE_PRX_DTX_P0
PCIE_PRX_DTX_N0

PCIE_PRX_DTX_P1
PCIE_PRX_DTX_N1

PCIE_PRX_DTX_P2
PCIE_PRX_DTX_N2

PCIE_PRX_DTX_N3

P_TX_ZVDD

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3

PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4

PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5

PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6

PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7

U10

P10

L10

U9

T6
T5

T9
T8

P7
P6

U7

P9

N6
N5

N9
N8

L7
L6

L9

K6
K5

K9
K8

J7
J6

P_GPP_RXP0
P_GPP_RXN0

P_GPP_RXP1
P_GPP_RXN1

P_GPP_RXP2
P_GPP_RXN2

P_GPP_RXP3
P_GPP_RXN3

P_ZVDDP

P_GFX_RXP0
P_GFX_RXN0

P_GFX_RXP1
P_GFX_RXN1

P_GFX_RXP2
P_GFX_RXN2

P_GFX_RXP3
P_GFX_RXN3

P_GFX_RXP4
P_GFX_RXN4

P_GFX_RXP5
P_GFX_RXN5

P_GFX_RXP6
P_GFX_RXN6

P_GFX_RXP7
P_GFX_RXN7

CPU@

UC1B

PCIE

P_GPP_TXP0
P_GPP_TXN0

P_GPP_TXP1
P_GPP_TXN1

P_GPP_TXP2
P_GPP_TXN2

P_GPP_TXP3
P_GPP_TXN3

P_ZVSS/P_RX_ZVDDP

P_GFX_TXP0
P_GFX_TXN0

P_GFX_TXP1
P_GFX_TXN1

P_GFX_TXP2
P_GFX_TXN2

P_GFX_TXP3
P_GFX_TXN3

P_GFX_TXP4
P_GFX_TXN4

P_GFX_TXP5
P_GFX_TXN5

P_GFX_TXP6
P_GFX_TXN6

P_GFX_TXP7
P_GFX_TXN7

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

3

R1
R2

R4
R3

N1
N2

N4
N3

U6

M2
M1

L1
L2

L4
L3

J1
J2

J4
J3

H2
H1

G1
G2

G4
G3

PCIE_PTX_DRX_P0
PCIE_PTX_DRX_N0

PCIE_PTX_DRX_P1
PCIE_PTX_DRX_N1

PCIE_PTX_DRX_P2
PCIE_PTX_DRX_N2

PCIE_PTX_DRX_P3
PCIE_PTX_DRX_N3

P_RX_ZVDD

PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0

PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1

PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2

PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N3

PCIE_CTX_GRX_P4
PCIE_CTX_GRX_N4

PCIE_CTX_GRX_P5
PCIE_CTX_GRX_N5

PCIE_CTX_GRX_P6
PCIE_CTX_GRX_N6

PCIE_CTX_GRX_P7
PCIE_CTX_GRX_N7

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

2

CC130.1U_0402_10V6-K
CC131.1U_0402_10V6-K

CC1.1U_0402_10V6-K
CC2.1U_0402_10V6-K

CC1320.22U_0402_16V6-K PSSD@
CC1330.22U_0402_16V6-K PSSD@

CC1340.22U_0402_16V6-K PSSD@
CC1350.22U_0402_16V6-K PSSD@

RC3196_0402_1%

CC1360.22U_0402_16V6-K PX@
CC1370.22U_0402_16V6-K PX@

CC1380.22U_0402_16V6-K PX@
CC1390.22U_0402_16V6-K PX@

CC1400.22U_0402_16V6-K PX@
CC1410.22U_0402_16V6-K PX@

CC1420.22U_0402_16V6-K PX@
CC1430.22U_0402_16V6-K PX@

CC1440.22U_0402_16V6-K PX@
CC1450.22U_0402_16V6-K PX@

CC1460.22U_0402_16V6-K PX@
CC1470.22U_0402_16V6-K PX@

CC1480.22U_0402_16V6-K PX@
CC1490.22U_0402_16V6-K PX@

CC1500.22U_0402_16V6-K PX@
CC1510.22U_0402_16V6-K PX@

PCIE_PTX_C_DRX_P0
PCIE_PTX_C_DRX_N0

PCIE_PTX_C_DRX_P1
PCIE_PTX_C_DRX_N1

PCIE_PTX_C_DRX_P2
PCIE_PTX_C_DRX_N2

PCIE_PTX_C_DRX_P3PCIE_PRX_DTX_P3
PCIE_PTX_C_DRX_N3

PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0

PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1

PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3

PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4

PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_N5

PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_N6

PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_N7

PCIE_PTX_C_DRX_P0 28
PCIE_PTX_C_DRX_N0 28

PCIE_PTX_C_DRX_P1 30
PCIE_PTX_C_DRX_N1 30

PCIE_PTX_C_DRX_P2 30
PCIE_PTX_C_DRX_N2 30

PCIE_PTX_C_DRX_P3 30
PCIE_PTX_C_DRX_N3 30

For SSD PCIE GEN3,Coupling CAP need 220nF

PCIE_CTX_C_GRX_P0 15
PCIE_CTX_C_GRX_N0 15

PCIE_CTX_C_GRX_P1 15
PCIE_CTX_C_GRX_N1 15

PCIE_CTX_C_GRX_P2 15
PCIE_CTX_C_GRX_N2 15

PCIE_CTX_C_GRX_P3 15
PCIE_CTX_C_GRX_N3 15

PCIE_CTX_C_GRX_P4 15
PCIE_CTX_C_GRX_N4 15

PCIE_CTX_C_GRX_P5 15
PCIE_CTX_C_GRX_N5 15

PCIE_CTX_C_GRX_P6 15
PCIE_CTX_C_GRX_N6 15

PCIE_CTX_C_GRX_P7 15
PCIE_CTX_C_GRX_N7 15

1

LAN

WLAN

SSDSSD

GPU

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2013/08/15

2013/08/15

2013/08/15

2

Title

FP4 (PCIE I/F)

FP4 (PCIE I/F)

FP4 (PCIE I/F)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Allsparks 5B

Allsparks 5B

Allsparks 5B

4 51

4 51

4 51

1

0.3

0.3

0.3

5

4

3

2

1

DDRA_DQ[0..63]

DDRA_DQS[0..7]

DDRA_DQS#[0..7]

DDRA_MA[0..15]

DDRA_DM[0..7]

D D

DDRA_MA0

AE28

DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11
DDRA_MA12
DDRA_MA13
DDRA_MA14
DDRA_MA15

DDRA_BS0#12
DDRA_BS1#12
DDRA_BS2#12

C C

DDRA_CLK012
DDRA_CLK0#12
DDRA_CLK112
DDRA_CLK1#12

MEM_MA_RST#12
MEM_MA_EVENT#12

DDRA_CKE012
DDRA_CKE112

DDRA_ODT012

B B

DDRA_ODT112

DDRA_CS0#12
DDRA_CS1#12

DDRA_RAS#12
DDRA_CAS#12
DDRA_WE#12

APU_MA_VREFDQ12

DDRA_BS0#
DDRA_BS1#
DDRA_BS2#

DDRA_DM0
DDRA_DM1
DDRA_DM2
DDRA_DM3
DDRA_DM4
DDRA_DM5
DDRA_DM6
DDRA_DM7

DDRA_DQS0
DDRA_DQS#0
DDRA_DQS1
DDRA_DQS#1
DDRA_DQS2
DDRA_DQS#2
DDRA_DQS3
DDRA_DQS#3
DDRA_DQS4
DDRA_DQS#4
DDRA_DQS5
DDRA_DQS#5
DDRA_DQS6
DDRA_DQS#6
DDRA_DQS7
DDRA_DQS#7

DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#

MEM_MA_RST#
MEM_MA_EVENT#

DDRA_CKE0
DDRA_CKE1

DDRA_ODT0
DDRA_ODT1

DDRA_CS0#
DDRA_CS1#

DDRA_RAS#
DDRA_CAS#
DDRA_WE#

APU_MA_VREFDQ
+MEM_VREF

MA_ADD0

Y27

MA_ADD1

Y29

MA_ADD2

Y26

MA_ADD3

W28

MA_ADD4

W29

MA_ADD5

W26

MA_ADD6

U29

MA_ADD7

W25

MA_ADD8

U26

MA_ADD9

AG29

MA_ADD10

U27

MA_ADD11

T28

MA_ADD12

AK26

MA_ADD13

T26

MA_ADD14/MA_BG1

T25

MA_ADD15/MA_ACT_L

AG26

MA_BANK0

AG27

MA_BANK1

T29

MA_BANK2/MA_BG0

E19

MA_DM0

D21

MA_DM1

K21

MA_DM2

F29

MA_DM3

AP28

MA_DM4

AV26

MA_DM5

AR22

MA_DM6

BC22

MA_DM7

K29

MA_DM8

H19

MA_DQS_H0

G19

MA_DQS_L0

B22

MA_DQS_H1

A22

MA_DQS_L1

F23

MA_DQS_H2

E23

MA_DQS_L2

G27

MA_DQS_H3

F27

MA_DQS_L3

AP25

MA_DQS_H4

AP26

MA_DQS_L4

AW27

MA_DQS_H5

AV27

MA_DQS_L5

AV22

MA_DQS_H6

AU22

MA_DQS_L6

BA21

MA_DQS_H7

AY21

MA_DQS_L7

L27

MA_DQS_H8

L26

MA_DQS_L8

AE25

MA_CLK_H0

AE26

MA_CLK_L0

AD26

MA_CLK_H1

AD27

MA_CLK_L1

AB28

MA_CLK_H2

AB29

MA_CLK_L2

AB25

MA_CLK_H3

AB26

MA_CLK_L3

N29

MA_RESET_L

AE29

MA_EVENT_L

P27

MA_CKE0

P29

MA_CKE1

AK27

MA0_ODT0

AL26

MA0_ODT1

AH25

MA1_ODT0

AL25

MA1_ODT1

AH26

MA0_CS_L0

AL29

MA0_CS_L1

AH29

MA1_CS_L0

AL28

MA1_CS_L1

AG24

MA_RAS_L/MA_RAS_L_ADD16

AK29

MA_CAS_L/MA_CAS_L_ADD15

AH28

MA_WE_L/MA_WE_L_ADD14

B19

MA_VREFDQ

T32

M_VREF

CPU@

UC1A

MEMORY A

MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15

MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23

MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31

MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39

MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47

MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55

MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

MA_CHECK0
MA_CHECK1
MA_CHECK2
MA_CHECK3
MA_CHECK4
MA_CHECK5
MA_CHECK6
MA_CHECK7

MA_ZVDDIO_MEM_S

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7

MA_DATA8
MA_DATA9

H17
J17
F20
H20
E17
F17
K18
E20

A21
C21
C23
D23
B20
B21
B23
A23

G22
H22
E25
G25
J20
E22
H23
J23

F26
E27
J26
J27
H25
E26
G28
G29

AN26
AP29
AR26
AP24
AN29
AN27
AR29
AR27

AU26
AV29
AU25
AW25
AU29
AU28
AW26
AT25

AV23
AW23
AV20
AW20
AR23
AT23
AR20
AT20

BB23
BB22
BB20
AY19
BA23
BC23
BC21
BB21

K26
K28
N26
N28
J29
K25
L29
N25

AD29

DDRA_DQ0
DDRA_DQ1
DDRA_DQ2
DDRA_DQ3
DDRA_DQ4
DDRA_DQ5
DDRA_DQ6
DDRA_DQ7

DDRA_DQ8
DDRA_DQ9
DDRA_DQ10
DDRA_DQ11
DDRA_DQ12
DDRA_DQ13
DDRA_DQ14
DDRA_DQ15

DDRA_DQ16
DDRA_DQ17
DDRA_DQ18
DDRA_DQ19
DDRA_DQ20
DDRA_DQ21
DDRA_DQ22
DDRA_DQ23

DDRA_DQ24
DDRA_DQ25
DDRA_DQ26
DDRA_DQ27
DDRA_DQ28
DDRA_DQ29
DDRA_DQ30
DDRA_DQ31

DDRA_DQ32
DDRA_DQ33
DDRA_DQ34
DDRA_DQ35
DDRA_DQ36
DDRA_DQ37
DDRA_DQ38
DDRA_DQ39

DDRA_DQ40
DDRA_DQ41
DDRA_DQ42
DDRA_DQ43
DDRA_DQ44
DDRA_DQ45
DDRA_DQ46
DDRA_DQ47

DDRA_DQ48
DDRA_DQ49
DDRA_DQ50
DDRA_DQ51
DDRA_DQ52
DDRA_DQ53
DDRA_DQ54
DDRA_DQ55

DDRA_DQ56
DDRA_DQ57
DDRA_DQ58
DDRA_DQ59
DDRA_DQ60
DDRA_DQ61
DDRA_DQ62
DDRA_DQ63

MA_ZVDDIO

1 2

RC4 39.2_0402_1%

DDRA_DQ[0..63] 12

DDRA_DQS[0..7] 12

DDRA_DQS#[0..7] 12

DDRA_MA[0..15] 12

DDRA_DM[0..7] 12

+1.35V

DDRB_MA[15..0]13

DDRB_BS0#13
DDRB_BS1#13
DDRB_BS2#13

DDRB_DM[7..0]13

DDRB_CLK013
DDRB_CLK0#13
DDRB_CLK113
DDRB_CLK1#13

MEM_MB_RST#13

MEM_MB_EVENT#13

DDRB_CKE013
DDRB_CKE113

DDRB_ODT013
DDRB_ODT113

DDRB_CS0#13
DDRB_CS1#13

DDRB_RAS#13
DDRB_CAS#13
DDRB_WE#13

APU_MB_VREFDQ13

DDRB_MA0
DDRB_MA1
DDRB_MA2
DDRB_MA3
DDRB_MA4
DDRB_MA5
DDRB_MA6
DDRB_MA7
DDRB_MA8
DDRB_MA9
DDRB_MA10
DDRB_MA11
DDRB_MA12
DDRB_MA13
DDRB_MA14
DDRB_MA15

DDRB_BS0#
DDRB_BS1#
DDRB_BS2#

DDRB_DM0
DDRB_DM1
DDRB_DM2
DDRB_DM3
DDRB_DM4
DDRB_DM5
DDRB_DM6
DDRB_DM7

DDRB_DQS0
DDRB_DQS#0
DDRB_DQS1
DDRB_DQS#1
DDRB_DQS2
DDRB_DQS#2
DDRB_DQS3
DDRB_DQS#3
DDRB_DQS4
DDRB_DQS#4
DDRB_DQS5
DDRB_DQS#5
DDRB_DQS6
DDRB_DQS#6
DDRB_DQS7
DDRB_DQS#7

DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#

MEM_MB_RST#
MEM_MB_EVENT#

DDRB_CKE0
DDRB_CKE1

DDRB_ODT0
DDRB_ODT1

DDRB_CS0#
DDRB_CS1#

DDRB_RAS#
DDRB_CAS#
DDRB_WE#

APU_MB_VREFDQ

AG31
AC30
AC31
AB32
AA32
AA33
AA31

AA30

AG32

AL31

AH32
AG33

AR30

AW30

BC30
BC26

AR32

AR33
AW32
AW33

BA29

AY29

BA25

AY25

AE33

AE32

AE30

AE31

AD32

AD33

AC33

AC32

AG30

AL30

AM32

AJ32

AM33

AJ33

AL32

AJ30

AL33

AH33

AK32

W32

W33

W30

W31

AJ31

DDRB_DQS[0..7]

DDRB_DQS#[0..7]

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6

Y33

MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10

Y32

MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14/MB_BG1

V32

MB_ADD15/MB_ACT_L

MB_BANK0
MB_BANK1
MB_BANK2/MB_BG0

D25

MB_DM0

D29

MB_DM1

E33

MB_DM2

J33

MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7

N33

MB_DM8

B26

MB_DQS_H0

A26

MB_DQS_L0

B30

MB_DQS_H1

A30

MB_DQS_L1

F32

MB_DQS_H2

E32

MB_DQS_L2

K32

MB_DQS_H3

J32

MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7

P32

MB_DQS_H8

N32

MB_DQS_L8

MB_CLK_H0
MB_CLK_L0
MB_CLK_H1
MB_CLK_L1
MB_CLK_H2
MB_CLK_L2
MB_CLK_H3
MB_CLK_L3

T33

MB_RESET_L
MB_EVENT_L

U32

MB_CKE0

U33

MB_CKE1

MB0_ODT0
MB0_ODT1
MB1_ODT0
MB1_ODT1

MB0_CS_L0
MB0_CS_L1
MB1_CS_L0
MB1_CS_L1

MB_RAS_L/MB_RAS_L_ADD16
MB_CAS_L/MB_CAS_L_ADD15
MB_WE_L/MB_WE_L_ADD14

A19

MB_VREFDQ

CPU@

UC1I

MEMORY B

MB_ZVDDIO_MEM_S

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7

MB_DATA8

MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15

MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23

MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31

MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39

MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47

MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55

MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

MB_CHECK0
MB_CHECK1
MB_CHECK2
MB_CHECK3
MB_CHECK4
MB_CHECK5
MB_CHECK6
MB_CHECK7

DDRB_DQS[0..7] 13

DDRB_DQS#[0..7] 13

DDRB_DQ0

A25

DDRB_DQ1

C25

DDRB_DQ2

C27

DDRB_DQ3

D27

DDRB_DQ4

B24

DDRB_DQ5

B25

DDRB_DQ6

B27

DDRB_DQ7

A27

DDRB_DQ8

A29

DDRB_DQ9

C29

DDRB_DQ10

B32

DDRB_DQ11

D32

DDRB_DQ12

B28

DDRB_DQ13

B29

DDRB_DQ14

A31

DDRB_DQ15

C31

DDRB_DQ16

E30

DDRB_DQ17

E31

DDRB_DQ22

G33

DDRB_DQ23

G32

DDRB_DQ20

C33

DDRB_DQ21

D33

DDRB_DQ19

G30

DDRB_DQ18

G31

DDRB_DQ24

J30

DDRB_DQ25

J31

DDRB_DQ26

L33

DDRB_DQ27

L32

DDRB_DQ29

H32

DDRB_DQ28

H33

DDRB_DQ30

L30

DDRB_DQ31

L31

DDRB_DQ36

AN31

DDRB_DQ32

AP32

DDRB_DQ39

AT32

DDRB_DQ35

AU32

DDRB_DQ33

AN33

DDRB_DQ37

AN32

DDRB_DQ34

AR31

DDRB_DQ38

AT33

DDRB_DQ41

AU30

DDRB_DQ44

AV32

DDRB_DQ43

BA33

DDRB_DQ47

AY32

DDRB_DQ45

AU33

DDRB_DQ40

AU31

DDRB_DQ46

AW31

DDRB_DQ42

AY33

DDRB_DQ54

BC31

DDRB_DQ53

BB30

DDRB_DQ50

BB28

DDRB_DQ52

AY27

DDRB_DQ49

BB32

DDRB_DQ48

BA31

DDRB_DQ51

BC29

DDRB_DQ55

BB29

DDRB_DQ60

BB27

DDRB_DQ57

BB26

DDRB_DQ58

BB24

DDRB_DQ59

AY23

DDRB_DQ61

BA27

DDRB_DQ56

BC27

DDRB_DQ63

BC25

DDRB_DQ62

BB25

N30
N31
R33
R32
M32
M33
R30
R31

MB_ZVDDIO

AF32

DDRB_DQ[63..0] 13

DATA16--DATA23 Byte internal swap

DATA24--DATA31 Byte internal swap

DATA32--DATA39 Byte internal swap

DATA40--DATA47 Byte internal swap

DATA48--DATA55 Byte internal swap

DATA56--DATA63 Byte internal swap

+1.35V

1 2

RC5 39.2_0402_1%

+1.35V

12

RC6

1K_0402_1%

A A

1K_0402_1%

RC8

@

12

1

1

2

2

.47U_0402_6.3V6K

CC21

CC22

5

+MEM_VREF

1

2

.1U_0402_10V6-K

1000P_0402_50V7K

CC23

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/15

2013/08/15

2013/08/15

Title

FP4 (MEM)

FP4 (MEM)

FP4 (MEM)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Allsparks 5B

Allsparks 5B

Allsparks 5B

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

5 51

5 51

1

5 51

0.3

0.3

0.3

5

+1.8VS

12

RC14
300_0402_5%

EC_SMB_CK216,31,35

EC_SMB_DA216,31,35

+1.8VS

+1.8VS

RC45
1K_0402_5%

HDT@

1 2

HDT@

12

APU_RST#

1

CC24
150P_0402_50V8-J

@

2

RC15
300_0402_5%

PWROK

1

CC25
150P_0402_50V8-J

@

2

RC48 33_0402_5%HDT@

2

CC27
.01U_0402_16V7-K

1

+1.8VS

6 1

1 2

5

2

1K_0404_4P2R_5%

G

S

D

QC23A

5

DMN5L06DWK-7 2N SOT363-6

G

3 4

D

QC23B
DMN5L06DWK-7 2N SOT363-6

APU_TRST#_R

RPC18
10K_0804_8P4R_5%

HDT@

1 8

2 7

3 6

4 5

APU_HDMI_TX2+26
APU_HDMI_TX2-26

APU_HDMI_TX1+26

HDMI eDP

eDP

+1.8VS

RPC4

1 4

2 3

APU_SIC

S

APU_SID

APU_HDMI_TX1-26

APU_HDMI_TX0+26
APU_HDMI_TX0-26

APU_HDMI_CLK+26
APU_HDMI_CLK-26

APU_EDP_TX0+25
APU_EDP_TX0-25

APU_EDP_TX1+25
APU_EDP_TX1-25

APU_SVT51
APU_SVC51
APU_SVD51

GFX_SVT50
GFX_SVC50
GFX_SVD50

APU_PWROK50,51

H_PROCHOT#35,43

With HDT+ Header

JHDT1

@

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

RC2544 33_0402_5%

18

18

20

20

APU_TCK

APU_TMS

APU_TDI

APU_TDO

APU_PWROK_BUF

APU_RST#_BUF

APU_DBRDY

HDT@

1 2

APU_TEST19_PLLTEST0

APU_TEST18_PLLTEST1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

SAMTE_ASP-136446-07-B

D D

PLACE CC24 CAPS CLOSE TO APU,CRB reserve 27pf

PLACE CC25 CAPS CLOSE TO APU,CRB reserve 27pf

C C

B B

APU_TRST#

A A

4

APU_HDMI_TX2+
APU_HDMI_TX2-

APU_HDMI_TX1+
APU_HDMI_TX1-

APU_HDMI_TX0+
APU_HDMI_TX0-

APU_HDMI_CLK+
APU_HDMI_CLK-

APU_EDP_TX0+
APU_EDP_TX0-

APU_EDP_TX1+
APU_EDP_TX1-

RC22 0_0402_5%

1 2
1 2

RC23 0_0402_5%
RC24 0_0402_5%

1 2

1 2

RC25 0_0402_5%
RC26 0_0402_5%

1 2
1 2

RC28 0_0402_5%

RC186 0_0402_5%

1 2

1 2

RC184 0_0402_5%

+1.8VS+1.8VS

RPC6

18
27
36
45

1K_0804_8P4R_5%

HDT@

HDT@

4

APU_SVT_R
APU_SVC_R
APU_SVD_R

APU_GFX_SVT_R
APU_GFX_SVC_R
APU_GFX_SVD_R

APU_SIC
APU_SID

APU_RST#
PWROK

APU_PROCHOT#_R
ALERT#

APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#

2

CC176
.01U_0402_16V7-K

1

APU_PWROK

APU_RST#

APU_TDIAPU_DBREQ# APU_DBREQ#

2

CC175

@

.01U_0402_16V7-K

1

C15
D17
D19

B15
B16
A18

B18
C17

D15
C19

A15
B17

H15
H14
D13
G15
J14
C13
A11

B6
A6

D7
C7

A7
B7

D9
C9

A2
A3

B4
A4

D5
C5

A5
B5

E2
E1

E3
E4

D1
D2

C1
B1

DP2_TXP0
DP2_TXN0

DP2_TXP1
DP2_TXN1

DP2_TXP2
DP2_TXN2

DP2_TXP3
DP2_TXN3

DP1_TXP0
DP1_TXN0

DP1_TXP1
DP1_TXN1

DP1_TXP2
DP1_TXN2

DP1_TXP3
DP1_TXN3

DP0_TXP0
DP0_TXN0

DP0_TXP1
DP0_TXN1

DP0_TXP2
DP0_TXN2

DP0_TXP3
DP0_TXN3

SVT0
SVC0
SVD0

SVT1
SVC1
SVD1

SIC
SID

RESET_L
PWROK

PROCHOT_L
ALERT_L

TDI
TDO
TCK
TMS
TRST_L
DBRDY
DBREQ_L

CPU@

UC1C

DISPLAY/SVI2/JTAG/TEST

DP_AUX_ZVSS

TEMPINRETURN

DP_STEREOSYNC/TEST36

VDDCR_GFX_SENSE

VDDCR_NB_SENSE

VDDCR_CPU_SENSE

VDDP_SENSE

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

1

CC26

.1U_0402_10V6-K HDT@

2

UC2

3

2A

2

GND

1

1A

SN74LVC2G07YZPR_WCSP6HDT@

DP_ZVSS

DP_BLON

DP_DIGON

DP_VARY_BL

DP2_AUXP
DP2_AUXN

DP2_HPD

DP1_AUXP
DP1_AUXN

DP1_HPD

DP0_AUXP
DP0_AUXN

DP0_HPD

RSVD_1
TEMPIN0
TEMPIN1
TEMPIN2

TEST410
TEST411

TEST4
TEST5
TEST6

TEST9
TEST10
TEST14
TEST15
TEST16
TEST17
TEST11
TEST18
TEST19

TEST28_H
TEST28_L

TEST31

TEST37

VSS_SENSE

4

2Y

5

VCC

6

1Y

3

DP_2K_ZVSS

A9

DP_150_ZVSS

B9

DP_ENBKL

G5

DP_ENVDD

G6

DP_EDP_PWM

F11

H9
G9
E9

APU_DDC_CLK

F7

APU_DDC_DATA

E7

APU_HDMI_HPD

F5

APU_EDP_AUX

F8

APU_EDP_AUX#

E8

APU_EDP_HPD

G8

K24

CORETYPE

E15
E14
E12
F14
AK24

TEST410

AL24

TEST411

P24

TEST4

N24

TEST5

AN24
AB8
Y9

APU_TEST14_BP0

B10

APU_TEST15_BP1

D11

APU_TEST16_BP2

A10

APU_TEST17_BP3

C11

APU_TEST11_BP4

B11

APU_TEST18_PLLTEST1

A14

APU_TEST19_PLLTEST0

B14

APU_TEST28_H_PLLCHARZ

A13

APU_TEST28_L_PLLCHARZ

B13

APU_TEST31_MEM_TEST

P26

APU_TEST36_STEREOSYNC

E11

APU_TEST37

A17

GFX_CORE_SEN

H11

APU_VDDNB_SEN_H

J12

APU_VDD_SEN_H

G12

VDD_095_FB_H

AY18

APU_VSS_SEN_L

H12

+1.8VS+1.8VS

3

RC11 2K_0402_1%
RC12 150_0402_1%

RPC26
1K_0404_4P2R_5%

HDT@

1 4

2 3

APU_PWROK_BUF

APU_RST#_BUF

2

For Carrzio
DisplayPort Auxiliary Channel pins are dual-mode pins and are 3.3V tolerant.
In I2C mode AUXP pins change to SCL, and AUXN pins change to SDA.
During this operation the pin type is B-IO33-OD. FDS

1 2
1 2

For Carrzio,
Hot Plug Detect pins is I-IO18-S,but 3.3V tolerant.
DP_VARY_BL, DP_BLON, DP_DIGON signals are VDD_18 level at the APU

APU_DDC_CLK 26
APU_DDC_DATA 26
APU_HDMI_HPD 26

APU_EDP_AUX 25
APU_EDP_AUX# 25
APU_EDP_HPD 25

TC7@

1

TC8@

1
1

TC9@
TC10@

1
1

TC11@

RC17 1K_0402_5%@

1 2

1

TC12@

RC19 1K_0402_5%@

1 2

RC20 1K_0402_5%@

1 2
1 2

RC21 1K_0402_5%@

1

TC13@
TC14@

1
1

TC15@

GFX_CORE_SEN 50
APU_VDDNB_SEN_H 51
APU_VDD_SEN_H 51

1

@

TC16

1 2

RC36 0_0402_5%

RC2538 0_0402_5%

1 2

RC37 0_0402_5%

1 2

HDMI

23
14

RPC3 1K_0404_4P2R_5%

1 2

RC29 1K_0402_5%@
RC30 1K_0402_5%

1 2

RC31 1K_0402_5%@

1 2
1 2

RC32 1K_0402_5%@

APU_VDD_SEN_L 51

APU_VDDNB_SEN_L 51

GFX_VSS_SEN 50

APU_VDDNB_SEN_H

APU_VDD_SEN_H

APU_VDD_SEN_L

GFX_CORE_SEN

GFX_VSS_SEN

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1

1

1

1

1

+1.8VS

TC17@

TC18@

TC19@

TC20@

TC21@

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

2

DP_EDP_PWM

Follow CRB @

Deciphered Date

Deciphered Date

Deciphered Date

1

APU_DDC_CLK
APU_DDC_DATA

APU_EDP_HPD

ALERT#
APU_PROCHOT#_R

CORETYPE

To EDP panel

+3VALW

2

G

12

DP_ENVDD

12

RC33

4.7K_0402_5%

@

RC43
100K_0402_5%

S

+3VALW

QC25A

DMN5L06DWK-7 2N SOT363-6

2

G

S

@

LCD Power IC can reserve,as IC EN VIH>=1.5V

+3VALW

QC26A

DMN5L06DWK-7 2N SOT363-6

DP_ENBKL

2

G

12

RC49
100K_0402_5%

@

S

@

PCH_ENBKL can to con EC ADC pin for CZ cost down because 1.8V level

2013/08/15

2013/08/15

2013/08/15

RC9 2K_0402_5%
RC10 2K_0402_5%

RC13 100K_0402_5%

+3VS

RC18
10K_0402_5%

1 2

5

G

61

D

QC24A
DMN5L06DWK-7 2N SOT363-6

1 2

RC34 0_0402_5%@

+3VS

RC39
10K_0402_5%

@

1 2

5

G

61

@

D

RC44 0_0402_5%

1 2

+3VS

1 2

RC47
10K_0402_5%

@

1 2

34

D

5

G

S

61

@

D

RC50 0_0402_5%

1 2

FP4 (DISPLAY/CLK/MISC)

FP4 (DISPLAY/CLK/MISC)

FP4 (DISPLAY/CLK/MISC)

Custom

Custom

Custom

1 2
1 2

1 2

RPC1

23
14

1K_0404_4P2R_5%

RC2537 100K_0402_5%

1 2

@

12

RC16

4.7K_0402_5%

QC24B

34

DMN5L06DWK-7 2N SOT363-6

D

S

12

RC38

4.7K_0402_5%

@

34

D

QC25B

S

DMN5L06DWK-7 2N SOT363-6

RC46

2.2K_0402_5%

@

PCH_ENBKL 25

QC26B
DMN5L06DWK-7 2N SOT363-6

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet

Allsparks 5B

Allsparks 5B

Allsparks 5B

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

1

+3VS_APU

+1.8VS

+3VALW_APU

PCH_EDP_PWM 25

PCH_ENVDD 25

6 51

6 51

6 51

0.3

0.3

0.3

of

5

1 2

RC56 33_0402_5%

RB751V-40_SOD323-2@

12

10K_0402_5%

DC2

12

DC4

SYS_PWRGD_RSYS_RESET#

@

RC51 33_0402_5%

1

CC28
150P_0402_50V8-J

2

1 2

1

CC29
150P_0402_50V8-J

2

+1.8VALW

RC63
1K_0402_5%

1 2

RSMRST#_R

2

CC30
.1U_0402_10V6-K

1

+1.8VS

12

RC68

@

SYS_PWRGD_R

1

CC31
1U_0402_6.3V6K

@

2

PCIE_WAKE# 30,35

APU_LPC_RST#35,36

PLT_RST#15,28,30

D D

EC_RSMRST#35

RSMRST# VDD_18_S5 power rail
Connected to 10-ms RC-delay circuit on VDD_18_S5 power rail.
(CRB PWR Dealy: 22K/0.1uF)

C C

EC_SYS_PWRGD35

I2C Bus, CZ have, 1.8V ;
CZL only have GPIO function, 3.3V.
so for common design, it's should not be GPIO setting

PCIE_WAKE#_RA

RC70 0_0402_5%

AGPIO5

B B

+3VALW_APU

12

RC2542
100K_0402_5%@

12

RC57
100K_0402_5%@

1 2

DC1

RC187 0_0402_5%

@

1 2

RB751V-40_SOD323-2

RC69 0_0402_5%

1 2

RB751V-40_SOD323-2

12

12

RC71

@

0_0402_5%

DC3

12

RB751V-40_SOD323-2

@

LPC_RST#_R

PCIE_RST#_R

PBTN_OUT#35

SYS_RESET#11

PM_SLP_S3#35
PM_SLP_S5#35

4

3

2

1

04/23 For TP SMBUS channel change

Q178A

APU_SMB_CLK2

UC1D

LPC_RST#_R
PCIE_RST#_R

RSMRST#_R

PWRBTN#_RPBTN_OUT#

12

RC64 0_0402_5%

PM_SLP_S3#

RC65 0_0402_5%

PM_SLP_S5#

RC66 0_0402_5%

APU_S5_MUX_CTRL9

KBRST#35
GATEA2035
EC_SCI#35

1 2

RC2551

AC_PRESENT16,35

HDA_SDIN034

SUSCLK11,30

@

0_0402_5%

LAN_CLKREQ0#28

WLAN_CLKREQ1#30

SSD_CLKREQ2#30

PCH_BT_OFF#30

GPU_CLKREQ#16

USB_OC1#32
USB_OC2#36

RC76 0_0402_5%

RPC11

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

1

CC32

2

12
12

TC47 @

AC_PRES

12

RC84

1 2

20M_0402_5%

YC1

1 2

202983-PG14

Max ESR < 65K ohm !!

18P_0402_50V8J

SYS_PWRGD_R
SYS_RESET#
PCIE_WAKE#_RA

PM_SLP_S3#_R
PM_SLP_S5#_R

AGPIO10
APU_S5_MUX_CTRL

TEST0
TEST1
TEST2

KBRST#

1

BOARD_ID1

IR_LED_L
LAN_CLKREQ0#
WLAN_CLKREQ1#
SSD_CLKREQ2#
PCH_BT_OFF#
GPU_CLKREQ#
BOARD_ID0
USB_OC1#
USB_OC2#

HDA_BITCLK
HDA_SDIN0_R
HDA_SDIN1
HDA_SDIN2
HDA_RST#
HDA_SYNC
HDA_SDOUT

I2C0SCl
I2C0SDA
I2C1SCL
I2C1SDA

BB12

LPC_RST_L

AN7

PCIE_RST_L/EGPIO26

AE4

RSMRST_L

AE1

PWR_BTN_L/AGPIO0

BC9

PWR_GOOD

AF2

SYS_RESET_L/AGPIO1

AG2

WAKE_L/AGPIO2

AK7

SLP_S3_L

AH5

SLP_S5_L

AE8

S0A3_GPIO/AGPIO10

AH8

S5_MUX_CTRL/EGPIO42

AH6

TEST0

AK8

TEST1/TMS

AE3

TEST2

AY15

ESPI_RESET_L/KBRST_L/AGPIO129

BC19

GA20IN/AGPIO126

AD7

LPC_PME_L/AGPIO22

BB13

LPC_SMI_L/AGPIO86

AG3

AC_PRES/USB_OC4_L/IR_RX0/AGPIO23

AD5

IR_TX0/USB_OC5_L/AGPIO13

AL8

IR_TX1/USB_OC6_L/AGPIO14

AN8

IR_RX1/AGPIO15

AE2

IR_LED_L/LLB_L/AGPIO12

BC15

CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92

BB17

CLK_REQ1_L/AGPIO115

BC17

CLK_REQ2_L/AGPIO116

BB18

CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131

BB16

CLK_REQG_L/OSCIN/EGPIO132

AH9

USB_OC0_L/TRST_L/AGPIO16

AG1

USB_OC1_L/TDI/AGPIO17

AH2

USB_OC2_L/TCK/AGPIO18

AL9

USB_OC3_L/TDO/AGPIO24

AU6

AZ_BITCLK/I2S_BCLK_MIC

AR8

AZ_SDIN0/I2S_DATA_MIC0

AP6

AZ_SDIN1/I2S_LR_PLAYBACK

AR5

AZ_SDIN2/I2S_DATA_MIC1

AU9

AZ_RST_L/I2S_LR_MIC

AT9

AZ_SYNC/I2S_BCLK_PLAYBACK

AR7

AZ_SDOUT/I2S_DATA_PLAYBACK

BB10

I2C0_SCL/EGPIO145

BB9

I2C0_SDA/EGPIO146

BB7

I2C1_SCL/EGPIO147

BC7

I2C1_SDA/EGPIO148

AG7

32K_X1

32K_X2

RTCCLK

AT1

X32K_X1

AT2

X32K_X2

CPU@

1

CC33

2

18P_0402_50V8J

ACPI/SD/AZ/GPIO/RTC/I2C/UART/MISC

UART1_CTS_L/BT_I2S_BCLK/EGPIO140

UART1_RXD/BT_I2S_SDI/EGPIO141

UART1_TXD/BT_I2S_SDO/EGPIO143

UART1_INTR/BT_I2S_LRCLK/AGPIO144

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

SD0_WP/EGPIO101

SD0_PWR_CTRL/AGPIO102

SD0_CD/AGPIO25

SD0_CLK/EGPIO95

SD0_CMD/EGPIO96

SD0_DATA0/EGPIO97
SD0_DATA1/EGPIO98
SD0_DATA2/EGPIO99

SD0_DATA3/EGPIO100

SD0_LED/EGPIO93

SCL0/I2C2_SCL/EGPIO113
SDA0/I2C2_SDA/EGPIO114

SCL1/I2C3_SCL/AGPIO19
SDA1/I2C3_SDA/AGPIO20

AGPIO3
AGPIO4
AGPIO5

AGPIO6/LDT_RST_L

AGPIO7/LDT_PWROK

AGPIO8
AGPIO9

VDDGFX_PD/AGPIO39

AGPIO40
AGPIO64
AGPIO65

AGPIO66/SHUTDOWN_L

AGPIO68/SGPIO_CLK

AGPIO69/SGPIO_LOAD

AGPIO71/SGPIO_DATAOUT

AGPIO72/SGPIO_DATAIN

SPKR/AGPIO91

BLINK/USB_OC7_L/AGPIO11

GENINT1_L/AGPIO89
GENINT2_L/AGPIO90

FANIN0/AGPIO84

FANOUT0/AGPIO85

UART0_CTS_L/EGPIO135

UART0_RXD/EGPIO136

UART0_RTS_L/EGPIO137

UART0_TXD/EGPIO138

UART0_INTR/AGPIO139

UART1_RTS_L/EGPIO142

BB2
BB5
BC2
BB4
AY5

BC3
BA3
BC5
BA5
BB6

BA15
AY17

AG5
AG4

AL5
AL6
AJ1
AJ3
AH1
AJ4
AK5
AD8
AG8
AW15
AU15

AT15
AU12
AT14
AR14
BC13

BA17

AN5

BB14
BA19

BC18
BB19

AY9
AW8
AV5
AV8
AW9

AV11
AU7
AT11
AR11
AP9

@

SD_WP
SD_PWR_CNTL
SD_CD#
SD_CLK_R
SD_CMD_R

SD_DATA0_R
SD_DATA1_R
SD_DATA2_R
SD_DATA3_R
SD_LED

APU_SMB_CLK
APU_SMB_DATA

APU_SMB_CLK2
APU_SMB_DATA2

AGPIO3

AGPIO5
LDT_RST_L
LDT_PWROK

AGPIO8

VDDGFX_PD
AGPIO40

VR_GFX_PWRGD

APU_SHUTDOWN#

PXS_RST#_R

HVB_EN
VR_VGA_PWRGD

PXS_PWREN_R
PCH_WLAN_OFF#

1

TC22

@

1

TC23

1

@

TC24

@

1

TC25

1

@

TC26

1

TC27@

1

TC28@

1

TC29@

1

TC30@

1

TC31@

APU_SMB_CLK 12,13,30
APU_SMB_DATA 12,13,30

AGPIO3 11

1

TC32@

1

TC33@

VDDGFX_PD 35

VR_GFX_PWRGD 35,50
PEDET 30

APU_SHUTDOWN# 16

1 2

RC74 0_0402_5%PX@

1 2

RC2539 0_0402_5%BOAC@

PCH_BEEP 34

BLINK 11

HVB_EN 11
VR_VGA_PWRGD 15,49

1 2

RC75 1K_0402_5%PX@

PCH_WLAN_OFF# 30

UART Bus:

1.8V CZ, no signla for CZL
it's should not be GPIO setting

APU_SMB_DATA2

DIMM1, DIMM2, WLAN,TP
SCL0/SDA0 is the SMBus port in the S0 power domain
SCL1/SDA1 is the SMBus port in the S5 power domain

2N7002KDWH_SOT363-6

6 1

D

3 4

D

2N7002KDWH_SOT363-6

Q178B

PXS_RST# 15

PX_EN 15,19

PXS_PWREN 19,48,49

G

2

5

G

S

S

PM_SLP_S3#
PM_SLP_S5#

USB_OC1#
USB_OC2#

APU_SMB_CLK2
APU_SMB_DATA2

APU_SMB_CLK
APU_SMB_DATA

KBRST#

PCH_BT_OFF#
PCH_WLAN_OFF#

LAN_CLKREQ0#
WLAN_CLKREQ1#
SSD_CLKREQ2#

GPU_CLKREQ#
APU_SHUTDOWN#

PCIE_WAKE#_RA
AC_PRES
AGPIO5
PBTN_OUT#

VDDGFX_PD
IR_LED_L

RPC28

14
23

2.2K_0404_4P2R_5%

APU_SMB_CLK2
APU_SMB_DATA2

RC89 2.2K_0402_5%@
RC90 2.2K_0402_5%@

RC2533 10K_0402_5%
RC2534 10K_0402_5%
RC2535 10K_0402_5%

RC79 10K_0402_5%@
RC80 100K_0402_5%@

RC88 10K_0402_5%@
RC2530 10K_0402_5%

TP_SMB_CLK 36

+3VS+3VS

TP_SMB_DAT 36

RPC7

1 4
2 3

@

10K_0404_4P2R_5%

1 2
1 2

RPC13

1 4
2 3

10K_0404_4P2R_5%

RPC27

23
14

2.2K_0404_4P2R_5%

RPC8

23
14

2.2K_0404_4P2R_5%
RPC9

18
27
36
45

10K_0804_8P4R_5%

1 2
1 2
1 2

PSSD@

1 2
1 2

RPC12

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

1 2
1 2

+3VALW

+3VALW_APU

+3VS_APU

+3VALW_APU

5

RC83

2.2K_0402_5%

@

1 2

TEST0
TEST1
TEST2

RC87
15K_0402_5%

1 2

PXS_PWREN_R
PXS_RST#_R

VR_VGA_PWRGD

PXS_PWREN_R
PXS_RST#_R

VR_VGA_PWRGD

SYS_RESET#

2

CC184
.1U_0402_10V6-K

1

EMC@

HDA_RST#
HDA_SYNC
HDA_SDOUT

RC2552

1K_0402_5%

RC2553

1K_0402_5%

RC2554

1K_0402_5%

1 2

1 2

1 2

0303 ADD for AMD HDA sequence workround

4

+3VALW_APU

HDA_SDIN1
HDA_SDIN2

AGPIO8
AGPIO40

AGPIO10

GPU_CLKREQ#

HDA_BITCLK
HDA_SDIN0_R

RSMRST#_R
SYS_PWRGD_R
VDDGFX_PD

Title

Title

Title

FP4 (GEVENT/GPIO/SD/AZ)

FP4 (GEVENT/GPIO/SD/AZ)

FP4 (GEVENT/GPIO/SD/AZ)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet

1 2

1 2

Deciphered Date

Deciphered Date

Deciphered Date

RC53
10K_0402_5%

128@

RC59
10K_0402_5%

256@

2013/08/15

2013/08/15

2013/08/15

RPC15

HDA_RST_AUDIO#34
HDA_SYNC_AUDIO34
HDA_BITCLK_AUDIO34
HDA_SDOUT_AUDIO34

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

3

HDA_RST#
HDA_SYNC
HDA_BITCLK
HDA_SDOUT

Only Cz pin(AGPIO66/ShutDown_L )have ShutDown_L function,
inter pull down for Cz,pull high for Czl

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

BOARD_ID0
BOARD_ID1

2013/08/15

2013/08/15

2013/08/15

RC52
10K_0402_5%

PSSD@

1 2

RC58
10K_0402_5%

SSD@

1 2

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

2

RPC24

1 4
2 3

10K_0404_4P2R_5%
RPC23

1 4
2 3

10K_0404_4P2R_5%

1 2

RC97 10K_0402_5%

1 2

RC100 10K_0402_5%

RC102 1K_0402_5%
RC103 10K_0402_5%@

RC106 100K_0402_5%
RC107 100K_0402_5%
RC2536 100K_0402_5%

12

1 2

1 2
1 2
1 2

@

Allsparks 5B

Allsparks 5B

Allsparks 5B

1

7 51

7 51

7 51

0.3

0.3

0.3

of

RC81

2.2K_0402_5%

@

1 2

RC85
15K_0402_5%

1 2

+3VS_APU

RC91 10K_0402_5%PX@
RC92 10K_0402_5%@

A A

RC94 10K_0402_5%@

RC95 100K_0402_5%@
RC96 100K_0402_5%PX@
RC98 2K_0402_5%@

1 2
1 2
1 2

1 2
1 2
1 2

RC82

2.2K_0402_5%

@

1 2

RC86
15K_0402_5%

1 2

5

SATA_PTX_DRX_P033
SATA_PTX_DRX_N033

HDD

SATA_PRX_DTX_N033
SATA_PRX_DTX_P033

SATA_PTX_DRX_P130
SATA_PTX_DRX_N130

SSD

SATA_PRX_DTX_N130

CLK0_PCI_EC11,35

CLK1_PCI_TPM11,36

SPI_CLK35
SPI_CS0#35

SPI_SO35

SPI_SI35

48M_X1

48M_X2

1

CC37
10P_0402_50V8J

2

LPC_PD

SATA1_DEVSLP_R

SATA0_DEVSLP_R
AGPIO76

SATA_PRX_DTX_P130

+0.95VS

SSD_DEVSLP_R30

+3VS_APU

SATA_LED#36

CLK_PCIE_GPU CLK_PCIE_GPU_R
CLK_PCIE_GPU# CLK_PCIE_GPU#_R

CLK_PCIE_LAN CLK_PCIE_LAN_R

CLK_PCIE_WLAN CLK_PCIE_WLAN_R

SPI_CLK
SPI_CS0#

SPI_SO
SPI_SI
SPI_WP#
SPI_HOLD#

RC109 1K_0402_1%
RC110 1K_0402_1%

RC180 10K_0402_5%@
RC112 10K_0402_5%@
RC2545 0_0402_5%

1 2

RC113 0_0402_5%PX@

1 2

RC114 0_0402_5%PX@

1 2

RC117 0_0402_5%

1 2

RC118 0_0402_5%

1 2

RC115 0_0402_5%

1 2

RC116 0_0402_5%

1 2

RC176 0_0402_5%PSSD@

1 2

RC177 0_0402_5%PSSD@

1 2

RC122 0_0402_5%

1 2

RC181 22_0402_5%

LPC_AD035,36
LPC_AD135,36
LPC_AD235,36
LPC_AD335,36

LPC_FRAME#11,35,36

SERIRQ35,36

RC124 0_0402_5%
RC125 0_0402_5%
RC182 10K_0402_5%
RC126 0_0402_5%
RC127 0_0402_5%
RC128 0_0402_5%
RC129 0_0402_5%

SPI_CS0#
SPI_SO
SPI_WP#

+VCC_SPI

1 4
2 3

1 2

RC2543 10K_0402_5%

D D

RC109 RC110 place to cpu within 1000mil

GPU

LAN

WLAN

SSD

C C

B B

A A

48MHz/10pF Crystal

1 2

RC130 1M_0402_5%

YC2

1

OSC1

1

2

NC12OSC2

48MHZ_10PF_7V48000017
CC36
10P_0402_50V8J

1 2

RC2527 10K_0402_5%

1 2

RC2526 10K_0402_5%

RPC22

1 4
2 3

10K_0404_4P2R_5%

CLK_PCIE_GPU15
CLK_PCIE_GPU#15

CLK_PCIE_LAN28
CLK_PCIE_LAN#28

CLK_PCIE_WLAN30
CLK_PCIE_WLAN#30

CLK_PCIE_SSD30
CLK_PCIE_SSD#30

4

NC2

3

5

4

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0

SATA_PTX_DRX_P1
SATA_PTX_DRX_N1

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1

1 2
1 2

1 2
1 2

1 2

12

DC5

@

TC37 @

1 2
1 2
1 2
1 2
1 2
1 2
1 2

QUAD@
QUAD@

8MB ROM

UC4

1

/CS

2

DO(IO1)

3

/WP(IO2)

4

GND

W25Q64FWSSIQ_SO8

RPC25

SPI_WP#
SPI_HOLD#

10K_0404_4P2R_5%

SPI_CS0#

4

3

UC1E

AU3

SATA_TX0P

AU4

SATA_TX0N

AV1

SATA_RX0N

AV2

SATA_RX0P

AY2

SATA_TX1P

AY1

SATA_TX1N

AW4

SATA_RX1N

AW3

SATA_CALRN
SATA_CALRP
SATA0_DEVSLP_R USB20_N3
SATA1_DEVSLP_R
SATA_ACT_L

RB751V-40_SOD323-2

CLK_PCIE_LAN#_RCLK_PCIE_LAN#

CLK_PCIE_WLAN#_RCLK_PCIE_WLAN#

CLK_PCIE_SSD_RCLK_PCIE_SSD
CLK_PCIE_SSD#_RCLK_PCIE_SSD#

X14M_25M_48M_OSC

1

48M_X1

48M_X2

LPCCLK0
LPCCLK1

1

TC38 @

1

TC39 @

LPC_PD

SPI_CLK_R
SPI_CS0#_R
SPI_CS2#_R
SPI_SO_R
SPI_SI_R
SPI_WP#_R
SPI_HOLD#_R
AGPIO76

/HOLDor/RESET(IO3)

VCC

CLK

DI(IO0)

SATA_RX1P

AW1

SATA_ZVSS

AW2

SATA_ZVDDP

AT17

DEVSLP0/EGPIO67

AT12

DEVSLP1/EGPIO70

BB15

SATA_ACT_L/AGPIO130

AU2

SATA_X1

AU1

SATA_X2

U4

GFX_CLKP

U3

GFX_CLKN

U1

GPP_CLK0P

U2

GPP_CLK0N

W4

GPP_CLK1P

W3

GPP_CLK1N

W1

GPP_CLK2P

W2

GPP_CLK2N

Y2

GPP_CLK3P

Y1

GPP_CLK3N

BC10

X25M_48M_OSC

T2

X48M_X1

T1

X48M_X2

AW14

LPCCLK0/EGPIO74

AY13

LPCCLK1/EGPIO75

BB11

LAD0

BA11

LAD1

AY11

LAD2

BA13

LAD3

AV14

LFRAME_L

BA1

ESPI_ALERT_L/LDRQ0_L

BC14

SERIRQ/AGPIO87

BC11

LPC_CLKRUN_L/AGPIO88

AE9

LPC_PD_L/AGPIO21

BC6

SPI_CLK/ESPI_CLK/EGPIO117

BB8

SPI_CS1_L/EGPIO118

AW7

SPI_CS2_L/ESPI_CS_L/EGPIO119

BA9

SPI_DI/ESPI_DATA/EGPIO120

AY7

SPI_DO/EGPIO121

AW11

SPI_WP_L/EGPIO122

BA7

SPI_HOLD_L/EGPIO133

AW12

SPI_TPM_CS_L/AGPIO76

CPU@

+VCC_SPI

8

SPI_HOLD#

7

SPI_CLK

6

SPI_SI

5

1

2

CLK/SATA/USB/SPI/LPC

CC35
.1U_0402_10V6-K

+VCC_SPI

USBCLK/25M_48M_OSC

USB_HSD0P
USB_HSD0N

USB_HSD1P
USB_HSD1N

USB_HSD2P
USB_HSD2N

USB_HSD3P
USB_HSD3N

USB_HSD4P
USB_HSD4N

USB_HSD5P
USB_HSD5N

USB_HSD6P
USB_HSD6N

USB_HSD7P
USB_HSD7N

USB_SS_ZVSS

USB_SS_ZVDDP

USB_SS_0TXP
USB_SS_0TXN

USB_SS_0RXP
USB_SS_0RXN

USB_SS_1TXP
USB_SS_1TXN

USB_SS_1RXP
USB_SS_1RXN

USB_SS_2TXP
USB_SS_2TXN

USB_SS_2RXP
USB_SS_2RXN

USB_SS_3TXP
USB_SS_3TXN

USB_SS_3RXP
USB_SS_3RXN

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

+VCC_SPI

40mil(25mA Max)

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

CLK_USB48M

AP8

USB_RCOMP

AP5

USB_ZVSS

RC132 0_0402_5%

RC133 0_0402_5%

AR2
AR1

AR3
AR4

AN2
AN1

AN3
AN4

AM1
AM2

AL2
AL1

AL3
AL4

AK2
AJ2

AD2
AD1

AA3
AA4

W9
W8

AA2
AA1

W5
W6

AC1
AC2

Y6
Y7

AC4
AC3

AB5
AB6

1 2

1 2

@

2013/08/15

2013/08/15

2013/08/15

USB20_P0
USB20_N0

USB20_P1
USB20_N1

USB20_P3

USB20_P4
USB20_N4

USB20_P5
USB20_N5

USB20_P6
USB20_N6

USBSS_CALRN
USBSS_CALRP

USB30_TX_P0
USB30_TX_N0

USB30_RX_P0
USB30_RX_N0

USB30_TX_P1
USB30_TX_N1

USB30_RX_P1
USB30_RX_N1

USB30_TX_P2
USB30_TX_N2

USB30_RX_P2
USB30_RX_N2

2

1

TC36@

1 2

RC108 11.8K_0402_1%

USB20_P0 36
USB20_N0 36

USB20_P1 25
USB20_N1 25

USB20_P3 30
USB20_N3 30

USB20_P4 36
USB20_N4 36

USB20_P5 32
USB20_N5 32

USB20_P6 32
USB20_N6 32

1 2

RC119 1K_0402_1%

1 2

RC120 1K_0402_1%

USB30_TX_P0 36
USB30_TX_N0 36

USB30_RX_P0 36
USB30_RX_N0 36

USB30_TX_P1 32
USB30_TX_N1 32

USB30_RX_P1 32
USB30_RX_N1 32

USB30_TX_P2 32
USB30_TX_N2 32

USB30_RX_P2 32
USB30_RX_N2 32

CarrzioL don't support USB_SS_[1:0]
Note: Route USB 3.0 ports starting from the lowest numbered port,
for example, Port0, Port1, Port2.
All unused ports should be the highest numbered ports.
For CZ and CZL Co-lay, can start from Port2

USB3.0 port0 must map to USB2.0 port4,
USB3.0 port1 must map to USB2.0 port5,
USB3.0 port2 must map to USB2.0 port6,
USB3.0 port3 must map to USB2.0 port7

+1.8VS

+1.8VALW

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

RC108 place to cpu within 1000mil

LEFT USB (2.0)

Camera

Blue Tooth

Card Reader

RIGHT USB (3.0) upper JUSB1

RIGHT USB (3.0) Lower JUSB2

+0.95VALW

Card Reader

RIGHT USB (3.0) upper JUSB1

RIGHT USB (3.0) Lower JUSB2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

2

2013/08/15

2013/08/15

2013/08/15

SPI_CLK

FP4 (SATA/USB/LPC/SPI)

FP4 (SATA/USB/LPC/SPI)

FP4 (SATA/USB/LPC/SPI)

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

1

RC134
10_0402_5%

EMC_NS@

1 2

2

CC38
10P_0402_50V8J

EMC_NS@

1

EMC

Allsparks 5B

Allsparks 5B

Allsparks 5B

1

8 51

8 51

8 51

0.3

0.3

0.3

5

+1.35V

+1.35V

1

1

1

CC45

CC44

CC63

2

2

D D

C C

+VCCRTC

B B

APU_S5_MUX_CTRL7

S5_MUX_CTRL:
Enable MUX(S0 to S3)-->LOW
Disable MUX(S3 to S0)-->HIGH
During S0 track VDDNB power
During S5/S4/S3 set to 0.775V

A A

2

22U_0603_6.3V6-M

22U_0603_6.3V6-M

+3VS_APU

+3VS

1 2

RC139

0_0603_5%

1

CC87

2

10U_0603_6.3V6M

+0.95VS

1

1

1

CC96

CC95

CC94

2

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

OK

+APU_CORE_NB

1

1

1

CC103

CC102

CC104

2

2

2

0.22U_0402_10V6K

0.22U_0402_10V6K

OK

RC141 10K_0402_5%

1 2

CC118

RC154

1 2

0_0402_5%

22U_0603_6.3V6-M

10U_0603_6.3V6M

0.22U_0402_10V6K

1

2

1

1

CC46

CC47

2

2

22U_0603_6.3V6-M

+1.8VS

1

CC97

CC98

2

10U_0603_6.3V6M

1

1

CC106

CC105

2

2

0.22U_0402_10V6K

AP2138N-1.5TRG1_SOT23-3

1U_0402_6.3V6K

+3VALW_APU

12

RC149
100K_0402_5%

@

1

CC48

CC64

2

22U_0603_6.3V6-M

22U_0603_6.3V6-M

1

1

CC89

CC88

2

2

@

22U_0603_6.3V6-M

1

1

CC152

2

2

0.22U_0402_10V6K

0.22U_0402_10V6K

1

CC108

CC107

2

0.22U_0402_10V6K

0.22U_0402_10V6K

UC5

1

Vin

Vout

2

GND

B+

2

G

QC16A

S

2N7002KDWH_SOT363-6

1

1

1

CC49

2

22U_0603_6.3V6-M

1

CC157

2

10U_0603_6.3V6M

1

CC153

2

0.22U_0402_10V6K

1

CC109

2

0.22U_0402_10V6K

3

+5VALW

12

RC150

1M_0402_5%

MUX_S5

61

D

+5VALW

1

CC65

CC50

2

2

2

@

@

22U_0603_6.3V6-M

22U_0603_6.3V6-M

+1.8VALW

1

0.22U_0402_10V6K

CC90

2

1

1

1

CC155

CC156

CC154

2

2

2

0.22U_0402_10V6K

0.22U_0402_10V6K

1

1

CC111

CC110

2

2

180P_0402_50V8-J

0.22U_0402_10V6K

follow CRB ACROSS VDDNB AND VSS SPLIT

+RTCBATT

1

CC119

2

1U_0402_6.3V6K

+5VALW

RC2547

10K_0402_5%

@

1 2

5

G

RC155

100K_0402_5%

+3VALW_APU

RC2555 0_0402_5%

RC2556 0_0402_5%@

1

CC52

2

1

0.22U_0402_10V6K

CC51

2

@

22U_0603_6.3V6-M

22U_0603_6.3V6-M

RC137 0_0805_5%PX@

CC91

10U_0603_6.3V6M

CC99

0.22U_0402_10V6K

1

2

1 2

MUX_S0

34

QC16B

D

2N7002KDWH_SOT363-6

S

12

1 2

1 2

Wake-on-Ring not supported:
+VDDIO_AZ_APU Connect to +1.5V S0 rail

+1.8VS

1 2

+3VALW_APU

1

2

0.22U_0402_10V6K

1

2

180P_0402_50V8-J

1

1

CC114

CC113

CC112

2

2

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

12

12

JCMOS1

RC142

SHORT PADS

470_0603_5%

@

13

D

S

RC2546
10K_0402_5%

+APU_CORE_NB

@

FCH_S5_POWER

RC2550

1 2

0_0402_5%

FCH_S5_POWER_COMP FCH_S5_POWER

1

180P_0402_50V8-J
CC127

@

2

+3VALW_APU_FCH

4

1

1

1

CC54

CC53

CC55

2

2

2

0.22U_0402_10V6K

0.22U_0402_10V6K

+0.95VS_GFX_APU+0.95VS

PX@

1

CC92

2

1

CC115

2

0.22U_0402_10V6K

@

EC_RTCRST#_ON

2

G

MUX_S0

1 2

1 2

@

1

CC79

2

1

CC93

2

10U_0603_6.3V6M

CC116

@

0.22U_0402_10V6K

1 2

0.22U_0402_10V6K

CC80

PX@

10U_0603_6.3V6M

0.22U_0402_10V6K

1

2

0.22U_0402_10V6K

12

RC143
100K_0402_5%

@

RC2549 0_0402_5%@

1

2

OK

RC136 0_0402_5%

RC2531 0_0402_5%

1

2

QC13

2N7002KW_SOT323-3

@

RC147 0_0402_5%

1

CC56

2

0.22U_0402_10V6K

1 2

0.22U_0402_10V6K

+VDDIO_AZ_APU+1.5VS

+0.95VALW

1

CC57

2

0.22U_0402_10V6K

1

CC76

CC77

2

1U_0402_6.3V6K

1

CC100

2

EDC 17A TDC 12A

+RTCBATT

RC140

EC_RTCRST#_ON 35

+3VALW_APU_FCH

8

UC6A

3

P

+_1

O1

2

-_1

G

AS393MTR-G1_SO8

4

FCH_S5_POWER_COMP

1

2

10U_0603_6.3V6M

CC58

1U_0402_6.3V6K

CC101

1 2

1

+1.35V

1

2

180P_0402_50V8-J

1

CC78

2

1U_0402_6.3V6K

+VDDCR_FCH_S5

1

+0.95VS

2

0.22U_0402_10V6K

+APU_CORE_NB

+RTCBATT_APU

1K_0402_5%

COMP_OUT1

+0.775VALW

+0.95VALW

MUX_S5

P25

3A

P28
T24
T27
U25
U28
V30
V33
W24
W27
Y25
Y28

Y30
AB24
AB27
AB30
AB33
AD25
AD28
AD30
AE24
AE27
AF30
AF33

AG25
AG28

AH24
AH27
AH30
AK25
AK28
AK30
AK33
AL27

AM30

AR19

0.2A

AE6

1.4A

AE5

AP19

0.2A

AP21

AP16

1.5A

AP18

AP10

0.5A

AR9

AP15

0.2A

AR15

AN12

0.8A

AP12

AP13

0.2A

AR12

AW19

7A

AU17
AU19
AV17
AV19

AW17

AL12
AL13
AL15
AL18
AL21
AN13
AN16
AN19
AN22

AR17

1

CC117

2

0.22U_0402_10V6K

+APU_CORE_NB

+5VALW

RC146
10K_0402_5%

1 2

RC148 1K_0402_5%

RC153

1 2

0_0603_5%

1 2

RC156

0_0603_5%@

+3VALW_APU_FCH

8

UC6B

5

P

+_2

COMP_OUT2

7

O2

6

-_2

G

AS393MTR-G1_SO8

4

RC2548 0_0402_5%@

1 2

POWER

VDDIO_MEM_S3_1
VDDIO_MEM_S3_2
VDDIO_MEM_S3_3
VDDIO_MEM_S3_4
VDDIO_MEM_S3_5
VDDIO_MEM_S3_6
VDDIO_MEM_S3_7
VDDIO_MEM_S3_8
VDDIO_MEM_S3_9
VDDIO_MEM_S3_10
VDDIO_MEM_S3_11
VDDIO_MEM_S3_12
VDDIO_MEM_S3_13
VDDIO_MEM_S3_14
VDDIO_MEM_S3_15
VDDIO_MEM_S3_16
VDDIO_MEM_S3_17
VDDIO_MEM_S3_18
VDDIO_MEM_S3_19
VDDIO_MEM_S3_20
VDDIO_MEM_S3_21
VDDIO_MEM_S3_22
VDDIO_MEM_S3_23
VDDIO_MEM_S3_24
VDDIO_MEM_S3_25
VDDIO_MEM_S3_26
VDDIO_MEM_S3_27
VDDIO_MEM_S3_28
VDDIO_MEM_S3_29
VDDIO_MEM_S3_30
VDDIO_MEM_S3_31
VDDIO_MEM_S3_32
VDDIO_MEM_S3_33
VDDIO_MEM_S3_34
VDDIO_MEM_S3_35

VDDIO_AUDIO

VDDP_GFX_2
VDDP_GFX_1

VDD_33_1
VDD_33_2

VDD_18_1
VDD_18_2

VDD_18_S5_1
VDD_18_S5_2

VDD_33_S5_1
VDD_33_S5_2

VDDP_S5_1
VDDP_S5_2

VDDCR_FCH_S5_1
VDDCR_FCH_S5_2

VDDP_6
VDDP_1
VDDP_2
VDDP_3
VDDP_4
VDDP_5

VDDCR_NB_1
VDDCR_NB_2
VDDCR_NB_3
VDDCR_NB_4
VDDCR_NB_5
VDDCR_NB_6
VDDCR_NB_7
VDDCR_NB_8
VDDCR_NB_9

VDDBT_RTC_G

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

CPU@

QC14

AON6414AL_DFN8-5

5

4

12

+5VALW

RC157
10K_0402_5%

1 2

RC158 1K_0402_5%

UC1F

VDDCR_CPU_1
VDDCR_CPU_2
VDDCR_CPU_3
VDDCR_CPU_4
VDDCR_CPU_5
VDDCR_CPU_6
VDDCR_CPU_7
VDDCR_CPU_8

VDDCR_CPU_9
VDDCR_CPU_10
VDDCR_CPU_11
VDDCR_CPU_12
VDDCR_CPU_13
VDDCR_CPU_14
VDDCR_CPU_15
VDDCR_CPU_16
VDDCR_CPU_17
VDDCR_CPU_18
VDDCR_CPU_19
VDDCR_CPU_20
VDDCR_CPU_21
VDDCR_CPU_22
VDDCR_CPU_23
VDDCR_CPU_24
VDDCR_CPU_25
VDDCR_CPU_26
VDDCR_CPU_42
VDDCR_CPU_31
VDDCR_CPU_43
VDDCR_CPU_32
VDDCR_CPU_44
VDDCR_CPU_33
VDDCR_CPU_45
VDDCR_CPU_34
VDDCR_CPU_46
VDDCR_CPU_35
VDDCR_CPU_47
VDDCR_CPU_36
VDDCR_CPU_28
VDDCR_CPU_29
VDDCR_CPU_40
VDDCR_CPU_30
VDDCR_CPU_37
VDDCR_CPU_49
VDDCR_CPU_38
VDDCR_CPU_39
VDDCR_CPU_48
VDDCR_CPU_41
VDDCR_CPU_27

VDDCR_GFX_14
VDDCR_GFX_15
VDDCR_GFX_16
VDDCR_GFX_17
VDDCR_GFX_18
VDDCR_GFX_19
VDDCR_GFX_20
VDDCR_GFX_21
VDDCR_GFX_22
VDDCR_GFX_23
VDDCR_GFX_24
VDDCR_GFX_25
VDDCR_GFX_26
VDDCR_GFX_27
VDDCR_GFX_28
VDDCR_GFX_29

VDDCR_GFX_1

VDDCR_GFX_2

VDDCR_GFX_3

VDDCR_GFX_4

VDDCR_GFX_5

VDDCR_GFX_6

VDDCR_GFX_7

VDDCR_GFX_8

VDDCR_GFX_9
VDDCR_GFX_10
VDDCR_GFX_11
VDDCR_GFX_12
VDDCR_GFX_30
VDDCR_GFX_31
VDDCR_GFX_32
VDDCR_GFX_33
VDDCR_GFX_34
VDDCR_GFX_35
VDDCR_GFX_36
VDDCR_GFX_37
VDDCR_GFX_13

1
2
3

RC151

5

1 2

AON6414AL_DFN8-5

4

12

3

+APU_CORE

U8

EDC 55A TDC 39A

W7
W12
W15
W18
W21
Y8
Y10
Y13
Y16
Y19
Y22
AB7
AB9
AB12
AB15
AB18
AB21
AD6
AD10
AD13
AD16
AD19
AD22
AE7
AE12
AK9
AG10
AK10
AG13
AK13
AG16
AK16
AG19
AK19
AG22
AK22
AH7
AE18
AE21
AH21
AG6
AH12
AN6
AH15
AH18
AL7
AK6
AE15

+APU_GFX

L8
L13
L16
L19
L22
N7
N12
N15
N18
N21
P8
P13
P16
P19
P22
T7
F12
F15
G11
G14
J8
J9
J11
K7
K12
K13
K15
K16
T12
T15
T18
T21
U13
U16
U19
U22
K19

1 2

RC144

AON6414AL_DFN8-5

1
2
3

4

0_0603_5%@

1
2
3

QC17

+APU_CORE

1

CC59

2

+APU_GFX

1

CC66

2

+1.35V

EDC 45A TDC 30A

VDDCR_CPU

VDDCR_NB

VDDCR_GFX

VDDIO_MEM_S3

VDDCR_FCH_S5

VDDP

VDDP_GFX

VDDP_S5

VDD_18

VDD_18_S5

VDD_33

VDD_33_S5

VDDIO_AUDIO

VDDBT_RTC_G

0_0603_5%@

QC15

5

1 2

RC152

AON6414AL_DFN8-5

1
2
3

4

2

1

1

2

1

2

1

2

0.22U_0402_10V6K

CC70

0.22U_0402_10V6K

CC84

0.22U_0402_10V6K

1

CC60

CC42

2

0.22U_0402_10V6K

1

1

CC71

2

2

0.22U_0402_10V6K

1

2

0.22U_0402_10V6K

3*22uf 0603 NC

+VDDCR_FCH_S5

0_0603_5%

1

2

0.22U_0402_10V6K

CC72

0.22U_0402_10V6K

CC85

CC120

@

1

CC61

2

1

2

0.22U_0402_10V6K

1

2

180P_0402_50V8-J

1

CC62

CC43

2

2

0.22U_0402_10V6K

0.22U_0402_10V6K

1

1

CC74

CC73

2

2

0.22U_0402_10V6K

0.22U_0402_10V6K

1

CC86

2

180P_0402_50V8-J

9*22uf 0805
8*0.22uf 0402
1*180pf 0402
6*22uf 0805
8*0.22uf 0402
1*180pf 0402
9*22uf 0805
9*0.22uf 0402
1*180pf 0402
8*22uf 0603
6*0.22uf 0402 split*4
1*180pf 0402 split*2
2*10uf 0603
1*0.22uf 0402

4*10uf 0603
6*0.22uf 0402
1*180pf 0402
1*10uf 0603
1*0.22uf 0402

1*10uf 0603
1*0.22uf 0402

1*22uf 0603 NC
1*10uf 0402

1*0.22uf 0402

1*10uf 0603
1*0.22uf 0402

1*10uf 0603

1*10uf 0403
1*0.22uf 0402

180P_0402_50V8-J

3*1uf 0402

1*0.22uf 0402

1

1

2

1

CC121

@

4.7U_0603_6.3V6K

+APU_CORE_NB +APU_CORE

1

2

RF_NS@

CC123

CC122

2

2

@

@

22U_0805_6.3V6M

4.7U_0603_6.3V6K

CC159

33P_0402_50V8J

CC160

33P_0402_50V8J

1

2

RF_NS@

RF_NS@

1

CC75

2

180P_0402_50V8-J

1

2

22U_0805_6.3V6M

CC161

33P_0402_50V8J

1

2

1

CC124

2

Decoupling cap
near APU ball

1

2

RF_NS@

1

1

CC39

CC40

CC41

2

2

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

OK

1

1

CC67

CC69

CC68

2

2

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

OK

1

1

CC82

CC83

CC81

2

2

0.22U_0402_10V6K

0.22U_0402_10V6K

DECOUPLING BETWEEN PROCESSOR AND DIMMs
ACROSS VDDIO AND VSS SPLIT

Design Guide CRBY51-75

8*22uf 0603
6*0.22uf 0402
1*180pf 0402
6*22uf 0603
8*0.22uf 0402
1*180pf 0402
9*22uf 0603
9*0.22uf 0402
1*180pf 0402
8*22uf 0603
6*0.22uf 0402 split*4
1*180pf 0402 split*2
2*10uf 0402
1*0.22uf 0402

4*10uf 0402
6*0.22uf 0402
1*180pf 0402
1*10uf 0402
1*0.22uf 0402

1*10uf 0402
1*0.22uf 0402

1*10uf 0402
1*0.22uf 0402

1*10uf 0402
1*0.22uf 0402

1*10uf 0603

1*10uf 0603
1*0.22uf 0402

3*1uf 0402

1*0.22uf 0402

QC1/QC2/QC3/QC4 Rds on should less possible, CRB is 11.8mohm,
there is no load swtich for 0.775V power, so it need mos

RC145

1 2

0_0603_5%@

5

QC18

For RF

+1.35V

1

1

CC165

.1U_0402_10V6-K

EMC_NS@

2

2

+0.95VS +APU_CORE_NB

1

1

CC169

.1U_0402_10V6-K

EMC_NS@

2

2

For EMC

9*22uf 0603
8*0.22uf 0402
1*180pf 0402
6*22uf 0603
8*0.22uf 0402 split *5
1*180pf 0402
13*22uf 0603
9*0.22uf 0402
1*180pf 0402
8*22uf 0603
8*0.22uf 0402 split*4
1*180pf 0402 split*2
2*10uf 0603
1*0.22uf 0402

4*10uf 0603
6*0.22uf 0402
1*180pf 0402
1*10uf 0603
1*0.22uf 0402

1*10uf 0603
1*0.22uf 0402

1*10uf 0603

1*10uf 0603
1*0.22uf 0402

1*10uf 0603

1*10uf 0603
1*0.22uf 0402

3*1uf 0402

1*0.22uf 0402

1

1

CC125

CC126

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

0.22U_0402_10V6K

+1.35V

CC163

33P_0402_50V8J

CC164

33P_0402_50V8J

CC162

33P_0402_50V8J

1

1

2

2

RF_NS@

RF_NS@

1

+APU_CORE

1

CC166

.1U_0402_10V6-K

EMC_NS@

CC170

.1U_0402_10V6-K

EMC_NS@

1

CC167

.1U_0402_10V6-K

EMC_NS@

CC168

.1U_0402_10V6-K

EMC_NS@

2

2

1

1

CC171

.1U_0402_10V6-K

EMC_NS@

CC172

.1U_0402_10V6-K

EMC_NS@

2

2

+0.95VS +APU_CORE

+APU_CORE_NB

+0.95VS

@

1 2

CC177 .1U_0402_10V6-K

@

CC178 .1U_0402_10V6-K

1 2

@

CC179 .1U_0402_10V6-K

1 2

@

CC180 .1U_0402_10V6-K

1 2

@

CC182 .1U_0402_10V6-K

1 2

@

1 2

CC183 .1U_0402_10V6-K

+APU_CORE+APU_GFX

+APU_CORE

+0.95VGS

RESERVE SPLIT CAP

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/08/15

2013/08/15

2013/08/15

2

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2013/08/15

2013/08/15

2013/08/15

Title

FP4 (POWER&DECOUPLING)

FP4 (POWER&DECOUPLING)

FP4 (POWER&DECOUPLING)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Allsparks 5B

Allsparks 5B

Allsparks 5B

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

1

9 51

9 51

9 51

0.3

0.3

0.3

5

4

3

2

1

UC1G

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62

GND

VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

L28
M4
M30
N10
N13
N16
N19
N22
N27
P1
P2
P4
P5
P12
P15
P18
P21
P30
P33
T4
T10
T13
T16
T19
T22
T30
U5
U12
U15
U18
U21
U24
V1
V2
V4
W10
W13
W16
W19
W22
Y4
Y5
Y12
Y15
Y18
Y21
Y24
AB1
AB2
AB4
AB10
AB13
AB16
AB19
AB22
AD4
AD9
AD12
AD15
AD18
AD21
AD24

A8
A12
A16
A20
A24

D D

C C

B B

A28
A32

B12
B33

D10
D12
D14
D16
D18
D20
D22
D24
D26
D28
D30

F19
F22
F25
F30
F33

G17
G20
G23
G26

H30

J15
J19
J22
J25
J28

K10
K22
K27
K30
K33

L12
L15
L18
L21
L25

B2

B8

C3
D4
D6
D8

F1

F2

F4

F9

G7

H4

J5

K1

K2

K4

L5

CPU@

AE10
AE13
AE16
AE19
AE22

AF1
AF4

AG9
AG12
AG15
AG18
AG21

AH4

AH10
AH13
AH16
AH19
AH22

AK1

AK4
AK12
AK15
AK18

AL16
AL19
AL22

AM4

AN9
AN10
AN15
AN18
AN21
AN25
AN28

AP1
AP2
AP4

AP7
AP22
AP27
AP30
AP33

AR6
AR25
AR28

AT4
AT19
AT22
AT30

AU5

AU8
AU11
AU14
AU20
AU23
AU27

AV4
AV7

AV9
AV12
AV15
AV25

VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186

CPU@

UC1H

GND

VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212

VSS_213
VSS_215
VSS_214

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

AV30
AV33
AW22
AY4
AY6
AY8
AY10
AY12
AY14
AY16
AY20
AY22
AY24
AY26
AY28
AY30
BB1
BB33
BC4
BC8
BC12
BC16
BC20
BC24
BC28
BC32

L24
AL10
AK21

UC1J

1

TC41@

1

TC42@

1

TC43@

U30
U31

AN30

RSVD_2
RSVD_3
RSVD_4

CPU@

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

3

2013/08/15

2013/08/15

2013/08/15

Title

FP4 (VSS)

FP4 (VSS)

FP4 (VSS)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

2

Wednesday, April 29, 2015

Allsparks 5B

Allsparks 5B

Allsparks 5B

10 51

10 51

10 51

1

0.3

0.3

0.3

5

4

3

2

+3VALW_APU +3VALW_APU +3VALW_APU +3VALW_APU+3VALW_APU+3VALW_APU +3VALW_APU +3VS_APU+3VS_APU +3VS_APU +3VS_APU

1

RC173
2K_0402_5%

@

12

RC167
10K_0402_5%

12

RC174
2K_0402_5%

@

12

RC168
10K_0402_5%

12

RC175
2K_0402_5%

@

RC179
10K_0402_5%

1 2

12

RC178
2K_0402_5%

@

12

RC163
10K_0402_5%

@

12

12

RC164
10K_0402_5%

@

RC171
2K_0402_5%

12

12

RC160
10K_0402_5%

@

RC169
2K_0402_5%

@

12

RC159

D D

LPC_FRAME#8,35,36

CLK1_PCI_TPM8,36

CLK0_PCI_EC8,35

AGPIO37

SYS_RESET#7

SUSCLK7,30

BLINK7

Connect to VSS to enable. If not used, leave

C C

unconnected to disable AMD Hardware Validated Boot

HVB_EN7

10K_0402_5%

12

RC161
10K_0402_5%

12

12

RC162
10K_0402_5%

@

RC170
2K_0402_5%

@

12

RC165
10K_0402_5%

12

RC172
2K_0402_5%

@

12

RC166
10K_0402_5%

12

STRAP PINS

LFRAME_L LPCCLK1 LPCCLK0 GEVENT2_L/AGPIO3 SYS_RESET_L RTCCLK BLINK(for CZL strap)

Signal

Int pull-up Int pull-up Int pull-up Int pull-up

Type II II I I I

PULL
HIGH

B B

PULL
LOW

II

SPI ROM

LPC ROM

Internal
CLK Gen

DefaultDefault

Reserved

Boot Fail Timer
Enabled

Boot Fail Timer
Disabled

Default

CZL CZ

Enhanced reset

1.8V SPI

logic (for quicker
S5 resume)

Default

Default to

3.3VSPI

traditional
reset logic

Default

III

Normal Power Up
&Reset Timing

Default Default

Reserved

Coin Battery

Direct DC

PWROK and RST_L
pin routed to APU

Default

Reserved

HVB_EN

II

floating

Disable HVB
on FP4 platforms

Default

connected to VSS

Enable HVB
on FP4 platforms

Type I straps become valid immediately after capture with the rising edge of RSMRST_L,they are captured only once when power is first applied to the processor

Type II straps become valid after PWR_GOOD is asserted,straps are captured every time the systems powers up from the S5 state. A transition from S3 to S0 does not trigger capture.
Type II straps should be pulled up to S0 power rail to prevent leakage when the signal is connected to a device in S0 power domain.

If the LPC bus is connected to devices that are on S0 power rail, then a pull-up resistor to VDD_33 is implemented.

All Strap pins must be configured with either external pull-up or pull-down resistors.

Platforms that are designed for AOAC complaint are recommended to use the Alternate Reset by strapping this pin to ‘1’ for CZ AGPIO3

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/08/15

2013/08/15

2013/08/15

3

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2013/08/15

2013/08/15

2013/08/15

2

Title

FP4 (STRAPS)

FP4 (STRAPS)

FP4 (STRAPS)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Allsparks 5B

Allsparks 5B

Allsparks 5B

11 51

11 51

11 51

1

of

0.3

0.3

0.3

DDR3 SO-DIMM A

5

4

3

2

1

DDRA_DQ[0..63]

DDRA_DQS[0..7]

APU_MA_VREFDQ5

DDRA_DQS#[0..7]

DDRA_MA[0..15]

DDRA_DM[0..7]

[email protected]

+1.35V

CD5

+1.35V

CD17

CD26

1

2

1

2

+0.675VS

DDR3 SO-DIMM A

VSS_2

VSS_4

DQS0#

DQS0

VSS_6

VSS_8

DQ12
DQ13

VSS_10

VSS_12

DQ14
DQ15

VSS_14

DQ20
DQ21

VSS_16

VSS_18

DQ22
DQ23

VSS_20

DQ28
DQ29

VSS_22

DQS3#

DQS3

VSS_24

DQ30
DQ31

VSS_26

CKE1

VDD_2

VDD_4

VDD_6

VDD_8

CK1#

RAS#

ODT0

ODT1

NC_2

VSS_28

DQ36
DQ37

VSS_30

VSS_32

DQ38
DQ39

VSS_34

DQ44
DQ45

VSS_35

DQS5#

DQS5

VSS_38

DQ46
DQ47

VSS_40

DQ52
DQ53

VSS_42

VSS_44

DQ54
DQ55

VSS_46

DQ60
DQ61

VSS_48

DQS7#

DQS7

VSS_50

DQ62
DQ63

VSS_52

VTT_2

GND2

BOSS2

+1.35V+1.35V

2

DDRA_DQ4

4

DQ4
DQ5

DQ6
DQ7

DM1

DM2

A15
A14

A11

A7

A6
A4

A2
A0

CK1

BA1

S0#

DM4

DM6

SDA
SCL

6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206
208

DDRA_DQ5

DDRA_DQS#0
DDRA_DQS0

DDRA_DQ6
DDRA_DQ7

DDRA_DQ12
DDRA_DQ13

DDRA_DM1
MEM_MA_RST#_C

DDRA_DQ14
DDRA_DQ15

DDRA_DQ20
DDRA_DQ21

DDRA_DM2

DDRA_DQ22
DDRA_DQ23

DDRA_DQ28
DDRA_DQ29

DDRA_DQS#3
DDRA_DQS3

DDRA_DQ30
DDRA_DQ31

DDRA_CKE1

DDRA_MA15
DDRA_MA14

DDRA_MA11
DDRA_MA7

DDRA_MA6
DDRA_MA4

DDRA_MA2
DDRA_MA0

DDRA_CLK1
DDRA_CLK1#

DDRA_BS1#
DDRA_RAS#

DDRA_CS0#
DDRA_ODT0

DDRA_ODT1

DDRA_DQ36
DDRA_DQ37

DDRA_DM4

DDRA_DQ38
DDRA_DQ39

DDRA_DQ44
DDRA_DQ45

DDRA_DQS#5
DDRA_DQS5

DDRA_DQ46
DDRA_DQ47

DDRA_DQ52
DDRA_DQ53

DDRA_DM6

DDRA_DQ54
DDRA_DQ55

DDRA_DQ60
DDRA_DQ61

DDRA_DQS#7
DDRA_DQS7

DDRA_DQ62
DDRA_DQ63

MEM_MA_EVENT#
APU_SMB_DATA
APU_SMB_CLK

1

CD69
33P_0402_50V8J

RF_NS@

2

1 2

R895 0_0402_5%

DDRA_CKE1 5

DDRA_CLK1 5
DDRA_CLK1# 5

DDRA_BS1# 5
DDRA_RAS# 5

DDRA_CS0# 5
DDRA_ODT0 5

DDRA_ODT1 5

MEM_MA_EVENT# 5
APU_SMB_DATA 7,13,30
APU_SMB_CLK 7,13,30

+0.675VS

0.65A@0.675V

MEM_MA_RST# 5

+VREF_CA_A0

D D

C C

B B

1 2

RD22 0_0402_5%

1 2

RD23 0_0402_5%

+1.35V

1 2

RC183 1K_0402_5%

A A

SA0_DIM1

SA1_DIM1

MEM_MA_EVENT#

2.2U_0603_10V6-K

+3VS

+VREF_MA_DQ

DDRA_DQ0
DDRA_DQ1

DDRA_DM0

DDRA_DQ2
DDRA_DQ3

DDRA_DQ8
DDRA_DQ9

DDRA_DQS#1
DDRA_DQS1

DDRA_DQ10
DDRA_DQ11

DDRA_DQ16
DDRA_DQ17

DDRA_DQS#2
DDRA_DQS2

DDRA_DQ18
DDRA_DQ19

DDRA_DQ24
DDRA_DQ25

DDRA_DM3

DDRA_DQ26
DDRA_DQ27

1

CD68
.1U_0402_10V6-K

2

DDRA_CKE0

DDRA_BS2#

DDRA_MA12
DDRA_MA9

DDRA_MA8
DDRA_MA5

DDRA_MA3
DDRA_MA1

DDRA_CLK0
DDRA_CLK0#

DDRA_MA10
DDRA_BS0#

DDRA_WE#
DDRA_CAS#

DDRA_MA13
DDRA_CS1#

DDRA_DQ32
DDRA_DQ33

DDRA_DQS#4
DDRA_DQS4

DDRA_DQ34
DDRA_DQ35

DDRA_DQ40
DDRA_DQ41

DDRA_DM5

DDRA_DQ42
DDRA_DQ43

DDRA_DQ48
DDRA_DQ49

DDRA_DQS#6
DDRA_DQS6

DDRA_DQ50
DDRA_DQ51

DDRA_DQ56
DDRA_DQ57

DDRA_DM7

DDRA_DQ58
DDRA_DQ59

SA0_DIM1

SA1_DIM1

DDRA_CKE05

DDRA_BS2#5

DDRA_CLK05
DDRA_CLK0#5

DDRA_BS0#5

DDRA_WE#5
DDRA_CAS#5

DDRA_CS1#5

1

CD63

2

CD@

[email protected]

JDDRL1

1
3
5
7
9

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

205
207

LCN_DAN06-K4406-0103

ME@

SMBUS ADD 0XA0h

VREF_DQ
VSS_1
DQ0
DQ1
VSS_3
DM0
VSS_5
DQ2
DQ3
VSS_7
DQ8
DQ9
VSS_9
DQS1#
DQS1
VSS_11
DQ10
DQ11
VSS_13
DQ16
DQ17
VSS_15
DQS2#
DQS2
VSS_17
DQ18
DQ19
VSS_19
DQ24
DQ25
VSS_21
DM3
VSS_23
DQ26
DQ27
VSS_25

CKE0
VDD_1
NC_1
BA2
VDD_3
A12/BC#
A9
VDD_5
A8
A5
VDD_7
A3
A1
VDD_9
CK0
CK0#
VDD_11
A10/AP
BA0
VDD_13
WE#
CAS#
VDD_15
A13
S1#
VDD_17
TEST
VSS_27
DQ32
DQ33
VSS_29
DQS4#
DQS4
VSS_31
DQ34
DQ35
VSS_33
DQ40
DQ41
VSS_36
DM5
VSS_37
DQ42
DQ43
VSS_39
DQ48
DQ49
VSS_41
DQS6#
DQS6
VSS_43
DQ50
DQ51
VSS_45
DQ56
DQ57
VSS_47
DM7
VSS_49
DQ58
DQ59
VSS_51
SA0
VDDSPD
SA1
VTT_1

GND1
BOSS1

RESET#

VDD_10

VDD_12

VDD_14

VDD_16

VDD_18

VREF_CA

EVENT#

DDRA_DQ[0..63] 5

DDRA_DQS[0..7] 5

DDRA_DQS#[0..7] 5

DDRA_MA[0..15] 5

DDRA_DM[0..7] 5

1 2

R1 0_0402_5%

Layout Note:
Place near DIMM1

.1U_0402_10V6-K

.1U_0402_10V6-K

CD7

CD6

1

@

2

10U_0805_10V6K

10U_0805_10V6K

1

CD19

CD18

2

Layout Note:
Place near DIMM1

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD28

CD27

@

2

2

+1.35V

12

RD1
1K_0402_1%

+VREF_MA_DQ

20mil 20mil

1

CD10

1

2

2

1

@

2

EMI

4.7U_0603_6.3V6K

CD22

1

CD1

2

.1U_0402_10V6-K

.1U_0402_10V6-K

CD11

4.7U_0603_6.3V6K

1

2

EMC@

MEM_MA_RST#_C

CD2

CD58

1000P_0402_50V7K

.1U_0402_10V6-K

.1U_0402_10V6-K

CD12

1

1

@

2

2

0.047U_0402_16V7K

1

CD23

@

2

.1U_0402_10V6-K

1

@

2

RD3
1K_0402_1%

1 2

.1U_0402_10V6-K

.1U_0402_10V6-K

CD8

1

2

22U_0805_6.3V6M

1

CD20

2

1U_0402_6.3V6K

1

CD29

2

.1U_0402_10V6-K

CD9

1

1

@

2

2

22U_0603_6.3V6-M

1

CD21

@

2

EMC@

4.7U_0603_6.3V6K

1

@

2

CD13

RD2

1K_0402_1%

RD4

1K_0402_1%

.1U_0402_10V6-K

CD14

1

2

1

CD24
33P_0402_50V8J

2

RF_NS@

+1.35V

EMC@

12

12

.1U_0402_10V6-K

CD15

1

2

1

2

1

CD3

2

.1U_0402_10V6-K

.1U_0402_10V6-K

CD16

1

@

2

CD25
33P_0402_50V8J

RF_NS@

1

2

1

2

EMC@

+VREF_CA_A0

CD4

1000P_0402_50V7K

.1U_0402_10V6-K

RF

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/10/22

2014/10/22

2014/10/22

Title

DDRIII SO-DIMM A

DDRIII SO-DIMM A

DDRIII SO-DIMM A

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Allsparks 5B

Allsparks 5B

Allsparks 5B

1

12 51

12 51

12 51

0.3

0.3

0.3

DDR3 SO-DIMM B

5

4

3

2

1

DDRB_DQ[0..63]

DDR3 SO-DIMM B

D D

C C

B B

+3VS

RD20 4.7K_0402_5%

1 2

RD24 0_0402_5%

+1.35V

1 2

RC7 1K_0402_5%

A A

SA0_DIM2

12

SA1_DIM2

MEM_MB_EVENT#

+3VS

2.2U_0603_10V6-K

+VREF_MB_DQ

DDRB_DQ0
DDRB_DQ1

DDRB_DM0

DDRB_DQ2
DDRB_DQ3

DDRB_DQ8
DDRB_DQ9

DDRB_DQS#1
DDRB_DQS1

DDRB_DQ10
DDRB_DQ11

DDRB_DQ16
DDRB_DQ17

DDRB_DQS#2
DDRB_DQS2

DDRB_DQ18
DDRB_DQ19

DDRB_DQ24
DDRB_DQ25

DDRB_DM3

DDRB_DQ26

+1.35V +1.35V

DDRB_CKE05

DDRB_BS2#5

DDRB_CLK05
DDRB_CLK0#5

DDRB_BS0#5

DDRB_WE#5
DDRB_CAS#5

DDRB_CS1#5

1

1

2

CD137
.1U_0402_10V6-K

2

CD72

CD@

DDRB_DQ27

DDRB_CKE0

DDRB_BS2#

DDRB_MA12
DDRB_MA9

DDRB_MA8
DDRB_MA5

DDRB_MA3
DDRB_MA1

DDRB_CLK0
DDRB_CLK0#

DDRB_MA10
DDRB_BS0#

DDRB_WE#
DDRB_CAS#

DDRB_MA13
DDRB_CS1#

DDRB_DQ32
DDRB_DQ33

DDRB_DQS#4
DDRB_DQS4

DDRB_DQ34
DDRB_DQ35

DDRB_DQ40
DDRB_DQ41

DDRB_DM5

DDRB_DQ42
DDRB_DQ43

DDRB_DQ48
DDRB_DQ49

DDRB_DQS#6
DDRB_DQS6

DDRB_DQ50
DDRB_DQ51

DDRB_DQ56
DDRB_DQ57

DDRB_DM7

DDRB_DQ58
DDRB_DQ59

SA0_DIM2

SA1_DIM2

JDDRH1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1
VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17
VSS1849DQ22

51

DQ18
DQ1953VSS19
VSS2055DQ28

57

DQ24
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3
A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4806-0103

ME@

SMBUS ADD 0XA2h

DQ4
DQ5

VSS3

DQS0

VSS6

DQ6
DQ7

VSS8
DQ12
DQ13

VSS10

DM1

DQ14
DQ15

DQ20
DQ21

DM2

DQ23

DQ29

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA

VTT2

2

DDRB_DQ4

4

DDRB_DQ5

6
8

DDRB_DQS#0

10

DDRB_DQS0

12
14

DDRB_DQ6

16

DDRB_DQ7

18
20

DDRB_DQ12

22

DDRB_DQ13

24
26

DDRB_DM1

28

MEM_MB_RST#_C

30
32

DDRB_DQ14

34

DDRB_DQ15

36
38

DDRB_DQ20

40

DDRB_DQ21

42
44

DDRB_DM2

46
48

DDRB_DQ22

50

DDRB_DQ23

52
54

DDRB_DQ28

56

DDRB_DQ29

58
60

DDRB_DQS#3

62

DDRB_DQS3

64
66

DDRB_DQ30

68

DDRB_DQ31

70
72

DDRB_CKE1

74
76

DDRB_MA15

78

A15
A14

A7

A6
A4

A2
A0

CK1

BA1

S0#

SCL

G2

80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

DDRB_MA14

DDRB_MA11
DDRB_MA7

DDRB_MA6
DDRB_MA4

DDRB_MA2
DDRB_MA0

DDRB_CLK1
DDRB_CLK1#

DDRB_BS1#
DDRB_RAS#

DDRB_CS0#
DDRB_ODT0

DDRB_ODT1

DDRB_DQ36
DDRB_DQ37

DDRB_DM4

DDRB_DQ38
DDRB_DQ39

DDRB_DQ44
DDRB_DQ45

DDRB_DQS#5
DDRB_DQS5

DDRB_DQ46
DDRB_DQ47

DDRB_DQ52
DDRB_DQ53

DDRB_DM6

DDRB_DQ54
DDRB_DQ55

DDRB_DQ60
DDRB_DQ61

DDRB_DQS#7
DDRB_DQS7

DDRB_DQ62
DDRB_DQ63

MEM_MB_EVENT#
APU_SMB_DATA
APU_SMB_CLK

1

CD142
33P_0402_50V8J

RF_NS@

2

1 2

R896 0_0402_5%

DDRB_CKE1 5

DDRB_CLK1 5
DDRB_CLK1# 5

DDRB_BS1# 5
DDRB_RAS# 5

DDRB_CS0# 5
DDRB_ODT0 5

DDRB_ODT1 5

+VREF_CA_B0

MEM_MB_EVENT# 5
APU_SMB_DATA 7,12,30
APU_SMB_CLK 7,12,30

+0.675VS

[email protected]

RF

MEM_MB_RST# 5

APU_MB_VREFDQ5

DDRB_DQS[0..7]

DDRB_DQS#[0..7]

DDRB_MA[0..15]

DDRB_DM[0..7]

1 2

R176 0_0402_5%

[email protected]

+1.35V

Layout Note:
Place near DIMM2

.1U_0402_10V6-K

CD136

+1.35V

CD62

.1U_0402_10V6-K

CD138

1

1

@

2

2

10U_0805_10V6K

10U_0805_10V6K

1

1

CD129

2

2

CD130

CD126

CD66

+0.675VS

1

2

DDRB_DQ[0..63] 5

DDRB_DQS[0..7] 5

DDRB_DQS#[0..7] 5

DDRB_MA[0..15] 5

DDRB_DM[0..7] 5

+1.35V

12

RD18
1K_0402_1%

RD19
1K_0402_1%

1 2

.1U_0402_10V6-K

CD140

1

2

1

2

22U_0805_6.3V6M

Layout Note:
Place near DIMM2

1U_0402_6.3V6K

1

CD133

@

2

+VREF_MB_DQ

20mil 20mil

.1U_0402_10V6-K

CD33

1

1

2

2

.1U_0402_10V6-K

.1U_0402_10V6-K

CD125

CD135

1

2

1

2

22U_0603_6.3V6-M

1U_0402_6.3V6K

1

1

CD123

@

2

2

CD67

1

@

2

@

1U_0402_6.3V6K

CD124

+VREF_CA_A0

1 2

CD134

@

.1U_0402_10V6-K

1

2

0.047U_0402_16V7K

1

2

MEM_MB_RST#_C

R180 0_0402_5%

.1U_0402_10V6-K

CD141

CD127

1

@

2

0.047U_0402_16V7K

1

@

CD139

CD128

2

1

2

CD120

.1U_0402_10V6-K

@

1000P_0402_50V7K

CD34

.1U_0402_10V6-K

1

@

2

0.047U_0402_16V7K

1

@

CD71

2

4.7U_0603_6.3V6K

for MEM_MB_RST# overshoot issue

1K_0402_1%

1K_0402_1%

.1U_0402_10V6-K

1

2

+1.35V

RD25

RD26

CD122

1

2

12

@

12

@

.1U_0402_10V6-K

CD70

1

2

CD131
33P_0402_50V8J

RF_NS@

@

1

2

1

2

CD60

.1U_0402_10V6-K

.1U_0402_10V6-K

CD132

1

CD121
33P_0402_50V8J

2

RF_NS@

+VREF_CA_B0

1

CD61

2

1000P_0402_50V7K

.1U_0402_10V6-K

1

2

RF

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/10/22

2014/10/22

2014/10/22

Title

DDRIII SO-DIMM B

DDRIII SO-DIMM B

DDRIII SO-DIMM B

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Allsparks 5B

Allsparks 5B

Allsparks 5B

1

13 51

13 51

13 51

0.3

0.3

0.3

5

4

3

2

1

Power-Up/Down Sequence

Multi-level Pin Straps

"Strato" has the following requirements with regards to power-supply
sequencing to avoid damaging the ASIC:

D D

C C

All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
preferred. The maximum slew rate on all rails is 50 mV/µs.

It is recommended that the 3.3-V rail ramps up first.

The 3.3-V, 1.8-V, and 0.95-V rails must reach their ready states at least 10 µs
before VDDC and VDDCI start to ramp up.

The external pull ups on the DDC/AUX signals (if applicable) should ramp up
before or after both VDDC and VDD_CT have ramped up.

The power rails that are shared with other components on the system should be
gated for the dGPU so that when the dGPU is powered down (for example,
AMD PowerXpress idle state), all the power rails are removed from the dGPU.
The gate circuits must meet the slew rate requirement (such as ≤ 50 mV/µs).

For power down, reversing the ramp-up sequence is recommended.

0 ~ 20 ms

0 ~ 20 ms

MLPS Bit DescriptionStrap Name

PS_0[1]

ROM_CONFIG[0]

PS_0[2]

ROM_CONFIG[1]

PS_0[3]

ROM_CONFIG[2]

PS_0[4] N/A

AUD_PORT_CONN_
PINSTRAP[0]

PS_0[5]

PS_1[1]

STRAP_BIF_GEN3_EN_A

PS_1[2]

STRAP_BIF_CLK_PM_EN

PS_1[3]

PS_1[4]

PS_1[5]

PS_2[1]

PS_2[2]

PS_2[3]

PS_2[4]

PS_2[5]

PS_3[1]
PS_3[2]
PS_3[3]

PS_3[4]

PS_3[5]

N/A

STRAP_TX_CFG_DRV_
FULL_SWING

STRAP_TX_DEEMPH_EN

N/A

N/A

STRAP_BIOS_ROM_EN

STRAP_BIF_VGA_DIS

N/A Reserved 1

BOARD_CONFIG[0]
BOARD_CONFIG[1]
BOARD_CONFIG[2]

AUD_PORT_CONN_
PINSTRAP[1]

AUD_PORT_CONN_
PINSTRAP[2]

If STRAP_BIOS_ROM_EN = 1,ROM_CONFIG[2:0] define the ROM type.
If STRAP_BIOS_ROM_EN = 0,ROM_CONFIG[2:0] define the primary
memory-aperture size.
Reserved for internal use only.
Must be 1 at reset.

The LSB (least significant bit) of the strap option that indicates the number of
audio-capable display outputs.

PCIe GEN3 capability.
1 = PCIe GEN3 is supported.
0 = PCIe GEN3 is not supported.

0 = The CLKREQB power management capability is disabled
1 = The CLKREQB power management capability is enabled

0 = The transmitter half-swing is enabled
1 = The transmitter full-swing is enabled

0 = Tx deemphasis disabled.
1 = Tx deemphasis enabled.

Reserved.

Reserved.

0 = Disable the external BIOS ROM device.
1 = Enable the external BIOS ROM device.

0 = VGA controller capacity enabled.
1 = The device will not be recognized as the system’s VGA
controller.

Board configuration related strapping, such as for memory ID

Determines the maximum number of digital display audio endpoints
that will be presented to the OS and user.

111 = No usable endpoints.
110 = One usable endpoint.
101 = Two usable endpoints.
100 = Three usable endpoints.
011 = Four usable endpoints.
010 = Five usable endpoints.
001 = Six usable endpoints.
000 = All endpoints are usable.

RECOMMENDED
SETTINGS

Design dependent

1

Design dependent

Design dependent

0

0Reserved for internal use only. Must be 0 at reset.

1

Design dependent

0

0

Design dependent

0

Design dependent

Design dependent

VDDR3(+3VGS)

VDD_CT(+1.8VGS)

10us min

PCIE_VDDC(+0.95VGS)

B B

VDDR1(+1.35VGS)

VDDC(+GPU_VDDC)

VDDCI(+GPU_VDDCI)

PERSTb(GPU_RST#)

100 ms min

100 us min

REFCLK(CLK_PCIE_VGA)

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/10/22

2014/10/22

2014/10/22

Title

VGA Notes List

VGA Notes List

VGA Notes List

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Allsparks 5B

Allsparks 5B

Allsparks 5B

1

14 51

14 51

14 51

0.3

0.3

0.3

5

4

3

2

1

PCIE_CTX_C_GRX_P[7..0]

PCIE_CTX_C_GRX_N[7..0]

PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0

PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1

PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3

PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4

PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_N5

PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_N6

PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_N7

CLK_PCIE_GPU
CLK_PCIE_GPU#

(1.8V@100mA PCIE_PVDD)

(0.95V@1500mA BIF_VDDC)

(0.95V@2700mA PCIE_VDDC)

CV24

CV25

CV26

1

1

1

2

2

2

PX@

PX@

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

U1A

PART 2 OF 16

AH52

PCIE_RX0P

AH50

PCIE_RX0N

AG53

PCIE_RX1P

AG51

PCIE_RX1N

AF52

PCIE_RX2P

AF50

PCIE_RX2N

AE53

PCIE_RX3P

AE51

PCIE_RX3N

AD52

PCIE_RX4P

AD50

PCIE_RX4N

AC53

PCIE_RX5P

AC51

PCIE_RX5N

AA53

PCIE_RX6P

AA51

PCIE_RX6N

Y52

PCIE_RX7P

Y50

PCIE_RX7N

W53

PCIE_RX8P

W51

PCIE_RX8N

V52

PCIE_RX9P

V50

PCIE_RX9N

U53

PCIE_RX10P

U51

PCIE_RX10N

R53

PCIE_RX11P

R51

PCIE_RX11N

P52

PCIE_RX12P

P50

PCIE_RX12N

N53

PCIE_RX13P

N51

PCIE_RX13N

M52

PCIE_RX14P

M50

PCIE_RX14N

L53

PCIE_RX15P

L51

PCIE_RX15N

AJ51

PCIE_REFCLKP

AJ53

PCIE_REFCLKN

AU48

PCIE_PVDD_1

AR48

PCIE_PVDD_2

U43

BIF_VDDC_1

U44

BIF_VDDC_2

U42

BIF_VDDC_3

W43

BIF_VDDC_4

AA42

PCIE_VDDC_1

AA43

PCIE_VDDC_2

AC42

PCIE_VDDC_3

CV21

1

2

PX@

1U_0402_6.3V6K

AG43

AG42

AC43

AE42
AE43
AE44

AA44

W42

R42

N42
N43

L43

PCIE_VDDC_4
PCIE_VDDC_5
PCIE_VDDC_6
PCIE_VDDC_7
PCIE_VDDC_8
PCIE_VDDC_9
PCIE_VDDC_10
PCIE_VDDC_11

EVDDC

EVDDQ0
EVDDQ1
NC_EVDDQ2

GPU@

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

PCIE_TX8P
PCIE_TX8N

PCIE_TX9P
PCIE_TX9N

PCIE_TX10P
PCIE_TX10N

PCIE_TX11P
PCIE_TX11N

PCIE_TX12P
PCIE_TX12N

PCIEXPRESS

PCIE_TX13P
PCIE_TX13N

PCIE_TX14P
PCIE_TX14N

PCIE_TX15P
PCIE_TX15N

PCIE_CALR_RX
PCIE_CALR_TX

NC_PX_EN_1

PERSTB

+1.8VGS

PCIE_CTX_C_GRX_P[7..0]4

PCIE_CTX_C_GRX_N[7..0]4

CLK_PCIE_GPU8
CLK_PCIE_GPU#8

CV17

CV18

1

1

2

2

PX@

PX@

1U_0402_6.3V6K

10U_0603_6.3V6M

+0.95VGS

CV23

CV27

CV253

1

1

1

2

2

2

PX@

PX@

PX@

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

D D

C C

1 2

RV3 0_0402_5%@

B B

PXS_RST#7

PLT_RST#7,28,30

VR_VGA_PWRGD7,49

A A

+3VGS

5

1

VCC

IN1

2

IN2

GND

MC74VHC1G08DFT2G_SC70-5

3

PX@

GPU_RST#

VR_VGA_PWRGD

OUT

UV1

4

GPU_RST#

DV1

2

3

BAT54AW_SOT323-3

1 2

RV313

PX@

0_0402_5%@

1

GPU_RST# 16,19

VGA_PWROK

VGA_PWROK 49

PCIE_CRX_GTX_P[7..0]

PCIE_CRX_GTX_N[7..0]

PCIE_CRX_C_GTX_P0 PCIE_CRX_GTX_P0

AL48

PCIE_CRX_C_GTX_N0 PCIE_CRX_GTX_N0

AL47

PCIE_CRX_C_GTX_P1

AL45

PCIE_CRX_C_GTX_N1

AL44

PCIE_CRX_C_GTX_P2

AJ48

PCIE_CRX_C_GTX_N2 PCIE_CRX_GTX_N2

AJ47

PCIE_CRX_C_GTX_P3

AG48

PCIE_CRX_C_GTX_N3

AG47

PCIE_CRX_C_GTX_P4

AG45

PCIE_CRX_C_GTX_N4

AG44

PCIE_CRX_C_GTX_P5

AE48

PCIE_CRX_C_GTX_N5

AE47

PCIE_CRX_C_GTX_P6

AC48

PCIE_CRX_C_GTX_N6

AC47

AC45

PCIE_CRX_C_GTX_N7

AC44

AA48
AA47

W48
W47

W45
W44

U48
U47

R48
R47

R45
R44

N48
N47

L48
L47

AN47
AN48

AK50

J48

PX_EN

J45

STRATO-M3-XT_FCBGA1093

RV2 1K_0402_1%PX@
RV1 1.69K_0402_1%PX@

12

RV304

PX@

1K_0402_5%

1 2
1 2

PX_EN

PCIE_CRX_GTX_P[7..0] 4

PCIE_CRX_GTX_N[7..0] 4

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

+0.95VGS

PX_EN 7,19

RV4

CV10.22U_0402_16V6-K PX@
CV20.22U_0402_16V6-K PX@

CV30.22U_0402_16V6-K PX@
CV40.22U_0402_16V6-K PX@

CV50.22U_0402_16V6-K PX@
CV60.22U_0402_16V6-K PX@

CV70.22U_0402_16V6-K PX@
CV80.22U_0402_16V6-K PX@

CV90.22U_0402_16V6-K PX@
CV100.22U_0402_16V6-K PX@

CV110.22U_0402_16V6-K PX@
CV120.22U_0402_16V6-K PX@

CV130.22U_0402_16V6-K PX@
CV140.22U_0402_16V6-K PX@

CV150.22U_0402_16V6-K PX@
CV160.22U_0402_16V6-K PX@

GPU_RST#

12

PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P2

PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3

PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4

PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5

PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6

PCIE_CRX_GTX_P7PCIE_CRX_C_GTX_P7
PCIE_CRX_GTX_N7

100K_0402_5%PX@

+0.95VGS

RF_NS@

33P_0402_50V8J

33P_0402_50V8J

CV488

CV489

1

1

2

2

RF_NS@

For RF

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/10/22

2014/10/22

2014/10/22

Title

ATI_STRATO_PCIE

ATI_STRATO_PCIE

ATI_STRATO_PCIE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Allsparks 5B

Allsparks 5B

Allsparks 5B

1

15 51

15 51

15 51

0.3

0.3

0.3

5

4

3

2

1

+3VGS

(3.3V@25mA VDDR3)

12

For EMC

+1.8VGS

1

2

GPU_RST#15,19

CV38

@

+0.95VGS

+1.8VGS

LV4

.1U_0402_16V7K

LV1 0_0402_5%PX@

(1.8V@13mA VDD_CT)

LV2 0_0402_5%PX@

GPU_SVC49
GPU_SVD49

GPU_SVT49

LV3

BLM15AG121SH1D_2P

CV37

1

2

@

.1U_0402_16V7K

PX@

1 2

BLM15AG121SH1D_2P

For EMC

LV5

CV43

1

For EMC

2

.1U_0402_16V7K

@

GPIO_19_CTF

12

+1.8VGS

PX@

1 2

(1.8V@250mA MPLL_PVDD)

10U_0603_6.3V6M

PX@

1 2

BLM15AG121SH1D_2P

GPU_RST#

RB751V-40_SOD323-2

Reserve

+3VGS

D D

10K_0404_4P2R_5%

GPIO21 can not be pull up, it will cause no-boot.

+3VGS

C C

12

PX@

10P_0402_50V8J

12

PX@

10P_0402_50V8J

B B

A A

1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2

PX@

RPV8

1 4

PX@

2 3

RPV6

PX@

10K_0804_8P4R_5%

1 2

1 2

1 2

1 2

CV34

2

YV1

PX@

GND1

OSC23GND2

CV41

18
27
36
45

RV25110K_0402_5% PX@

1

OSC1

4

GPU_GPIO5

RV1810K_0402_5% @

GPU_GPIO0

RV2110K_0402_5% @

GPU_GPIO8

RV2310K_0402_5% @

GPU_GPIO9

RV2410K_0402_5% @

GPU_GPIO10

RV2510K_0402_5% @

GPU_GPIO11

RV2710K_0402_5% @

GPU_GPIO12

RV2810K_0402_5% @

GPU_GPIO13

RV2910K_0402_5% @

GPU_GPIO22

RV3010K_0402_5% @

GPU_GPIO30

RV3110K_0402_5% @

GPU_GPIO6

RV3310K_0402_5% @

GPU_GPIO29

RV3410K_0402_5% @

GPU_GPIO1

RV24610K_0402_5% @

GPU_GPIO2

RV24710K_0402_5% @

GPU_GPIO3

RV24810K_0402_5% @

GPU_GPIO4

RV24910K_0402_5% @

GPU_GPIO20

RV25010K_0402_5% @

GPIO_7_BLON

RV25710K_0402_5% @

GPU_GPIO15

RV25910K_0402_5% @

GPU_GPIO16

RV25810K_0402_5% @

RV2604.7K_0402_5% PX@
RV2614.7K_0402_5%

GPU_HPD1
GPIO_14_HPD2

GPIO_18_HPD3
GENERICE_HPD4
GENERICF_HPD5
GENERICG_HPD6

GPU_GPIO21

JTAG_TRSTB

RV4610K_0402_5% PX@

RV2525.11K_0402_1% @

JTAG_TRSTB

RV25310K_0402_5% @

12

RV431K_0402_5% PX@

12

27MHZ_10PF_7V27000050

GPU_SCL
GPU_SDA

TESTEN

TESTEN

XTALIN

RV54
1M_0402_5%

PX@

XTALOUT

CV28

1

2

PX@

1U_0402_6.3V6K

CV29

1

2

PX@

1U_0402_6.3V6K

1 2

@

1K_0402_1%

PX@

(1.8V@75mA SPLL_PVDD)

1

1

CV35

CV36

2

2

PX@

PX@

1U_0402_6.3V6K

10U_0603_6.3V6M

CV39

CV40

CV42

1

1

1

2

2

2

1U_0402_6.3V6K

10U_0603_6.3V6M

PX@

PX@

PX@

(0.95V@100mA SPLL_VDDC)

10U_0603_6.3V6M

DV3

1 2

PX@
PX@

1 2

RV76

47K_0402_5%

+VDDR3

+VDD_CT+1.8VGS

VGA_SMB_CLK
VGA_SMB_DATA

GPU_SCL
GPU_SDA

12

RV150_0402_5% PX@

12

RV160_0402_5% PX@

12

RV170_0402_5% PX@

RV244

RV22
1K_0402_1%

1 2

1

CV254

2

PX@

.1U_0402_10V6-K

+MPLL_PVDD

1

CV256

2

PX@

.1U_0402_10V6-K

CV44

1

1

CV255

2

2

PX@

1U_0402_6.3V6K

PX@

FOR ONE TIME CTF USE 47K
FOR RESETABLE CTF USE 2K

PS_0
PS_1
PS_2
PS_3

GPU_SVC_R
GPU_SVD_R
GPU_SVT_R

+SPLL_VDDC

.1U_0402_10V6-K

PX@

RV77

+SPLL_VDDC

1

CV45

2

1 2

47K_0402_5%

BC37
BC39
BD37
BD39

AV34
AV36
AW34
AW36

BE43
BC41
BE41
BG41

AL51
AL53

BD21
BC21

BD17
BD19
BC17

BC49
BC48

BM20

BE19
BE39
BE15
BH43
BH27
BE23
BE17
BH25
BH29
BE21

AW23

AV23

AW25

AV21
AV20

@

MMBT3906_SOT23-3

100K_0402_5%

PART 5 OF 16

VDDR3_1
VDDR3_2
VDDR3_3
VDDR3_4

GPIO_5_REGHOT_AC_BATT

VDD_CT_1
VDD_CT_2
VDD_CT_3
VDD_CT_4

MLPS_0
MLPS_1
MLPS_2
MLPS_3

SMBCLK
SMBDAT

SCL
SDA

GPIO_SVC
GPIO_SVD
GPIO_SVT

DDCVGACLK
DDCVGADATA

TEST_PG

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9

GPU@

NC_10

PART 7 OF 16

SPLL_PVDD

SPLL_PVSS

SPLL_VDDC

PLLS XTAL

MPLL_PVDD_1
MPLL_PVDD_2

SPLL_CLKTESTA
SPLL_CLKTESTB

PLL_ANALOG_IN

GPU@

PLL_ANALOG_OUT

QV1

@

RV69

20K_0402_5%

@

12

@

RV78

@

PX@

1 2

RV68 0_0402_5%

U1D

GPIO_7_BLON

GPIO_8_ROMSO

GPIO_9_ROMSI

GPIO_10_ROMSCK

GPIO_14_HPD2

GPIO_17_THERMAL_INT

GPIO_18_HPD3

GPIO_19_CTF

GPIO_22_ROMCSB

GPIO

GENERICE_HPD4
GENERICF_HPD5

GENERICG_HPD6

NC_IDSC_ANALOGOUT

NC_IDSC_IL0
NC_IDSC_PWM0
NC_IDSC_PWM1
NC_IDSC_CMON

U1G

XO_IN2

XO_IN

XTALIN

XTALOUT

STRATO-M3-XT_FCBGA1093

+3VGS

E

3

B

2

C

1

12

2

B

CV48

.1U_0402_10V6-K

1

2

GPIO_11
GPIO_12
GPIO_13

GPIO_15
GPIO_16

GPIO_20
GPIO_21

GPIO_29

GPIO_30
GENERICA
GENERICB
GENERICC
GENERICD

VARY_BL

CLKREQB

NC_DSM_0
NC_DSM_1

NC_PS_4

BH50

BH52

BJ53

BJ51

BD15
BC15

BD23
BC23

12

12

13

C

E

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4

GPIO_6

WAKEB

DIGON

HPD1

CLKTESTA
CLKTESTB

PLL_ANALOG_IN

RV66
20K_0402_5%

@

RV70
20K_0402_5%

@

QV11
MMBT3904_SOT23-3

@

BG27
BH23
BN19
BG29
BE27
BH35
BC29
BA45
BG39
BH37
BH39
BE29
BC31
BD31
BK28
BG31
BG37
BD29
BK36
BC27
BH33
BH31
BH41
BE25
BG25
BE45
BC45
BG23
BL19
BK42
BA53
AW49

BM44

AW45
AW47

BK44

CEC

J47
AK52

G48
F47
F45
G45
F43
BG33
BG35
BC43

STRATO-M3-XT_FCBGA1093

XO_IN2+SPLL_PVDD

XO_IN

10K_0404_4P2R_5%

XTALIN

XTALOUT

PAD

1
1

PAD

PLL_ANALOG_OUT

GPU_GPIO0
GPU_GPIO1
GPU_GPIO2
GPU_GPIO3
GPU_GPIO4
GPU_GPIO5
GPU_GPIO6
GPIO_7_BLON
GPU_GPIO8
GPU_GPIO9
GPU_GPIO10
GPU_GPIO11
GPU_GPIO12
GPU_GPIO13
GPIO_14_HPD2
GPU_GPIO15
GPU_GPIO16
GPU_GPIO17
GPIO_18_HPD3
GPIO_19_CTF
GPU_GPIO20
GPU_GPIO21
GPU_GPIO22
GPU_GPIO29
GPU_GPIO30

GENERICE_HPD4
GENERICF_HPD5
GENERICG_HPD6

GPU_HPD1

CEC_1

1

GPU_CLKREQ#_R

PX@

1 2

4.7K_0402_5%

RPV9

PX@
1 4
2 3

TV11

@

TV10

@

PAD

1

TV8

@

1 2

RV55

16.2K_0402_1%

keep out to noisy area.

RV79

12

RV71

PX@

100K_0402_5%

RB751V-40_SOD323-2

RV8 10K_0402_5%@

RV9 0_0402_5%@

RV10

TV2

@

PAD

RV26 0_0402_5%@

RV321

PX@

PX@

1 2

2.2K_0402_5%

12

DV2

@

12
12

PX@

12

10K_0402_5%

GPU_PROCHOT#

12

RV60_0402_5% PX@

12

+3VGS

@

RV268

1 2

4.7K_0402_5%

+1.8VGS

(1.8V@300mA VDDR4)

+3VGS

1 2

+1.8VGS

RV300

Place VREF divider and CAP close to ASIC

C

2

B

CV47

.1U_0402_10V6-K

E

3 1

PX@

1

2

AC_PRESENT 7,35

GPU_PROCHOT# 35

GPU_CLKREQ# 7

PART 1 OF 16

GPU@

1

1

CV258

CV257

2

2

PX@

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

RV254

@

10K_0402_5%

221_0402_1%

1 2

PX@

12

PX@

RV255

110_0402_1%

1 2

1 2

QV2
MMBT3904WH_SOT323-3

PX@

U1E

JTAG_TDO

JTAG_TMS

JTAG

JTAG_TCK

JTAG_TRSTB

AV38
AV39
AW38
AW39

BD33
BC33
BC35
BD35

BH9
BM18
BK18

BG9

BL11
BN11

BK20

1

CV259

2

PX@

.1U_0402_10V6-K

JTAG_TDI

TESTEN

RV620_0402_5% PX@

RV2430_0402_5% @

VDDR4_1
VDDR4_2
VDDR4_3
VDDR4_4

SWAPLOCKA
SWAPLOCKB
GENLK_CLK
GENLK_VSYNC

DVPCLK
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
MVP_DVOCNTL_0
MVP_DVOCNTL_1

VREFG

JTAG_TDO

BH47

JTAG_TDI

BG48

JTAG_TMS

BE47

JTAG_TCK

BG45

BH45

TESTEN
JTAG_TRSTB

BG49

STRATO-M3-XT_FCBGA1093

U1C

PART 6 OF 16

DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9

DVPDATA_10

DVP

DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

GPU@

WRST# 35

APU_SHUTDOWN# 7

1

TV3 PAD@

1

TV12 PAD@

1

TV13 PAD@

1

TV14 PAD@

BH11
BG11
BH13
BG13
BH15
BG15
BH17
BG17
BH19
BG19
BH21
BG21
BM12
BK12
BN13
BL13
BM14
BK14
BN15
BL15
BM16
BK16
BN17
BL17

STRATO-M3-XT_FCBGA1093

+1.8VGS

+1.8VGS

RV316

RV315

+1.8VGS

SVC SVD

0

110

PX@

0_0402_5%

(1.8V@70mA AVDD)

PX@

0_0402_5%

RV319

0_0402_5%

Output Voltage (V)

00

1

1

(1.8V@117mA VDD1DI)

12

+VDD1DI

1

CV260

2

PX@

1U_0402_6.3V6K

.1U_0402_16V7K

12

+AVDD

1

1

CV262

@

2

2

PX@

1U_0402_6.3V6K

.1U_0402_16V7K

(1.8V@13mA TSVDD)

12

PX@

1U_0402_6.3V6K

GPU Internal Thermal Sensor

1.1

1.0

0.9

0.8

1

@

2

CV261

PX@

CV263

+TSVDD

1

CV46

2

PX@

PAD @

47K_0402_5%

VGA_SMB_CLK

VGA_SMB_DATA

GPU_SVD
GPU_SVC
GPU_SVT

+AVDD

DAC1_RSET

RV256

499_0402_1%

1 2

TV9

BC47

BA47

AR47

AM52

AM50

AW21

AW20

BC19

1

12

RV73

PX@

1 2

RV57

PX@

0_0402_5%

RV58
10K_0402_5%

@

1 2

1 2

RV63
10K_0402_5%

PX@

1 2

1 2

U1F

PART 8 OF 16

VDD1DI

VSS1DI

DAC1

AVDD

AVSSQ

RSET

STRATO-M3-XT_FCBGA1093

GPU@

U1B

PART 16 OF 16

TSVDD

TSS FDO

TSVSS

GPIO_28_FDO

TS_A

GPU@

+3VGS

12

RV74
47K_0402_5%

PX@

QV10A

2N7002KDWH_SOT363-6

+VDDIO_GPU+1.8VGS

RV61
10K_0402_5%

PX@

RV64
10K_0402_5%@

R

G

B

AVSSN

VSYNC
HSYNC

DPLUS

DMINUS

STRATO-M3-XT_FCBGA1093

G

2

S

RV59
10K_0402_5%

@

1 2

RV65
10K_0402_5%

@

1 2

AP50

AN51

AN53

AP52

GPU_VSYNC

AR49

GPU_HSYNC

AU49

BD25

BC25

BD27

61

PX@

D

QV10B

2N7002KDWH_SOT363-6

1

@

2

CV490

.1U_0402_16V7K

RPV10

1 4
2 3

PX@

10K_0404_4P2R_5%

GPU_DPLUS

1

TV4 PAD@

GPU_DMINUS

1

TV5 PAD@

GPIO_28_FDO

Must be held low before PCIe reset deassertion

RV75
10K_0402_5%

PX@

1 2

+3VGS

EC_SMB_CK2 6,31,35

G

5

S

34

PX@

D

EC_SMB_DA2 6,31,35

Multi-level Pin Straps

MLPS Bit DescriptionStrap Name

ROM_CONFIG[0]

PS_0[1]
PS_0[2]
PS_0[3]

PS_0[4] N/A

PS_0[5]

PS_1[1]

STRAP_BIF_GEN3_EN_A

PS_1[2]

STRAP_BIF_CLK_PM_EN

PS_1[3]

STRAP_TX_CFG_DRV_
FULL_SWING

PS_1[4]

PS_1[5]

STRAP_TX_DEEMPH_EN

PS_2[1]

PS_2[2]

PS_2[3]

STRAP_BIOS_ROM_EN

PS_2[4]

PS_2[5]

PS_3[1]
PS_3[2]
PS_3[3]

PS_3[4]

PS_3[5]

If STRAP_BIOS_ROM_EN = 1,ROM_CONFIG[2:0] define the ROM type.

ROM_CONFIG[1]

If STRAP_BIOS_ROM_EN = 0,ROM_CONFIG[2:0] define the primary

ROM_CONFIG[2]

memory-aperture size.
Reserved for internal use only.
Must be 1 at reset.

AUD_PORT_CONN_

The LSB (least significant bit) of the strap option that indicates the number of

PINSTRAP[0]

audio-capable display outputs.

PCIe GEN3 capability.
1 = PCIe GEN3 is supported.
0 = PCIe GEN3 is not supported.

0 = The CLKREQB power management capability is disabled
1 = The CLKREQB power management capability is enabled

N/A

0 = The transmitter half-swing is enabled
1 = The transmitter full-swing is enabled

0 = Tx deemphasis disabled.
1 = Tx deemphasis enabled.

N/A

Reserved.

N/A

Reserved.

0 = Disable the external BIOS ROM device.
1 = Enable the external BIOS ROM device.

0 = VGA controller capacity enabled.
1 = The device will not be recognized as the system’s VGA

STRAP_BIF_VGA_DIS

controller.

N/A Reserved 1

Board configuration related strapping, such as for memory ID

BOARD_CONFIG[0]
BOARD_CONFIG[1]
BOARD_CONFIG[2]

AUD_PORT_CONN_
PINSTRAP[1]
AUD_PORT_CONN_
PINSTRAP[2]

GDDR5 VRAM auto detect , no need memory ID.
config as 000

Determines the maximum number of digital display audio endpoints
that will be presented to the OS and user.

111 = No usable endpoints.
110 = One usable endpoint.
101 = Two usable endpoints.
100 = Three usable endpoints.
011 = Four usable endpoints.
010 = Five usable endpoints.
001 = Six usable endpoints.
000 = All endpoints are usable.

Capacitor Value (nF) Bits [5:4]

680

00

82

01

10

10

NC

11

Bit

MLPS

5 4 3 2 1

1 1

PS_0[5:1]

PS_1[5:1]

PS_2[5:1]

PS_3[5:1]

8.45K_0402_1%

00 1

1 1

00001

1 1

0

1 1

0 0 0

+1.8VGS +1.8VGS

12

RV37

PX@

PS_0

12

1

CV30

RV41

2K_0402_1%

PS_2

4.75K_0402_1%

.01U_0402_16V7-K

@

PX@

2

+1.8VGS +1.8VGS

12

RV44
10K_0402_5%

@

12

1

RV51

CV32
.01U_0402_16V7-K

PX@

@

2

RECOMMENDED
SETTINGS

Design dependent

256M=001

BOM

RV314

PX@

disable =1

R_pd (Ω)

RV49

PX@

4750

2000

2000

4990

4990

5620

10000

NC

12

RV38

8.45K_0402_1%PX@

12

12

RV45
10K_0402_5%

@

12

Design dependent

Design dependent

Design dependent

Design dependent

Design dependent

Design dependent

1

2

1

2

No usable endpoints =1

Gen3 support =1

enable=1

disable =0

111 = No usable endpoints.

R_pu (Ω) Bits [3:1]

NC

8450

4530

6980

4530

3240

3400

4750

Note: 0402 1% resistors are required.

R_pu R_pd C(nF)

8.45K 2K NC

8.45K 2K

NC 4.75K

NC 4.75K

PS_1

2K_0402_1%

PS_3

4.75K_0402_1%

1

0

0Reserved for internal use only. Must be 0 at reset.

1

0

0

0

000

001

010

011

100

101

110

111

NC

NC

NC

CV31
.01U_0402_16V7-K

@

CV33
.01U_0402_16V7-K

@

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2014/10/22

2014/10/22

2014/10/22

Title

ATI_STRATO_PCIE

ATI_STRATO_PCIE

ATI_STRATO_PCIE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

D

D

D

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Allsparks 5B

Allsparks 5B

Allsparks 5B

16 51

16 51

16 51

0.3

0.3

0.3

5

+1.8VGS

1 2

RV80

D D

+0.95VGS

1 2

RV81

PX@

0_0603_5%

C C

(1.8V@75mA DP_VDDR)

PX@

0_0603_5%

PX@

1

2

CV264

10U_0603_6.3V6M

(0.95V@140mA DP_VDDC)

PX@

1

2

CV268

10U_0603_6.3V6M

+DP_VDDR

@

CV49

10U_0603_6.3V6M

10U_0603_6.3V6M

@

PX@

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CV50

CV267

@

PX@

1

1

2

2

1U_0402_6.3V6K

CV269

CV51

@

@

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CV266

CV265

+DP_VDDC

@

1

2

1U_0402_6.3V6K

CV270

AW42

DP_VDDR_1

AU44

DP_VDDR_2

AW43

DP_VDDR_3

AU42

1

2

AU43

BA42

AR44

AW44

AJ42
AJ43
AJ44

AL42
AN42
AN43
AN44
AR42
AR43

DP_VDDR_4
DP_VDDR_5
DP_VDDR_6
DP_VDDR_7
DP_VDDR_8

DP_VDDC_1
DP_VDDC_2
DP_VDDC_3
DP_VDDC_4
DP_VDDC_5
DP_VDDC_6
DP_VDDC_7
DP_VDDC_8
DP_VDDC_9

4

PART 9 OF 16

U1N

TX2P_DPA0P

TX2M_DPA0N

TX1P_DPA1P

TX1M_DPA1N

TX0P_DPA2P

TX0M_DPA2N

TXCAP_DPA3P

TXCAM_DPA3N

DDCAUX3P

TMDP A/B

DDCAUX3N

BL41

BN41

BK40

BM40

BL39

BN39

BK38

BM38

BL37

BN37

3

U1O

PART 10 OF 16

AUX1P

AUX1N

DDC1CLK

DDC1DATA

BL27

BN27

BK26

BM26

BL25

BN25

BK24

BM24

BK22

BM22

BL23

BN23

TX2P_DPC0P

TX2M_DPC0N

TX1P_DPC1P

TX1M_DPC1N

TX0P_DPC2P

TX0M_DPC2N

TXCCP_DPC3P

TXCCM_DPC3N

TMDP C/D

2

PART 11 OF 16

1

U1P

TXOUT_L3P

TXOUT_L3N

TX2P_L2P_DPE0P

TX2M_L2N_DPE0N

TX1P_L1P_DPE1P

TX1M_L1N_DPE1N

TX0P_L0P_DPE2P

TX0M_L0N_DPE2N

TXCEP_LP_DPE3P

TXCEM_LN_DPE3N

DDCAUX5P

DDCAUX5N

TMDP E/F

BB52

BB50

BC53

BC51

BD52

BD50

BE53

BE51

BF52

BF50

BE48

BE49

AUX2P

AUX2N

DDC2CLK

DDC2DATA

Deciphered Date

Deciphered Date

Deciphered Date

BL35

BN35

BK34

BM34

BL33

BN33

BK32

BM32

BK30

BM30

BL31

BN31

STRATO-M3-XT_FCBGA1093

RV83

2014/10/22

2014/10/22

2014/10/22

2

1 2

PX@

150_0402_1%

TXOUT_U3P

TXOUT_U3N

TX5P_U2P_DPF0P

TX5M_U2N_DPF0N

TX4P_U1P_DPF1P

TX4M_U1N_DPF1N

TX3P_U0P_DPF2P

TX3M_U0N_DPF2N

TXCFP_UP_DPF3P

TXCFM_UN_DPF3N

BA49

DPEF_CALR

GPU@

Title

Title

Title

ATI_STRATO_PCIE

ATI_STRATO_PCIE

ATI_STRATO_PCIE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

DDCAUX6P

DDCAUX6N

Allsparks 5B

Allsparks 5B

Allsparks 5B

TX5P_DPB0P

TX5M_DPB0N

TX4P_DPB1P

TX4M_DPB1N

TX3P_DPB2P

B B

PX@

DPAB_CALR

BM42

DPAB_CALR

GPU@

1 2

RV84

150_0402_1%

A A

5

TX3M_DPB2N

TXCBP_DPB3P

TXCBM_DPB3N

DDCAUX4P

DDCAUX4N

4

BL49

BN49

BK48

BM48

BL47

BN47

BK46

BM46

BL45

BN45

STRATO-M3-XT_FCBGA1093

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1 2

RV82

150_0402_1%

Issued Date

Issued Date

Issued Date

DPCD_CALR DPEF_CALR

3

BM28

DPCD_CALR

GPU@

2014/10/22

2014/10/22

2014/10/22

PX@

TX5P_DPD0P

TX5M_DPD0N

TX4P_DPD1P

TX4M_DPD1N

TX3P_DPD2P

TX3M_DPD2N

TXCDP_DPD3P

TXCDM_DPD3N

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

AT52

AT50

AU53

AU51

AV52

AV50

AW53

AW51

AY52

AY50

AR53

AR51

STRATO-M3-XT_FCBGA1093

17 51

17 51

17 51

1

0.3

0.3

0.3

5

4

3

2

1

U1H

D D

BB23

BB19

BG6

AL11
AA18
AT31
AA21
AA33
AA36
AA45
AA49

AA5
AC1

AW27

AC15

C C

B B

AG23

AG31

AG15
AG25

AG29
AG39

AW48

AG49

AC25

AC29
AC39
BA51
AC49

BK10
AV25

AE27

AC31

AE45
AE49

AJ33

AU10

AL15
AJ18
AJ21
AL39
AJ36
AJ45
AJ49

AB52

AC5

R23

R31

AE5
AG1
AC9

AG5

AG9

PART 14 OF 16

A11

VSS_1

L23

VSS_2

A15

VSS_3

L41

VSS_4

A19

VSS_5

L31

VSS_6

A23

VSS_7

K17

VSS_8

A27

VSS_9
VSS_10

A31

VSS_11

L13

VSS_12

A35

VSS_13

A39

VSS_15
VSS_16

A43

VSS_17
VSS_18

A47

VSS_19

B50

VSS_20

A7

VSS_21

K21

VSS_22

W9

VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31

GND 1

VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42

T50

VSS_43

T52

VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73

AJ5

VSS_74
VSS_75

GPU@

AL1

VSS_76

AL9

VSS_77

AL18

VSS_78

AL21

VSS_79

AC23

VSS_80

AL33

VSS_81

AL36

VSS_82

BL29

VSS_83

AL49

VSS_84

AW5

VSS_85

AJ10

VSS_86

AR9

VSS_87

AN16

VSS_88

AN21

VSS_89

AN27

VSS_90

AN33

VSS_91

AN38

VSS_92

BA48

VSS_93

AN5

VSS_94

AP16

VSS_95

AN20

VSS_96

AP27

VSS_97

AN34

VSS_98

AP38

VSS_99

AB50

VSS_100

AR1

VSS_101

AW9

VSS_102

AN45

VSS_103

BE31

VSS_104

AR5

VSS_105

AT16

VSS_106

AT20

VSS_107

R27

VSS_108

AT34

VSS_109

AT38

VSS_110

G49

VSS_111

AE10

VSS_112

D4

VSS_113

AN49

VSS_114

AU5

VSS_115

AV15

VSS_116

AV16

VSS_117

AV33

VSS_118

AW1

VSS_119

BC9

VSS_120

BB41

VSS_122

BE5

VSS_123

B4

VSS_124

BN7

VSS_125

BC6

VSS_126

BA5

VSS_127

R11

VSS_128

BC1

VSS_129

BM10

VSS_130

BE37

VSS_131

BC5

VSS_132

BB21

VSS_133

BB17

VSS_135

BJ27

VSS_136

BJ29

VSS_137

BB31

VSS_138

BB33

VSS_139

BB35

VSS_140

BB37

VSS_141

BE33

VSS_142

BM4

VSS_143

BB15

VSS_144

BG43

VSS_145

AW33

VSS_146

BG5

VSS_147

BL9

VSS_148

BG1

VSS_149

BE11

VSS_150

STRATO-M3-XT_FCBGA1093

AW29

AN10

BA11

BB39

AV27

AV29

AU47

BM36
BG51

BH7

VSS_152

BE9

VSS_153

BJ11

VSS_154

BJ13

VSS_155

BJ15

VSS_156

BJ5

VSS_157

BJ7

VSS_158

BJ9

VSS_159

BK2

VSS_160

E5

VSS_161

D52

VSS_162

D2

VSS_163

E11

VSS_164

E13

VSS_165

E15

VSS_166

E17

VSS_167

E19

VSS_168

E21

VSS_169

E23

VSS_170

E25

VSS_171

E27

VSS_172

E29

VSS_173

E31

VSS_174

E33

VSS_175

E35

VSS_176

E37

VSS_177

E39

VSS_178

E41

VSS_179

E43

VSS_180

E45

VSS_181

E47

VSS_182

E49

VSS_183

L5

VSS_184

E7

VSS_185

E9

VSS_186

G1

VSS_187
VSS_188

J43

VSS_189

G5

VSS_190

L15

VSS_191

N11

VSS_192

G53

VSS_193

J49

VSS_194

J5

VSS_195

K50

VSS_196

K52

VSS_197

L45

VSS_198
VSS_199

J15

VSS_200
VSS_201

J19

VSS_202

R9

VSS_203

J23

VSS_204

K25

VSS_205

K33

VSS_206
VSS_207

J31

VSS_208
VSS_209

J35

VSS_210
VSS_211

J39

VSS_212

L1

VSS_213

J11

VSS_214
VSS_215

K29

VSS_216

L49

VSS_217

AL5

VSS_218

L9

VSS_219

K37

VSS_220

N45

VSS_221

N49

VSS_222

N5

VSS_223
VSS_224
VSS_225

GPU@

PART 15 OF 16

U1I

R1

VSS_226

AA10

VSS_227

R16

VSS_228

AT27

VSS_229

R20

VSS_230

R34

VSS_231

R38

VSS_232

AL43

VSS_233

BG53

VSS_234

AV31

VSS_235

AW31

VSS_236

R49

VSS_237

R5

VSS_238

T15

VSS_239

V20

VSS_240

T27

VSS_241

V34

VSS_242

T39

VSS_243

BE7

VSS_244

U10

VSS_245

U45

VSS_246

U49

VSS_247

U5

VSS_248

Y15

VSS_249

V21

VSS_250

V27

VSS_251

V33

VSS_252

Y39

VSS_253

W1

VSS_254

AC11

VSS_255

R43

VSS_256

GND 2

W49

VSS_257

W5

VSS_258

J51

VSS_259

Y18

VSS_260

AT23

VSS_261

Y21

VSS_262

Y33

VSS_263

Y36

VSS_264

J27

VSS_265

BJ25

VSS_266

BL21

VSS_267

BE35

VSS_268

BA43

VSS_269

BK50

VSS_270

BK52

VSS_271

BJ17

VSS_272

BJ19

VSS_273

BJ21

VSS_274

BJ23

VSS_275

BB25

VSS_276

BB27

VSS_277

BB29

VSS_278

BJ31

VSS_279

BJ33

VSS_280

BJ35

VSS_281

BJ37

VSS_282

BJ39

VSS_283

BJ41

VSS_284

BJ43

VSS_285

BJ45

VSS_286

BJ49

VSS_287

BM50

VSS_288

BN43

VSS_289

BN29

VSS_290

BL43

VSS_291

BJ47

VSS_292

BN21

VSS_293

AR45

VSS_294

AU45

VSS_295

STRATO-M3-XT_FCBGA1093

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/10/22

2014/10/22

2014/10/22

Title

ATI_STRATO_PCIE

ATI_STRATO_PCIE

ATI_STRATO_PCIE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Allsparks 5B

Allsparks 5B

Allsparks 5B

1

18 51

18 51

18 51

0.3

0.3

0.3

5

4

3

2

1

+GPU_VDDC

CV333

CV332

1

1

2

2

PX@

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

D D

C C

+3.3VS TO +3VGS +1.35V TO +1.35VGS

+5VALW

PXS_PWREN7,48,49

B B

+1.8VALW to +1.8VGS

+/- 2%

1

CV110

10U_0805_25V6K

PX@

2

AON6414AL
VDS=30V VGS=20V, ID=50A,
Rds=8mohm @ VGS=10V
VGS(th)=2.5V Max

A A

(0.825V to 1.225V@60A VDDC)

CV320

CV334

1

2

PX@

1U_0402_6.3V6K

RV92

1 2

20K_0402_1%

+1.8VALW

CV319

PX@

1U_0402_6.3V6K

PX@

PXS_PWREN

12

1

1

2

2

PX@

1U_0402_6.3V6K

RV96
100K_0402_5%

PX@

QV19
AON6414AL_DFN8-5

5

CV324

CV323

CV322

PX@

1U_0402_6.3V6K

4

CV112

PX@

1 2

1

2

1U_0402_6.3V6K

LP2301ALT1G_SOT23-3

13

D

S

2N7002KW_SOT323-3

1
2
3

0.1U_0402_25V6-K

CV325

1

1

1

2

2

2

PX@

PX@

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

+GPU_VDDC

22U_0603_6.3V6-M

Need OPEN

+3VS +3VGS

JV1

QV13

RV93

12

PX@

10K_0402_5%

CV101

QV17

+1.8VGS

1

2

10U_0603_6.3V6M

CV321

1

2

PX@

1U_0402_6.3V6K

PXS_PWREN# PXS_PWREN#

2

G

PX@

PX@

CV326

CV328

CV327

1

1

1

2

2

2

PX@

PX@

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

1

CV461

CV462

CV460

2

2

2

PX@

PX@

PX@

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

2

@

112

JUMP_43X39

D

S

13

PX@

G

2

PX@

1 2

0.1U_0402_25V6-K

+/- 3% 0.5A

1

CV104

CV105

2

PX@

PX@

10U_0603_6.3V6M

12

RV99
120K_0402_5%

PX@

CV329

1

2

PX@

1U_0402_6.3V6K

1

CV463

2

PX@

22U_0603_6.3V6-M

13

D

S

CV330

1

2

PX@

1U_0402_6.3V6K

1

1

CV465

CV464

2

2

PX@

PX@

22U_0603_6.3V6-M

CV93

1

2

PX@

10U_0603_6.3V6M

1

CV106
1U_0603_25V6M

2

PX@

R3

PX@

QV23

G

2N7002KW_SOT323-3

PX@

AA15
AA16

AA23
AA25

CV331

1

AA29
AA31
AA34

2

AA38
AA39

PX@

1U_0402_6.3V6K

AC16
AC18
AE25
AC20
AC21
AC33
AC34
AC27
AC36
AC38
AE16
AE18
AA27
AE20

1

1

CV467

CV466

AA20
AE34

2

2

AE36

PX@

PX@

AE38
AG16

22U_0603_6.3V6-M

22U_0603_6.3V6-M

AG18
AG21
AG20
AG27
AE29
AG34
AG33
AG36
AG38

AE23
AE31

AN15
AN18
AP20
AN23
AN25
AN29
AN31
AP34

CV94

12

1

RV90
470_0603_5%

@

2

PX@

1U_0402_6.3V6K

13

D

QV15

S

2N7002KW_SOT323-3

REV@

100K_0402_5%

12

B+

PXS_PWREN# PXS_PWREN#PXS_PWREN#

2

2

U1J

PART 12 OF 16

POWER1

VDDC_69
VDDC_70
VDDC_71
VDDC_72
VDDC_73
VDDC_74
VDDC_75
VDDC_76
VDDC_77
VDDC_78
VDDC_79
VDDC_80
VDDC_81
VDDC_82
VDDC_83
VDDC_84
VDDC_85
VDDC_86
VDDC_87
VDDC_88
VDDC_89
VDDC_90
VDDC_91
VDDC_92
VDDC_93
VDDC_94
VDDC_95
VDDC_96
VDDC_97
VDDC_98

VDDC_99
VDDC_100
VDDC_101
VDDC_102
VDDC_103
VDDC_104
VDDC_105
VDDC_106
VDDC_107
VDDC_108
VDDC_109
VDDC_110
VDDC_111
VDDC_112
VDDC_113
VDDC_114
VDDC_115
VDDC_116
VDDC_117
VDDC_118
VDDC_119
VDDC_120
VDDC_121
VDDC_122
VDDC_123
VDDC_124
VDDC_125
VDDC_126
VDDC_127
VDDC_128
VDDC_129
VDDC_130

FB_VDDC

FB_VSSC

AN36
AN39
AP15
AP18
AP21
AP23
AP25
AP29
AP31
AP33
AP36
AP39
AT15
AT18
AT21
AE21
AT25
AT29
AE33
AT33
AT36
AT39
R15
R18
AE15
R21
R36
R25
R29
R33
AE39
R39
T16
T18
T21
T23
T25
T29
T31
T33
T36
T38
V16
V18
T20
V23
V25
V29
V31
T34
V36
V38
V15
Y16
Y27
Y23
Y25
Y29
Y31
Y34
Y38
V39

GPU_VDDC_SENSE

AV18

GPU_VSSC_SENSE

AW18

STRATO-M3-XT_FCBGA1093

CV271

1

2

PX@

1U_0402_6.3V6K

CV300

PX@

1U_0402_6.3V6K

CV316

1

2

PX@

1U_0402_6.3V6K

PXS_PWREN#

CV272

1

2

PX@

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

CV317

1

2

PX@

1U_0402_6.3V6K

CV274

CV273

1

1

2

2

PX@

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

CV302

CV301

1

1

2

2

PX@

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

+GPU_VDDC

CV318

CV303

1

1

2

2

PX@

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

RV308 0_0402_5%

CV287

1

2

PX@

CV275

1

2

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

+5VALW

NOBACO@

BACO@

CV280

CV282

CV281

CV279

CV276

CV277

CV278

1

1

1

1

1

1

1

2

2

2

2

2

2

2

PX@

PX@

PX@

PX@

PX@

PX@

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

CV290

CV289

CV291

CV293

CV294

CV288

PX@

CV292

1

1

1

1

1

1U_0402_6.3V6K

12

2

PX@

2

PX@

1U_0402_6.3V6K

RV94

1 2

56K_0402_1%

PX@

1

CV470.1U_0402_16V7K

2

1U_0402_6.3V6K

1

2

2

2

PX@

PX@

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

GPU_VDDC_SENSE 49
GPU_VSSC_SENSE 49

CV95

1

2

PX@

10U_0603_6.3V6M

13

D

2

G

S

PX@

2N7002KW_SOT323-3

BACO@

RV306 0_0402_5%

BACO_VDDC_1.35V

QV12

2

G

2

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

QV18

12

BACO@

2

G

+GPU_VDDC +0.95VGS+1.8VGS

12

13

D

S

1

2

VDDC_1
VDDC_2

AJ34

VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24

Y20

VDDC_25
VDDC_26
VDDC_27

AJ27

VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32
VDDC_33
VDDC_34
VDDC_35
VDDC_36
VDDC_37
VDDC_38
VDDC_39
VDDC_40

AL16

VDDC_41

AL34

VDDC_42

AJ16

VDDC_43

AJ23

VDDC_44

AJ25

VDDC_45

AJ29

VDDC_46

AJ31

VDDC_47

AJ38

VDDC_48
VDDC_49
VDDC_50

AJ15

VDDC_51

AL27

VDDC_52

AJ20

VDDC_53

AL23

VDDC_54

AL25

VDDC_55

AL29

VDDC_56

AL31

VDDC_57

AL38

VDDC_58

AL20

VDDC_59

AJ39

VDDC_60
VDDC_61
VDDC_62
VDDC_63
VDDC_64
VDDC_65
VDDC_66
VDDC_67
VDDC_68

GPU@

PXS_PWREN#

2

G

12

RV98
470_0603_5%

@

13

D

QV24

G

S

2N7002KW_SOT323-3REV@

+GPU_VDDC

CV284

CV285

CV283

CV286

1

1

1

1

2

2

2

2

PX@

PX@

PX@

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

+GPU_VDDC

CV295

CV296

CV297

CV299

CV298

1

1

1

1

1

2

2

2

2

2

PX@

PX@

PX@

PX@

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

+1.35V +1.35VGS

CV96

1

AON6554_DFN

2

PX@

QV14

PX@

4

12

RV95

CV102
499K_0402_1%

@

PX@

1 2

+5VALW

BACO@

1 2

RV307

20K_0402_5%

13

D

QV26

S

2N7002KW_SOT323-3

RV89
470_0603_5%

@

2N7002KW_SOT323-3REV@

W11

AW7

AG7

BACO@

F7
G15
AE9

W7

AJ9

AR7
AU9
L39

BA9
BC7
L11
J13

N9
J17
G19
J21
G23
J25
G27
J29
G31
J33
G35
J37
G39
G43
J41
L19

J9
L27
L35
AA9

U9

AN9

R7

AC7

AL7

G6

BE6

1

CV477

2

EMC_NS@

PART 13 OF 16

VDDR1_1
VDDR1_2
VDDR1_3
VDDR1_4
VDDR1_5
VDDR1_6
VDDR1_7
VDDR1_8
VDDR1_9
VDDR1_10
VDDR1_11
VDDR1_12
VDDR1_13
VDDR1_14
VDDR1_15
VDDR1_16
VDDR1_17
VDDR1_18
VDDR1_19
VDDR1_20
VDDR1_21
VDDR1_22
VDDR1_23
VDDR1_24
VDDR1_25
VDDR1_26
VDDR1_27
VDDR1_28
VDDR1_29
VDDR1_30
VDDR1_31
VDDR1_32
VDDR1_33
VDDR1_34
VDDR1_35
VDDR1_36
VDDR1_37
VDDR1_38
VDDR1_39
VDDR1_40
VDDR1_41
VDDR1_42
VDDR1_43
VDDR1_44
VDDR1_45
VDDR1_46

GPU@

1

CV476

2

.1U_0402_16V7K

.1U_0402_16V7K

EMC_NS@

For EMC

12

BACO@

CV469

BACO@

13

D

QV25

S

2N7002KW_SOT323-3

U1K

AA12

VDDCI_1

AC12

VDDCI_2

AE12

VDDCI_3

AG12

VDDCI_4

AJ12

VDDCI_5

AL12

CV352

CV351

CV350

1

1

VDDCI_6

AN12

VDDCI_7

AR12

VDDCI_8

AU12

VDDCI_9

M13

VDDCI_10

M15

VDDCI_11

M17

VDDCI_12

M19

VDDCI_13

M21

VDDCI_14

M23

VDDCI_15

M25

VDDCI_16

M27

VDDCI_17

M29

VDDCI_18

POWER 2

M31

VDDCI_19

M33

VDDCI_20

M35

VDDCI_21

M37

VDDCI_22

M39

VDDCI_23

AW12

VDDCI_24

N12

VDDCI_25

R12

VDDCI_26

U12

VDDCI_27

W12

VDDCI_28

BB13

VDDCI_29

BC13

VDDCI_30

BE13

VDDCI_31

AW15

FB_VDDCI

AW16

FB_VSSCI

STRATO-M3-XT_FCBGA1093

1

1

1

CV475

2

EMC_NS@

CV479

CV478

2

2

EMC_NS@

EMC_NS@

.1U_0402_16V7K

.1U_0402_16V7K

1

2

2

2

PX@

PX@

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

CV360

1

2

PX@

1U_0402_6.3V6K

GPU_VDDCI_SENSE
GPU_VSSCI_SENSE

+GPU_VDDCI+1.35VGS+GPU_VDDC

1

1

CV480

CV481

2

2

EMC_NS@

EMC_NS@

.1U_0402_16V7K

.1U_0402_16V7K

BACO Circuites

1

2

.1U_0402_16V7K

+3VGS +3VGS +3VGS

RV301

BACO@

10K_0402_5%

1 2

RV118

1 2

BACO@

1.5K_0402_1%

1

BACO@

CV468

2

.1U_0402_16V7K

UV10

1

OE

2

A

BACO@

3

GND

74AHC1G126GV_SOT753-5

RV302 0_0402_5%@

+1.35VGS

(1.35V @2A VDDR1) (0.8V to 0.9V @10A VDDCI)

CV74

CV337

CV336

CV335

1

1

1

2

2

2

PX@

PX@

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

PX@

CV341

CV338

CV339

CV340

1

1

1

2

2

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

1

CV61

AW11

2

2

2

2

PX@

PX@

PX@

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_10V6-K

+1.35VGS

CV348

CV347

1

1

1

CV349

2

2

2

PX@

PX@

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0603_6.3V6K

AG11
AR11

BC11

1

1

1

CV473

CV472

CV474

2

2

2

.1U_0402_16V7K

EMC_NS@

EMC_NS@

EMC_NS@

.1U_0402_16V7K

.1U_0402_16V7K

+/- 3% 6A

CV99

CV98

1
2
35

0.1U_0402_25V6-K

1

2

PX@

10U_0603_6.3V6M

1

1

1

CV491

330U_B2_2.5VM_R9M

CV492

330U_B2_2.5VM_R9M

CV498

330U_B2_2.5VM_R9M

+

+

+

2

2

2

QV22

2

G

12

1

1

CV100

RV91
470_0603_5%

@

2

2

PX@

PX@

13

.1U_0402_10V6-K

D

10U_0603_6.3V6M

1

CV496

+

2

330U_B2_2.5VM_R9M

1

+

2

12

RV97
470_0603_5%

@

13

D

S

2N7002KW_SOT323-3REV@

QV16

2

G

CV499

330U_B2_2.5VM_R9M

S

2N7002KW_SOT323-3

REV@

PXS_PWREN

RV305 0_0402_5%

GPU_RST#

GPU_RST#15,16

PX_EN

PX_EN7,15

PX_EN =0, for Normal Operation
PX_EN =1, for BACO mode to shut down power rails except VDDR3, PCIE_VDDC and 1.8V rail

2

G

+GPU_VDDCI

CV80

CV82

CV81

CV83

1

2

PX@

1U_0402_6.3V6K

CV359

1

2

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

PX@

+GPU_VDDCI

CV358

PX@

1U_0402_6.3V6K

1

1

1

CV84

2

2

2

PX@

PX@

PX@

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

CV356

1

1

2

2

PX@

1U_0402_6.3V6K

GPU_VDDCI_SENSE 49
GPU_VSSCI_SENSE 49

+GPU_VDDCI+1.35VGS+GPU_VDDC

CV482

33P_0402_50V8J

CV484

RF_NS@

1

2

RF_NS@

1

1

2

RF_NS@

1

2

2

RF_NS@

33P_0402_50V8J

CV483

33P_0402_50V8J

CV487

CV485

33P_0402_50V8J

33P_0402_50V8J

CV486

33P_0402_50V8J

1

1

2

2

RF_NS@

RF_NS@

For RF

+3VGS

CV471

.1U_0402_16V7K

1 2

RV303

5

BACO@

VCC

10K_0402_5%

BACO@

1 2

4

Y

12

5

1

IN1

2

BACO@

IN2

3

UV11

VCC

BACO_VDDC_1.35V

4

OUT

GND

MC74VHC1G08DFT2G_SC70-5

12

RV320
100K_0402_5%

BACO@

BACO_VDDC_1.35V 49

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2014/10/22

2014/10/22

2014/10/22

Title

ATI_STRATO_PCIE

ATI_STRATO_PCIE

ATI_STRATO_PCIE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

D

D

D

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Allsparks 5B

Allsparks 5B

Allsparks 5B

19 51

19 51

19 51

0.3

0.3

0.3

5

4

3

2

1

CHB@

51.1_0402_1%

DQB1_D[31..0]

DQB0_D[31..0]

MAB0_[8..0]

MAB1_[8..0]

120P_0402_50V8-J

DQA1_D[31..0]

DQA0_D[31..0]

MAA0_[8..0]

MAA1_[8..0]

D D

C C

+1.35VGS

RV101

40.2_0402_1%

@

RV102

100_0402_1%

@

+1.35VGS

RV103

40.2_0402_1%

@

B B

RV104

100_0402_1%

@

12

12

12

12

1

2

1

2

DRAM_RSTA21,22

DQA1_D[31..0] 22

DQA0_D[31..0] 21

MAA0_[8..0] 21

MAA1_[8..0] 22

MVREFDA

CV113
1U_0402_6.3V6K

@

MVREFDB

CV114
1U_0402_6.3V6K

@

CHA@

51.1_0402_1%

120P_0402_50V8-J

U1L

G51

F52
F50
E53
D50
C49
A49
D48
B48
C47
D46
B46
D44
B44
C43
D42
A41
D40
B40
C39
C37
A37
D36
B36
C35
D34
B34
C33
D32
B32
C31
D30

L33

G33

F37

G37

F39
K39
F29

G29

F33
L37

J53
H52

B42
C41

E51
C45
B38
A33

H50
A45
D38
B30

L29

K35
K31

K27
F35

M41

G25

F41

G41

F31

L25

DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_12
DQA0_13
DQA0_14
DQA0_15
DQA0_16
DQA0_17
DQA0_18
DQA0_19
DQA0_20
DQA0_21
DQA0_22
DQA0_23
DQA0_24
DQA0_25
DQA0_26
DQA0_27
DQA0_28
DQA0_29
DQA0_30
DQA0_31

MAA0_0
MAA0_1
MAA0_2
MAA0_3
MAA0_4
MAA0_5
MAA0_6
MAA0_7
MAA0_8
MAA0_9

WCKA0_0
WCKA0B_0

WCKA0_1
WCKA0B_1

EDCA0_0
EDCA0_1
EDCA0_2
EDCA0_3

DDBIA0_0
DDBIA0_1
DDBIA0_2
DDBIA0_3

ADBIA0

CSA0B_0
CSA0B_1

CASA0B
RASA0B
WEA0B

CKEA0

CLKA0
CLKA0B

MEM_CALRA

DRAM_RSTA

PART 3 OF 16

MEMORY INTERFACE BANK A

DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31

WCKA1_0

WCKA1B_0

WCKA1_1

WCKA1B_1

EDCA1_0
EDCA1_1
EDCA1_2
EDCA1_3

DDBIA1_0
DDBIA1_1
DDBIA1_2
DDBIA1_3

CSA1B_0
CSA1B_1

CASA1B
RASA1B

MVREFDA

A29

DQA1_0

D28

DQA1_1

B28

DQA1_2

C27

DQA1_3

B26

DQA1_4

C25

DQA1_5

A25

DQA1_6

D24

DQA1_7

B24

DQA1_8

C23

DQA1_9

D22
B22
D20
B20
C19
D18
A17
D16
B16
C15
C13
A13
D12
B12
C11
D10
B10
C9
D8
B8
C7
B6

K19

MAA1_0

F17

MAA1_1

G13

MAA1_2

F15

MAA1_3

F13

MAA1_4

F11

MAA1_5

F23

MAA1_6

L21

MAA1_7

F19

MAA1_8

G17

MAA1_9

C17
B18

A5
C5

D26
C21
B14
A9

C29
A21
D14
D6

G21

ADBIA1

K15
F21

K23
L17
G11

WEA1B

F25

CKEA1

F9

CLKA1

G9

CLKA1B

F27

GPU@

STRATO-M3-XT_FCBGA1093

DQA1_D1
DQA1_D2
DQA1_D3
DQA1_D4
DQA1_D5
DQA1_D6
DQA1_D7
DQA1_D8
DQA1_D9
DQA1_D10
DQA1_D11
DQA1_D12
DQA1_D13
DQA1_D14
DQA1_D15
DQA1_D16
DQA1_D17
DQA1_D18
DQA1_D19
DQA1_D20
DQA1_D21
DQA1_D22
DQA1_D23
DQA1_D24
DQA1_D25
DQA1_D26
DQA1_D27
DQA1_D28
DQA1_D29
DQA1_D30
DQA1_D31

MAA1_1
MAA1_2
MAA1_3
MAA1_4
MAA1_5
MAA1_6
MAA1_7
MAA1_8

WCKA1_0
WCKA1B_0

WCKA1_1
WCKA1B_1

EDCA1_0
EDCA1_1
EDCA1_2
EDCA1_3

DDBIA1_0
DDBIA1_1
DDBIA1_2
DDBIA1_3

ADBIA1

CASA1B
RASA1B

WEA1B

CLKA1B

MVREFDA

CKEA1

CLKA1

WCKA1_0 22
WCKA1B_0 22

WCKA1_1 22
WCKA1B_1 22

EDCA1_0 22
EDCA1_1 22
EDCA1_2 22
EDCA1_3 22

DDBIA1_0 22
DDBIA1_1 22
DDBIA1_2 22
DDBIA1_3 22

ADBIA1 22

CASA1B 22
RASA1B 22

CLKA1B 22

DRAM_RSTB23,24

WEA1B 22

CKEA1 22

CLKA1 22

DQA0_D0 DQA1_D0
DQA0_D1
DQA0_D2
DQA0_D3
DQA0_D4
DQA0_D5
DQA0_D6
DQA0_D7
DQA0_D8
DQA0_D9
DQA0_D10
DQA0_D11
DQA0_D12
DQA0_D13
DQA0_D14
DQA0_D15
DQA0_D16
DQA0_D17
DQA0_D18
DQA0_D19
DQA0_D20
DQA0_D21
DQA0_D22
DQA0_D23
DQA0_D24
DQA0_D25
DQA0_D26
DQA0_D27
DQA0_D28
DQA0_D29
DQA0_D30
DQA0_D31

MAA0_0 MAA1_0
MAA0_1
MAA0_2
MAA0_3
MAA0_4
MAA0_5
MAA0_6
MAA0_7
MAA0_8

WCKA0_021
WCKA0B_021

WCKA0_121
WCKA0B_121

EDCA0_021
EDCA0_121
EDCA0_221
EDCA0_321

DDBIA0_021
DDBIA0_121
DDBIA0_221
DDBIA0_321

ADBIA021

CSA0B_021 CSA1B_0 22

CASA0B21
RASA0B21
WEA0B21

CKEA021

CLKA021
CLKA0B21

1 2

10_0402_1%

1

2

CHA@

RV108

12

RV107

CV115

CHA@

WCKA0_0
WCKA0B_0

WCKA0_1
WCKA0B_1

EDCA0_0
EDCA0_1
EDCA0_2
EDCA0_3

DDBIA0_0
DDBIA0_1
DDBIA0_2
DDBIA0_3

ADBIA0

CSA0B_0 CSA1B_0

CASA0B
RASA0B
WEA0B

CKEA0

CLKA0
CLKA0B

1 2

RV105

12

120_0402_1%

DRAM_RSTA_R

RV111

4.99K_0402_1%

CHA@

CHA@

DQB1_D[31..0] 24

DQB0_D[31..0] 23

MAB0_[8..0] 23

MAB1_[8..0] 24

DQB0_D0

AJ1

DQB0_D1

AH4

DQB0_D2

AH2

DQB0_D3

AG3

DQB0_D4

AF2

DQB0_D5

AE3

DQB0_D6

AE1

DQB0_D7

AD4

DQB0_D8

AD2

DQB0_D9

AC3

DQB0_D10

AB4

DQB0_D11

AB2

DQB0_D12

Y4

DQB0_D13

Y2

DQB0_D14

W3

DQB0_D15

V4

DQB0_D16

U1

DQB0_D17

T4

DQB0_D18

T2

DQB0_D19

R3

DQB0_D20

N3

DQB0_D21

N1

DQB0_D22

M4

DQB0_D23

M2

DQB0_D24

L3

DQB0_D25

K4

DQB0_D26

K2

DQB0_D27

J3

DQB0_D28

H4

DQB0_D29

H2

DQB0_D30

G3

DQB0_D31

F2

MAB0_0

W10

MAB0_1

U6

MAB0_2

N7

MAB0_3

R6

MAB0_4

N6

MAB0_5

L6

MAB0_6

AC6

MAB0_7

AA11

MAB0_8

W6

U7

WCKB0_0

WCKB0_023
WCKB0B_023

WCKB0_123
WCKB0B_123

EDCB0_023
EDCB0_123
EDCB0_223
EDCB0_323

DDBIB0_023
DDBIB0_123
DDBIB0_223
DDBIB0_323

ADBIB023

CSB0B_023

CASB0B23
RASB0B23
WEB0B23

CKEB023

CLKB023
CLKB0B23

1 2

12

RV109

CV116

CHB@

CHB@

10_0402_1%

1

2

RV110

RV106

12

RV112

4.99K_0402_1%

CHB@

1 2

120_0402_1%

DRAM_RSTB_R

WCKB0B_0

WCKB0_1
WCKB0B_1

EDCB0_0
EDCB0_1
EDCB0_2
EDCB0_3

DDBIB0_0
DDBIB0_1
DDBIB0_2
DDBIB0_3

ADBIB0

CSB0B_0

CASB0B
RASB0B
WEB0B

CKEB0

CLKB0
CLKB0B

CHB@

AC10

AE11

U3
V2

E1
E3

AF4
AA3

P2

J1

AJ3

AA1

P4
F4

AA7

R10
AA6

U11

L7

AE6

J6
J7

AL6

DQB0_0
DQB0_1
DQB0_2
DQB0_3
DQB0_4
DQB0_5
DQB0_6
DQB0_7
DQB0_8
DQB0_9
DQB0_10
DQB0_11
DQB0_12
DQB0_13
DQB0_14
DQB0_15
DQB0_16
DQB0_17
DQB0_18
DQB0_19
DQB0_20
DQB0_21
DQB0_22
DQB0_23
DQB0_24
DQB0_25
DQB0_26
DQB0_27
DQB0_28
DQB0_29
DQB0_30
DQB0_31

MAB0_0
MAB0_1
MAB0_2
MAB0_3
MAB0_4
MAB0_5
MAB0_6
MAB0_7
MAB0_8
MAB0_9

WCKB0_0
WCKB0B_0

WCKB0_1
WCKB0B_1

EDCB0_0
EDCB0_1
EDCB0_2
EDCB0_3

DDBIB0_0
DDBIB0_1
DDBIB0_2
DDBIB0_3

ADBIB0

CSB0B_0
CSB0B_1

CASB0B
RASB0B
WEB0B

CKEB0

CLKB0
CLKB0B

MEM_CALRB

DRAM_RSTB

PART 4 OF 16

U1M

MEMORY INTERFACE BANK B

DQB1_10
DQB1_11
DQB1_12
DQB1_13
DQB1_14
DQB1_15
DQB1_16
DQB1_17
DQB1_18
DQB1_19
DQB1_20
DQB1_21
DQB1_22
DQB1_23
DQB1_24
DQB1_25
DQB1_26
DQB1_27
DQB1_28
DQB1_29
DQB1_30
DQB1_31

WCKB1_0

WCKB1B_0

WCKB1_1

WCKB1B_1

EDCB1_0
EDCB1_1
EDCB1_2
EDCB1_3

DDBIB1_0
DDBIB1_1
DDBIB1_2
DDBIB1_3

CSB1B_0
CSB1B_1

MVREFDB

AK4

DQB1_0

AL3

DQB1_1

AM2

DQB1_2

AM4

DQB1_3

AN3

DQB1_4

AP2

DQB1_5

AP4

DQB1_6

AR3

DQB1_7

AT2

DQB1_8

AT4

DQB1_9

AU1
AU3
AW3
AY2
AY4
BA1
BB4
BC3
BD2
BD4
BF2
BF4
BG3
BH2
BH4
BJ1
BJ3
BK4
BN5
BK6
BM6
BL7

AN11

MAB1_0

AN6

MAB1_1

AU7

MAB1_2

AR10

MAB1_3

AW6

MAB1_4

AW10

MAB1_5

AJ6

MAB1_6

AJ7

MAB1_7

AN7

MAB1_8

AU11

MAB1_9

BB2
BA3

BN9
BM8

AN1
AV2
BE3
BL5

AK2
AV4
BE1
BK8

AJ11

ADBIB1

AU6
AL10

AG10

CASB1B

AR6

RASB1B

BA12

WEB1B

AE7

CKEB1

BA6

CLKB1

BA7

CLKB1B

AG6

GPU@

STRATO-M3-XT_FCBGA1093

DQB1_D0
DQB1_D1
DQB1_D2
DQB1_D3
DQB1_D4
DQB1_D5
DQB1_D6
DQB1_D7
DQB1_D8
DQB1_D9
DQB1_D10
DQB1_D11
DQB1_D12
DQB1_D13
DQB1_D14
DQB1_D15
DQB1_D16
DQB1_D17
DQB1_D18
DQB1_D19
DQB1_D20
DQB1_D21
DQB1_D22
DQB1_D23
DQB1_D24
DQB1_D25
DQB1_D26
DQB1_D27
DQB1_D28
DQB1_D29
DQB1_D30
DQB1_D31

MAB1_0
MAB1_1
MAB1_2
MAB1_3
MAB1_4
MAB1_5
MAB1_6
MAB1_7
MAB1_8

WCKB1_0

WCKB1B_0

WCKB1_1

WCKB1B_1

EDCB1_0
EDCB1_1
EDCB1_2
EDCB1_3

DDBIB1_0
DDBIB1_1
DDBIB1_2
DDBIB1_3

ADBIB1

CSB1B_0

CASB1B
RASB1B

WEB1B

CLKB1B

MVREFDB

CKEB1

CLKB1

WCKB1_0 24

WCKB1B_0 24

WCKB1_1 24

WCKB1B_1 24

EDCB1_0 24
EDCB1_1 24
EDCB1_2 24
EDCB1_3 24

DDBIB1_0 24
DDBIB1_1 24
DDBIB1_2 24
DDBIB1_3 24

ADBIB1 24

CSB1B_0 24

CASB1B 24
RASB1B 24

WEB1B 24

CKEB1 24

CLKB1 24

CLKB1B 24

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/10/22

2014/10/22

2014/10/22

Title

ATI_STRATO_PCIE

ATI_STRATO_PCIE

ATI_STRATO_PCIE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Allsparks 5B

Allsparks 5B

Allsparks 5B

1

20 51

20 51

20 51

0.3

0.3

0.3

5

4

3

2

1

C2
C13
R13

R2

D2
D13
P13

P2

J12
J11

J3

H11
K10
K11
H10

K4

H5

H4

K5

J5

A5

U5

12

J1

J10

12

J13

J4

G3
G12

L3

L12

D5

D4

P5

P4

A10
U10

J14

J2

H1

K1

B5

G5

L5

T5
B10
D10
G10
L10
P10
T10
H14
K14

G1

L1

G4

L4

C5

R5
C10
R10
D11
G11
L11
P11
G14
L14

MF=1 Mirror

UV3

MF=0 MF=1 MF=0MF=1

EDC0 EDC3
EDC1 EDC2
EDC2 EDC1
EDC3 EDC0

DBI0# DBI3#
DBI1# DBI2#
DBI2# DBI1#
DBI3# DBI0#

CK
CK#
CKE#

BA0/A2 BA2/A4
BA1/A5 BA3/A3
BA2/A4 BA0/A2
BA3/A3 BA1/A5

A8/A7 A10/A0
A9/A1 A11/A6
A10/A0 A8/A7
A11/A6 A9/A1
A12/RFU/NC

VPP/NC1
VPP/NC2

MF
SEN
ZQ

ABI#
RAS# CAS#
CS# WE#
CAS# RAS#
WE# CS#

WCK01# WCK23#
WCK01 WCK23

WCK23# WCK01#
WCK23 WCK01

VREFD1
VREFD2
VREFC

RESET#

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14

170-BALL

SGRAM GDDR5

VRAM@

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9
DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25
VDDQ26
VDDQ27
VDDQ28
VDDQ29
VDDQ30
VDDQ31
VDDQ32
VDDQ33
VDDQ34
VDDQ35
VDDQ36

VSSQ1

VSSQ2

VSSQ3

VSSQ4

VSSQ5

VSSQ6

VSSQ7

VSSQ8

VSSQ9

VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
VSSQ20
VSSQ21
VSSQ22
VSSQ23
VSSQ24
VSSQ25
VSSQ26
VSSQ27
VSSQ28
VSSQ29
VSSQ30
VSSQ31
VSSQ32
VSSQ33
VSSQ34
VSSQ35
VSSQ36

H5GQ1H24AFR-T2L_BGA170

DQA0_D8

A4

DQA0_D9

A2

DQA0_D10

B4

DQA0_D11

B2

DQA0_D12

E4

DQA0_D15

E2

DQA0_D13

F4

DQA0_D14

F2
A11
A13
B11
B13
E11
E13
F11
F13

DQA0_D30

U11

DQA0_D29

U13

DQA0_D31

T11

DQA0_D28

T13

DQA0_D27

N11

DQA0_D26

N13

DQA0_D24

M11

DQA0_D25

M13
U4
U2
T4
T2
N4
N2
M4
M2

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

BYTE1

BYTE3

+1.35VGS

Channel A - Lower 32 bits

12

RV123

2.37K_0402_1%

12

RV125

5.49K_0402_1%

CV120

1

2

CHA@

1U_0402_6.3V6K

DQA0_D[31..0]

RV114 120_0402_1%

1 2

CHA@

RV121 120_0402_1%

1 2

CHA@

1

1

CV121

2

2

1U_0603_25V6

1U_0603_25V6

CHA@

CHA@

1

CV370

2

CHA@

1U_0402_6.3V6K

MAA0_[8..0]

1

2

1U_0402_6.3V6K

CHA@

CV122

1

CV369

2

CHA@

0.1U_0402_10V7K

VREFC_A00

CV361

1

2

1U_0603_25V6

CHA@

CV138

+1.35VGS

CV123

CHA@

0.1U_0402_10V7K

EDCA0_220

EDCA0_020

DDBIA0_220

DDBIA0_020

CLKA020
CLKA0B20
CKEA020

RV120 120_0402_1%

ADBIA020
RASA0B20
CSA0B_020
CASA0B20
WEA0B20

WCKA0B_120
WCKA0_120

WCKA0B_020
WCKA0_020

DRAM_RSTA20,22

1

1

1

CV124

CV125

2

2

0.1U_0402_10V7K

CHA@

2

CHA@

CHA@

0.1U_0402_10V7K

0.1U_0402_10V7K

1

1

CV141

CV140

2

2

CHA@

0.1U_0402_10V7K

CHA@

0.1U_0402_10V7K

1

CV139

2

D D

C C

B B

A A

DQA0_D[31..0]20

MAA0_[8..0]20

CLKA0

CLKA0B

+1.35VGS

CHA@

CHA@

+1.35VGS

UV2 SIDE UV3 SIDE

2

1

CV119

1

2

1U_0603_25V6

CHA@

CHA@

10U_0603_6.3V6M

+1.35VGS +1.35VGS

1

1

CV371

CV372

2

2

CHA@

CHA@

1U_0402_6.3V6K

1U_0402_6.3V6K

+1.35VGS

+1.35VGS

1 2

CHA@

CV126

1

CV142

2

CHA@

0.1U_0402_10V7K

EDCA0_2

EDCA0_0

DDBIA0_2

DDBIA0_0

MAA0_2
MAA0_5
MAA0_4
MAA0_3

MAA0_7

MAA0_1
MAA0_0
MAA0_6
MAA0_8

RV269 0_0402_5%CHA@

RV270 0_0402_5%CHA@

+1.35VGS

CLKA0
CLKA0B
CKEA0

ADBIA0

RASA0B

CSA0B_0

CASA0B

WEA0B

WCKA0B_1
WCKA0_1

WCKA0B_0
WCKA0_0

DRAM_RSTA

12

12

MF=0 No Mirror

UV2

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC1

U5

VPP/NC2

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD1

U10

VREFD2

J14

VREFC

J2

RESET#

H1

VSS1

K1

VSS2

B5

VSS3

G5

VSS4

L5

VSS5

T5

VSS6

B10

VSS7

D10

VSS8

G10

VSS9

L10

VSS10

P10

VSS11

T10

VSS12

H14

VSS13

K14

VSS14

G1

VDD1

L1

VDD2

G4

VDD3

L4

VDD4

C5

VDD5

R5

VDD6

C10

VDD7

R10

VDD8

D11

VDD9

G11

VDD10

L11

VDD11

P11

VDD12

G14

VDD13

L14

VDD14

170-BALL

SGRAM GDDR5

VRAM@

H5GQ1H24AFR-T2L_BGA170

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25
VDDQ26
VDDQ27
VDDQ28
VDDQ29
VDDQ30
VDDQ31
VDDQ32
VDDQ33
VDDQ34
VDDQ35
VDDQ36

VSSQ1

VSSQ2

VSSQ3

VSSQ4

VSSQ5

VSSQ6

VSSQ7

VSSQ8

VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
VSSQ20
VSSQ21
VSSQ22
VSSQ23
VSSQ24
VSSQ25
VSSQ26
VSSQ27
VSSQ28
VSSQ29
VSSQ30
VSSQ31
VSSQ32
VSSQ33
VSSQ34
VSSQ35
VSSQ36

DQA0_D23

A4

DQA0_D22

A2

DQA0_D20

B4

DQA0_D21

B2

DQA0_D19

E4

DQA0_D16

E2

DQA0_D18

F4

DQA0_D17

F2
A11
A13
B11
B13
E11
E13
F11
F13

DQA0_D1

U11

DQA0_D3

U13

DQA0_D0

T11

DQA0_D2

T13

DQA0_D4

N11

DQA0_D5

N13

DQA0_D7

M11

DQA0_D6

M13
U4
U2
T4
T2
N4
N2
M4
M2

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

+1.35VGS

BYTE2

BYTE0

+1.35VGS

CHA@

1U_0402_6.3V6K

CHA@

10U_0603_6.3V6M

1

2

+1.35VGS

RV116 120_0402_1%

1 2

CLKA0

CHA@

RV122 120_0402_1%

1 2

CLKA0B

CHA@

+1.35VGS

12

RV124

CHA@

2.37K_0402_1%

12

RV126

5.49K_0402_1%

CHA@

1

2

1

CV381

1

CV128

1U_0603_25V6

CHA@

1

2

CV129

2

2

CHA@

1U_0603_25V6

1

CV374

CV375

2

CHA@

CHA@

1U_0402_6.3V6K

1U_0402_6.3V6K

CV127

CHA@

1U_0402_6.3V6K

1U_0603_25V6

CHA@

1

2

VREFC_A01

1

CV362

2

1U_0402_6.3V6K

CHA@

1

1

2

1

1

CV131

CV130

CV373

CHA@

0.1U_0402_10V7K

1U_0603_25V6

CHA@

CV132

2

2

2

CHA@

CHA@

0.1U_0402_10V7K

0.1U_0402_10V7K

1

2

1

1

CV377

0.1U_0402_10V7K

CHA@

CV379

CV376

2

2

CHA@

0.1U_0402_10V7K

EDCA0_120

EDCA0_320

DDBIA0_120

+1.35VGS

DDBIA0_320

+1.35VGS

+1.35VGS

1 2

CHA@

RV271 120_0402_1%

1

CV133

CV134

2

CHA@

0.1U_0402_10V7K

1

1

CV380

CV378

2

2

CHA@

CHA@

0.1U_0402_10V7K

0.1U_0402_10V7K

EDCA0_1

EDCA0_3

DDBIA0_1

DDBIA0_3

CLKA0
CLKA0B

CKEA0

MAA0_4
MAA0_3
MAA0_2
MAA0_5

MAA0_0
MAA0_6

MAA0_7

MAA0_1
MAA0_8

RV272 0_0402_5%

CHA@

RV273 0_0402_5%CHA@

ADBIA0

CASA0B

WEA0B

RASA0B

CSA0B_0

WCKA0B_0
WCKA0_0

WCKA0B_1
WCKA0_1

DRAM_RSTA

+1.35VGS

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/10/22

2014/10/22

2014/10/22

Title

ATI_STRATO_PCIE

ATI_STRATO_PCIE

ATI_STRATO_PCIE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Allsparks 5B

Allsparks 5B

Allsparks 5B

1

21 51

21 51

21 51

0.3

0.3

0.3

5

Channel A - Upper 32 bits

DQA1_D[31..0]20

D D

1 2

CLKA1

1 2

CLKA1B

C C

+1.35VGS

12

RV137

CHA@

2.37K_0402_1%

12

RV139

CHA@

5.49K_0402_1%

B B

+1.35VGS +1.35VGS

2

CV153

1

CHA@

10U_0603_6.3V6M

+1.35VGS

1

A A

1U_0402_6.3V6K

CHA@

CV390

2

CHA@

1U_0402_6.3V6K

DQA1_D[31..0]

RV127 120_0402_1%

CHA@

RV129 120_0402_1%

CHA@

VREFC_A10

1

CV363

2

1U_0402_6.3V6K

CHA@

MAA1_[8..0]

+1.35VGS

EDCA1_220

EDCA1_020 EDCA1_320

DDBIA1_220

+1.35VGS

DDBIA1_020

+1.35VGS

CLKA120
CLKA1B20
CKEA120

1 2

RV276 120_0402_1%CHA@

ADBIA120

CASA1B20

WEA1B20

RASA1B20

CSA1B_020

WCKA1B_120

WCKA1_120

WCKA1B_020

WCKA1_020

DRAM_RSTA20,21

UV4 SIDE UV5 SIDE

1

1

1U_0603_25V6

CHA@

1

2

CV158

CV157

2

2

CHA@

CHA@

0.1U_0402_10V7K

0.1U_0402_10V7K

1

1

CV386

CV385

2

2

CHA@

CHA@

0.1U_0402_10V7K

0.1U_0402_10V7K

CV156

CV382

CHA@

0.1U_0402_10V7K

CHA@

1U_0603_25V6

1

2

1

2

1

1

CV154

CV155

2

2

CHA@

CHA@

1U_0603_25V6

1U_0603_25V6

1

1

CV383

CV384

2

2

CHA@

CHA@

1U_0402_6.3V6K

1U_0402_6.3V6K

+1.35VGS

1

CV159

2

CV388

RV274 0_0402_5%CHA@

RV275 0_0402_5%CHA@

1

2

CHA@

0.1U_0402_10V7K

1

CV387

2

CHA@

0.1U_0402_10V7K

DDBIA1_2

DDBIA1_0

CV160

CHA@

0.1U_0402_10V7K

EDCA1_2

EDCA1_0

CLKA1
CLKA1B
CKEA1

MAA1_4
MAA1_3
MAA1_2
MAA1_5

MAA1_0
MAA1_6
MAA1_7
MAA1_1
MAA1_8

ADBIA1

CASA1B

WEA1B
RASA1B

CSA1B_0

WCKA1B_1
WCKA1_1

WCKA1B_0
WCKA1_0

1

2

12

12

DRAM_RSTA

CV389

C2
C13
R13

R2

D2
D13
P13

P2

J12
J11

J3

H11
K10
K11
H10

K4

H5

H4

K5

J5

A5

U5

J1

J10
J13

J4

G3
G12

L3

L12

D5

D4

P5

P4

A10
U10

J14

J2

H1

K1

B5

G5

L5

T5
B10
D10
G10

L10
P10
T10
H14
K14

G1
L1
G4
L4
C5

R5
C10
R10
D11
G11

L11
P11
G14

L14

4

MF=1 Mirror

UV4

MF=0 MF=1 MF=0MF=1

EDC0 EDC3
EDC1 EDC2
EDC2 EDC1
EDC3 EDC0

DBI0# DBI3#
DBI1# DBI2#
DBI2# DBI1#
DBI3# DBI0#

CK
CK#
CKE#

BA0/A2 BA2/A4
BA1/A5 BA3/A3
BA2/A4 BA0/A2
BA3/A3 BA1/A5

A8/A7 A10/A0
A9/A1 A11/A6
A10/A0 A8/A7
A11/A6 A9/A1
A12/RFU/NC

VPP/NC1
VPP/NC2

MF
SEN
ZQ

ABI#
RAS# CAS#
CS# WE#
CAS# RAS#
WE# CS#

WCK01# WCK23#
WCK01 WCK23

WCK23# WCK01#
WCK23 WCK01

VREFD1
VREFD2
VREFC

RESET#

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14

170-BALL

SGRAM GDDR5

VRAM@

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25
VDDQ26
VDDQ27
VDDQ28
VDDQ29
VDDQ30
VDDQ31
VDDQ32
VDDQ33
VDDQ34
VDDQ35
VDDQ36

VSSQ1

VSSQ2

VSSQ3

VSSQ4

VSSQ5

VSSQ6

VSSQ7

VSSQ8

VSSQ9

VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
VSSQ20
VSSQ21
VSSQ22
VSSQ23
VSSQ24
VSSQ25
VSSQ26
VSSQ27
VSSQ28
VSSQ29
VSSQ30
VSSQ31
VSSQ32
VSSQ33
VSSQ34
VSSQ35
VSSQ36

H5GQ1H24AFR-T2L_BGA170

3

DQA1_D23

A4

DQA1_D22

A2

DQA1_D20

B4

DQA1_D21

B2

DQA1_D16

E4

DQA1_D17

E2

DQA1_D18

F4

DQA1_D19

F2
A11
A13
B11
B13
E11
E13
F11
F13

DQA1_D1

U11

DQA1_D2

U13

DQA1_D0

T11

DQA1_D3

T13

DQA1_D4

N11

DQA1_D5

N13

DQA1_D7

M11

DQA1_D6

M13
U4
U2
T4
T2
N4
N2
M4
M2

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

BYTE2

BYTE0

10U_0603_6.3V6M

+1.35VGS

1U_0402_6.3V6K

CHA@

CHA@

+1.35VGS

RV128 120_0402_1%

1 2

CLKA1

CHA@

RV130 120_0402_1%

1 2

CLKA1B

CHA@

+1.35VGS

12

RV138

2.37K_0402_1%

CHA@

12

RV140

5.49K_0402_1%

CHA@

1

2

1

1

2

1

CV162

CV161

2

2

CHA@

CHA@

1U_0603_25V6

1U_0603_25V6

1

1

CV393

CV399

2

2

CHA@

CHA@

1U_0402_6.3V6K

1U_0402_6.3V6K

VREFC_A11

1

CV364

2

1U_0402_6.3V6K

CHA@

1

1

1

CV164

CV163

2

2

CHA@

CHA@

1U_0603_25V6

1U_0603_25V6

1

1

CV392

CV391

2

2

CHA@

CHA@

1U_0402_6.3V6K

0.1U_0402_10V7K

1

CV165

CV166

2

2

CHA@

CHA@

0.1U_0402_10V7K

0.1U_0402_10V7K

1

1

CV395

CV394

2

2

CHA@

CHA@

0.1U_0402_10V7K

0.1U_0402_10V7K

EDCA1_120MAA1_[8..0]20

DDBIA1_120

DDBIA1_320

1

CV168

CV167

2

CHA@

0.1U_0402_10V7K

1

CV396

CV397

2

CHA@

CHA@

0.1U_0402_10V7K

0.1U_0402_10V7K

+1.35VGS

+1.35VGS

RV279

1 2

CHA@

1

CV398

2

RV277 0_0402_5%CHA@

RV278 0_0402_5%CHA@

120_0402_1%

2

EDCA1_1

EDCA1_3

DDBIA1_1

DDBIA1_3

CLKA1
CLKA1B
CKEA1

MAA1_2
MAA1_5
MAA1_4
MAA1_3

MAA1_7
MAA1_1
MAA1_0
MAA1_6
MAA1_8

RASA1B

CASA1B
WEA1B

WCKA1B_0
WCKA1_0

WCKA1B_1
WCKA1_1

+1.35VGS+1.35VGS

12

12

ADBIA1

CSA1B_0

DRAM_RSTA

MF=0 No Mirror

UV5

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC1

U5

VPP/NC2

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD1

U10

VREFD2

J14

VREFC

J2

RESET#

H1

VSS1

K1

VSS2

B5

VSS3

G5

VSS4

L5

VSS5

T5

VSS6

B10

VSS7

D10

VSS8

G10

VSS9

L10

VSS10

P10

VSS11

T10

VSS12

H14

VSS13

K14

VSS14

G1

VDD1

L1

VDD2

G4

VDD3

L4

VDD4

C5

VDD5

R5

VDD6

C10

VDD7

R10

VDD8

D11

VDD9

G11

VDD10

L11

VDD11

P11

VDD12

G14

VDD13

L14

VDD14

170-BALL

SGRAM GDDR5

VRAM@

H5GQ1H24AFR-T2L_BGA170

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25
VDDQ26
VDDQ27
VDDQ28
VDDQ29
VDDQ30
VDDQ31
VDDQ32
VDDQ33
VDDQ34
VDDQ35
VDDQ36

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8

VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
VSSQ20
VSSQ21
VSSQ22
VSSQ23
VSSQ24
VSSQ25
VSSQ26
VSSQ27
VSSQ28
VSSQ29
VSSQ30
VSSQ31
VSSQ32
VSSQ33
VSSQ34
VSSQ35
VSSQ36

1

DQA1_D12

A4

DQA1_D10

A2

DQA1_D13

B4

DQA1_D11

B2

DQA1_D14

E4

DQA1_D9

E2

DQA1_D15

F4

DQA1_D8

F2
A11
A13
B11
B13
E11
E13
F11
F13

DQA1_D30

U11

DQA1_D29

U13

DQA1_D31

T11

DQA1_D28

T13

DQA1_D27

N11

DQA1_D26

N13

DQA1_D24

M11

DQA1_D25

M13
U4
U2
T4
T2
N4
N2
M4
M2

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

BYTE1

BYTE3

+1.35VGS+1.35VGS

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/10/22

2014/10/22

2014/10/22

Title

ATI_STRATO_PCIE

ATI_STRATO_PCIE

ATI_STRATO_PCIE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Allsparks 5B

Allsparks 5B

Allsparks 5B

1

22 51

22 51

22 51

0.3

0.3

0.3

5

Channel B- Lower 32 bits

DQB0_D[31..0]20

MAB0_[8..0]20

1U_0603_25V6

CV402

CHB@

120_0402_1%CHB@

1

2

CHB@

1U_0402_6.3V6K

+1.35VGS

VREFC_B00

1

CV365

2

CHB@

1U_0402_6.3V6K

1

1

CV189

CV188

1

2

CV190

2

2

1U_0402_6.3V6K

CHB@

1U_0603_25V6

1U_0603_25V6

CHB@

CHB@

1

1

CV404

CV400

2

2

CHB@

0.1U_0402_10V7K

1U_0603_25V6

CHB@

CV401

D D

RV141 120_0402_1%

1 2

CLKB0

CLKB0B

C C

B B

A A

CHB@

RV143

1 2

+1.35VGS

12

RV151

CHB@

2.37K_0402_1%

12

RV153

CHB@

5.49K_0402_1%

2

CV187

1

CHB@

10U_0603_6.3V6M

+1.35VGS +1.35VGS

1

1

CV408

2

2

CHB@

CHB@

1U_0402_6.3V6K

1U_0402_6.3V6K

DQB0_D[31..0]

MAB0_[8..0]

1 2

CHB@

1

2

CHB@

0.1U_0402_10V7K

CV406

0.1U_0402_10V7K

RV280 0_0402_5%CHB@

RV281 0_0402_5%CHB@

CV193

1

2

CHB@

0.1U_0402_10V7K

CV405

CHB@

1

2

CHB@

0.1U_0402_10V7K

EDCB0_2

EDCB0_0

DDBIB0_2

DDBIB0_0

MAB0_2
MAB0_5
MAB0_4
MAB0_3

MAB0_7
MAB0_1
MAB0_0
MAB0_6
MAB0_8

ADBIB0
RASB0B
CSB0B_0
CASB0B
WEB0B

+1.35VGS

CV194

1

2

CLKB0
CLKB0B

CKEB0

WCKB0B_1
WCKB0_1

WCKB0B_0
WCKB0_0

DRAM_RSTB

CV407

12

12

EDCB0_220

EDCB0_020 EDCB0_320

DDBIB0_220

+1.35VGS

DDBIB0_020

+1.35VGS

CLKB020
CLKB0B20
CKEB020

RV282 120_0402_1%

ADBIB020

RASB0B20
CSB0B_020
CASB0B20

WEB0B20

WCKB0B_120

WCKB0_120

WCKB0B_020

WCKB0_020

DRAM_RSTB20,24

1

1

CV191

CV192

2

2

CHB@

0.1U_0402_10V7K

1

1

CV403

2

2

CHB@

CHB@

0.1U_0402_10V7K

0.1U_0402_10V7K

MF=0 No Mirror MF=1 Mirror

UV6

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC1

U5

VPP/NC2

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD1

U10

VREFD2

J14

VREFC

J2

RESET#

H1

VSS1

K1

VSS2

B5

VSS3

G5

VSS4

L5

VSS5

T5

VSS6

B10

VSS7

D10

VSS8

G10

VSS9

L10

VSS10

P10

VSS11

T10

VSS12

H14

VSS13

K14

VSS14

G1

VDD1

L1

VDD2

G4

VDD3

L4

VDD4

C5

VDD5

R5

VDD6

C10

VDD7

R10

VDD8

D11

VDD9

G11

VDD10

L11

VDD11

P11

VDD12

G14

VDD13

L14

VDD14

SGRAM GDDR5

VRAM@

4

MF=0 MF=1 MF=0MF=1

170-BALL

H5GQ1H24AFR-T2L_BGA170

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25
VDDQ26
VDDQ27
VDDQ28
VDDQ29
VDDQ30
VDDQ31
VDDQ32
VDDQ33
VDDQ34
VDDQ35
VDDQ36

VSSQ1

VSSQ2

VSSQ3

VSSQ4

VSSQ5

VSSQ6

VSSQ7

VSSQ8

VSSQ9

VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
VSSQ20
VSSQ21
VSSQ22
VSSQ23
VSSQ24
VSSQ25
VSSQ26
VSSQ27
VSSQ28
VSSQ29
VSSQ30
VSSQ31
VSSQ32
VSSQ33
VSSQ34
VSSQ35
VSSQ36

3

DQB0_D22

A4

DQB0_D20

A2

DQB0_D23

B4

DQB0_D16

B2

DQB0_D21

E4

DQB0_D18

E2

DQB0_D19

F4

DQB0_D17

F2
A11
A13
B11
B13
E11
E13
F11
F13

DQB0_D1

U11

DQB0_D3

U13

DQB0_D0

T11

DQB0_D2

T13

DQB0_D4

N11

DQB0_D5

N13

DQB0_D7

M11

DQB0_D6

M13
U4
U2
T4
T2
N4
N2
M4
M2

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

+1.35VGS

CHB@

BYTE2

+1.35VGS

RV144 120_0402_1%

1 2

10U_0603_6.3V6M

1U_0402_6.3V6K

CHB@

CHB@

CLKB0

CLKB0B

+1.35VGS

CHB@

UV7 SIDEUV6 SIDE

1

2

CV196

CV195

2

1

1U_0603_25V6

CHB@

1

1

CV410

CV411

2

2

CHB@

1U_0402_6.3V6K

BYTE0

+1.35VGS+1.35VGS

1

CV417

2

1U_0402_6.3V6K

CHB@

CHB@

1U_0402_6.3V6K

1U_0603_25V6

12

12

CHB@

1

2

RV152

2.37K_0402_1%

RV154

5.49K_0402_1%

1

CV197

2

1U_0603_25V6

CHB@

CV409

CHB@

0.1U_0402_10V7K

CHB@

RV142 120_0402_1%

1 2

CHB@

1U_0402_6.3V6K

1

1

CV198

2

2

1U_0603_25V6

CHB@

1

1

CV413

2

2

CHB@

0.1U_0402_10V7K

1

2

CV199

CV412

VREFC_B01

CV366

CHB@

1

2

CHB@

0.1U_0402_10V7K

1

2

CHB@

0.1U_0402_10V7K

CV200

CV415

CHB@

0.1U_0402_10V7K

0.1U_0402_10V7K

CHB@

EDCB0_120

DDBIB0_120

+1.35VGS

DDBIB0_320

+1.35VGS

+1.35VGS

1 2

RV285 120_0402_1%CHB@

1

1

CV202

CV201

2

2

CHB@

0.1U_0402_10V7K

1

1

CV416

CV414

2

2

CHB@

0.1U_0402_10V7K

EDCB0_1

EDCB0_3

DDBIB0_1

DDBIB0_3

CLKB0
CLKB0B

CKEB0

MAB0_4
MAB0_3
MAB0_2
MAB0_5

MAB0_0
MAB0_6

MAB0_7
MAB0_1

MAB0_8

12

RV283 0_0402_5%

CHB@

12

RV284 0_0402_5%CHB@

ADBIB0
CASB0B
WEB0B
RASB0B
CSB0B_0

WCKB0B_0
WCKB0_0

WCKB0B_1
WCKB0_1

DRAM_RSTB

+1.35VGS

2

UV7

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC1

U5

VPP/NC2

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD1

U10

VREFD2

J14

VREFC

J2

RESET#

H1

VSS1

K1

VSS2

B5

VSS3

G5

VSS4

L5

VSS5

T5

VSS6

B10

VSS7

D10

VSS8

G10

VSS9

L10

VSS10

P10

VSS11

T10

VSS12

H14

VSS13

K14

VSS14

G1

VDD1

L1

VDD2

G4

VDD3

L4

VDD4

C5

VDD5

R5

VDD6

C10

VDD7

R10

VDD8

D11

VDD9

G11

VDD10

L11

VDD11

P11

VDD12

G14

VDD13

L14

VDD14

170-BALL

SGRAM GDDR5

VRAM@

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25
VDDQ26
VDDQ27
VDDQ28
VDDQ29
VDDQ30
VDDQ31
VDDQ32
VDDQ33
VDDQ34
VDDQ35
VDDQ36

VSSQ1

VSSQ2

VSSQ3

VSSQ4

VSSQ5

VSSQ6

VSSQ7

VSSQ8

VSSQ9

VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
VSSQ20
VSSQ21
VSSQ22
VSSQ23
VSSQ24
VSSQ25
VSSQ26
VSSQ27
VSSQ28
VSSQ29
VSSQ30
VSSQ31
VSSQ32
VSSQ33
VSSQ34
VSSQ35
VSSQ36

H5GQ1H24AFR-T2L_BGA170

1

DQB0_D14

A4

DQB0_D8

A2

DQB0_D15

B4

DQB0_D11

B2

DQB0_D12

E4

DQB0_D10

E2

DQB0_D13

F4

DQB0_D9

F2
A11
A13
B11
B13
E11
E13
F11
F13

DQB0_D27

U11

DQB0_D28

U13

DQB0_D30

T11

DQB0_D29

T13

DQB0_D31

N11

DQB0_D26

N13

DQB0_D24

M11

DQB0_D25

M13
U4
U2
T4
T2
N4
N2
M4
M2

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

BYTE1

BYTE3

+1.35VGS

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/10/22

2014/10/22

2014/10/22

Title

ATI_STRATO_PCIE

ATI_STRATO_PCIE

ATI_STRATO_PCIE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Allsparks 5B

Allsparks 5B

Allsparks 5B

1

23 51

23 51

23 51

0.3

0.3

0.3

5

4

3

2

1

Channel B - Upper 32 bits

1 2

1 2

2

CV221

1

CHB@

10U_0603_6.3V6M

1

CV426

2

CHB@

1U_0402_6.3V6K

DQB1_D[31..0]

MAB1_[8..0]

RV155 120_0402_1%

CHB@

RV157 120_0402_1%

CHB@

+1.35VGS

12

CHB@

12

CHB@

UV8 SIDE

1

CV230

2

1U_0603_25V6

1U_0603_25V6

CHB@

CHB@

1

1

CV420

2

2

CHB@

CHB@

1U_0402_6.3V6K

1U_0402_6.3V6K

5

+1.35VGS

RV165

2.37K_0402_1%

RV167

5.49K_0402_1%

1

1

CV231

2

2

1U_0603_25V6

CHB@

1

CV419

2

CHB@

1U_0402_6.3V6K

+1.35VGS

CHB@

1

2

1

2

CV235

CV424

DDBIB1_2

DDBIB1_0

CLKB1
CLKB1B
CKEB1

MAB1_4
MAB1_3
MAB1_2
MAB1_5

MAB1_0
MAB1_6

MAB1_7

MAB1_1

MAB1_8

RV286 0_0402_5%CHB@

RV287 0_0402_5%CHB@

1

CV236

2

CHB@

0.1U_0402_10V7K

1

CV423

2

CHB@

0.1U_0402_10V7K

EDCB1_2

EDCB1_0

ADBIB1
CASB1B
WEB1B
RASB1B
CSB1B_0

WCKB1B_1
WCKB1_1

WCKB1B_0
WCKB1_0

+1.35VGS

CHB@

0.1U_0402_10V7K

12

12

DRAM_RSTB

1

CV425

2

EDCB1_220

EDCB1_020

DDBIB1_220

+1.35VGS

DDBIB1_020

+1.35VGS

CLKB120
CLKB1B20
CKEB120

1 2

RV290 120_0402_1%

ADBIB120
CASB1B20
WEB1B20
RASB1B20
CSB1B_020

WCKB1B_120
WCKB1_120

WCKB1B_020
WCKB1_020

VREFC_B10

1

DRAM_RSTB20,23

CV367

2

1U_0402_6.3V6K

CHB@

1

1

CV233

CV232

CV418

1U_0603_25V6

0.1U_0402_10V7K

CHB@

CHB@

CV234

2

2

CHB@

CHB@

0.1U_0402_10V7K

0.1U_0402_10V7K

1

1

CV421

CV422

2

2

CHB@

CHB@

0.1U_0402_10V7K

0.1U_0402_10V7K

DQB1_D[31..0]20

MAB1_[8..0]20

D D

CLKB1

CLKB1B

C C

B B

+1.35VGS

+1.35VGS

A A

MF=1 Mirror

UV8

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC1

U5

VPP/NC2

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD1

U10

VREFD2

J14

VREFC

J2

RESET#

H1

VSS1

K1

VSS2

B5

VSS3

G5

VSS4

L5

VSS5

T5

VSS6

B10

VSS7

D10

VSS8

G10

VSS9

L10

VSS10

P10

VSS11

T10

VSS12

H14

VSS13

K14

VSS14

G1

VDD1

L1

VDD2

G4

VDD3

L4

VDD4

C5

VDD5

R5

VDD6

C10

VDD7

R10

VDD8

D11

VDD9

G11

VDD10

L11

VDD11

P11

VDD12

G14

VDD13

L14

VDD14

170-BALL

SGRAM GDDR5

VRAM@

4

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25
VDDQ26
VDDQ27
VDDQ28
VDDQ29
VDDQ30
VDDQ31
VDDQ32
VDDQ33
VDDQ34
VDDQ35
VDDQ36

VSSQ1

VSSQ2

VSSQ3

VSSQ4

VSSQ5

VSSQ6

VSSQ7

VSSQ8

VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
VSSQ20
VSSQ21
VSSQ22
VSSQ23
VSSQ24
VSSQ25
VSSQ26
VSSQ27
VSSQ28
VSSQ29
VSSQ30
VSSQ31
VSSQ32
VSSQ33
VSSQ34
VSSQ35
VSSQ36

H5GQ1H24AFR-T2L_BGA170

MF=0 No Mirror

UV9

DQB1_D23

A4

DQB1_D22

A2

DQB1_D20

B4

DQB1_D21

B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

DQB1_D19
DQB1_D18
DQB1_D17
DQB1_D16

DQB1_D0
DQB1_D1
DQB1_D4
DQB1_D2
DQB1_D7
DQB1_D3
DQB1_D6
DQB1_D5

+1.35VGS

BYTE2

BYTE0

+1.35VGS

1U_0402_6.3V6K

+1.35VGS

1

2

CHB@

10U_0603_6.3V6M

CHB@

+1.35VGS

RV156 120_0402_1%

1 2

CLKB1

CHB@

RV158 120_0402_1%

1 2

CLKB1B

CHB@

+1.35VGS

12

RV166

CHB@

2.37K_0402_1%

12

RV168

CHB@

5.49K_0402_1%

UV9 SIDE

2

1

CV435

CV222

CHB@

1U_0402_6.3V6K

1

1U_0402_6.3V6K

CHB@

1

1

CV224

CV223

CV225

2

2

1U_0402_6.3V6K

CHB@

2

1U_0603_25V6

1U_0603_25V6

CHB@

CHB@

1

1

CV431

CV427

2

2

CHB@

0.1U_0402_10V7K

CHB@

1U_0603_25V6

1

CV428

2

3

1

2

1U_0603_25V6

CHB@

1

CV429

2

CV226

CHB@

0.1U_0402_10V7K

1

1

CV228

CV227

2

2

CHB@

CHB@

0.1U_0402_10V7K

0.1U_0402_10V7K

1

1

2

1

CV433

CV430

2

2

CHB@

CHB@

0.1U_0402_10V7K

0.1U_0402_10V7K

Security Classification

Security Classification

Security Classification

EDCB1_120

EDCB1_320

DDBIB1_120

+1.35VGS

DDBIB1_320

+1.35VGS

1 2

RV291

VREFC_B11

1

CV368

2

1U_0402_6.3V6K

CHB@

1

CV229

2

CHB@

0.1U_0402_10V7K

1

CV434

CV432

2

CHB@

0.1U_0402_10V7K

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

RV288 0_0402_5%

RV289 0_0402_5%

120_0402_1%

CHB@

EDCB1_1

EDCB1_3

DDBIB1_1

DDBIB1_3

CLKB1
CLKB1B
CKEB1

MAB1_2
MAB1_5
MAB1_4
MAB1_3

MAB1_7

MAB1_1
MAB1_0
MAB1_6

MAB1_8

CHB@

CHB@

+1.35VGS

2014/10/22

2014/10/22

2014/10/22

12

12

ADBIB1
RASB1B
CSB1B_0
CASB1B
WEB1B

WCKB1B_0
WCKB1_0

WCKB1B_1
WCKB1_1

DRAM_RSTB

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

2

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC1

U5

VPP/NC2

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD1

U10

VREFD2

J14

VREFC

J2

RESET#

H1

VSS1

K1

VSS2

B5

VSS3

G5

VSS4

L5

VSS5

T5

VSS6

B10

VSS7

D10

VSS8

G10

VSS9

L10

VSS10

P10

VSS11

T10

VSS12

H14

VSS13

K14

VSS14

G1

VDD1

L1

VDD2

G4

VDD3

L4

VDD4

C5

VDD5

R5

VDD6

C10

VDD7

R10

VDD8

D11

VDD9

G11

VDD10

L11

VDD11

P11

VDD12

G14

VDD13

L14

VDD14

170-BALL

SGRAM GDDR5

VRAM@

Deciphered Date

Deciphered Date

Deciphered Date

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31

H5GQ1H24AFR-T2L_BGA170

2014/10/22

2014/10/22

2014/10/22

DQB1_D9

A4

DQB1_D8

A2

DQB1_D10

B4

DQB1_D11

B2

DQB1_D14

E4

DQB1_D12

E2

DQB1_D13

F4

DQB1_D15

F2
A11
A13
B11
B13
E11
E13
F11
F13

DQB1_D30

U11

DQB1_D29

U13

DQB1_D31

T11

DQB1_D28

T13

DQB1_D27

N11

DQB1_D26

N13

DQB1_D24

M11

DQB1_D25

M13
U4
U2
T4
T2
N4
N2
M4
M2

B1

VDDQ1

D1

VDDQ2

F1

VDDQ3

M1

VDDQ4

P1

VDDQ5

T1

VDDQ6

G2

VDDQ7

L2

VDDQ8

B3

VDDQ9

D3

VDDQ10

F3

VDDQ11

H3

VDDQ12

K3

VDDQ13

M3

VDDQ14

P3

VDDQ15

T3

VDDQ16

E5

VDDQ17

N5

VDDQ18

E10

VDDQ19

N10

VDDQ20

B12

VDDQ21

D12

VDDQ22

F12

VDDQ23

H12

VDDQ24

K12

VDDQ25

M12

VDDQ26

P12

VDDQ27

T12

VDDQ28

G13

VDDQ29

L13

VDDQ30

B14

VDDQ31

D14

VDDQ32

F14

VDDQ33

M14

VDDQ34

P14

VDDQ35

T14

VDDQ36

A1

VSSQ1

C1

VSSQ2

E1

VSSQ3

N1

VSSQ4

R1

VSSQ5

U1

VSSQ6

H2

VSSQ7

K2

VSSQ8

A3

VSSQ9

C3

VSSQ10

E3

VSSQ11

N3

VSSQ12

R3

VSSQ13

U3

VSSQ14

C4

VSSQ15

R4

VSSQ16

F5

VSSQ17

M5

VSSQ18

F10

VSSQ19

M10

VSSQ20

C11

VSSQ21

R11

VSSQ22

A12

VSSQ23

C12

VSSQ24

E12

VSSQ25

N12

VSSQ26

R12

VSSQ27

U12

VSSQ28

H13

VSSQ29

K13

VSSQ30

A14

VSSQ31

C14

VSSQ32

E14

VSSQ33

N14

VSSQ34

R14

VSSQ35

U14

VSSQ36

Title

Title

Title

ATI_STRATO_PCIE

ATI_STRATO_PCIE

ATI_STRATO_PCIE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

+1.35VGS

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

1

BYTE1

BYTE3

Allsparks 5B

Allsparks 5B

Allsparks 5B

24 51

24 51

24 51

0.3

0.3

0.3

5

4

3

2

1

LCD POWER CIRCUIT

PCH_ENBKL

R11

@

1 2

+3VS

W=60mils W=60mils

U9

5

OUT

IN

GND

4

FLG

D D

R873 0_0402_5%

PCH_ENVDD6

1 2

R7

100K_0402_5%

@

EN

AP22802AW5-7_SOT25-5

For AP2820A,EN VIH >=1.5V

C199

.1U_0402_10V6-K

12

CD@

1

2

1 2

1

R22 0_0603_5%

2

3

+LCDVDD_CON

BKOFF#35

C8

.1U_0402_10V6-K

CD@

C7

4.7U_0603_6.3V6K

1

1

2

2

PCH_ENBKL6

0_0402_5%

1 2

R12

0_0402_5%

R14

1 2

0_0402_5%

DISPOFF#

ENBKL

12

R16
100K_0402_5%

ENBKL 35

1 2

PCH_EDP_PWM6

+3VS+3VS

GPU_VDDC_B+

2A 80 mil

C C

GPU_VDDC_B+

PCH_ENVDD

R94

1 2

100K_0402_5%

1 2

R96

0_0402_5%

.1U_0402_10V6-K

@

@

C201

@

AO3401A_SOT23-3

Q33

LEDVDD_EN#

Q173

2

G

1

PJA138K_SOT23-3

2

0_0805_5%

S

G

2

12

1

3

+LEDVDD

12

R17

D

@

13

R95

100K_0402_5%

@

D

S

@

2A 80 mil

4.7U_0805_25V6-K

0.1U_0402_25V6

1

1

C14

C15

CD@

2

2

APU_EDP_HPD6

C1957

0.1U_0402_25V6

1

2

@

1M_0402_5%

R15

@

1 2

1 2

R875 0_0402_5%

G

2

13

D

S

Q174
2N7002KW_SOT323-3

@

EDP_HPD_OUT

12

R874
100K_0402_5%

@

APU_EDP_TX1-6
APU_EDP_TX1+6

APU_EDP_TX0-6
APU_EDP_TX0+6

APU_EDP_AUX6
APU_EDP_AUX#6

R19

+LCDVDD_CON

+LEDVDD

0_0402_5%

1 2

C18 .1U_0402_10V6-K
C17 .1U_0402_10V6-K

1 2

C16 .1U_0402_10V6-K

1 2
1 2

C19 .1U_0402_10V6-K

C20 .1U_0402_10V6-K

1 2
1 2

C21 .1U_0402_10V6-K

W=60mils

W=60mils

Reserve for power consumption test

CMOS Camera

B B

EMI request

A A

USB20_P1

USB20_N1

DMIC_CLK34

DMIC_DATA34

USB20_N18
USB20_P18

4

1

L13

4

1

EXC24CH900U_4P

+3VS_CMOS

W=40mils

1 2

R98 0_0402_5%
R97 0_0402_5%

1 2

R177 0_0603_5%

+3VS

W=40mils

EMC_NS@

For EMI

USB20_P1_R

3

3

USB20_N1_R

2

2

+3VS

W=40 mils

USB20_N1_R
USB20_P1_R

1 2

1

2

1 2

R135 0_0603_5%

C251

.1U_0402_10V6-K

CD@

JCT1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

ACES_50228-00871-001

ME@

+3VS_CMOS

GND1

GND2

9

10

+3VS_CMOS

1

2

W=40mils

C4
10U_0603_6.3V6M

@

DMIC_CLK

1

C200

0.047U_0402_25V7K

2

C11

1

EMC@

2

100P_0402_50V8J

EMI request

DISPOFF#

470P_0402_50V7K

1

C12

EMC_NS@

2

INVT_PWM

EMC_NS@

1

C13

2

INVT_PWM

12

R20
100K_0402_5%

JEDP1

1

EDP_TX1­EDP_TX1+

EDP_TX0­EDP_TX0+

EDP_AUX
EDP_AUX#

EDP_HPD_OUT

DISPOFF#
INVT_PWM

470P_0402_50V7K

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

G1

22

G2

23

G3

24

G4

ACES_50406-02071-001

ME@

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/10/22

2014/10/22

2014/10/22

Title

eDP/ CMOS/Touch screen

eDP/ CMOS/Touch screen

eDP/ CMOS/Touch screen

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet

Allsparks 5B

Allsparks 5B

Allsparks 5B

25 51

25 51

25 51

1

of

0.3

0.3

0.3

5

4

3

2

1

HDMI CONN

Repeater

HDMI_TX0+_C

12

APU_DDC_CLK

APU_DDC_DATA

12

12

12

12

12

12

12

12

5

C220 .1U_0402_10V6-KRP@

12

C219 .1U_0402_10V6-KRP@

12

C40 .1U_0402_10V6-KRP@

12

C218 .1U_0402_10V6-KRP@

12

C42 .1U_0402_10V6-KRP@

12

C41 .1U_0402_10V6-KRP@

12

C221 .1U_0402_10V6-KRP@

12

C222 .1U_0402_10V6-KRP@

S

G

5

S

34

D

Q180B
2N7002KDWH_SOT363-6

APU_HDMI_TX0+_R

APU_HDMI_TX0-_R

APU_HDMI_TX1+_R

APU_HDMI_TX1-_R

APU_HDMI_TX2+_R

APU_HDMI_TX2-_R

APU_HDMI_CLK+_R

APU_HDMI_CLK-_R

1 2

RHD13 499_0402_1%

1 2

RHD14 499_0402_1%

1 2

RHD15 499_0402_1%

1 2

RHD16 499_0402_1%

1 2

RHD17 499_0402_1%

1 2

RHD18 499_0402_1%

1 2

RHD19 499_0402_1%

1 2

RHD20 499_0402_1%

+3VS

HDMI_TX0-_C
HDMI_TX1+_C
HDMI_TX1-_C
HDMI_TX2+_C
HDMI_TX2-_C
HDMI_CLK+_C
HDMI_CLK-_C

APU_DDC_CLK HDMI_TX1+_C
APU_DDC_DATA

I2C Control enable.Internal pull down at ~150kΩ, 3.3V I/O
I2C_CTL_EN:
* L: default, Pin control is selected
H:I2C control is selected

+3VS

G

2

HDMI_DDC_CLK_CON

61

D

Q180A

2N7002KDWH_SOT363-6

HDMI2012F2SF-900T04_4P

4

112

L24

EMC@

HDMI2012F2SF-900T04_4P

4

112

L25

EMC@

HDMI2012F2SF-900T04_4P

4

112

L26

EMC@

HDMI2012F2SF-900T04_4P

4

112

L27

EMC@

13

D

2

G

S

HDMI_DDC_DAT_CON

334

2

334

2

334

2

334

2

QHD1

2N7002KW_SOT323-3

HDMI_TX0+_CON

HDMI_TX0-_CON

HDMI_TX1+_CON

HDMI_TX1-_CON

HDMI_TX2+_CON

HDMI_TX2-_CON

HDMI_CLK+_CON

HDMI_CLK-_CON

100K_0402_5%

R203

2

2

2

CH11

CH10

CH12

1

1

1

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

RP@

RP@

RP@

+3VS

+3VS

+3VS

HDMI_HPD_OUT_CON

12

HDMI_DDC_DAT_CON
HDMI_DDC_CLK_CON

HDMI_CLK-_CON

HDMI_CLK+_CON
HDMI_TX0-_CON

HDMI_TX0+_CON
HDMI_TX1-_CON

HDMI_TX1+_CON
HDMI_TX2-_CON

HDMI_TX2+_CON

APU_HDMI_TX0+6

CPU L2

APU_HDMI_TX0-6
APU_HDMI_TX1+6

CPU L1

APU_HDMI_TX1-6
APU_HDMI_TX2+6

CPU L0

APU_HDMI_TX2-6

APU_HDMI_CLK+6

APU_HDMI_CLK-6

D D

C C

B B

APU_HDMI_TX0+

APU_HDMI_TX0-

APU_HDMI_TX1+

APU_HDMI_TX1-

APU_HDMI_TX2+

APU_HDMI_TX2-

APU_HDMI_CLK+

APU_HDMI_CLK-

APU_DDC_CLK6
APU_DDC_DATA6

C1968 .1U_0402_10V6-K

C1967 .1U_0402_10V6-K

C1970 .1U_0402_10V6-K

C1965 .1U_0402_10V6-K

C1966 .1U_0402_10V6-K

C1964 .1U_0402_10V6-K

C1969 .1U_0402_10V6-K

C1971 .1U_0402_10V6-K

APU_HDMI_CLK+_R

APU_HDMI_CLK-_R

APU_HDMI_TX0+_R

APU_HDMI_TX0-_R

APU_HDMI_TX1+_R

APU_HDMI_TX1-_R

APU_HDMI_TX2+_R

APU_HDMI_TX2-_R

RDS-ON (max) = 20 OHM, VGS-TH (max) = 4V

A A

+3VS

1 2

CH9 .1U_0402_10V6-K

RP@

2

2

CD@

CH13

1

1

C1961

.1U_0402_10V6-K

.01U_0402_16V7-K

RP@

12

RH12

0_0402_5%

@

VDDRX

DC coupling enable; Internal pull down at ~150kΩ, 3.3V I/O.
L: default, AC coupling input
H: DC coupling input

Enable active DDC buffer; Internal pull up at ~150KΩ, 3.3V I/O
L: default, passive DDC pass-through
H: active DDC buffer with default threshold
M: active DDC buffer without internal pull up resistor

Output pre-emphasis setting; Internal pull down at ~150kΩ, 3.3V I/O.
L: no pre-emphasis
H: 1.6dB pre-emphasis
M: 2.5dB pre-emphasis

RH11 4.7K_0402_5%@

RH6 4.7K_0402_5%@

RH7 4.7K_0402_5%

RP@

RH45 4.7K_0402_5%@

RH46 4.7K_0402_5%@

APU_HDMI_HPD

5V_HDMI_S0

4

12

RH14 0_0603_5%

+1.5VS

RP@

11
19
20
40
31

HDMI_TX2+_C

1

HDMI_TX2-_C

2
4

HDMI_TX1-_C

5

HDMI_TX0+_C

6

HDMI_TX0-_C

7

HDMI_CLK+_C

9

HDMI_CLK-_C

10

I2C_CTL_EN

8

DCIN_EN

13
14

DDCBUF

16

PRE

17

EQ

18
35
41

12

RH8

4.99K_0402_1%

RP@

RH47 RH48 C15 C16for 8407 reserve

1 2

RH47 0_0402_5%

@

C1962

.01U_0402_16V7-K

12

CFG

12

EQ

EQ

12

12

ISET

12

12

R39 0_0402_5%

100K_0402_5%

CONN

JHDMI

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Utility

13

CEC

GND1

12

CK-

11

CK_shield

GND2

10

CK+

9

D0-

GND3

8

D0_shield

7

D0+

GND4

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

LOTES_AHDM0006-P008A

ME@

U39

VDD33
VDD15_1
VDD15_2
VDD15_3
VDD15_4

IN_D2p
IN_D2n
IN_D1p
IN_D1n
IN_D0p
IN_D0n
IN_CKp
IN_CKn

I2C_CTL_EN
DCIN_EN/SCL_CTL
DDCBUF/SDA_CTL
PRE
EQ/I2C_ADDR
REXT
GND
EPAD

PS8201ATQFN40GTR2A0_TQFN40_5X5

RP@

+1.5VS

2

@

1

Configuration pin, 3.3V IO, internal pull down at ~150kΩ. 3.3V I/O.
L: HDMI ID disable
H: HDMI ID enable

For PS8201A

Receiver equalization setting; Internal pull down at ~150kΩ, 3.3V I/O.
L: programmable EQ for channel loss up to 6.5dB @ 3Gbps
H: programmable EQ for channel loss up to 9.5dB @ 3Gbps
M: programmable EQ for channel loss up to 3dB @ 3Gbps

For PS8407A only

TMDS output swing adjustment; Internal pull down at ~150kΩ, 3.3V I/O.
L: default
H: increase +13%
M: reduce -13%

+3VS

C

Q43

E

3 1

12

R910

20

21

22

23

21

OUT_CKn

22

OUT_CKp

24

OUT_D0n

25

OUT_D0p

26

OUT_D1n

27

OUT_D1p

29

OUT_D2n

30

OUT_D2p

32

SCL_SNK

33

SDA_SNK

38

SCL_SRC

39

SDA_SRC

3

HPD_SRC

36

PD#

28

HPD_SNK

23

CFG

15

NC_1

12

NC_2

34

NC_3

37

NC_4

1 2

VDD33

RH48 0_0402_5%

@

+3VS

RH1 4.7K_0402_5%@

+3VS

RH2 4.7K_0402_5%RP@
RH3 4.7K_0402_5%@

+3VS

RH4 4.7K_0402_5%RP@
RH5 4.7K_0402_5%@

Follow Zx05 and beema

2

1 2

R202 150K_0402_5%

B

MMBT3904WH_SOT323-3

HDMI_CLK-_R
HDMI_CLK+_R
HDMI_TX0-_R
HDMI_TX0+_R
HDMI_TX1-_R
HDMI_TX1+_R
HDMI_TX2-_R
HDMI_TX2+_R

HDMI_DDC_CLK_CON
HDMI_DDC_DAT_CON
APU_DDC_CLK
APU_DDC_DATA

APU_HDMI_HPD

HDMI_HPD_OUT_CON
CFG

VDDRX
ISET
VDD33

+3VS

C1963

.01U_0402_16V7-K

12

12
12

12
12

+5VS 5V_HDMI_S0

SUSP37

5V_HDMI_S0

RPE4

2.2K_0404_4P2R_5%

1 4

2 3

2

@

1

DCIN_EN

DDCBUF

PRE

HDMI_HPD_OUT_CON

Q5

1 3

D

LP2301ALT1G_SOT23-3

G

2

F2

0.5A_8V_KMC3S050RY

21

0.5A

S

3

D32

21 9

4

3

8

EMC_NS@

D31

21 9

4

3

8

EMC_NS@

D3

21 9

4

3

8

EMC_NS@

2014/10/22

2014/10/22

2014/10/22

HDMI_TX0+_CONHDMI_TX0+_CON

9

10

8

HDMI_CLK+_CON

7

7

HDMI_CLK-_CON

6

65

HDMI_TX1-_CON

9

10

HDMI_TX1+_CON

8

HDMI_TX2-_CON

7

7

HDMI_TX2+_CON

6

65

9

10

HDMI_DDC_DAT_CON

8

7

7

5V_HDMI_S0

6

65

Close to JHDMI1

Title

Title

Title

HDMI_CONN

HDMI_CONN

HDMI_CONN

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

D

D

D

Monday, May 04, 2015

Monday, May 04, 2015

Monday, May 04, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

Allsparks 5B

Allsparks 5B

Allsparks 5B

26 51

26 51

26 51

1

HDMI_TX0-_CON HDMI_TX0-_CON

2

HDMI_CLK+_R

HDMI_CLK-_R

HDMI_TX0+_R

HDMI_TX0-_R

HDMI_TX1+_R

HDMI_TX1-_R

HDMI_TX2+_R

HDMI_TX2-_R

EXC24CH900U_4P

112

4

L20

EXC24CH900U_4P

112

4

L21

EXC24CH900U_4P

112

4

L22

EXC24CH900U_4P

112

4

L23

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

2

334

2

334

2

334

2

334

HDMI_CLK+_CON

4

HDMI_CLK-_CON

5

3

AZ1045-04F_DFN2510P10E-10-9

HDMI_TX1-_CON

1

HDMI_TX1+_CON

2

HDMI_TX2-_CON

4

HDMI_TX2+_CON

5

3

AZ1045-04F_DFN2510P10E-10-9

HDMI_HPD_OUT_CON HDMI_HPD_OUT_CON

1

HDMI_DDC_DAT_CON

2

HDMI_DDC_CLK_CON HDMI_DDC_CLK_CON

4

5V_HDMI_S0

5

3

AZ1045-04F_DFN2510P10E-10-9

For EMC

+3VS

RHD21
1K_0402_5%

@

APU_HDMI_HPD

CD@

1

C261

.1U_0402_10V6-K

2

APU_HDMI_HPD6

1 2

12

R205

100K_0402_5%

@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

0.3

0.3

0.3

5

4

3

+12VS_WF

2

1

D D

+3VS

12

CW5

1 2

CW6

1 2

RW3
1K_0402_1%

@

WF_MUTE#

GAIN0

GAIN1

AVCC

GVDD

RINN

RINP

PBTL

0.1U_0402_25V6

0.1U_0402_25V6

U16

1

SD

2

FAULT

3

LINP

4

LINN

5

GAIN0

6

GAIN1

7

AVCC

8

AGND

9

GVDD

10

PLIMIT

11

RINN

12

RINP

13

NC
PBTL14PVCCR2

GNDA_WF

RINN

RINP

PVCCL1
PVCCL2

BSPL

OUTPL
PGND1
OUTNL

BSNL
BSNR

OUTNR

PGND2
OUTPR

BSPR

PVCCR1

GND

TPA3113D2PWPR_HTSSOP28

29

RA207 0_0402_5%@

RA206 0_0402_5%@

RA208 0_0402_5%@

Layout need short together

Gain Setting operation

GAIN1 GAIN0 Gain Ri(KΩ)

RW11
10_0603_5%

1 2

CODEC_WF_MUTE#34

EC_WF_MUTE#35

C C

WF_MUTE#

RW33 10K_0402_5%@

B B

12

MONO_OUT34

CODEC_WF_MUTE#

GNDA_WF

GNDA_WF

+5VS

GNDA_WF

GNDA_WF

12

RW150_0402_5%

2

1

1 2

RW32 0_0402_5%

1 2

RW2 1K_0402_5%

@

12

CW186 1U_0603_25V6M

12

CW187 1U_0603_25V6M

12

RW1320K_0402_1%

1 2

CW1881U_0603_25V6M

1 2

RW16 100K_0402_1%

RW25 10K_0402_5%@

RW26 10K_0402_5%@

RW27 10K_0402_5%

RW28 10K_0402_5%

CW8
22P_0402_50V8-J

@

12

12

12

12

1 2

RW31 17.4K_0402_1%

1 2

RW1430K_0402_1%

1 2

RW12 62K_0402_1%

AVCC

PBTL

1

12

R884

41.2K_0402_1%

CW7

2

@

GAIN0

GAIN1

680P_0402_50V7K

*

GNDA_WFGNDA_WF

A A

12

RW34
0_0805_5%

28
27
26
25

CW9 0.47U_0603_25V6-K

24
23
22
21
20
19
18

CW10 0.47U_0603_25V6-K

17
16
15

1 2

1 2

1 2

0 0

0 1

1 0

1 1

1 2

1 2

20

26

32

36

CW184

0.1U_0402_25V6

1

2

CW185

0.1U_0402_25V6

1

2

GNDA_WF

B+

0_0805_5%

12

RW10

+12VS_WF

@

SPKWF+
SPKWF-

RW29 0_0805_5%

LW3 HCB1608KF-181T20_2PEMC_NS@
LW4 HCB1608KF-181T20_2PEMC_NS@

RW30 0_0805_5%

WFPWR_EN35

1 2
1 2

R909

B+

R907

12

12

1

2

GNDA_WF GNDA_WF

B+ +12VS_WF

2A 80 mil

1 2

100K_0402_5%

1 2

0_0402_5%

.1U_0402_10V6-K

C1960

1

@

2

CA185

1000P_0402_50V7K

EMC_NS@

1

2

AO3401A_SOT23-3

S

Q176

2

G

SPKWF+_C
SPKWF-_C

CA186

1000P_0402_50V7K

G

2

12

13

D

S

1
2
3
4

EMC_NS@

GNDA_WF

D

13

C1958

1

R908

100K_0402_5%

2

Q177

2N7002KW_SOT323-3

JSWF1

1
2
G1
G2

ACES_50273-0020N-001

ME@

2A 80 mil

0.1U_0402_25V6

STUFF for power consumption test

2015/03/04 ADD

CW182

10U_0805_25V6K

1

2

SPKWF+

SPKWF-

CW183

10U_0805_25V6K

1

2

60

30

15

9

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/10/22

2014/10/22

2014/10/22

Title

SUBWOOFER

SUBWOOFER

SUBWOOFER

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Wednesday, April 29, 2015

Allsparks 5B

Allsparks 5B

Allsparks 5B

1

27 51

27 51

27 51

0.3

0.3

0.3

5

4

3

2

1

+3VALW TO +3VALW_LAN

+3VALW_LAN rising time (10%~90%):

Need short

JL1

112

JUMP_43X79

D D

LAN_PWR_ON#35

LAN_WAKE#30,35

C C

+3VS

12

RL9
1K_0402_1%

ISOLATE#

12

RL11
15K_0402_5%

@

LAN_PWR_ON#

1 2

RL21 0_0402_5%

PCIE_WAKE#_R

PCIE_PRX_DTX_N04
PCIE_PRX_DTX_P04

+3VALW_LAN+3VALW +3VALW_LAN +LAN_VDDREG

2

@

PLT_RST#7,15,30

0.5ms＜spec＜100ms

width : 40 mils

CL5

@

1 2

RL8

2.49K_0402_1%

@

1 2
1 2

TL3 @

TL4 @

1 2

RL12

0_0402_5%

CL12 .1U_0402_10V6-K
CL13 .1U_0402_10V6-K

CL10 close to Pin18
CL11 close to Pin17

1

2

4.7U_0603_6.3V6K

+3VALW_LAN
RSET_LAN
+LAN_VDD10
LAN_XTALO
LAN_XTALI

1

LAN_DISABLE#LAN_PWR_ON#

1

+LAN_REGOUT
+LAN_VDDREG
+LAN_VDD10
PCIE_WAKE#_R
ISOLATE#
PLT_RST#
PCIE_PRX_C_DTX_N0
PCIE_PRX_C_DTX_P0

CD@

+3VALW_LAN

RL19

10K_0402_5%

@

width : 40 mils

1

CL10

4.7U_0603_6.3V6K

2

1 2

1 2

RL18 0_0402_5%

1

CL11
.1U_0402_10V6-K

2

LAN_CLKREQ0# 7

1 2

RL7 0_0603_5%

1

CL6

2

1

CL7

2

.1U_0402_10V6-K

.1U_0402_10V6-K

Close to Pin11 Close to Pin32Close to Pin32

LAN_CLKREQ#_R

UL1

33

GND

32

AVDD33_2

31

RSET

30

AVDD10

29

CKXTAL2

28

CKXTAL1

27

LED0

26

LED1/GPO

25

LED2

24

REGOUT

23

VDDREG

22

DVDD10

21

LANWAKEB

20

ISOLATEB

19

PERSTB

18

HSON

17

HSOP

RTL8111H-CG_QFN32_4X4

REFCLK_N

REFCLK_P

HSIN
HSIP

CLKREQB

AVDD33_1

MDIN3

MDIP3

AVDD10_2

MDIN2

MDIP2

MDIN1

MDIP1

AVDD10_1

MDIN0

MDIP0

CLK_PCIE_LAN#

16

CLK_PCIE_LAN

15

PCIE_PTX_C_DRX_N0

14

PCIE_PTX_C_DRX_P0

13

LAN_CLKREQ#_R

12

+3VALW_LAN

11

LAN_MDI3-

10

LAN_MDI3+

9

+LAN_VDD10

8

LAN_MDI2-

7

LAN_MDI2+

6

LAN_MDI1-

5

LAN_MDI1+

4

+LAN_VDD10

3

LAN_MDI0-

2

LAN_MDI0+

1

CLK_PCIE_LAN# 8
CLK_PCIE_LAN 8
PCIE_PTX_C_DRX_N0 4
PCIE_PTX_C_DRX_P0 4

LAN_MDI3- 29
LAN_MDI3+ 29

LAN_MDI2- 29
LAN_MDI2+ 29
LAN_MDI1- 29
LAN_MDI1+ 29

LAN_MDI0- 29
LAN_MDI0+ 29

B B

LAN_XTALI

LAN_XTALO

1

CL14
12P_0402_50V8-J

2

+LAN_REGOUT

For RTL8111H (LDO mode)

60mil 60mil

1

CL34
.1U_0402_10V6-K

2

1 2

RL6 0_0805_5%

+LAN_VDD10

1

2

CL17
.1U_0402_10V6-K

1

CL18
.1U_0402_10V6-K

2

1

CL19
.1U_0402_10V6-K

2

1

CL20
.1U_0402_10V6-K

2

1

CL21
1U_0402_6.3V6K

2

@

1

CL22
.1U_0402_10V6-K

2

@

CL15

12P_0402_50V8-J

1

1

25MHZ_10PF_7V25000014

2

YL1

OSC1

GND2

GND12OSC2

4

3

Close to Pin3, 8, 22, 30 Close to Pin22(Reserved)

Layout Note: RL6,CL16 must be
within 200mil to Pin36,

A A

5

4

+LAN_REGOUT: Width =60mil

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/10/22

2014/10/22

2014/10/22

Title

Title

Title

LAN_RTL8111GH

LAN_RTL8111GH

LAN_RTL8111GH

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Allsparks 5B

Allsparks 5B

Allsparks 5B

1

28 51

28 51

28 51

0.3

0.3

0.3

5

4

3

2

1

DL1/DL2
1'S PN:SC300003M00

D D

TL1

24

AZ3033-04F_DFN2525P10E10

7

I/O3

6

NC3

+3VALW_LAN

LAN_MDI2- LAN_MDI3-

C C

LAN_MDI1+

+3VALW_LAN

5

VDD

4

NC2

2

NC1

9

I/O4

DL1

AZ3033-04F_DFN2525P10E10

7

I/O3

6

NC3

5

VDD

4

NC2

2

NC1

9

I/O4

DL2

EMC_NS@

EMC_NS@

I/O1

NC4

GND

NC5

I/O2

I/O1

NC4

GND

NC5

I/O2

LAN_MDI3+LAN_MDI2+

1

8

11

10

3

1

8

11

10

3

LAN_MDI0+

LAN_MDI0-LAN_MDI1-

2

CL24

0.22U_0402_16V6-K

1

EMC@

LAN_MDI0+28

LAN_MDI0-28

LAN_MDI1+28

LAN_MDI1-28

LAN_MDI2+28

LAN_MDI2-28

LAN_MDI3+28

LAN_MDI3-28

LAN_MDI0+

LAN_MDI0-

LAN_MDI1+

LAN_MDI1-

LAN_MDI2+

LAN_MDI2-

LAN_MDI3+

LAN_MDI3-

MCT1

23

MX1+

22

MX1-

21

MCT2

20

MX2+

19

MX2-

18

MCT3

17

MX3+

16

MX3-

15

MCT4

14

MX4+

13

MX4-

BOTH_GST5009 LF

TCT1

TD1+

TD1-

TCT2

TD2+

TD2-

TCT3

TD3+

TD3-

TCT4

TD4+

TD4-

1

2

3

4

5

6

7

8

9

10

11

12

MCT

LAN_MDO0+

LAN_MDO0-

MCT

LAN_MDO1+

LAN_MDO1-

MCT

LAN_MDO2+

LAN_MDO2-

MCT

LAN_MDO3+

LAN_MDO3-

0.022U_0603_50V7K

CL32

12

1

2

EMC_NS@

CHASSIS1_GND

RL17
20_0603_5%

1

CL25
1000P_1206_2KV7-K

EMC@

2

1

DL3

1

PDT5061_DO-214AA

2

2

EMC@

Place Close to TL1

JRJ1

B B

LAN_MDO0+

LAN_MDO0-

1 2

RL14 0_0402_5%EMC@

1 2

RL15 0_0402_5%EMC@

1 2

RL16 0_0402_5%EMC@

1 2

RL24 0_0402_5%

EMC_NS@

CHASSIS1_GND

A A

Reserve for EMI go rural solution

5

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

2014/10/22

2014/10/22

2014/10/22

3

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2014/10/22

2014/10/22

2014/10/22

LAN_MDO1+

LAN_MDO2+

LAN_MDO2-

LAN_MDO1-

LAN_MDO3+

LAN_MDO3-

2

1

PR1+

2

PR1-

3

PR2+

4

PR3+

5

PR3-

6

PR2-

7

PR4+

8

PR4-

FOX_JMP1S01-R4700-7H

ME@

Title

Title

Title

LAN_Transformer

LAN_Transformer

LAN_Transformer

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Wednesday, April 29, 2015

Allsparks 5B

Allsparks 5B

Allsparks 5B

GND_4

GND_3

GND_2

GND_1

12

11

10

9

CHASSIS1_GND

1

29 51

29 51

29 51

0.3

0.3

0.3

A

Mini-Express Card(WLAN/WiMAX)

Need short

+3VS_WLAN+3VS

@

J6

2

R129
10K_0402_5%

1 2

AOAC@

112

JUMP_43X79

WLAN_CLKREQ_Q#

1 1

+3VS_WLAN

RC2524
10K_0402_5%

@

1 2

WLAN_PCIE_WAKE#

+3VS

+3VS_WLAN

G

2

2 2

WLAN_CLKREQ1#7

AOAC@

R883 0_0402_5%

Q165

13

D

S

2N7002KW_SOT323-3

1 2

1

C190
.1U_0402_10V6-K

2

B

USB20_P38
USB20_N38

PCIE_PTX_C_DRX_P14
PCIE_PTX_C_DRX_N14

PCIE_PRX_DTX_P14
PCIE_PRX_DTX_N14

CLK_PCIE_WLAN8
CLK_PCIE_WLAN#8

1 2

PCIE_WAKE#7,35

LAN_WAKE#28,35

R876 0_0402_5%@

1 2

R57 0_0402_5%@

WLAN_CLKREQ_Q#
WLAN_PCIE_WAKE#

C

JWLAN

1

GND1

3

USB_D+

5

USB_D-

7

GND2

9

SDIO_CLK

11

SDIO_CMD

13

SDIO_DAT0

15

SDIO_DAT1

17

SDIO_DAT2

19

SDIO_DAT3

21

SDIO_WAKE

23

SDIO_RESET

25

27

29

31

33

GND3

35

PETP0

37

PETN0

39

GND4

41

PERP0

43

PERN0

45

GND5

47

REFCLKP0

49

REFCLKN0

51

GND6

53

CLKEQ0#

55

PEWAKE0#

57

GND7

59

RSRVD/PETP1

61

RSRVD/PETN1

63

GND8

65

RSRVD/PERP1

67

RERVD/PERN1

69

GND9

71

RSRVD1

73

RSRVD2

75

GND10

77

GND15

LCN_DAN05-67406-0102

ME@

WLAN

KEY E
PIN24~PIN31 NC PIN

RSRVD/W_DISABLE#2

3.3VAUX1

3.3VAUX2
LED#1

PCM_CLK

PCM_SYNC

PCM_IN

PCM_OUT

LED#2

GND11

UART_WAKE

UART_RX

UART_TX
UART_CTS
UART_RTS

RSRVD10

RSRVD11

RSRVD9

COEX3
COEX2
COEX1

SUSCLK

PERSTO#

W_DISABLE#1

I2C_DATA

I2C_CLK

ALERT
RSRVD6
RSRVD7
RSRVD8

RSRVD12

3.3VAUX3

3.3VAUX4

GND14

D

+3VS_WLAN

2
4
6
8
10
12
14
16
18
20
22

24
26
28
30

32
34
36
38
40
42
44
46
48
50
52
54
56

58
60
62
64
66
68
70
72
74

76

1

T4@

1

T5@

EC_TX_RSVD
EC_RX_RSVD

SUSCLK_R
PLT_RST#
BT_OFF#
WLAN_OFF#

APU_SMB_DATA_R
APU_SMB_CLK_R

EC_TX_R

+3VS_WLAN

1 2

R62 0_0402_5%@

1 2

R63 0_0402_5%@

1 2

R886 0_0402_5%

1 2

R55 0_0402_5%

1 2

R53 1K_0402_5%

1 2

R56 0_0402_5%

1 2

R58 0_0402_5%@

1 2

R59 0_0402_5%@

1 2

R887 0_0402_5%

12

R186
100K_0402_5%

EC_RX 35

SUSCLK 7,11
PLT_RST# 7,15,28

PCH_BT_OFF# 7

PCH_WLAN_OFF# 7

APU_SMB_DATA 7,12,13
APU_SMB_CLK 7,12,13

EC_TX 35

E

12

SSD

C209

22U_0603_6.3V6-M

1

2

SATA_PRX_DTX_P18
SATA_PRX_DTX_N18

SATA_PTX_DRX_N18
SATA_PTX_DRX_P18

2A

C207

4.7U_0402_6.3V6M

CD@

C198

.1U_0402_10V6-K

1

2

CD@

SATA_PTX_DRX_N1
SATA_PTX_DRX_P1

1

2

Ac coupling-Cap place near NGFF CONN within 500mil

PCIE_PTX_C_DRX_N3
PCIE_PTX_C_DRX_P3

PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3

PCIE_PTX_C_DRX_N2
PCIE_PTX_C_DRX_P2

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2

1 2

R172 0_0402_5%PSSD@

1 2

R173 0_0402_5%PSSD@

1 2

R175 0_0402_5%PSSD@

1 2

R174 0_0402_5%PSSD@

SATA_PTX_C_DRX_N1
SATA_PTX_C_DRX_P1

SATA_PRX_C_DTX_P1
SATA_PRX_C_DTX_N1

1

2

C208
.1U_0402_10V6-K

1

T6@

+3.3V_NGFF

1

C197
.1U_0402_10V6-K

2

CD@

+3.3V_NGFF

PLT_RST#

+3.3V_NGFF

R146
10K_0402_5%

@

1 2

R147
10K_0402_5%

1 2

SSD_CLKREQ2# 7

SSD_DEVSLP_R 8

PLT_RST#

EMC_NS@

1

CC158
150P_0402_50V8-J

2

JNGFF1

NGFF

1

GND0

3

GND1

5

PERN3

7

PERP3

9

GND2

11

PETN3

13

PETP3

15

GND3

17

PERN2

19

PERP2

21

GND4

23

PETN2

25

PETP2

27

PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3

PCIE_PTX_C_DRX_N3
PCIE_PTX_C_DRX_P3

CLK_PCIE_SSD#8
CLK_PCIE_SSD8

+3.3V_NGFF

R905

SATA_PRX_C_DTX_P1SATA_PRX_DTX_P1
SATA_PRX_C_DTX_N1SATA_PRX_DTX_N1

SATA_PTX_C_DRX_N1
SATA_PTX_C_DRX_P1

R904 10K_0402_5%

12

0_0402_5%

12

R894
0_0402_5%

@

1 2

12

C249 0.01U_0402_25V7KSSD@

12

C248 0.01U_0402_25V7KSSD@

12

C247 0.01U_0402_25V7KSSD@

12

C246 0.01U_0402_25V7KSSD@

PEDET7

GND5

29

PERN1

31

PERP1

33

GND6

35

PETN1

37

PETP1

39

GND7

41

PERN0/SATA-B+

43

PERP0/SATA-B-

45

GND8

47

PETN0/SATA-A-

49

PETP0/SATA-A+

51

GND9

53

REFCLKN

55

REFCLKP

57

GND10

NC

59

NC

61
63

NC
NC

65

67

NC19

69

PEDET(NC-PCIE/GND-SATA)

71

GND11

73

GND12

75

GND13

76

GND15

ME@

PERST#(O)(0/3.3V)/NC
CLKREQ#(IO)(0/3.3V)/NC
PEWAKE#(IO)(0/3.3V)/NC

SUSCLK(32kHZ)(O)(0/3.3V)

DEREN_40-42191-067B1RHFL

1204
NEW symbol

3.3V_1

3.3V_2
NC1
NC2

DAS/DSS#(IO)

3.3V_3

3.3V_4

3.3V_5

3.3V_6
NC3
NC4
NC5
NC6
NC7
NC8
NC9

NC10
NC11

DEVSLP(O)

NC12
NC13
NC14
NC15
NC16

NC17
NC18

NC
NC
NC
NC

3.3V_7

3.3V_8

3.3V_9

GND14

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58

60
62
64
66

68
70
72
74

77

SSD_DEVSLP_R

1 2

R898 0_0402_5%PSSD@

1 2

R877 0_0402_5%PSSD@

PCIE_PTX_C_DRX_N34
PCIE_PTX_C_DRX_P34

PCIE_PRX_DTX_N34
PCIE_PRX_DTX_P34

PCIE_PTX_C_DRX_N24
PCIE_PTX_C_DRX_P24

PCIE_PRX_DTX_N24
PCIE_PRX_DTX_P24

R145 0_0805_5%

+3VS +3.3V_NGFF

3 3

4 4

For PCIE interface SSD

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2014/10/22

2014/10/22

2014/10/22

Title

NGFF WLAN

NGFF WLAN

NGFF WLAN

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Allsparks 5B

Allsparks 5B

Allsparks 5B

E

30 51

30 51

30 51

0.3

0.3

0.3

5

4

3

+3VS

2

1

Fintek thermal sensor
placed near DIMM

U15

1

VCC

2

DP1

3

DN1

4

DP2

5

DN2

F75303M_MSOP10

Address 1001_101xb

SCL

SDA

ALERT#

THERM#

GND

10

9

8

7

6

EC_SMB_CK2

EC_SMB_DA2

R882

4.7K_0402_5%

@

1 2

EC_SMB_CK2 6,16,35

EC_SMB_DA2 6,16,35

CD@

C47

+3VS

1

2

REMOTE+_R1

REMOTE-_R1

REMOTE+_R2 THERM_L

REMOTE-_R2

D D

.1U_0402_10V6-K

REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-:
Trace width/space:10/10 mil
Trace length:<8"

C C

REMOTE+_R1

C271

3300P_0402_50V7-K

REMOTE-_R1

REMOTE+_R2

C272

3300P_0402_50V7-K

REMOTE-_R2

1

2

@

1

2

@

Near GPU&VRAM

C

2

Q105

B

MMBT3904WH_SOT323-3

E

3 1

Near CPU core

C

2

Q106

B

MMBT3904WH_SOT323-3

E

3 1

FAN Conn

+5VS

1 2

R52 0_0603_5%

1

C206

B B

10U_0805_10V6K

2

.1U_0402_10V6-K

C205

@

0.5A

1

2

+5VS_FAN1

EC_FAN1_SPEED35
EC_FAN1_PWM35

JFAN1

1

1

2

2

3

3

4

4

5

GND1

6

GND2

ACES_85205-04001

ME@

+5VS

1 2

R141 0_0603_5%

1

C204

10U_0805_10V6K

A A

5

4

2

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Issued Date

Issued Date

.1U_0402_10V6-K

C203

@

0.5A

1

2

2014/10/22

2014/10/22

2014/10/22

3

+5VS_FAN2

EC_FAN2_SPEED35
EC_FAN2_PWM35

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

JFAN2

1

1

2

2

3

3

4

4

5

GND1

6

GND2

ACES_85205-04001

ME@

2014/10/22

2014/10/22

2014/10/22

2

Title

Title

Title

Thermal sensor/FAN CONN

Thermal sensor/FAN CONN

Thermal sensor/FAN CONN

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Allsparks 5B

Allsparks 5B

Allsparks 5B

1

31 51

31 51

31 51

of

0.3

0.3

0.3

A

B

C

D

E

USB20_P5_RUSB20_P5

USB20_N5_R

USB30_RX_R_N1

1

D9

1

2

EMC_NS@

2

USB30_TX_R_N2USB30_TX_C_N2USB30_TX_N2
USB20_P6_RUSB20_P6

USB30_RX_R_P2USB30_RX_P2

+USB_VCCA

C55

C56

C57

9
1
8
3
7
2
6
4
5

1

D10

1

2

EMC_NS@

2

AZ5425-01F_DFN1006P2E2

+USB_VCCA

C59 100U_1206_6.3V6M

@

C62

C63

JUSB2

9
1
8
3
7
2
6
4
5

FOX_UEA1111-RC612-7H

ME@

+

1 2

220U_6.3V_M

1 2

1U_0603_25V6M@

1 2

470P_0402_50V7K@

JUSB1

StdA_SSTX+
VBUS
StdA_SSTX­D+
GND_DRAIN
D-

GND_1

StdA_SSRX+

GND_2

GND_5

GND_3

StdA_SSRX-

GND_4

FOX_UEA1111-RC612-7H

ME@

+USB_VCCA

1

1

2

2

AZ5425-01F_DFN1006P2E2

1 2

1 2

1U_0603_25V6M@

1 2

470P_0402_50V7K@

StdA_SSTX+
VBUS
StdA_SSTX­D+
GND_DRAIN
D-

GND_1

StdA_SSRX+

GND_2

GND_5

GND_3

StdA_SSRX-

GND_4

D11

EMC_NS@

10
11
12
13

10
11
12
13

Right SIDE USB3.0 PORT X2

+5VALW

2.2U_0603_10V6-K

1 2

C58

1 1

USB_ON#35

USB_ON# USB_OC1#

U11

1

GND

Vout1

2

Vout27VIN1

VIN23Vout3

4

FLG

EN

G547I2P81U_MSOP8

Low Active 2A

2 2

3 3

For EMC

8

6
5

USB30_RX_N1

USB30_RX_P1

USB30_TX_C_N1

USB30_TX_C_P1

USB20_P5

USB20_N5

USB30_RX_N2

USB30_RX_P2

USB30_TX_C_N2

USB30_TX_C_P2

USB20_N6

USB20_P6

+USB_VCCA

1

C61
1000P_0402_50V7K

@

2

L15

1

1

4

4

EXC24CH900U_4P

L16

1

1

4

4

EXC24CH900U_4P

L8

4

4

1

1

EXC24CH900U_4P

L9

1

4

EXC24CH900U_4P

L10

1

4

EXC24CH900U_4P

EXC24CH900U_4P

1

4

L11

USB_OC1# 7

EMC@

USB30_RX_R_N1

2

2

USB30_RX_R_P1

3

3

EMC@

USB30_TX_R_N1

2

2

USB30_TX_R_P1

3

3

EMC@

USB20_P5_R

3

3

USB20_N5_R

2

2

EMC@

USB30_RX_R_N2

EMC@

EMC@

2

3

2

3

2

3

2

USB30_RX_R_P2

3

USB30_TX_R_N2

2

USB30_TX_R_P2

3

2

3

USB20_N6_R

USB20_P6_R

1

4

1

4

1

4

USB30_TX_P18

USB30_TX_N18

USB20_P58

USB20_N58

USB30_RX_P18

USB30_RX_N18

USB30_TX_P28

USB30_TX_N28

USB20_P68

USB20_N68

USB30_RX_P28

USB30_RX_N28

USB30_TX_N1 USB30_TX_C_N1 USB30_TX_R_N1

USB20_N5
USB30_RX_P1 USB30_RX_R_P1

USB30_RX_N1

USB20_N6 USB20_N6_R

USB30_RX_N2 USB30_RX_R_N2

1 2

C210 .1U_0402_10V6-K

1 2

C211 .1U_0402_10V6-K

USB30_RX_R_N1 USB30_RX_R_N1

9

USB30_RX_R_P1 USB30_RX_R_P1

8

USB30_TX_R_N1 USB30_TX_R_N1

7

USB30_TX_R_P1 USB30_TX_R_P1

6

For EMC

1 2

C64 .1U_0402_10V6-K

1 2

C65 .1U_0402_10V6-K

USB30_TX_C_P1 USB30_TX_R_P1USB30_TX_P1

D24

EMC_NS@

1

1

10

9

7

6 5

AZ1045-04F_DFN2510P10E-10-9

2

2

4

4

5

3

3

8

USB30_TX_C_P2USB30_TX_P2 USB30_TX_R_P2

1 2

R74 0_0402_5%@

1 2

R76 0_0402_5%@

1 2

R64 0_0402_5%@

1 2

R65 0_0402_5%@

1 2

R79 0_0402_5%@

1 2

R78 0_0402_5%@

1 2

R68 0_0402_5%@

1 2

R69 0_0402_5%@

1 2

R70 0_0402_5%@

1 2

R71 0_0402_5%@

1 2

R72 0_0402_5%@

1 2

R73 0_0402_5%@

USB20_P5_R

USB20_N5_R

AZ5425-01F_DFN1006P2E2

D12

EMC_NS@

USB30_RX_R_N2USB30_RX_R_N2

9

10

8

USB30_TX_R_N2 USB30_TX_R_N2

USB30_TX_R_P2 USB30_TX_R_P2

4 4

9

7

7

6

6 5

AZ1045-04F_DFN2510P10E-10-9

1

1

USB30_RX_R_P2USB30_RX_R_P2

2

2

4

4

5

3

3

8

USB20_P6_R

USB20_N6_R

1

2

AZ5425-01F_DFN1006P2E2

D33

1

2

EMC_NS@

1

D34

1

2

EMC_NS@

2

AZ5425-01F_DFN1006P2E2

For EMC

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2014/10/22

2014/10/22

2014/10/22

Title

USB2.0/USB3.0 PORT (LEFT)

USB2.0/USB3.0 PORT (LEFT)

USB2.0/USB3.0 PORT (LEFT)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Allsparks 5B

Allsparks 5B

Allsparks 5B

E

32 51

32 51

32 51

0.3

0.3

0.3

A

B

C

D

E

F

G

H

SATA HDD Conn.

1 1

JHDD

1

SATA_PTX_DRX_P08
SATA_PTX_DRX_N08

SATA_PRX_DTX_N08
SATA_PRX_DTX_P08

2 2

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

SATA_PRX_DTX_P0

1 2

C66 .01U_0402_16V7-K

1 2

C67 .01U_0402_16V7-K

1 2

C68 .01U_0402_16V7-K

1 2

C69 .01U_0402_16V7-K

+5VS_HDD

SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0

SATA_PRX_C_DTX_N0SATA_PRX_DTX_N0
SATA_PRX_C_DTX_P0

1

2

2

GND1

3

3

4

4

5

GND2

5

6

6

7

7

8

8

9

9

10

10

HRS_TF31-10S-0P5SH-800

ME@

11

12

R891 0_0805_5%

+5VS

3 3

4 4

A

B

C

12

C1955

22U_0603_6.3V6-M

C1956

4.7U_0402_6.3V6M

1

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

D

1

2

2014/10/22

2014/10/22

2014/10/22

E

2A

+5VS_HDD

CD@

1

C1950
.1U_0402_10V6-K

2

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

F

2014/10/22

2014/10/22

2014/10/22

Title

Title

Title

HDD CONN

HDD CONN

HDD CONN

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet

Wednesday, April 29, 2015

G

Allsparks 5B

Allsparks 5B

Allsparks 5B

33 51

33 51

33 51

H

of

0.3

0.3

0.3

5

4

3

2

1

+3VS +5VS+3.3VD

RA2 0_0603_5%

1 2

CA8

1U_0402_6.3V6K

CA7

.1U_0402_10V6-K

2

RA2090_0402_5%

1 2

1 2

0_0402_5%

1

1

1

2

CA1

2

1

Close to Pin9

@

1 2

.1U_0402_10V6-K

RA44

0_0402_5%

SPKR_MUTE#EC_MUTE#

12

RA43
10K_0402_5%

CA40

12

RA14
10K_0402_5%

.1U_0402_10V6-K

1 2

A_RING3_CONN36

A_RING2_CONN36

DMIC_DATA25

HDA_RST_AUDIO#7

A_PLUG_IN36

PC_BEEPPC_BEEP1

Close to Pin1

D D

C C

B B

+3.3VD DVDD_IO

RA11 0_0402_5%@

1 2

+1.5VS

1 2

RA40 0_0402_5%

+1.8VS

EC_MUTE#35

BEEP#35

PCH_BEEP7

BAT54CW_SOT323-3

@

DA1

2

3

12

RB751V-40_SOD323-2
DA4

RA35

RA10 0_0603_5%EMC_NS@

LA25 BLM15PD600SN1D_2P

1 2

MICBIASB

RA38 2.2K_0402_5%
RA37 2.2K_0402_5%

1 2

+3VS

+3VS

2

CA4

4.7U_0603_6.3V6K

1

Close to Pin36

1 2

1 2

EMC@

DMIC_DATA
DMIC_CLK

HDA_RST_AUDIO#

RA205100K_0402_1%

1 2

RA204200K_0402_1%

12

CA14 1U_0402_6.3V6K

2

CA35

4.7U_0603_6.3V6K

1

Close to Pin19

RA190_0402_5%
RA180_0402_5%

1 2

1

2

JSENSE

CA178

10U_0805_10V6K

LINE1_L
LINE1_R

A_RING3_CONN

A_RING2_CONN

LINE1_VREF_L
LINE1_VREF_R

DMIC_DATA_R

12

DMIC_CLK_R

12

SPKR_MUTE#

PC_BEEP

VDD_STB

1 2

2A

+5VD

DVDD_IO

CA19

.1U_0402_10V6-K

CA18

.1U_0402_10V6-K

+3.3VD

2

2

1

1

RA1990_0402_5%

@

UA1

22
21

24
23

17
18

31
30

47
11

12

13
14

37
35

36

20

19

49

1

LINE1-L(PORT-C-L)
LINE1-R(PORT-C-R)

LINE2-L(PORT-E-L)
LINE2-R(PORT-E-R)

MIC2-L(PORT-F-L)/RING
MIC2-R(PORT-F-R)/SLEEVE

LINE1-VREFO-L
LINE1-VREFO-R

2

GPIO0/DMIC-DATA

3

GPIO1/DMIC-CLK

PDB
RESETB

PCBEEP

HP/LINE1_JD(JD1)
MIC2/LINE2_JD(JD2)

CBP
CBN

CPVDD

VD33_STB

MIC_CAP

4

DC_DET
Thermal_PAD

ALC3248-CG_MQFN48_6X6

RA1 0_0402_5%EMC_NS@

RA4 0_0402_5%EMC_NS@

RA6 0_0402_5%EMC_NS@

RA9 0_0402_5%EMC_NS@

RA12 0_0402_5%EMC_NS@

RA13 0_0402_5%EMC_NS@

Use 250mils wide trace bridging
AGND and DGND at codec

41

9

DVDD

PVDD1

DVDD-IO

ALC3248

1 2

1 2

1 2

1 2

1 2

1 2

C230 .1U_0402_10V6-KEMC_NS@

1 2

C231 .1U_0402_10V6-KEMC_NS@

1 2

C9 .1U_0402_10V6-KEMC_NS@

1 2

26

40

46

PVDD2

AVDD1

AVDD2

HPOUT-L(PORT-I-L)

HPOUT-R(PORT-I-R)

SPDIF-OUT/GPIO2

SPDIFO/FRONT_JD(JD3)/GPIO3

RA8 0_0402_5%

RA210 0_0402_5%

1

CA39
1U_0402_6.3V6K

Close to

2

Pin40

SPK-OUT-L-

SPK-OUT-L+

SPK-OUT-R+

SPK-OUT-R-

SYNC
BCLK

SDATA-OUT

SDATA-IN

MONO-OUT

MIC2-VREFO

LDO3-CAP
LDO2-CAP
LDO1-CAP

VREF

CPVEE

AVSS1
AVSS2

GNDAGND

1 2

1 2

43
42

45
44

32
33

10
6

5
8

48

16

29

7
39
27

28

15
34

25
38

+5VA

+1.5VS

+1.8VS

@

SPK_L­SPK_L+

SPK_R+
SPK_R-

HPOUT_L
HPOUT_R

HDA_SYNC_AUDIO
HDA_BITCLK_AUDIO

HDA_SDOUT_AUDIO

SDATA_IN

RA16 33_0402_5%

MONO_OUT

MICBIASB

CA2 4.7U_0603_6.3V6K

1 2

CA3 4.7U_0603_6.3V6K

1 2
1 2

CA5 4.7U_0603_6.3V6K
RA47 2.2K_0402_5%

1 2

@

1 2

CA17 1U_0402_6.3V6K

CA36 1U_0402_6.3V6K

1 2

12

CA11

2

1

HDA_SDIN0

.1U_0402_10V6-K

2

1

RA7 0_0603_5%

1 2

CA15

4.7U_0603_6.3V6K
CA180

1

2

CD@

HDA_SYNC_AUDIO 7
HDA_BITCLK_AUDIO 7

HDA_SDOUT_AUDIO 7

MONO_OUT 27

+5VS

2.2U_0603_6.3V6K

HDA_SDIN0 7DMIC_CLK25
CODEC_WF_MUTE# 27

SPK_R+
SPK_R-

SPK_L+
SPK_L-

LINE1_L

CA41 1U_0402_6.3V6K

LINE1_VREF_L

1 2

RA41 4.7K_0402_5%

HPOUT_L
HPOUT_R

LINE1_VREF_R

1 2

RA42 4.7K_0402_5%

LINE1_R

CA42 1U_0402_6.3V6K

LA12 BLM15BX750SN1D_2P

1 2

LA13 BLM15BX750SN1D_2P

1 2

LA10 BLM15BX750SN1D_2P

1 2

LA11 BLM15BX750SN1D_2P

1 2

EMC@

EMC@

EMC@

EMC@

12

1 2

RA21 47_0402_1%
RA20 47_0402_1%

1 2

12

CA153

1000P_0402_50V7K

EMC@

EMC@

CA154

1000P_0402_50V7K

EMC@

1

1

2

2

CA152

1000P_0402_50V7K

CA151

1000P_0402_50V7K

1

1

2

2

A_HP_OUTL_R 36
A_HP_OUTR_R 36

SPK_R+_CON
SPK_R-_CON

SPK_L+_CON
SPK_L-_CON

EMC@

JSPK1

1

1

2

2

3

3

4

4

5

GND1

6

GND2

ACES_85205-04001

ME@

HDA_RST_AUDIO#

HDA_SYNC_AUDIO

+3VALW

+3VL

To solve the background noise while combojack connecting to an

A A

active speaker and system entry into S3/S4/S5 without analog power.

5

@

1 2

RA39 0_0402_5%

1 2

RA203 0_0402_5%

VDD_STB

1

CA37

2

100P_0402_50V8J

EMC_NS@

EMC_NS@

4

DMIC_CLK HDA_BITCLK_AUDIO

DMIC_DATA

1

CA38

2

100P_0402_50V8J

For EMI

3

CA23

CA24

1

1

1

CA22

2

2

2

68P_0402_50V8J

EMC_NS@

33P_0402_50V8J

22P_0402_50V8-J

22P_0402_50V8-J

EMC_NS@

EMC_NS@

HDA_SDOUT_AUDIO

RA27

EMC_NS@

1 2

27_0402_5%

HDA_SDIN0

CA25

CA26

1

1

2

2

33P_0402_50V8J

EMC_NS@

EMC_NS@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

For EMI

2014/10/22

2014/10/22

2014/10/22

SPK_L+

SPK_L-

SPK_R+

SPK_R-

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

2

EMC_NS@

1 2

RA194 15_0402_5%

EMC_NS@

1 2

RA195 15_0402_5%

1 2

EMC_NS@

RA196 15_0402_5%

1 2

EMC_NS@

RA197 15_0402_5%

Deciphered Date

Deciphered Date

Deciphered Date

CA173 220P_0402_50V7KEMC_NS@

1 2

CA174 220P_0402_50V7KEMC_NS@

1 2

1 2

CA176 220P_0402_50V7KEMC_NS@

1 2

CA177 220P_0402_50V7KEMC_NS@

For EMI

2014/10/22

2014/10/22

2014/10/22

Title

Title

Title

Codec_ALC3248

Codec_ALC3248

Codec_ALC3248

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

1

Allsparks 5B

Allsparks 5B

Allsparks 5B

34 51

34 51

34 51

of

0.3

0.3

0.3

5

+1.8VALW

+3VALW_R

+3VS

1 2

RE75 0_0402_5%EXT@

1 2

RE76 0_0402_5%

SHARE@

1 2

RE95 0_0402_5%INT@

D D

+VFSPI

Change RE6 to 0ohm jump

WRST#16

+3VALW_R

1 2

DE1

RB751V-40_SOD323-2

1 2

RE8 100K_0402_5%

+3VALW_R

RPE2

2 3
1 4

C C

+3VS

2.2K_0404_4P2R_5%

RPE3

1 4
2 3

2.2K_0404_4P2R_5%

Thermal Sensor&CPU&GPU

+3VL

1 2

RE38 100K_0402_5%

1 2

RE93 10K_0402_5%

MIRROR@

B B

A A

1 2

RE40 10K_0402_5%

1 2

RE63 10K_0402_5%@

RE43 10K_0402_5%

RE44 10K_0402_5%

MIRROR@

RE46 10K_0402_5%

NOMIRROR@

1 2

RE101 10K_0402_5%EXT@

For EMI

CLK0_PCI_EC

RE2 10_0402_5%

5

@

1 2

12

12

12

EMC_NS@

10P_0402_50V8J

GPG2

GPG2

GPG2

when mirror, GPG2 pull high
when no mirror, GPG2 pull low

EC_SPI_WP#

BKOFF#
AC_PRESENT

EMC_NS@

LID_SW#

EC_ON_3V

+3VALW

CE2

+3VL

+3VALW_R

1

2

NOVO#

PIN33 SET OD for 5V
PIN93 SET OD for 1.8V

@

1

2

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK2
EC_SMB_DA2

EC_ON_3V45

BATT& CHARGE

.01U_0402_16V7-K

C48

1

2

@

CE12

1U_0402_6.3V6K

KSI[0..7]36

+3VL

EC_SPI_CS0#

EC_SPI_SO

SYSON

KSO[0..17]36

KBRST#7

LPC_FRAME#8,11,36

LPC_AD38,36
LPC_AD28,36
LPC_AD18,36
LPC_AD08,36

CLK0_PCI_EC8,11

EC_APU_ALWEN47,48

EC_RX30
EC_TX30

APU_LPC_RST#7,36

EC_SCI#

EC_SCI#7

GATEA20

GATEA207

KSI[0..7]

KSO[0..17]

EC_SMB_CK1
EC_SMB_DA1

KSI7
KSI6
WRST#

1

PAD @

1

PAD @

1

PAD @

1

PAD @

1

PAD @

1

PAD @

1

PAD @

1

PAD @

For factory EC flash

ON/OFF36

EC_ON_3V

EC_SMB_CK143,44
EC_SMB_DA143,44

PCH_CMOSP37

LAN_PWR_ON#28

EC_SMB_CK26,16,31
EC_SMB_DA26,16,31

LAN_WAKE#

LAN_WAKE#28,30

USB_ON#

USB_ON#32

USB_CHG_EN

AC_PRESENT

SHARE@

EC_SPI_CS0#

1 2

RE45 0_0402_5%

SHARE@

EC_SPI_SI

1 2

RE47 0_0402_5%

SHARE@

EC_SPI_SO

1 2

RE48 0_0402_5%

SHARE@

EC_SPI_CLK

1 2

RE49 0_0402_5%

U17

1

CS#

2

SO(O1)

EC_SPI_WP# EC_SPI_CLK

3

WP#

VSS4SI(IO0)

GD25D10BTIGR_SO8

EXT@

APU_LPC_RST#

BATT_TEMP

ACIN#

ON/OFF

RE87 0_0402_5%EXT@

RE88 0_0402_5%EXT@

1

@

2

USB_CHG_EN36

EC_RSMRST#7

PCIE_WAKE#7,30
AC_PRESENT7,16

1 2

1 2

CE13
.1U_0402_10V6-K

1 2

RE73 0_0402_5%

SERIRQ_EC
LPC_FRAME#

CLK0_PCI_EC
WRST#

EC_APU_ALWEN
EC_RX
EC_TX
APU_LPC_RST#

1 2

RE70 0_0402_5%

1 2

RE72 0_0402_5%

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1

IT1

KSO2

IT2

KSO3

IT3

KSO4

IT4

KSO5

IT5

KSO6
KSO7
KSO8
KSO9

IT6

KSO10

IT7

KSO11

IT8

KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

ON/OFF

1 2

RE91 0_0402_5%@

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK2
EC_SMB_DA2

12

8

VCC

7

NC

6

RE90 0_0402_5%EXT@

SCLK

5

RE89 0_0402_5%EXT@

CE20 220P_0402_50V7KEMC_NS@

CE16 100P_0402_50V8JEMC_NS@

CE17 100P_0402_50V8JEMC_NS@

CE18 1U_0402_6.3V6K@

4

Close EC

CE3

1 2

.1U_0402_10V6-K

1 2

RE6 0_0402_5%

4
5
6
7
8

9
10
13
14
15
16
17
22
23

126

58
59
60
61
62
63
64
65
36
37
38
39
40
41
42
43
44
45
46
51
52
53
54
55
56
57

110
111
115
116
117
118

94
95

112
125

33
35
93

2

RE290_0402_5%

128

SPI_CS0#

SPI_SI

SPI_SO

SPI_CLK

+3VALW

1 2

1 2

1 2

1 2

1 2

1 2

4

VCOREVCC

+3VS

11

12

3

UE1

KBRST#/GPB6
SERIRQ/GPM6
LFRAME#/GPM5
LAD3/GPM3
LAD2/GPM2
LAD1/GPM1
LAD0/GPM0
LPCCLK/GPM4
WRST#
ECSMI#/GPD4
SIN0/PWUREQ#/BBO/SMCLK2ALT/GPC7
SOUT0/LPCPD#/GPE6
LPCRST#/GPD2
ECSCI#/GPD3
GA20/GPB5

KSI0/STB#
KSI1/AFD#
KSI2/INIT#
KSI3/SLIN#
KSI4
KSI5
KSI6
KSI7
KSO0/PD0
KSO1/PD1
KSO2/PD2
KSO3/PD3
KSO4/PD4
KSO5/PD5
KSO6/PD6
KSO7/PD7
KSO8/ACK#
KSO9/BUSY
KSO10/PE
KSO11/ERR#
KSO12/SLCT
KSO13
KSO14
KSO15
KSO16/SMOSI/GPC3
KSO17/SMISO/GPC5

PWRSW/GPB3
XLP_OUT/GPB4
SMCLK1/GPC1
SMDAT1/GPC2
SMCLK2/PECI/GPF6
SMDAT2/PECIRQT#/GPF7
CRX1/SIN1/SMCLK3/GPH1/ID1
CTX1/SOUT1/SMDAT3/GPH2/ID2

VSTBY0
GPE4

GINT/CTS0#/GPD5
RTS1#/GPE5
CLKRUN#/GPH0/ID0

CK32KE/GPJ7
CK32K/GPJ6

VBAT

IT8371E-128/DX
LQFP128

Int. K/B
Matrix

SPI_CS0# 8

SPI_SI 8

SPI_SO 8

SPI_CLK 8

1

CE23
.1U_0402_10V6-K

EXT@

2

EC_SPI_SI

VCORE

VCC

SM Bus

WAKE UP

GPIO

Clock

1 2

RE1 0_0603_5%

1 2

RE3 0_0603_5%

@

+3VALW_R

+VFSPI

+3VALW_EC

minimum trace width 12 mil

74

50

92

121

127

114

AVCC

VFSPI

VSTBY2

VSTBY3

VSTBY4

VSTBY126VSTBY5

PWM

LPC

DAC2/TACH0B/SMINT6/GPJ2
DAC3/TACH1B/SMINT7/GPJ3

DAC

PS2CLK0/TMB0/CEC/GPF0

PS2

EXTERNAL SERIAL FLASH

SPI Flash ROM

UART

GPIO

L80HLAT/BAO/SMCLK4/GPE0

VSS1

VSS2

VSS4

VSS5

VSS349VSS6

AVSS

1

27

75

91

113

122

EC_AGND

+3VS

1

CE19
.1U_0402_10V6-K

2

GPU_VR_HOT#49

VR_HOT#44,50,51

+3VL

+3VALW

All capacitors close to EC

1

CE6

2

.1U_0402_10V6-K

CD@

PWM0/GPA0
PWM1/GPA1
PWM2/GPA2

PWM3/GPA3
PWM4/SMCLK5/GPA4
PWM5/SMDAT5/GPA5

PWM6/SSCK/GPA6
PWM7/RIG1#/GPA7

TMRI0/GPC4

TMRI1/GPC6

ADC0/GPI0
ADC1/SMINT0/GPI1
ADC2/SMINT1/GPI2

ADC

ADC3/SMINT2/GPI3
ADC4/SMINT3/GPI4

ADC5/DCD1#/GPI5
ADC6/DSR1#/GPI6
ADC7/CTS1#/GPI7

DAC4/DCD0#/GPJ4

DAC5/RIG0#/GPJ5

PS2DAT0/TMB1/GPF1
SMCLK0/SMINT8/GPF2
SMDAT0/SMINT9/GPF3

PS2CLK2/SMINT10/GPF4
PS2DAT2/SMINT11/GPF5

GPH3/ID3/YM

GPH4/ID4/YP

GPH5/ID5/DM

GPH6/ID6/DP

FSCE#/GPG3
FMOSI/GPG4
FMISO/GPG5

FSCK/GPG7

AC_IN#/GPB0

LID_SW#/GPB1

EGAD/GPE1
EGCS#/GPE2
EGCLK/GPE3

SMINT5/GPJ1

SSCE0#/GPG2
SSCE1#/GPG0

DSR0#/GPG6

BTN#/GPG1
CRX0/GPC0

CTX0/TMA0/GPB2

RI1#/GPD0
RI2#/GPD1

TACH2/SMINT4/GPJ0

TACH1A/TMA1/GPD7

TACH0A/GPD6

L80LLAT/SMDAT4/GPE7

IT8371E-128-DX_LQFP128_14X14

1 2

RE102 0_0402_5%

EC_GPU_HOT#

1 2

RE34 0_0402_5%

H_PROCHOT#_EC

3

+3VALW_R +3VALW_R

1

1

1

CE8

CE7

2

2

.1U_0402_10V6-K

.1U_0402_10V6-K

24
25
28
29

EC_FAN2_PWM

30

EC_FAN1_PWM

31
32
34
120
124

SUSP#

66
67

BATT_TEMP

68
69
70
71
72
73

78
79

H_PROCHOT#_EC

80

EC_RTCRST#_ON USB_CHG_EN

81

85
86

EC_GFX_ON_R

87
88

TP_CLK

89

TP_DATA

90

96
97

1 2

98

RE99 0_0402_5%

99

EC_SPI_CS0#

101

EC_SPI_SI

102

EC_SPI_SO

103

EC_SPI_CLK

105

108

ACIN#
LID_SW#

109

82
83

1 2

RE92 0_0402_5%

84

77
100

GPG2

106
104
107
119

BKOFF#

EC_ON_5V

123
18
21
76

SYSON

EC_FAN2_SPEED

48

EC_FAN1_SPEED

47

EC_GFX_PWRGD

19
20

34

D

5

QE1B

G

S

2N7002KDWH_SOT363-6

61

D

2

QE1A

G

S

2N7002KDWH_SOT363-6

CE10

2

.1U_0402_10V6-K

12

RE71 0_0402_5%

1

CE24
47P_0402_50V8J

@

2

1

CE14
47P_0402_50V8J

@

2

1

CE11

@

2

.1U_0402_10V6-K

PWR_LED1# 36
BATT_CHG_LED# 36
BATT_LOW_LED# 36
LED_KB_PWM 36

EC_FAN2_PWM 31

EC_FAN1_PWM 31

BEEP# 34

PWR_LED2# 36

CHG_MOD1 36
SUSP# 37,46,47

NTC_V 43

TURBO_V 43,44

BATT_TEMP 43,44

BATT_I 44

ENBKL 25

ADP_I 43,44

ADAPTER_ID 42,44

CHG_MOD2 36

VR_APU_PWRGD 51

MAINPWON 43,45

EC_RTCRST#_ON 9

CAPS_LED# 36

PBTN_OUT# 7

NUM_LED# 36
TP_CLK 36
TP_DATA 36

CHG_MOD3 36

EC_VR_ON 51

EC_SYS_PWRGD 7

LID_SW# 36

EC_MUTE# 34

ADAPTER_ID_ON# 44

PM_SLP_S5# 7

WFPWR_EN 27

NOVO# 36
BKOFF# 25
EC_ON_5V 45

PM_SLP_S3# 7
EC_WF_MUTE# 27
SYSON 46

EC_FAN2_SPEED 31

EC_FAN1_SPEED 31

RE61 0_0402_5%

TP_LOCK_LED# 36

GPU_PROCHOT# 16

H_PROCHOT# 6,43

3

PIN70 1.8V IN

RE62 0_0402_5%

RE74 1K_0402_5%

EC_GPU_HOT#

EC_ON_3V

VDDGFX_PD

1 2

1 2

1 2

1 2

RE67 0_0603_5%

1 2

RE68 0_0603_5%

PROCHOT# 43

EC_GFX_ON 50

VR_GFX_PWRGD 7,50

ACIN#

2N7002KW_SOT323-3

+3VL

1 2

RE94 0_0402_5%

13

D

S

@

RE42
100K_0402_5%

1 2

QE2

G

1

CE4
.1U_0402_10V6-K

2

EC_AGND

2

2

+3VALW_EC

1

CE5
1000P_0402_50V7K

2

EC_AGND

+3VS

EC_FAN2_SPEED

EC_FAN1_SPEED

EC_FAN2_PWM

EC_FAN1_PWM

ENBKL

EC_GFX_ON

TP_CLK

TP_DATA

EC_GFX_PWRGD

GATEA20

EC_SCI#

USB_ON#

LAN_WAKE#

SUSP#

EC_ON_5V

SUSP#

SYSON

EC_APU_ALWEN

SERIRQ

1 2

RE66 10K_0402_5%

1 2

RE10 10K_0402_5%

1 2

RE65 10K_0402_5%@

1 2

RE11 10K_0402_5%@

1 2

RE9 100K_0402_5%@

1 2

RE60 10K_0402_5%@

12

RE12 4.7K_0402_5%

12

RE13 4.7K_0402_5%

1 2

RE69 10K_0402_5%

1 2

RE85 10K_0402_5%

1 2

RE86 10K_0402_5%

1 2

RE15 100K_0402_5%

1 2

RE64 100K_0402_5%

1 2

RE5 10K_0402_5%

1 2

RE18 100K_0402_5%@

1 2

RE81 100K_0402_5%

1 2

RE19 100K_0402_5%

1 2

RE21 100K_0402_5%

1 2

RE23 100K_0402_5%

1 2

RE83 10K_0402_5%

VDDGFX_PD=0 -> VDDCR_GFX VRM turned ON.
VDDGFX_PD=1 -> VDDCR_GFX VRM turned OFF

+5VALW

@

+3VALW_R

@

+3VS

SERIRQ_EC

CC173

.1U_0402_10V6-K

@

SERIRQ_EC

12

GPG2

RE96 0_0402_5%EXT@

1 2

VDDGFX_PD7

RE59 10K_0402_5%

@

will cost down in future if EC internal logic verify ok

+3VS

1 2

RE58 10K_0402_5%@

61

Issued Date

Issued Date

Issued Date

D

2

G

S

ACIN 44

VDDGFX_PD

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

RE78
0_0402_5%

SHARE@

1 2

1

2

1

2

RE80 0_0402_5%

RE98 0_0402_5%EXT@

13

D

QE10

2

G

S

2N7002KW_SOT323-3EXT@

1 2

12

RE7
100K_0402_5%

@

QE9A
2N7002KDWH_SOT363-6

@

2014/10/22

2014/10/22

2014/10/22

UE2

VCCA

VCCB

GND

EO

A43B4

G2129TL1U_SC70-6

SHARE@

INT@

12

12

RE97
100K_0402_5%

EXT@

VDDGFX_PD_R

1

2

@

QE9B
2N7002KDWH_SOT363-6

3 4

D

G

5

@

0.1U_0402_25V6

1

C270

@

2

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

6

5

4

QE7

2

G

@

CE22
1000P_0402_50V7K

S

Deciphered Date

Deciphered Date

Deciphered Date

RE79
0_0402_5%

SHARE@

1 2

SERIRQ

1

CC174
.1U_0402_10V6-K

@

2

SERIRQ

EC_GFX_ON

13

D

S

2N7002KW_SOT323-3

VR_GFX_PWRGDEC_GFX_PWRGD

8371DX
MIRROR
SHARE ROM

8371DX
NO-MIRROR
INT ROM

★

8371DX
MIRROR
EXT ROM

+3VS+VFSPI +3VS

RE77
10K_0402_5%

SHARE@

1 2

SERIRQ 8,36

DX SERIRQ level follow VFSPI level

2014/10/22

2014/10/22

2014/10/22

1

MIRROR@

SHARE@

NOMIRROR@

INT@

QUAD@

MIRROR@

EXT@

QUAD@

Title

Title

Title

EC ITE8371LQFP

EC ITE8371LQFP

EC ITE8371LQFP

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

D

D

D

Date: Sheet of

Date: Sheet of

Date: Sheet of

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

1

Allsparks 5B

Allsparks 5B

Allsparks 5B

35 51

35 51

35 51

0.3

0.3

0.3

5

ON/OFF switch/PWR LED

NOVO#35

D D

1

3

SW6

T4BJB16_4P

2

4

ON/OFFBTN#

PWR_LED2#35

AZ5425-01F_DFN1006P2E2

NOVO#

ON/OFF

1

2

1

2

D2

EMC_NS@

+3VL

R80
100K_0402_5%

1 2

1 2

R82 0_0402_5%

@

PWR_LED2#

2

C1942
220P_0402_50V7K

1

EMC_NS@

@

1 2

J7

SHORT PADS

@

1 2

J8

SHORT PADS

ON/OFFBTN#

LED1

1 2

B1931TX--05P-000314_WHITE

1 2

R899 0_0402_5%

D15

2

1

3

BAT54CW_SOT323-3

@

1 2

R151 0_0402_5%

1 2

R142 390_0402_5%

NOVO_BTN#

ON/OFF

+3VL

1 2

+3VALW

R148
100K_0402_5%

ON/OFF 35

PWR_LED2#

4

3

2

1

K/B Connector

D35

+3VS

1

221

AZ5725-01F_DFN1006P2X2

KSI[0..7]

KSO[0..17]

KSI[0..7] 35

KSO[0..17] 35

300_0402_5%

12

12

R885

R90
300_0402_5%

USB I/O Connector

1

D36

1

2

EMC_NS@

2

AZ5425-01F_DFN1006P2E2

EMC@

D23

1

221

AZ5725-01F_DFN1006P2X2

EMC@

NUM_LED# LED_KB_C

NUM_LED#35

PWR_NUM_LED
CAPS_LED#

CAPS_LED#35

PWR_CAPS_LED
KSO17
KSO16
KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1

JKB

30

30

GND_2

29

29

GND_1

28

28

27

27

26

26

25

25

24

24

23

23

22

22

21

21

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

ACES_50504-03041-001

ME@

32
31

LED_KB_PWM35

+5VS

1 2

R897 0_0603_5%

2

1

1 2

C182

@

0.1U_0402_10V6K

R889
100K_0402_5%

Q175

1

D

2

G

S

3

PJA3436_SOT23-3

JKBL

1

1

2

2

3

3

4

4

5

GND1

6

GND2

ACES_88514-00401-071

ME@

LED_KB_C

TP/B Connector

C C

TP_SMB_DAT7

TP_SMB_CLK7

TP_DATA35
TP_CLK35

B B

TPM

A A

+3VS

1 2

1A 1A(50mA MAX)

R110 0_0603_5%TPM@

UTPM1

1

NC_1

2

NC_2

3

NC_3

7

PP

6

NC_4

9

NC_7

LFRAME#

4

GND_1

11

GND_2

18

GND_3

5

NC_5

8

NC_6

12

NC_8

CLK_RUN#

13

NC_9

14

NC_10

Z32H320TC_TSSOP28

TPM@

LPCPD#
SERIRQ

LRESET#

5

GND_4

VDD3
VDD1

LAD0
LAD1

LAD2
LAD3

LCLK
VDD2

@

@

1

2

C115

100P_0402_50V8J

1

C176
.1U_0402_10V6-K

2

TPM@

24
10

28

R111 10K_0402_5%TPM@

27
26
23
22
20
17

25
21
19
15

16

R83 0_0402_5%

+3VS

1

2

C116

100P_0402_50V8J

For EMC

1 2

1 2

TPM@

TP_DATA
TP_CLK
TP_PWR

TPM@

R84

1

2

1 2

0_0402_5%

TP_CLK
TP_DATA

C177
.1U_0402_10V6-K

TP_PWR

1

2

C114

.1U_0402_10V6-K

JTP

1

1

2

2

3

3

4

4

5

5

6

6

G1
G2

CVILU_CF31061D0R4-10-NH

ME@

312

AZC199-02S.R7G_SOT23-3EMC_NS@

+3VS_TPM

1

C178
.1U_0402_10V6-K

2

TPM@

+3VS_TPM

SERIRQ 8,35

LPC_AD0 8,35
LPC_AD1 8,35
LPC_FRAME# 8,11,35
LPC_AD2 8,35
LPC_AD3 8,35

CLK1_PCI_TPM 8,11

APU_LPC_RST# 7,35

TP_PWR

7
8

DT1

+3VS_TPM

4

USB charger

Hall Sensor

+3VL

@

.1U_0402_10V6-K

USB20_P08
USB20_N08

USB_CHG_EN35

CHG_MOD135
CHG_MOD235
CHG_MOD335

0.01U_0402_25V7K

1 2

R880 0_0402_5%

+5VALW

C181

12

USB_OC2#7

ILIM_SEL

STATUS#_U

USB_CHG_EN

ILIM_SEL

1

USB20_P0

3

USB20_N0

2

13

5

CHG_MOD1

6

CHG_MOD2

7

CHG_MOD3

8

R121

R119 100K_0402_5%

R120 10K_0402_5%

R122

2.2A

U3

IN

OUT

DP_IN

DP_OUT

DM_IN

DM_OUT

GND

STATUS#

ILIM_SEL
FAULT#
EN

ILIM_LO

CLT1

ILIM_HI
CLT2
CLT3

GND_Pad

TPS2546RTER_QFN16_4X4

12

10K_0402_5%

1 2

@

12

12

@

10K_0402_5%

+USB_VCCB

12

USB20_P0_R

10

USB20_N0_R

11
14

STATUS#_U

9

ILIM_SEL

4

48.7K_0402_1%

ILIM_LO

1 2

15

R118

ILIM_HI

16

1 2

R117

17

22.6K_0402_1%

+5VALW

Left Side USB2.0 Port X 1 (USB/B)

USB20_P0_R

1 2

R67 0_0402_5%

USB20_N0_R

1 2

R66 0_0402_5%

pin name

S0 CDP

Charge port
Pin5 Enable

S3 DCP AUTO

H for all

S4/S5
DCP AUTO

S0 SDP1 0/1

Normal port
Pin5 Enable
H for S0/S3

S3 SDP1

L for S4/S5

S4/S5 Disable 0/1

SDP2 (No Discharge from/to CDP)
SDP1(Discharge from/to any charging state including CDP)

USB20_P0_CONN

USB20_N0_CONN

6pin number 87

1

0

Ctl2Ctl1 ILM_SELCtl3

1

11 0

100

00

11

11000 0/1

4

1

0/1

0/1

+USB_VCCB

USB20_N0_CONN

1 2

R167 0_0402_5%

1 2

R168 0_0402_5%

USB20_P0_CONN

NOVO_BTN#

USB20_P4

USB20_P48

USB20_N4

USB20_N48

USB30_RX_P0

USB30_RX_P08

USB30_RX_N0

USB30_RX_N08

USB30_TX_P0

USB30_TX_P08

USB30_TX_N0

USB30_TX_N08

A_RING2_CONN34
A_HP_OUTL_R34
A_HP_OUTR_R34
A_PLUG_IN34
A_RING3_CONN34

+3VS

A_RING2_CONN
A_HP_OUTL_R
A_HP_OUTR_R
A_PLUG_IN
A_RING3_CONN

JUSB3

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

GND1

27

28

28

29

GND2

29

30

30

HRS_TF31-30S-0P5SH-800

ME@

31

32

GNDA

LED

1 2

R900 0_0402_5%

C1

+VCC_LID

+3VS

R901 0_0402_5%

+5VS

1

C3

U4

1

1

GND

OUTPUT

2

2

VCC

AH9247NTR-G1_SOT23-3

100P_0402_50V8J

2

LID_SW#

3

LID_SW# 35

R902 0_0402_5%

+3VALW

R903 0_0402_5%

+5VALW

3

1 2

@

1 2
1 2

LED_PWR_S0

LED_PWR_S0
PWR_LED1#

PWR_LED1#35
BATT_LOW_LED#35
BATT_CHG_LED#35

@

BATT_LOW_LED#
BATT_CHG_LED#
SATA_LED#

SATA_LED#8

TP_LOCK_LED#

TP_LOCK_LED#35

LED_PWR_S5

LED_PWR_S5

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

JLED

1

1

2

2

GND1

3

3

4

4

5

GND2105

6

6

7

7

8

8

ACES_51571-0080N-AT1

ME@

2014/10/22

2014/10/22

2014/10/22

9

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2014/10/22

2014/10/22

2014/10/22

Title

Title

Title

KBD/PWR/IO/LED/TP Conn.

KBD/PWR/IO/LED/TP Conn.

KBD/PWR/IO/LED/TP Conn.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

D

D

D

Date: Sheet of

Date: Sheet of

Date: Sheet

1

Tuesday, May 05, 2015

Tuesday, May 05, 2015

Tuesday, May 05, 2015

Allsparks 5B

Allsparks 5B

Allsparks 5B

36 51

36 51

36 51

of

0.3

0.3

0.3

A

B

C

D

E

+5VALW+5VLP

1 1

SUSP26

SUSP#35,46,47

12

SUSP

+1.8VALW to +1.8VS

+/- 2%

2 2

C141

10U_0805_25V6K

+1.8VALW

1

@

2

5

12

R85
100K_0402_5%

Q39

AON6414AL_DFN8-5

R86
100K_0402_5%

@

13

D

Q6

2

G

S

2N7002KW_SOT323-3

+/- 5% 1.5A

+1.8VS

1
2
3

4

1.8VS_GATE_R 1.8VS_GATE

1

C143

0.01U_0402_25V7K

2

1 2

R106

0_0402_5%

820K_0402_5%

1

C140
10U_0603_6.3V6M

2

12

R107

1 2

R104

0_0402_5%

SUSP#

1

C142
1U_0603_25V6M

2

D

S

1 2

R4 0_0402_5%

1 2

R161 0_0402_5%

1U_0402_6.3V6K

12

R109

470K_0402_5%

13

Q45

2

G

2N7002KW_SOT323-3

1

1

C180

AON6414AL
VDS=30V VGS=20V, ID=50A,
Rds=8mohm @ VGS=10V
VGS(th)=2.5V Max

B+

SUSP

C179
1U_0402_6.3V6K

2

2

12

R108
470_0603_5%

13

D

Q46

2

G

S

2N7002KW_SOT323-3REV@

3VSON

5VSON

@

Load Switch
+5VALW To +5VS
+3VALW To +3VS

+3VALW

1

C224
1U_0402_6.3V6K

2

@

+5VALW

1

C223
1U_0402_6.3V6K

2

@

+5VALW

+0.95VALW to +0.95VS

+/- 1.5%

1

C225

10U_0805_25V6K

@

2

VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=16mohm

+0.95VALW

+3VS, C173 --> 2.74ms
+5VS, C176 --> 2.03ms

U13

1

VIN1_1

2

VIN1_2

3VSON

5VSON

Q41
AON6552_DFN8-5

5

3

EN1

4

BIAS

5

EN2

6

VIN2_1

7

VIN2_2

APL3523AQBI-TRG_TDFN14_2X3

1
2
3

4

0.95VS_GATE_R

1

C228

0.01U_0402_25V7K

2

VOUT1_2
VOUT1_1

VOUT2_2
VOUT2_1

+0.95VS

1 2

R103
0_0402_5%

820K_0402_5%

GPAD

14
13

12

C173 2200P_0402_25V7-K

SS1

11

GND

10

C227 1000P_0402_50V7K

SS2

9
8

15

+/-5% 8.3A

1

C229
10U_0603_6.3V6M

2

12

R99

+3VS_LS

1 2

1 2

+5VS_LS

R105

0_0402_5%

1 2

R102
0_0402_5%

@

1

C226
1U_0603_25V6M

2

1.8VS_GATE

12

0.95VS_GATE

13

D

S

Need Short

J11

@

2

112

JUMP_43X118

112

12

SUSP

+5VS

@

2

B+

J12

JUMP_43X118

Need Short

AON6414AL
VDS=30V VGS=20V, ID=50A,
Rds=8mohm @ VGS=10V
VGS(th)=2.5V Max

R101

470K_0402_5%

@

Q37

2

G

2N7002KW_SOT323-3

@

+3VS

1

C175

0.1U_0402_10V7-K

2

1

C174

@

0.1U_0402_10V7-K

2

Q40

2

G

@

12

R100
470_0603_5%

13

D

S

2N7002KW_SOT323-3REV@

@

+3VALW to +3VALW_APU

3 3

.1U_0402_10V6-K

1 2

PCH_CMOSP35

R87 0_0402_5%@

12

R89

100K_0402_5%

@

+3VALW +3VALW_APU

1

C129

@

2

Need Short

J9

112

JUMP_43X79

LP2301ALT1G_SOT23-3

REV@

S

Q29

G

2

1

2

@

2

Id=3.2A

D

13

C131
.1U_0402_10V6-K

@

1

C130

0.01U_0402_25V7K

@

2

For DisCharge

2N7002KW_SOT323-3

+0.675VS

12

13

D

S

REV@

R88
47_0603_5%

@

Q8

2

G

SUSP

reserve to cut off APU 3VALW when clear CMOS

4 4

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2014/10/22

2014/10/22

2014/10/22

Title

DC V TO VS INTERFACE

DC V TO VS INTERFACE

DC V TO VS INTERFACE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet

Wednesday, April 29, 2015

Allsparks 5B

Allsparks 5B

Allsparks 5B

E

37 51

37 51

37 51

of

0.3

0.3

0.3

5

D D

AC
MODE

A1

VIN

V

PU301

V

BATT
MODE

C C

BATT

B1

4

B2

A2

+3VLP

V

A4

A3

+3VALW

B4

B3

V

B5

V

V

VR_ON

EC

V

10

A2

PU904

V

B+

EC_ON

ON/OFF

NOVO

PU901
+CPU_CORE

V

11 VR_REDY

3

PCH_PWR_EN#

1

DPWROK_EC

4

PCH_RSMRST#

5

PBTN_OUT#

PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#

V

PM_SLP_SUS#

12

PCH_PWROK

13

SYS_PWROK

SYSON

2

2

Q25,+3V_PCH

V

3

+3V_PCH

1

V

V

PM_DRAM_PWRGD

V V

6

PCH

H_CPUPWRGD

CPU_PLTRST#

14

V

15

16

CPU

V

V

V

V

NVDD_PWR_EN

(DIS)

7

+1.35V
PU501

V

Q31

V

+5VS

Vb

DGPU_PWR_EN

(DIS)

Va

+VGA_CORE

V

PU801

DGPU_PWROK

+1.5VS_VGA

V

PU601

VV

B B

SUSP#,SUSP

9

Q32

V

+3VS

PU602

V

+1.5VS

PU502

V

+1.05VSP_VGA

V

PU702

+3VS_VGA

V

Q27

VGA

V

V V

+0.675V

SUS_VCCP

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

8

3

PU701

V

+1.05VS

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/10/22

2014/10/22

2014/10/22

Title

Title

Title

Power sequence Block

Power sequence Block

Power sequence Block

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Wednesday, April 29, 2015

Allsparks 5B

Allsparks 5B

Allsparks 5B

1

38 51

38 51

38 51

0.3

0.3

0.3

5

D D

C C

4

3

2

1

B B

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2014/10/22

2014/10/22

2014/10/22

2

Title

Virtual symbol

Virtual symbol

Virtual symbol

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Allsparks 5B

Allsparks 5B

Allsparks 5B

39 51

39 51

39 51

1

0.3

0.3

0.3

5

4

3

2

1

H1
HOLEA

D D

C C

B B

1

PAD_CT6P0B5P0D2P3

H3
HOLEA

1

PAD_SHAPET9P31X9P55B5P0D2P3

H6
HOLEA

1

PAD_CT7P0D4P0

H13
HOLEA

1

PAD_CT7P0D4P0

H18
HOLEA

1

PAD_C6P0D6P0N

H21
HOLEA

H4
HOLEA

1

PAD_CT9P0D5P0

H7
HOLEA

1

PAD_SHAPET10P65X9P31B5P0D2P3

H14
HOLEA

1

PAD_CT7P0D4P0

H19
HOLEA

1

PAD_C2P3D2P3N

H22
HOLEA

H5
HOLEA

1

PAD_SHAPET8P0X9P5B5P0D2P3

H8
HOLEA

1

PAD_C6P0D3P2

H15
HOLEA

1

PAD_CT6P0D2P6

H20
HOLEA

1

PAD_O2P9X2P3D2P9X2P3N

H23
HOLEA

CHASSIS1_GND

H9
HOLEA

1

PAD_D4P6

H16
HOLEA

1

PAD_CT6P0D2P6

H10
HOLEA

1

PAD_CB5P0D2P3

H17
HOLEA

1

PAD_O2P9X2P3D2P9X2P3N

FD1

1

FIDUCIAL_C40M80

FD4

1

FIDUCIAL_C40M80

H11
HOLEA

1

PAD_CT4P0B5P0D2P3

FD2

1

FIDUCIAL_C40M80

FD5

1

FIDUCIAL_C40M80

H12
HOLEA

1

PAD_CT5P0B8P0D3P3

SH5

1

1

SPRING_FINGER_6.2X1.64

SH6

1

1

SPRING_FINGER_6.2X1.64

SH7

1

1

FD3

1

FIDUCIAL_C40M80

FD6

1

FIDUCIAL_C40M80

ME@

ME@

ME@

SH8

ME@

1

1

SPRING_FINGER_6.2X1.64

SH9

ME@

1

1

SPRING_FINGER_6.2X1.64

SH10

ME@

1

1

1

PAD_C4P0D4P0N

A A

5

1

PAD_C4P0D4P0N

4

1

PAD_C5P0D2P3

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2014/10/22

2014/10/22

2014/10/22

3

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2014/10/22

2014/10/22

2014/10/22

SPRING_FINGER_6.2X1.64

Title

Title

Title

Hole

Hole

Hole

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Wednesday, April 29, 2015

SPRING_FINGER_6.2X1.64

Allsparks 5B

Allsparks 5B

Allsparks 5B

1

40 51

40 51

40 51

0.3

0.3

0.3

5

4

3

2

1

Richtek

+12V/600mA

RT8059GQW

Switch Mode

FOR Subwoofer

D D

B+

Adaptor

20V/135W

Silergy

SYX198CQNC

Converter

FOR SYSTEM

EN PGOOD

PAGE 39

Silergy

SYX198BQNC

Converter

FOR SYSTEM

EN PGOOD

PAGE 39

TI

TPS51716RUKR

S5

WQFN20_3X3

S3

Switch Mode

C C

TI
BQ24780RUYR
QFN24_4X4

Battery Charger

Switch Mode

PAGE 46

SMBus

FOR DDR

Silergy

SYX198DQNC

Converter

FOR SYSTEM

EN PGOOD

PAGE 39

Onsemi

ISL62771HRTZ
TQFN40_5X5

Switch Mode

FOR CPU Core

+5VLP/ 100mA

+5VALW/7A

+3VLP/ 100mA

+3VALW/ 7A

+1.35V/20A

+0.675VS/2A

PGOOD

+0.95VALW/ 7.5A

+APU_GFX/30A/45A

PGOODEN

EN PGOOD

Silergy

SY8868QMC
QFN10_2X2

Switch Mode

EN PGOOD

FOR CPU+GPU

Silergy

SY8868QMC
QFN10_2X2

Switch Mode

FOR VGA

EN PGOOD

ANPEC

APL5325BI-TRG
SOT23-5

LDO

FOR CPU

EN PGOOD

+1.8VALW/3.5A

+0.95VSP_VGA/3.5A

+1.5VSP/200mA

EN

ANPEC

APL5071A
SOT23-5

LDO

FOR CPU

+0.775VALW/200mA

Battery

Li-ion

B B

4S1P/60WH

A A

5

Onsemi

ISL62771HRTZ
TQFN40_5X5

Switch Mode

FOR CPU Core

Interisl

ISL6277AHRZ
QFN48_6X6

Switch Mode

EN

FOR GPU CORE

4

+APU_CORE/39A/55A

+APU_CORE_NB/12A/17A

PGOODEN

PGOOD_NB

+VGA_VDDC/60A

+VGA_VDDCI/10A

PGOOD

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/10/22

2014/10/22

2014/10/22

Title

Power Diagram

Power Diagram

Power Diagram

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Allsparks 5B

Allsparks 5B

Allsparks 5B

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

41 51

41 51

41 51

0.2

0.2

0.2

5

4

3

2

1

VIN

PF101

JDCIN1

1

1
2
3
4

D D

C C

5

CVILU_CI2105P2HR1-NH

ME@

APDINAPDIN

2
3
4
5

12A_24V_F1206HB12V024T/M

1 2

ADAPTER_ID 35,44

12

PC101

EMC_NS@

1000P_0402_50V7K

12

EMC@

@

PJ101

JUMP_43X118

112

470P_0402_50V7K

PC102

2

+3VL

12

12

EMC@

PC104

EMC_NS@

470P_0402_50V7K

1000P_0402_50V7K

PC103

ACES_50273-0020N-001

JRTC1

G1
G2

ME@

RTC_VCC

1

1

2

2

3
4

1 2

1K_0603_5%

RB751V-40_SOD323-2

PR101

PD101

12

PD102

12

RB751V-40_SOD323-2

+VCCRTC

1U_0402_10V6K

PC105

2

1

@

B B

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/10/22

2014/10/22

2014/10/22

Title

DCIN / RTC

DCIN / RTC

DCIN / RTC

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Allsparks 5B

Allsparks 5B

Allsparks 5B

1

42 51

42 51

42 51

of

0.2

0.2

0.2

5

JBATT1

D D

C C

10
11

12
GND1
GND2

GND3

GND4

SUYIN_125022HB012M200ZL

VMB2

1

1

2

2

3

3

4

4

EC_SMCA

5

5

EC_SMDA

6

6

7

7

8

8

9

9

10
11
12
13
14
15
16

12

12

PR201

100_0402_1%

BATT_TEMP_IN

PF201

15A_24V_F1206HB15V024T/M

1 2

PR202

100_0402_1%

PR208

1 2

100K_0402_1%

PR213

1 2

10K_0402_5%

EMC@

VMB

PC201

+3VALW

HCB2012KF-121T50_0805

1 2

HCB2012KF-121T50_0805

1 2

HCB2012KF-121T50_0805

1 2

12

1000P_0402_50V7K

EC_SMB_CK1 35,44

EC_SMB_DA1 35,44

BATT_TEMP 35,44

4

PH201 under CPU botten side :

PL201

PL202

PL203

EMC@

EMC@

EMC@

CPU thermal protection at 92+-3 degree C
Recovery at 56 +-3 degree C

BATT+

12

PC202

0.01U_0402_25V7K

EMC@

+5VLP

H_PROCHOT#6,35

2N7002KW_SOT323-3

PQ201

@

13

D

S

A/D

PROCHOT#35

PC203

0.1U_0603_25V7-M

@

1 2

+3VS

1 2

ADP_OCP_1

2

G

PR215

1 2

0_0402_5% @

3

PR206
100K_0402_1%

@

OTP_N_003

@

1 2

0_0402_5%

PR214

@

PU201

1

VCC

TMSNS1

2

GND

RHYST1

3

OT1

TMSNS2

4

RHYST2

OT2

G718TM1U_SOT23-8

2

For KB930 --> Keep PU1 circuit
(Vth = 0.825V)

For KB9012 (Red square) --> Remove PU201 circuit, but keep PR206
PH201, PR205,PR211,PQ201,PR208,PR212

NTC_V_1

10K_0402_1%

10K_0402_1%

PR207

+3VALW

12

PR204

13.7K_0402_1%

12

@

PR212
0_0402_5%

1 2

NTC_V

12

12

35

ADP_I35,44

8

OTP_N_002

7

6

ADP_OCP_2

5

MAINPWON 35,45

PR203

4.42K_0402_1%

@

Turbo_V_1

1 2

PR209

57.6K_0402_1%

1 2

@

PR210

PR211

0_0402_5%

1 2

1 2

@

@

35,44

Turbo_V

PR205

21.5K_0402_1%

@

PH201

100K_0402_1%_TSM0B104F4251RZ

1

B B

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/10/22

2014/10/22

2014/10/22

Title

BATTERY CONN/OTP

BATTERY CONN/OTP

BATTERY CONN/OTP

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Allsparks 5B

Allsparks 5B

Allsparks 5B

1

43 51

43 51

43 51

0.2

0.2

0.2

5

4

3

2

1

12

ADP_I35,43

BATT_I35

TURBO_V35,43

PQ301
AON6414AL_DFN8-5

5

4

12

12

PR323 0_0402_5%

VIN

12

PR331
1M_0402_5%

@

1
2
3

PR302

4.7_0603_5%

PR307

4.02K_0603_1%

1 2

P2

12

PC302

0.022U_0402_25V7K

2N7002WT1G

S

1M_0402_5%

PR304

@

12

PR308

PR312

4.02K_0603_1%

64.9K_0603_1%

1 2

PC314

1 2

0.1U_0402_25V6

BQ24780_VDD

ACIN35

1 2

1 2

PC323 100P_0402_50V8J

PC322 100P_0402_50V8J

VIN

PC301

12

PR330
750_0603_1%

470P_0402_50V7K

D D

C C

B B

+3VALW

AON6414AL_DFN8-5

1
2
3

4

PQ304

D

13

@

G

2

12

1M_0402_5%

PR305

@

@

EC_SMB_DA135,43

EC_SMB_CK135,43

1 2

PC324 100P_0402_50V8J

PQ302

P3

5

PC303

1 2

12

VIN

12

PR310
432K_0603_1%

PR315 10K_0402_5%@

PR316 100K_0402_5%@

1 2

PR317 0_0402_5%

1 2

PR319 0_0402_5%

1 2

PR320 0_0402_5%

1 2

PR321 0_0402_5%

1 2

PR322 0_0402_5%

VR_HOT#35,50,51

+3VALW

143K_0402_1%

PC325

0.1U_0402_25V6

JUMP_43X118

EMC_NS@

10U_0805_25V6K

12

12

1 2

PR328

@

PJ301

2

112

PC307

1U_0603_25V6K

VIN

PD301

1 2

RB751V-40_SOD323-2

PC312

12

1U_0603_25V6K

12

PC304

1 2

10U_0805_25V6K

12

B+

PD302

1 2

PR311
10_1206_5%

1 2

PR327
0_0402_5%

1 2

12

PR332
100K_0402_1%

28

11

12

10

13

14

21

PR301

0.01_1206_1%

1

2

EMC_NS@

0.1U_0402_25V6

PC305

1 2

RB751V-40_SOD323-2

ACP

2

ACP

VCC

6

ACDET

BQ24780RUYR_QFN24_4X4

3

CMSRC

4

ACDRV

5

ACOK

SDA

PU301

SCL

7

IADP

8

IDCHG

9

PMON

PROCHOT#

CMPIN

CMPOUT

ILIM

1 2

32.4K_0402_1%
PR329

4

3

5

12

PC306

0.1U_0402_25V6

BQ24780_BATDRV

499K_0402_1%

PR303

12

4

PC308

0.01U_0402_25V7K

1 2

321

B+

PQ303
AON6414AL_DFN8-5

B+

ACN

BQ24780_VDD

1

ACN

24

REGN

25

BTST

26

HIDRV

27

PHASE

23

LODRV

22

GND

29

PAD

18

BATDRV

17

BATSRC

20

SRP

19

SRN

TB_STAT#

BATPRES#

16

15

PC313

2.2U_0603_10V6-K

1 2

PR313

BST_CHG

1 2

2.2_0603_5%

DH_CHG

LX_CHG

DL_CHG

BQ24780_BATDRV

PR324

PR325

PR326

BATT_TEMP 35,43

PC315

12

0.047U_0603_16V7K

12

10_0603_5%

12

10_0603_5%

12

10_0603_5%

4

4

12

5

PQ306

AON7408L_DFN8-5

321

5

PQ307

AON7408L_DFN8-5

321

PC321

0.1U_0402_25V6

1 2

EMC_NS@

4.7UH_PCMB063T-4R7MS_5.5A_20%
PL301

1 2

12

PR318

2.2_0805_5%

EMC_NS@

12

PC318

1200P_0402_50V7-K

EMC_NS@

PC310

PC309

1 2

1 2

2200P_0402_25V7-K

CHG

SRP

SRN

PC311

10U_0805_25V6K

10U_0805_25V6K

PR314

0.01_1206_1%

1

2

12

PC319

0.1U_0402_25V6

check BATT+ real current

4

3

PC316

1 2

1 2

PC317

10U_0805_25V6K

10U_0805_25V6K

12

PC320

0.1U_0402_25V6

BATT+

61

PR333

0_0402_5%

12

PC326

PC327

680P_0402_50V7K

@

A A

DSPQ308A

1 2

1

12

0.1U_0402_25V6

2

ADAPTER_ID_ON#_G

2

G

@

2N7002KDWH_SOT363-6

ADAPTER_ID 35,42

1

PD303
AZ5123-01F.R7GR_DFN1006P2X2

2

5

PR334
1M_0402_5%

12

@

34

D

5

G

@

S

PQ308B

2N7002KDWH_SOT363-6

ADAPTER_ID_ON# 35

4

IchargeLIM=7A
IDischargeLIM=10A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/10/22

2014/10/22

2014/10/22

Title

Title

Title

CHARGER

CHARGER

CHARGER

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Allsparks 5B

Allsparks 5B

Allsparks 5B

44 51

44 51

44 51

1

0.2

0.2

0.2

5

4

3

2

1

B+

@

PJ401

2

112

JUMP_43X79

D D

EC_ON_3V35

12

2

2N7002KW_SOT323-3

PR405

0_0402_5%

PQ401

G

@

MAINPWON35,43

PR408

100K_0402_5%

@

C C

@

PR402

0_0402_5%

12

1 2

13

D

S

12

PR407
330_0603_5%

@

12

12

EC_ON_R

PC411

2.2U_0603_10V7K

@

PC401

1.5A

EMC@

0.1U_0402_25V6

12

PC402

PR403

0_0402_5%

B+

10U_0805_25V6K

12

12

PC428

PR422

0_0603_5%

@

12

PR401

1M_0402_5%

10U_0805_25V6K

12

12

@

PC408

PR406

1M_0402_5%

0.1U_0402_25V6

12

12

@

PC426

10U_0805_25V6K

+3V_VIN

+3VALW_FB

PU401

7

EN2

8

IN

9

GND

1

EN1

3

FB

8

7

6

5

2

PG

6

BS

10

LX

4

OUT

SYX198BQNC_QFN10_3X3

5

LDO

PU403
APL5155KAI-TRG_SO8

VIN

VOUT

GND

NC1

NC3

NC2

EN

NC/ADJ

Thermal_Pad

9

@

+3V_PWRGD

+3VBS

+3VLX

+3VALW_P+3VALW_EN

100mA

1

2

3

4

1 2

0.1U_0603_25V7-M

+3VLP

12

PC409

4.7U_0603_6.3V6K

100mA

PC403

1

@

PTP401
PAD

PC412

1 2

0.01U_0402_25V7K

12

PR418

@

16.5K_0402_1%

12

PR419

@

10K_0402_1%

PL401

1 2

2.2UH_PCMB063T-2R2MS_8A_20%

12

PR404

2.2_0805_5%

EMC_NS@

12

PC410

1200P_0402_50V7-K

EMC_NS@

12

PC427

@

10U_0805_25V6K

1 2

1K_0402_1%

PR421

0_0603_5%

@

PR409

12

12

PC404

+3VL

150mA LDO ,FB=1.24V ,Vout=3.3V

+3VALW

@

7A

+3VALW_P

12

12

22U_0805_6.3V6M

12

PC406

PC405

PC407

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

+3VLP

PJ402

2

JUMP_43X79

@

PJ403

2

JUMP_43X39

112

+3VL

112

+3VALW
TDC :7A
OCP :9A
Tolerance: +/-5%

+3VALW

PR410
100K_0402_5%

@

1 2

@

12

12

PC418

22U_0805_6.3V6M

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

12

12

PC419

PC421

PC420

22U_0805_6.3V6M

22U_0805_6.3V6M

2

22U_0805_6.3V6M

12

@

+5VALW_P

12

@

PC430

22U_0805_6.3V6M

2014/10/22

2014/10/22

2014/10/22

+5VALW

+5VALW

PJ405

2

112

@

JUMP_43X79

PC429

22U_0805_6.3V6M

Title

Title

Title

PWR_3VALW/5VALW

PWR_3VALW/5VALW

PWR_3VALW/5VALW

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

TDC :7A
OCP :9A
Tolerance: +/-5%

Allsparks 5B

Allsparks 5B

Allsparks 5B

1

45 51

45 51

45 51

0.2

0.2

0.2

PL402

2014/10/22

2014/10/22

2014/10/22

PR411

1 2

0_0402_5%

PR412

1 2

0_0402_5%

@

B B

B+

PR420

EC_ON_5V35

EC_ON_R

A A

5

0_0402_5%

PR413

0_0402_5%

@

12

12

@

PJ404

2

JUMP_43X79

@

0.1U_0402_25V6

2.5A

112

12

PC413

12

PC422

4

12

12

PC415

PC414

EMC@

0.1U_0402_25V6
10U_0805_25V6K

12

PR416

1M_0402_5%

PC417

1 2

10U_0805_25V6K

1U_0603_25V6M

+5VFB

+5V_VIN

+5VVCC

PU402

8

IN

9

GND

5

VCC

1

EN

3

FB

SYX198CQNC_QFN10_3X3

+5V_PWRGD

2

PG

BS

LX

OUT

LDO

change to 1000pf for usb switch on siv
6800pf soft start 2ms
47nf soft start 7ms

PC416

1 2

6

+5VBS

0.1U_0603_25V7-M

10

+5VLX

PR414

+5VALW_OUT+5VALW_EN

4

7

1 2

10_0402_1%

100mA

change for EE's request

+5VLP

12

PC423

4.7U_0603_6.3V6K

PC425

1 2

1000P_0402_50V7K

3

1 2

1K_0402_1%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

+3V_PWRGD

2.2UH_PCMB063T-2R2MS_8A_20%

12

+5VALW_P

12

PR417

1 2

PR415

2.2_0805_5%

EMC_NS@

PC424

1200P_0402_50V7-K

EMC_NS@

A

1 1

1k for 500K
12k for 670K

+3VALW

1.35V_GND 1.35V_GND

PR502

PR504

1K_0402_1%

1 2

10K_0402_1%

20

PU501

21

PAD

1

PGOOD

VTTSNS

2 2

+0.675VSP

2A

@

+VTT_REFP

PJ504

2

112

JUMP_43X79

@

3 3

PC507

12

22U_0805_6.3V6M

+1.35V

12

PC508

22U_0805_6.3V6M

1U_0402_6.3V6K

+0.675VS+0.675VSP

PC512

2A

12

1.35V_GND

PC514

0.1U_0402_25V6

1.35V_GND

PC515

0.01U_0402_25V7K

2

VLDOIN

3

VTT

TPS51716RUKR_WQFN20_3X3

4

VTTGND

5

VTTREF

VREF

6

VREF

1 2

30K_0402_1%

1 2

12

1.35V_GND 1.35V_GND

12

19

MODE

GND

7

PR509

1.35V_GND

B

12

PR505

78.7K_0402_1%

18

TRIP

REFIN

8

REFIN

12

PR510

93.1K_0402_1%

12

PC501

0.1U_0402_10V7K

S3_1.35V

S5_1.35V

16

17

S5

S3

VBST

DRVH

DRVL

PGND

VDDQSNS

9

10

@

PR501 0_0402_5%

1 2

PR503 0_0402_5%

12

12

PC502 0.1U_0402_10V7K

@

0_0603_5%

BST_1.35V

15

1 2

PR507 0_0402_5%

14

13

SW

12

V5IN

11

SUSP# 35,37,47

SYSON 35

PC506

PR506

0.1U_0603_25V7-M

12

UG_1.35V

12

LX_1.35V

+5VALW

12

PC510
1U_0603_25V6M

LG_1.35V

4

4

2A

1.35V_B+

12

PC503

EMC_NS@

5

321

PC504

0.1U_0402_25V6

PQ501

AON6372_DFN8-5

0.47UH_PCMC063T-R47MN_17.5A_20%

12

1.35V_SN

PQ502

AON6764_DFN

12

123 5

C

12

12

PC505

10U_0805_25V6K

10U_0805_25V6K

PL501

1 2

PR508

4.7_1206_5%

EMC_NS@

PC513
1000P_0402_50V9-J

EMC_NS@

PJ501

2

JUMP_43X79

112

B+

@

1

+

PC516

PC509

2

390U_2.5V_M

ESR=10mohm

D

+1.35V
TDC :10A + VRAM 12A (16A)
OCP :29~36A
Tolerance: +/-3%

PJ502

2

112

JUMP_43X118@

PJ503

@

2

112

1

1

+

2

390U_2.5V_M

12

+

PC521

2

PC519

330U_D2_2V_Y

@

JUMP_43X118

12

PC520

@

22U_0805_6.3V6M

22U_0805_6.3V6M

+1.35V

PJ505

1 2

JUMPER

1.35V_GND

4 4

A

@

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

C

2014/10/22

2014/10/22

2014/10/22

Title

1.35VS/+0.675VS

1.35VS/+0.675VS

1.35VS/+0.675VS

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Allsparks 5B

Allsparks 5B

Allsparks 5B

D

46 51

46 51

46 51

0.2

0.2

0.2

A

+5VALW

12

PC622

1 1

+3VALW

SUSP#35,37,46

2 2

PR602

1 2

0_0402_5%

+1.8VALW

50mA

2

PJ601

JUMP_43X39

@

EN_1_5VSP

12

1 2

112

PC601

PC604

.1U_0402_10V6-K

@

50mA

2

PR605
0_0402_5%

12

4.7U_0603_6.3V6K

PJ603

112

JUMP_43X39

@

PC605

EN_0_775VSPEC_APU_ALWEN

12

PC608

.1U_0402_10V6-K

@

1U_0603_25V6M

12

PR618
100K_0402_5%

@

+3VS

3

12

4.7U_0603_6.3V6K

VIN

2

GND

1

SHDN

B

PU601

6

VCNTL

5

VIN1

VOUT1

9

VIN2

VOUT2

8

EN

7

POK

GND

G971LADJF11U_SO8

1

VFB=0.8V

PU602

4

VOUT

5

SET

APL5701-ABI-TRG_SOT23-5

VFB=0.6V

C

Vout=1.516V
TDC :350mA
Tolerance: +/-75mv

+1.5VSP +1.5VS

50mA

12

PC603
10U_0603_6.3V6M

PJ602

2

JUMP_43X39

112

@

3
4

2

FB

12

12

PR604

2.94K_0402_1%

PR607

10K_0402_1%

12

12

PR601

21.5K_0402_1%

12

PR603

24K_0402_1%

+0.775VALWP +0.775VALW

200mA

PJ604

2

JUMP_43X39

12

PC606
220P_0402_50V7K

@

PC607
10U_0603_6.3V6M

12

PC602
220P_0402_50V7K

@

Vout=0.7764V
TDC :200mAZ
Tolerance: +/-50mv

112

@

D

+1.05VALW
TDC :7.5A
OCP :12A
Tolerance: +/-50mv

0.95VLAW change to 1.05VALW on SIV

+1.05VALWP

PJ606

2

JUMP_43X118

@

PC617

22U_0805_6.3V6M

Title

Title

2014/10/22

2014/10/22

2014/10/22

Title

+1.35VS_VGA/+1.5VS

+1.35VS_VGA/+1.5VS

+1.35VS_VGA/+1.5VS

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

+0.95VALW

112

Allsparks 5B

Allsparks 5B

Allsparks 5B

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

D

47 51

47 51

47 51

PJ605

2

JUMP_43X79

@

+3VALW

112

EMC@

0.95VS_EN

1 2

PR611

100K_0402_5%@

PU603

B+_0.95VS

8

12

12

12

PC610

PC611

0.1U_0402_25V6
10U_0805_25V6K

0.95VS_ILNT

IN

9

GND

PC613

3

10U_0805_25V6K

ILMT

2

PG

PR616
10K_0402_5%

1 2

+3VALW

BYP

LDO

SYX198DQNC_QFN10_3X3

4.7U_0603_6.3V6K

B

1

EN

0.95VS_BS

6

BS

0.95VS_LX

10

LX

4

FB

7

0.95VS_LDO

5

PC619

0_0603_5%

1 2

12

PR610

12

PC618

4.7U_0603_6.3V6K

PC612

0.1U_0603_25V7-M

1 2

+3VALW

PL601

0.68UH_PCMB063T-R68MS_16A_+-20%

1 2

12

PR612

4.7_0603_5%

EMC_NS@

12

PC621

12

330P_0402_50V8J

PC620

680P_0402_50V7K

EMC_NS@

PR615

1K_0402_1%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1 2

0.95VS_FB

2014/10/22

2014/10/22

2014/10/22

C

12

PR614
27K_0402_1%

change to 27K for EE's request

12

PR617

34K_0402_1%

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

12

12

PC614

22U_0805_6.3V6M

Deciphered Date

Deciphered Date

Deciphered Date

12

12

PC615

PC616

22U_0805_6.3V6M

22U_0805_6.3V6M

EC_APU_ALWEN

EC_APU_ALWEN35,48

3 3

1 2

PR609

0_0402_5%

12

PC609
.1U_0402_10V6-K

@

B+

4 4

A

0.2

0.2

0.2

5

4

3

2

Vout =0.954V
TDC :4.5A
OCP :6A
Tolerance: +/-3%

1

+3VALW

GPU 0.95VGS Current 4.72A

PR710

1

4

8

PU702

VIN

EN

SS

1_8VS_LX

10K_0402_5%

1 2

0.95VGS_PG

9

2

LX1

PG

5

LX2

6

LX3

10

OUT

7

FB

GND

3

SY8868QMC_QFN10_2X2

1_8VS_FB

12

PR723
100K_0402_1%

0.95VGS_LX

0.95VGS_FB

12

PR716
100K_0402_1%

PL703

1UH_PH041H-1R0MS_3.8A_20%

1 2

12

PR718

4.7_0603_5%

EMC_NS@

12

PC727
680P_0402_50V7K

EMC_NS@

PL702

0.68UH_PCMB063T-R68MS_16A_+-20%

1 2

12

PR711

4.7_0603_5%

EMC_NS@

12

PC717
680P_0402_50V7K

EMC_NS@

12

+0.95VSP_VGA

PJ704

2

12

12

12

PC713

PC714

22U_0805_6.3V6M

22U_0805_6.3V6M

12

@

PC715

22U_0805_6.3V6M

PR715

59K_0402_1%

1 2

PC719

220P_0402_50V7K

12

@

PC731

PC730

22U_0805_6.3V6M

22U_0805_6.3V6M

12

JUMP_43X79

@

+1.8VALW

PJ706

+1.8VSP

12

12

PC723

PC725

PC724

22U_0805_6.3V6M

22U_0805_6.3V6M

PR722

200K_0402_1%

1 2

PC729

47P_0402_50V8J

22U_0805_6.3V6M

12

2

JUMP_43X79

@

112

+0.95VGS

112

Vout=1.8V
TDC :3.8A
OCP :6A
Tolerance: +/-3%

+1.8VALW

TDC :2.3A + GPU MAX 1.5A

D D

+3VALW

PR714

PXS_PWREN

PR721

0_0402_5%

1 2

56K_0402_1%

PJ705

2

JUMP_43X79

@

112

PXS_PWREN7,19,49

C C

+5VALW

EC_APU_ALWEN35,47

B B

EC_APU_ALWEN

1 2

EMC_NS@

EN_1.8VSP

1M_0402_5%

PR720

2

12

PJ703

JUMP_43X79

@

1_8VS_PVIN

12

PC720

0.1U_0402_10V6-K

1 2

112

EMC_NS@

EN_0.95VGS

1M_0402_5%

12

PC721

22U_0805_6.3V6M

12

PC726

.1U_0402_10V6-K

@

PR713

0.95VGS_PVIN

12

12

12

PC710

PC711

PC712

22U_0805_6.3V6M

12

PC716

.1U_0402_10V6-K

22U_0805_6.3V6M

PC718

0.01U_0402_25V7K

1 2

0.1U_0402_10V6-K

1 2

+3VALW

PR717
10K_0402_5%

1 2

1_8VS_PG

PC722

22U_0805_6.3V6M

1 2

9

PU703

1

VIN

4

EN

8

SS

3

PC728

0.01U_0402_25V7K

2

LX1

PG

5

LX2

6

LX3

10

OUT

7

FB

GND

SY8868QMC_QFN10_2X2

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/10/22

2014/10/22

2014/10/22

Title

+1.05VS/+1.05VS_VGA

+1.05VS/+1.05VS_VGA

+1.05VS/+1.05VS_VGA

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Allsparks 5B

Allsparks 5B

Allsparks 5B

1

48 51

48 51

48 51

0.2

0.2

0.2

5

6277A_RTN

1 2

GPU_VSSCI_SENSE19

D D

+VDDIO_GPU

12

12

@

PC937

PC949

1U_0402_6.3V6K

.1U_0402_10V6-K

C C

PRE-PWROK METAL VID CODES

SVDSVC

Boot Voltage

00

1.1V

0

1.0V(Default)

110 0.9V

11

0.8V

PR952

BACO_VDDC_1.35V

5

1 2

56K_0402_1%

NOBACO@

1 2

PD702

RB751V-40_SOD323-2

PR1168

0_0402_5%

PXS_PWREN7,19,48

B B

A A

BACO_VDDC_1.35V19

PR924

1 2

10K_0402_1%

12

PR929

1 2

130K_0402_1%

GPU_EN_R

12

@

PC946

12

.1U_0402_10V6-K

BACO@

+GPU_VDDCI

GPU_VDDCI_SENSE19

VSUMP_GPU_NB

2.61K_0402_1%

PH901

10K_0402_NTC

VSUMN_GPU_NB

PR922

1 2

47K_0402_1%

1 2

470K_0402_3%_NCP15WM474E03RC

GPU_VR_HOT#35

PC920

0.1U_0402_25V6- K

VGA_PWROK15

+5VS

PR953 10K_0402_5%@

ISEN3_GPU

ISEN2_GPU

ISEN1_GPU

PR917

0_0402_5%

@

PR920

100_0402_1%

1 2

PR902

100_0402_1%

1 2

PR907

0_0402_5%

12

PR913

1 2

1000P_0402_50V7K

PH902

1 2

+3VGS

+3VGS

12

VSUM-_GPU

VSUM+_GPU

12

12

11K_0402_1%

PR916

PC914

PR930

2.2K_0402_5%

PR975

1 2

1.91K_0402_1%

12

12

PC912

0.033U_0402_16 V7K

change on SIV

1 2

6277A_VDD

GPU_SVC16

GPU_SVD16

GPU_SVT16

GPU_EN_R

12

PR941

12

PC941

0.22U_0402_10V6 K

12

1 2

12

330P_0402_50V8J

@

12

0.22U_0402_10V6K

+VDDIO_GPU

1 2

130K_0402_1%

SDV

PC942

0.22U_0402_10V6 K

PR957

2.61K_0402_1%

PH904

10K_0402_NTC

PC936

PC913

0.033U_0402_16 V7K

1 2

12

12

1 2

PC935

0.1U_0402_25V6

change on SIV

1 2

1K_0402_1%

@

PC915

PC930

12

0.1U_0402_25V6- K

PC943

0.22U_0402_10V6 K

PR961

11K_0402_1%

@

1000P_0402_50V7K

PR918

PR944

10K_0402_1%

PC901

12

@

680P_0402_50V7K

1 2

1K_0402_1%

Rdroop: change on SIV

1 2

PC907

1000P_0402_50V7K

change on SIV

1 2

@

PC909

12

@

PR921

10K_0402_5%

12

PR923

10K_0402_5%

IMON_GPU_NB

12

PR926 0_0402_5%

12

PR927 0_0402_5%

12

PR931 0_0402_5%

12

PR932 0_0402_5%

12

PR934 0_0402_5%

12

PR936 0_0402_5%

1 2

PR1042

47K_0402_1%

1 2

PH903

470K_0402_3%_NCP15WM474E03RC

1 2

PC945

0.1U_0402_25V6

12

12

PC961

PC960

0.1U_0402_25V7- K

0.22U_0402_16V6 -K

change on SIV

PR903

PR985

1 2

10K_0402_5%

GPU_SVC_P

GPU_SVD_P

GPU_SVT_P

PR901

2K_0402_1%

1 2

10K_0402_5%

4

PR908
499_0402_1%

change on SIV

PR958

4

12

@

1 2

62K_0402_1%

change on SIV

PU902

ISEN2_NB1VSEN_NB

2

NTC_NB

3

IMON_NB

4

SVC

5

VR_HOT_L

6

SVD

7

VDDIO

8

SVT

9

ENABLE

10

PWROK

11

IMON

12

NTC

49

PAD

PR955

1 2

845_0402_1%

12

@

0.22U_0402_10V6K

PR904

1 2

PC908

56P_0402_50V8J

48

ISEN1_NB

ISEN3

13

1 2

PC950

1 2

1 2

PR905

PC906

34K_0402_1%

150P_0402_50V8-J

set FSW=300K on SIV

change on SIT

+3VS

12

PR919

PR940

@

10K_0402_5%

1 2

45

44

43

42

41

47

46

FB_NB

FCCM_NB

COMP_NB

ISUMP_NB

ISUMN_NB

PGOOD_NB

ISL6277AHRZ_QFN48_6X6

RTN

ISEN214ISEN115ISUMN17VSEN18ISUMP16FB220FB21COMP22PGOOD

19

6277A_FB

6277A_RTN

6277A_VSEN

6277A_FB2

6277A_ISUMN

1 2

100P_0402_50V8J

12

PC951

@

330P_0402_50V8J

12

PC978

12

PC963

1000P_0402_50V7K

@

95.3K_0402_1%

set FSW=300K on SIV

40

39

38

LGATEX

PHASEX

PWM2_NB

23

6277A_COMP

PC947

1 2

PR959

2K_0402_1%

Rdroop: change on SIV

330P_0402_50V8J

37

UGATEX

BOOTX

BOOT2

UGATE2

PHASE2

LGATE2

PWM_Y

LGATE1

PHASE1

UGATE1

BOOT1

24

1 2

100_0402_1%

0_0402_5%

0_0402_5%

1 2

100_0402_1%

LGATE_GPU_NB1

PHASE_GPU_NB1

UGATE_GPU_NB1

VIN

VDDP

VDD

1 2

PR954

499_0402_1%

PR965

PR967

PR969

PR974

36

35

34

33

32

31

30

29

28

27

26

25

+3VGS

12

12

+5VS

+5VALW

BOOT_GPU_NB1

BOOT2_GPU

UGATE2_GPU

PHASE2_GPU

LGATE2_GPU

6277A_VDDP

6277A_VDD

PWM_6277A_GPU

12

PR947

LGATE1_GPU

PHASE1_GPU

UGATE1_GPU

BOOT1_GPU

10K_0402_5%

1 2

PR960

150K_0402_1%

change on SIT

PR964

2K_0402_1%

+GPU_VDDC

10P_0402_50V8J

PR994

12

@

0_0603_5%

PR906 0_0603_5%

12

PR909

0_0402_5%

6277A_VDD

1 2

PC944

1 2

PC948

47P_0402_50V8J

1 2

PC957

150P_0402_50V8-J

12

@

680P_0402_50V7K

GPU_VDDC_SENSE 19

GPU_VSSC_SENSE 19

1 2

PC902

0.22U_0603_25V7K

12

PWM_6277A_GPU

GPU_VDDC_B+

PR925

0_0402_5%

12

12

PC919

0.22U_0603_25V7K

1 2

PR935

1_0603_5%

PC922

1 2

1U_0603_6.3V7-K

VR_VGA_PWRGD 7,15

1 2

@

PR956

34K_0402_1%

1 2

@

PC959

PU901

6

UGATE1VCC

7

FCCM

BOOT

3

PWM

PHASE

4

LGATE

GND

9

TP

ISL6208BCRZ-T_QFN8_2X2

PC921

1 2

3

2

1

GPU_VDDC_B+

PJ901

2

112

@

B+

JUMP_43X118

12

12

12

PC905

0.1U_0402_25V6

PC904

EMC_PXNS@

1 2

PR980

2.2_0603_5%

4

4

123 5

123 5

1 2

PC923

0.22U_0603_16V7K

1 2

PC958

0.22U_0603_16V7K

0.22U_0603_16V7K

PC903

PQ901

10U_0805_25V6K

10U_0805_25V6K

AON6372_DFN

1 2

PL901

0.36UH +-20% PCME064T-R36MS1R405 24A

PR911

ISEN3_GPU

4.7_0603_5%

EMC_PXNS@

PQ902

AON6764_DFN

1 2

12

PC911
680P_0402_50V7K

EMC_PXNS@

VSUM+_GPU

VSUM-_GPU

GPU_VDDC_B+

12

12

12

PC918

0.1U_0402_25V6

PC917

PC916

EMC_PXNS@

10U_0805_25V6K

4

4

10U_0805_25V6K

PQ903

AON6372_DFN

123 5

5

PR937

4.7_0603_5%

4

EMC_PXNS@

1 2

PQ910

PQ904

123 5

AON6764_DFN

AON6764_DFN

@

321

12

PC931
680P_0402_50V7K

EMC_PXNS@

GPU_VDDC_B+

12

12

12

PC940

0.1U_0402_25V6

EMC_PXNS@

PC938

PC939

10U_0805_25V6K

4

PQ905

AON6372_DFN

123 5

4

PQ906

AON6764_DFN

123 5

@

10U_0805_25V6K

5

PR963

4.7_0603_5%

EMC_PXNS@

1 2

4

PQ1107

AON6764_DFN

12

PC962

321

680P_0402_50V7K

EMC_PXNS@

GPU_VDDC_B+

12

12

12

PC966

0.1U_0402_25V6

EMC_PXNS@

PC964

PQ907

4

PQ908

1 2

PC967

4

PC965

AON6372_DFN

10U_0805_25V6K

10U_0805_25V6K

123 5

PR981

AON6764_DFN

4.7_0603_5%

EMC_PXNS@

1 2

12

PC974
680P_0402_50V7K

123 5

EMC_PXNS@

VSUMP_GPU_NB

VSUMN_GPU_NB

0.36UH_PCMB063T-R36MS_20A_20%

1 2

PR982

3.65K_0402_1%

1 2

PR984

10_0402_1%

1 2

PR912

10K_0402_1%

1 2

PR914

3.65K_0402_1%

1 2

PR915

10_0402_1%

ISEN2_GPU

VSUM+_GPU

VSUM-_GPU

ISEN1_GPU

VSUM+_GPU

VSUM-_GPU

1 2

change on SIV

change on SIV

GPU_VDDC
FSW=300KHz
Slew rate:12.5mv/us
TDC=50A
OCP=90A
Load Line=1.5mohm
Ripple:+/-20mv
Max AC :VID_VDDC +80mv
MIN AC: VID_VDDC -50mv

1 2

PL902

0.36UH +-20% PCME064T-R36MS1R405 24A

change on SIV

1 2

PR942

10K_0402_1%

1 2

PR943

3.65K_0402_1%

1 2

PR945

10_0402_1%

1 2

PL903

0.36UH +-20% PCME064T-R36MS1R405 24A

change on SIV

PR966

10K_0402_1%

1 2

PR968

3.65K_0402_1%

1 2

PR970

10_0402_1%

1 2

+GPU_VDDCI

PL904

ESR=9mohm

2

1

1

12

12

+

+

PC968

PC969

PC970

2

2

560U_2.5V_M

330U_D2_2V_Y

22U_0805_6.3V6M

ESR=10mohm

1

1

1

+

+

+

PC924

PC926

PC927

2

2

2

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y

ESR=9mohm

12

12

12

12

PC952

PC932

PC934

PC933

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

GPU_VDDCI
Vboot=TBD
FSW=400KHz
Slew rate :12.5mv/us
TDC=10A
OCP=24A
Disable Load Line
Ripple:+/-20mv
AC: VID_VDDCI+/-100mv

12

12

PC971

PC973

PC972

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

22U_0805_6.3V6M

1

+

2

12

PC925

330U_D2_2V_Y

PC953

22U_0805_6.3V6M

2014/10/22

2014/10/22

2014/10/22

1

+

2

12

1

+

PC929

PC928

2

330U_D2_2V_Y

330U_D2_2V_Y

PC954

22U_0805_6.3V6M

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

+GPU_VDDC

1

+

PC955

2

@

Deciphered Date

Deciphered Date

Deciphered Date

330U_D2_2V_Y

Title

Title

Title

2014/10/22

2014/10/22

2014/10/22

PWR_CPU Core

PWR_CPU Core

PWR_CPU Core

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Allsparks 5B

Allsparks 5B

Allsparks 5B

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

49 51

49 51

49 51

UGATE3_GPU

BOOT3_GPU

2

PHASE3_GPU

8

5

PR933

0_0603_5%

1 2

+5VALW

PR928

0_0603_5%

1 2

+5VS

@

1U_0603_6.3V7-K

BOOT3_GPU

LGATE3_GPU

3

1 2

2.2_0603_5%

BOOT3_GPU_R

1 2

PR910

PC910

0.22U_0603_16V7K

UGATE2_GPU

PHASE2_GPU

BOOT2_GPU

1 2

PR939

2.2_0603_5%

LGATE2_GPU

UGATE1_GPU

PHASE1_GPU

BOOT1_GPU

1 2

PR962

2.2_0603_5%

LGATE1_GPU

UGATE_GPU_NB1

PHASE_GPU_NB1

BOOT_GPU_NB1

LGATE_GPU_NB1

0.2

0.2

0.2

5

+1.8VS

4

3

2

1

PR868

1K_0402_1%

220_0402_5%

12

PR866

@

12

PR865

@

VR_HOT#35,44,51

1 2

PR1017

0_0402_5%

5

12

1K_0402_1%

@

220_0402_5%

12

PR1027

10K_0402_5%

PR1029

10K_0402_5%

VSUM-

VSUM+

PR867

PR863

@

1K_0402_1%

220_0402_5%

+1.8VS

12

PC1012
.1U_0402_10V6-K

@

12
@

12
@

PH1001

12

12

PR1033

2.61K_0402_1%

1 2

10K_0402_1%_TSM0A103F34D1RZ

+1.8VS

GFX_B+

12

12

@

PC1005

PC1004

1U_0402_6.3V6K

.1U_0402_10V6-K

12

12

PR1003

33K_0402_5%

set FSW=300K on SIV

33

34

35

36

COMP_NB

LGATE_NB

PGOOD_NB

RTN17ISUMN15ISEN1

VSEN

16

62771_FB

GFX_VSS_SEN

GFX_CORE_SEN

100P_0402_50V8J

12

PC1028

330P_0402_50V8J

12

12

PC1044

1000P_0402_50V7K

12

PR1004

10K_0402_5%

10K_0402_5%

31

32

BOOT_NB

PHASE_NB

UGATE_NB

BOOT2

UGATE2

PHASE2

LGATE2

LGATE1

PHASE1

UGATE1

BOOT1

COMP

FB18PGOOD

19

20

62771_COMP

62771_FB_2

1 2

PC1024

Rdroop: change on SIT

PC1043

330P_0402_50V8J

VDDP

VDD

TP

41

1 2

PR1037

1.3K_0402_1%

30

29

28

27

62771_VDDP

26

62771_VDD

25

24

23

22

21

1 2

PR1031

499_0402_1%

GFX_BOOT2

GFX_UGATE2

GFX_PHASE2

GFX_LGATE2

GFX_LGATE1

GFX_PHASE1

GFX_UGATE1

GFX_BOOT1

+3VS

12

PR1022

@

1 2

12

1.91K_0402_1%

change on SIV

change on SIT

1 2

100P_0402_50V8J

1 2

PR1038

162K_0402_1%

PR1040

6277_FB_36277_FB_3

2K_0402_1%

@

PC1042

680P_0402_50V7K

PC1025

6277_FB_1

1 2

12

1_0603_5%

PC1010

1U_0603_6.3V7-K

1 2

32.4K_0402_1%

1 2

PC1027

150P_0402_50V8-J

3

PR1016

12

PC1011

VR_GFX_PWRGD 7,35

@

PR1032

GFX_UGATE1

GFX_PHASE1

GFX_BOOT1

GFX_LGATE1

1 2

PR1019

0_0603_5%

1 2

PR1015

0_0603_5%

1U_0603_6.3V7-K

1 2

@

GFX_UGATE2

GFX_PHASE2

GFX_BOOT2

GFX_LGATE2

1 2

PR1008

2.2_0603_5%

PC1006

0.22U_0603_16V7K

+5VALW

+5VS

1 2

PR1023

2.2_0603_5%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

12

PR1002

PR1001

0_0402_5%

@

@

37

38

39

40

PU1001

FB_NB

1 2

PR1006

1 2

12

PC1021

0.22U_0402_10V6K

PR1039

11K_0402_1%

GFX_CORE_SEN6

GFX_VSS_SEN6

1 2

PR1007 100K_0402_1%

12

0_0402_5%

+1.8VS

PR1018

0_0402_5%

PR1020

@

1.91K_0402_1%

PC1022

0.22U_0402_10V6K

12

@

PC1040

0.033U_0402_16V7K

+APU_GFX

PR1012

10K_0402_1%

GFX_SVC6

PR1014

GFX_SVD6

GFX_SVT6

APU_PWROK6,51

+3VS

12

12

100K_0402_1%

12

1 2

1 2

0.1U_0402_25V6

12

PC1041

PR1021

PC1023

0.1U_0402_25V7-K

133K_0402_1%

1

2

3

4

5

6

7

8

9

10

1 2

PC1016

PR1036

10K_0402_5%

NTC_NB

IMON_NB

SVC

VR_HOT_L

SVD

VDDIO

SVT

ENABLE

PWROK

IMON

1000P_0402_50V7K

62771NTC

12

@

1 2

PR1169

100_0402_1%

1 2

PR1170

100_0402_1%

ISUMP_NB

11

1 2

PR1030

1.54K_0402_1%

change on SIV

1 2

PC1026

0.22U_0402_10V6K

4

VSEN_NB

ISUMN_NB

ISL62771HRTZ_TQFN40_5X5

ISUMP14ISEN212NTC

13

@

5

4

321

4

1 2

PC1017

0.22U_0603_16V7K

123 5

2014/10/22

2014/10/22

2014/10/22

1.5A

PQ1001

AON6372_DFN

12

PR1009

4.7_0603_5%

EMC_NS@

PQ1002

AON6764_DFN

12

PC1009

680P_0402_50V7K

EMC_NS@

5

4

PQ1003

321

4

PQ1004

AON6764_DFN

123 5

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

2

12

PC1001

0.1U_0402_25V6

EMC_NS@

AON6372_DFN

12

PR1024

4.7_0603_5%

EMC_NS@

12

PC1020

680P_0402_50V7K

EMC_NS@

12

Deciphered Date

Deciphered Date

Deciphered Date

2

PJ1001

12

PC1003

10U_0805_25V6K

10U_0805_25V6K

1 2

0.36UH_PCMB063T-R36MS_20A_20%

change on SIV

PR1010

PR1013

1 2

1 2

3.65K_0402_1%

10K_0402_1%

VSUM+

ISEN1

JUMP_43X79

PL1001

GFX_B+

12

PC1002

B+

112

@

PR1011

1 2

10_0402_1%

VSUM-

1.5A

12

12

12

PC1015

PC1014

PC1013

10U_0805_25V6K

0.1U_0402_25V6

EMC_NS@

PR1028

1 2

10K_0402_1%

ISEN2

12

12

12

PC1032

PC1031

PC1029

PC1030

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

2014/10/22

2014/10/22

2014/10/22

10U_0805_25V6K

1 2

PL1002

0.36UH_PCMB063T-R36MS_20A_20%

change on SIV

PR1026

1 2

3.65K_0402_1%

VSUM+

12

12

12

PC1035

PC1033

PC1034

22U_0805_6.3V6M

22U_0805_6.3V6M

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

+APU_GFX
FSW=300KHz
TDC=30A
EDC=45A
OCP:56A
Load Line=2.1mohm
Ripple:+/-20mv
Max AC :VID_APU_GFX +70mv
MIN AC: VID_APU_GFX -20mv

+APU_GFX

1

1

+

2

560U_2.5V_M

ESR=10mohm

12

@

PC1038

PC1037

22U_0805_6.3V6M

22U_0805_6.3V6M

ESR=9mohm

1

2

1

+

PC1008

2

@

330U_D2_2V_Y

Cost down 1pcs

1

+

+

PC1019

PC1018

2

560U_2.5V_M

330U_D2_2V_Y

ESR=9mohm

12

@

PC1039

22U_0805_6.3V6M

Allsparks 5B

Allsparks 5B

Allsparks 5B

50 51

50 51

50 51

PC1007

ESR=10mohm

PR1025

10_0402_1%

1 2

VSUM-

12

12

PC1036

22U_0805_6.3V6M

22U_0805_6.3V6M

Title

Title

Title

PWR-VGA_CORE

PWR-VGA_CORE

PWR-VGA_CORE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

0.2

0.2

0.2

12

@

D D

C C

B B

A A

GFX_SVC

GFX_SVD

GFX_SVT

EC_GFX_ON35

1 2

PR1035

47K_0402_1%

6277_NTC_1

PH1002

12

470K_0402_5%_TSM0B474J4702RE

PR1041

10K_0402_1%

12

PR864

@

+5VS

ISEN2

ISEN1

62771NTC

12

5

62771_RTN_APU

VSUM-_NB

62771NTC_NB_R

1 2

PC1122

1000P_0402_50V7K

VSUM+_NB

VR_HOT#35,44,50

+5VS

1 2

PR1172

0_0402_5%

12
@

PR1171

100_0402_1%

1 2

PR1106

100_0402_1%

12

PR1105

0_0402_5%

12

12

PR1108

2.61K_0402_1%

NB_NTCS

PH1101

1 2

10K_0402_NTC

PR1116

47K_0402_1%

1 2

PH1102

1 2

470K_0402_3%_NCP15WM474E03RC

+1.8VS

PR1139

10K_0402_5%

PR1140

10K_0402_5%

VSUM-_APU

VSUM+_APU

APU_VDDNB_SEN_L6

+APU_CORE_NB

D D

C C

B B

APU_VDDNB_SEN_H6

PR1117
10K_0402_1%

1 2

12

PR1122

133K_0402_1%

12

12

PR1112

EC_VR_ON35

APU_PWROK6,50

@

@

11K_0402_1%

APU_SVC6

APU_SVD6

APU_SVT6

12

APU_NTCS

1 2

12

PR1146

2.61K_0402_1%

PH1104

10K_0402_NTC

PC1168
330P_0402_50V8J

@

1 2

@

PC1166

330P_0402_50V8J

330P_0402_50V8J

1 2

PC1110

0.033U_0402_16V7K

1 2

PC1121

0.1U_0402_25V6

1 2

PR1118 0_0402_5%

1 2

PR1120 0_0402_5%

1 2

PR1121 0_0402_5%

1 2

PR1124 0_0402_5%

1 2

PR1126 0_0402_5%

1 2

PR1127

1 2

PR1128 0_0402_5%

PR1129

133K_0402_1%

1 2

PC1125

0.1U_0402_25V6

12

12

PC1131

PC1132

0.22U_0402_10V6K

12

PR1150

11K_0402_1%

+1.8VS

12

12

PRE-PWROK METAL VID CODES

SVDSVC

Boot Voltage

00
0
110 0.9V

A A

1.1V

1.0V

11

0.8V(Default)

62771_SVC_A

62771_SVD_A

62771_SVT_A

12

PR1161

PR1162

PR1163

1K_0402_1%

1K_0402_1%

@

12

@

1K_0402_1%

@

@

12

12

PR1164

PR1166

PR1165

220_0402_5%

220_0402_5%

220_0402_5%

@

@

PC1101

680P_0402_50V7K

1 2

@

PC1109

IMON_NB

0_0402_5%

12

APU_NTC_1

12

0.22U_0402_10V6K

12

@

change on SIV

1 2

100P_0402_50V8J

12

PR1133

PC1141

0.047U_0402_25V7K

4

FB_NB_3

12

@

PR1101

2K_0402_1%

1 2

PR1102

1.54K_0402_1%

change on SIV

FB_NB_1

1 2

PC1107

PR1107
499_0402_1%

PC1112

0.033U_0402_16V7K

PR1114

1.02K_0402_1%

1 2

1 2

@

PR1115

PC1120

10K_0402_5%

0.22U_0402_10V6K

62771_SVC_A

62771_VRHOT_A

62771_SVD_A

62771_VDDIO_A

62771_SVT_A

62771_EN_A

62771_PWROK_A

62771A_IMON

10

PR1131

47K_0402_1%

62771NTC_APU

1 2

1 2

PH1103

470K_0402_3%_NCP15WM474E03RC

10K_0402_1%

ISEN2_APU

ISEN1_APU

PC1133

0.1U_0402_25V6

1 2

12

PR1147

10K_0402_5%

PC1142

0.1U_0402_25V7-K

+1.8VS

12

PC1167

@

.1U_0402_10V6-K

@

12

1 2

110K_0402_1%

VSUM-_NB_11

12

@

PU1101

1

NTC_NB

2

IMON_NB

3

SVC

4

VR_HOT_L

5

SVD

6

VDDIO

7

SVT

8

ENABLE

9

PWROK

IMON

1 2

2K_0402_1%

change on SIV

12

PC1169

PR1103

12

PR1144

@

1U_0402_6.3V6K

1 2

PC1108
47P_0402_50V8J

FB_NB_2

1 2

PC1102

150P_0402_50V8-J

VSEN_NB

38

39

40

VSEN_NB

ISUMP_NB

ISUMN_NB

ISL62771HRTZ_TQFN40_5X5

13

11

1 2

@

PC1136

0.22U_0402_10V6K

FB_NB

37

FB_NB

ISUMP14ISEN212NTC

COMP_NB

35

36

COMP_NB

PGOOD_NB

VSEN

16

62771_VSEN_APU

62771_ISUM-_APU

12

1 2

@

PR1104

33K_0402_5%

set FSW=300K on SIV

PGOOD_NB

LGATE_NB

PHASE_NB

UGATE_NB

BOOT_NB

31

33

34

LGATE_NB

UGATE_NB32PHASE_NB

RTN17ISUMN15ISEN1

COMP

FB18PGOOD

19

20

62771_FB_APU

62771_RTN_APU

1 2

PC1134

100P_0402_50V8J

PC1137

330P_0402_50V8J

12

PC1151

330P_0402_50V8J

12

PC1152

0.1U_0402_25V6

BOOT_NB

BOOT2

UGATE2

PHASE2

LGATE2

VDDP

VDD

LGATE1

PHASE1

UGATE1

BOOT1

41

PGOOD_APU

PGOOD_NB

APU_FB_2

1 2

PR1148

2.32K_0402_1%

change on SIV

TP

1 2

100_0402_1%

PR1153

0_0402_5%

PR1154

0_0402_5%

1 2

100_0402_1%

30

29

28

27

26

25

24

23

22

21

1 2

499_0402_1%

PR1152

PR1156

1 2

0_0402_5%

1 2

PR1143

12

12

BOOT2_APU

UGATE2_APU

PHASE2_APU

LGATE2_APU

APU_VDDP

APU_VDD

LGATE1_APU

PHASE1_APU

UGATE1_APU

BOOT1_APU

PR1134

PR1135

0_0402_5%

+3VS

1 2

1 2

PR1149

200K_0402_1%

PR1151

2K_0402_1%

+APU_CORE

UGATE_NB

PHASE_NB

BOOT_NB

LGATE_NB

PR1132

1.91K_0402_1%

1 2

PC1135

47P_0402_50V8J

APU_FB_1

APU_FB_3

12
@

APU_VDD_SEN_H 6

APU_VDD_SEN_L 6

1 2

PR1109

2.2_0603_5%

1 2

PR1125

1_0603_5%

1 2

PC1123

1U_0603_6.3V7-K

VR_APU_PWRGD 35

1 2

1 2

PC1138

150P_0402_50V8-J

1 2

@

PC1143

680P_0402_50V7K

BOOT_NB_R

0.22U_0603_25V7K

PR1145

32.4K_0402_1%

1 2

PC1111

1 2

@

UGATE2_APU

PHASE2_APU

LGATE2_APU

3

PC1124

1U_0603_6.3V7-K

UGATE1_APU

PHASE1_APU

BOOT1_APU

LGATE1_APU

BOOT2_APU

1 2

PR1119

0_0402_5%

1 2

PR1123

0_0402_5%

4

4

@

1 2

1 2

PR1155

2.2_0603_5%

123 5

123 5

+5VALW

+5VS

PR1136

2.2_0603_5%

PQ1101

AON6372_DFN

PQ1102

AON6764_DFN

BOOT1_R_A

BOOT2_R_A

0.22U_0603_25V7K

12

0.22U_0603_25V7K

1 2

PC1153

10U_0805_25V6K

PC1103

1 2

PC1129

12

12

PR1110

4.7_0603_5%

EMC_NS@

12

PC1119
680P_0402_50V7K

EMC_NS@

2

+APU_CORE_NB
FSW=300KHz

CPU_NB_B+

12

PC1105

PC1104

EMC_NS@

10U_0805_25V6K

0.1U_0402_25V6

VSUM+_NB

VSUM-_NB

12

4

PQ1103

AON6372_DFN

123 5

4

4

PQ1104

AON6764_DFN

123 5

PJ1101

2

112

@

JUMP_43X79

PL1101

1 2

0.36UH_PCMB063T-R36MS_20A_20%

change on SIV

1 2

PR1111

3.65K_0402_1%

1 2

PR1113

10_0402_1%

CPU_CORE_B+

12

12

PC1127

PC1126

EMC_NS@

10U_0805_25V6K

10U_0805_25V6K

5

12

PR1137

4.7_0603_5%

EMC_NS@

PQ1108

AON6764_DFN

12

PC1130
680P_0402_50V7K

321

@

EMC_NS@

PJ1102

2

JUMP_43X79

1

+

PC1106

PC1128

2

68U_25V_M

0.1U_0402_25V6

ISEN1_APU

1 2

10K_0402_1%

VSUM+_APU

1 2

3.65K_0402_1%

VSUM-_APU

1 2

10_0402_1%

TDC=12A
EDC=17A
OCP:25A

B+

Load Line=4mohm
Ripple:+/-20mv
Max AC :VID_APU_CORE_NB +70mv
MIN AC: VID_APU_CORE_NB -40mv

112

@

B+

1 2

PL1102

0.36UH_PCMB063T-R36MS_20A_20%

change on SIV

PR1141

PR1138

PR1142

ESR=10mohm

+APU_CORE_NB

1

1

12

12

12

+

+

PC1113

PC1114

2

2

PC1115

330U_D2_2V_Y

560U_2.5V_M

22U_0805_6.3V6M

12

12

12

PC1117

PC1165

PC1118

PC1116

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

ESR=9mohm

+APU_CORE
FSW=300KHz
TDC=39A
EDC=55A
OCP:70A
Load Line=2.1mohm
Ripple:+/-20mv
Max AC :VID_APU_CORE +70mv
MIN AC: VID_APU_CORE -20mv

+APU_CORE

1

PC1164

22U_0805_6.3V6M

CPU_CORE_B+

1

1

1

12

4

PQ1105

AON6372_DFN

123 5

4

4

PQ1106

AON6764_DFN

123 5

12

12

PC1144

10U_0805_25V6K

5

321

PC1148

PC1145

EMC_NS@

0.1U_0402_25V6

10U_0805_25V6K

1 2

PL1103

12

PR1157

ISEN2_APU

4.7_0603_5%

PQ1109

EMC_NS@

AON6764_DFN

@

12

PC1154
680P_0402_50V7K

EMC_NS@

VSUM+_APU

VSUM-_APU

1 2

PR1159

10K_0402_1%

1 2

PR1158

3.65K_0402_1%

1 2

PR1160

10_0402_1%

0.36UH_PCMB063T-R36MS_20A_20%

change on SIV

12

@

1

+

PC1139

2

2

330U_D2_2V_Y

12

12

12

PC1155

PC1156

PC1162

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

@

12

12

+

+

+

PC1146

PC1147

PC1140

2

2

PC1149

PC1150

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y

PC1157

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

12

12

12

12

12

PC1160

PC1158

PC1159

PC1161

PC1163

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2014/10/22

2014/10/22

2014/10/22

Title

PWR_CPU Core

PWR_CPU Core

PWR_CPU Core

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

D

D

D

Date: Sheet of

Date: Sheet of

Date: Sheet of

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

1

Allsparks 5B

Allsparks 5B

Allsparks 5B

51 51

51 51

51 51

0.2

0.2

0.2