Keithley Instruments, Inc. warrants this product to be free from defects in material and workmanship for a
period of 3 years from date of shipment.
Keithley Instruments, Inc. warrants the following items for 90 days from the date of shipment: probes,
cables, rechargeable batteries, diskettes, and documentation.
During the warranty period, we will, at our option, either repair or replace any product that proves to be
defective.
T o e xercise this w arranty, write or call your local K eithley representati v e, or contact K eithle y headquarters in
Cleveland, Ohio. You will be given prompt assistance and return instructions. Send the product, transportation prepaid, to the indicated service facility. Repairs will be made and the product returned, transportation
prepaid. Repaired or replaced products are warranted for the balance of the original warranty period, or at
least 90 days.
LIMIT A TION OF W ARRANTY
This warranty does not apply to defects resulting from product modification without Keithley’s express written consent, or misuse of any product or part. This warranty also does not apply to fuses, software, nonrechargeable batteries, damage from battery leakage, or problems arising from normal wear or failure to follow instructions.
THIS WARRANTY IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED OR IMPLIED, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR USE.
THE REMEDIES PROVIDED HEREIN ARE B UYER’S SOLE AND EXCLUSIVE REMEDIES.
NEITHER KEITHLEY INSTRUMENTS, INC. NOR ANY OF ITS EMPLOYEES SHALL BE LIABLE
FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OF ITS INSTRUMENTS AND SOFTWARE EVEN IF KEITHLEY INSTRUMENTS, INC., HAS BEEN ADVISED IN ADVANCE OF THE POSSIBILITY OF SUCH DAMAGES.
SUCH EXCLUDED DAMAGES SHALL INCLUDE, BUT ARE NOT LIMITED TO: COSTS OF
REMOVAL AND INSTALLATION, LOSSES SUSTAINED AS THE RESULT OF INJURY TO ANY PERSON, OR DAMAGE TO PROPERTY.
The print history shown below lists the printing dates of all Revisions and Addenda created
for this manual. The Revision Le vel letter increases alphabetically as the manual under goes subsequent updates. Addenda, which are released between Revisions, contain important change information that the user should incorporate immediately into the manual. Addenda are numbered
sequentially. When a new Re vision is created, all Addenda associated with the previous Re vision
of the manual are incorporated into the new Revision of the manual. Each ne w Revision includes
a revised copy of this print history page.
Revision A (Document Number 2000-902-01).................................................................May 1995
Revision B (Document Number 2000-902-01).............................................................. March 1997
All Keithley product names are trademarks or registered trademarks of Keithley Instruments, Inc.
Other brand names are trademarks or registered trademarks of their respective holders.
Safety Precautions
The following safety precautions should be observed before using this product and any associated instrumentation. Although some instruments and accessories would normally be used with non-hazardous v oltages, there
are situations where hazardous conditions may be present.
This product is intended for use by qualified personnel who recognize shock hazards and are familiar with the
safety precautions required to avoid possible injury. Read the operating information carefully before using the
product.
The types of product users are:
Responsible body is the individual or group responsible for the use and maintenance of equipment, and for en-
suring that operators are adequately trained.
Operators use the product for its intended function. They must be trained in electrical safety procedures and
proper use of the instrument. They must be protected from electric shock and contact with hazardous live circuits.
Maintenance personnel perform routine procedures on the product to keep it operating, for example, setting
the line voltage or replacing consumable materials. Maintenance procedures are described in the manual. The
procedures explicitly state if the operator may perform them. Otherwise, they should be performed only by service personnel.
Service personnel are trained to work on live circuits, and perform safe installations and repairs of products.
Only properly trained service personnel may perform installation and service procedures.
Exercise extreme caution when a shock hazard is present. Lethal voltage may be present on cable connector
jacks or test fixtures. The American National Standards Institute (ANSI) states that a shock hazard e xists when
voltage levels greater than 30V RMS, 42.4V peak, or 60VDC are present. A good safety practice is to expect
that hazardous voltage is present in any unknown circuit before measuring.
Users of this product must be protected from electric shock at all times. The responsible body must ensure that
users are prevented access and/or insulated from every connection point. In some cases, connections must be
exposed to potential human contact. Product users in these circumstances must be trained to protect themselves
from the risk of electric shock. If the circuit is capable of operating at or above 1000 volts, no conductive part
of the circuit may be exposed.
As described in the International Electrotechnical Commission (IEC) Standard IEC 664, digital multimeter
measuring circuits (e.g., Keithley Models 175A, 199, 2000, 2001, 2002, and 2010) measuring circuits are Installation Category II. All other instruments’ signal terminals are Installation Category I and must not be connected to mains.
Do not connect switching cards directly to unlimited power circuits. They are intended to be used with impedance limited sources. NEVER connect switching cards directly to AC mains. When connecting sources to
switching cards, install protective devices to limit fault current and voltage to the card.
Before operating an instrument, make sure the line cord is connected to a properly grounded power receptacle.
Inspect the connecting cables, test leads, and jumpers for possible wear, cracks, or breaks before each use.
For maximum safety, do not touch the product, test cables, or any other instruments while power is applied to
the circuit under test. ALWAYS remove power from the entire test system and discharge an y capacitors before:
connecting or disconnecting cables or jumpers, installing or removing switching cards, or making internal
changes, such as installing or removing jumpers.
Do not touch any object that could provide a current path to the common side of the circuit under test or power
line (earth) ground. Always make measurements with dry hands while standing on a dry, insulated surface capable of withstanding the voltage being measured.
Do not exceed the maximum signal levels of the instruments and accessories, as defined in the specifications
and operating information, and as shown on the instrument or test fixture panels, or switching card.
When fuses are used in a product, replace with same type and rating for continued protection against fire hazard.
Chassis connections must only be used as shield connections for measuring circuits, NOT as safety earth ground
connections.
If you are using a test fixture, keep the lid closed while power is applied to the device under test. Safe operation
requires the use of a lid interlock.
If a screw is present, connect it to safety earth ground using the wire recommended in the user documentation.
!
The symbol on an instrument indicates that the user should refer to the operating instructions located in
the manual.
The symbol on an instrument shows that it can source or measure 1000 volts or more, including the combined effect of normal and common mode voltages. Use standard safety precautions to avoid personal contact
with these voltages.
The WARNING heading in a manual explains dangers that might result in personal injury or death. Always
read the associated information very carefully before performing the indicated procedure.
The CAUTION heading in a manual explains hazards that could damage the instrument. Such damage may
invalidate the warranty.
Instrumentation and accessories shall not be connected to humans.
Before performing any maintenance, disconnect the line cord and all test cables.
To maintain protection from electric shock and fire, replacement components in mains circuits, including the
power transformer, test leads, and input jacks, must be purchased from Keithley Instruments. Standard fuses,
with applicable national safety approvals, may be used if the rating and type are the same. Other components
that are not safety related may be purchased from other suppliers as long as they are equivalent to the original
component. (Note that selected parts should be purchased only through Keithley Instruments to maintain accuracy and functionality of the product.) If you are unsure about the applicability of a replacement component,
call a Keithley Instruments office for information.
T o clean the instrument, use a damp cloth or mild, water based cleaner . Clean the exterior of the instrument only .
Do not apply cleaner directly to the instrument or allow liquids to enter or spill on the instrument.
The information in this section deals with routine type maintenance that can be performed by
the operator. This information is arranged as follows:
•Setting line voltage and replacing fuse — Explains how to select the alternate po wer line
voltage setting, and how to replace a blown power line fuse.
•Amps fuse replacement — Explains how to replace a blown current fuse.
Setting line voltage and replacing fuse
A rear panel fuse located next to the A C receptacle (in the power module) protects the power
line input of the instrument. If the line voltage setting needs to be changed or the line fuse needs
to be replaced, perform the following steps.
W ARNINGDisconnect the line cord at the rear panel and remove all test leads connected to the instru-
ment (front and rear) before replacing the line fuse or changing the line voltage setting.
1.Place the tip of a flat-blade screwdriv er into the po wer module by the fuse holder assembly (see Figure 1-1). Gently push in and to the left. Release pressure on the assembly and
its internal spring will push it out of the power module.
2.Remove the fuse and replace it with the type listed in Table 1-1.
CAUTIONFor continued protection against fire or instrument damage, only replace
fuse with the type and rating listed. If the instrument repeatedly blows fuses,
locate and correct the cause of the trouble before replacing the fuse.
3.If configuring the instrument for a different line voltage, remo ve the line voltage selector
from the assembly and rotate it to the proper position. When the selector is installed into
the fuse holder assembly, the correct line voltage appears inverted in the window.
4.Install the fuse holder assembly into the power module by pushing it in until it locks in
place.
WARNING:NO INTERNAL OPERATOR SERVICABLE PARTS,SERVICE BY QUALIFIED PERSONNEL ONLY.
WARNING:NO INTERNAL OPERATOR SERVICABLE PARTS,SERVICE BY QUALIFIED PERSONNEL ONLY.
CAUTION:FOR CONTINUED PROTECTION AGAINST FIRE HAZARD,REPLACE FUSE WITH SAME TYPE AND RATING.
CAUTION:FOR CONTINUED PROTECTION AGAINST FIRE HAZARD,REPLACE FUSE WITH SAME TYPE AND RATING.
×
Routine Maintenance1-3
Figure 1-2
Power module
Model 2000
HI
1000V
350V
PEAK
!
PEAK
LO
500V
1
PEAK
SENSE
INPUT
Ω 4W
!
2
MADE IN
U.S.A.
IEEE-488
(CHANGE IEEE ADDRESS
TRIGGER
LINK
!
3 5
VMC
4 6
EXT TRIG
!
FUSE LINE
250mAT
100 VAC
(SB)
120 VAC
220 VAC
125mAT
240 VAC
(SB)
FROM FRONT PANEL)
RS232
120
LINE RATING
50, 60
400HZ
17 VA MAX
Line Voltage Selector
Fuse
Spring
Fuse Holder Assembly
Table 1-1
Fuse rating
Line voltageFuse ratingKeithley part no.
100/120V
220/240V
0.25A slow-blow 5 × 20mm
0.125A slow-blow 5
20mm
FU-96-4
FU-91
220
240
120
100
Window
1-4Routine Maintenance
AMPS fuse replacement
WARNINGMake sure the instrument is disconnected from the power line and other equipment before
replacing the AMPS fuse.
1.Turn off the power and disconnect the power line and test leads.
2.From the front panel, gently push in the AMPS jack with your thumb and rotate the fuse
carrier one-quarter turn counter-clockwise. Release pressure on the jack and its internal
spring will push the fuse carrier out of the socket.
3.Remove the fuse and replace it with the same type 3A, 250V, fast blow: Keithley
part number FU-99-1.
CAUTIONDo not use a fuse with a higher current rating than specified or instrument
damage may occur. If the instrument repeatedly blows fuses, locate and correct the cause of the trouble before replacing the fuse.
4.Install the new fuse by reversing the procedure.
2
Troubleshooting
2-2Troubleshooting
Introduction
WARNINGThe information in this section is intended for qualified service personnel.
Some of these procedures may expose you to hazardous voltages. Do not per form these hazardous procedures unless you are qualified to do so.
This section of the manual will assist you in troubleshooting the Model 2000. Included are
self-tests, test procedures, troubleshooting tables, and circuit descriptions. It is left to the discretion of the repair technician to select the appropriate tests and documentation needed to troubleshoot the instrument. This section is arranged as follows:
•Repair considerations — Covers some considerations that should be noted before making any repairs to the Model 2000.
•Power-on test — Describes the tests that are performed on memory elements each time
the instrument is turned on.
•Front panel tests — Provides the procedures to test the functionality of the front panel
keys and the display.
•Principles of operation — Provides support documentation for the various troubleshooting tests and procedures. Included is some basic circuit theory for the display board,
power supply, digital circuitry and analog circuitry.
•Display board checks — Provides display board checks that can be made if front panel
tests fail.
•Power supply checks — Provides po wer supply checks that can be made if the inte grity
of the power supply is questionable.
•Digital circuitry checks — Provides some basic checks for the digital circuitry.
•Analog signal switching states — Provides tables to check switching states of various
relays, FETs, analog switches and the A/D multiplexer for the basic measurement functions and ranges.
•Built-in test overview — Summarizes the b uilt-in tests, which can be used to test and e xercise the various digital and analog circuits.
•Built-in test documentation — Provides a detailed analysis of each built-in test.
Troubleshooting2-3
Repair considerations
Before making any repairs to the Model 2000, be sure to read the following considerations.
CAUTIONThe PC-boards are built using surface mount techniques and require special-
ized equipment and skills for repair. If you are not equipped and/or qualified,
it is strongly recommended that you send the unit back to the factory for repairs or limit repairs to the PC-board replacement level. Without proper
equipment and training, you could damage a PC-board beyond repair.
1.Repairs will require various degrees of disassembly. However, it is recommended that
the Front Panel Tests and Built-In-Test be performed prior to any disassembly. The disassembly instructions for the Model 2000 are contained in Section 3 of this manual.
2.Do not make repairs to surface mount PC-boards unless equipped and qualified to do so
(see previous CAUTION).
3.When working inside the unit and replacing parts, be sure to adhere to the handling precautions and cleaning procedures explained in Section 3.
4.Many CMOS devices are installed in the Model 2000. These static-sensitive devices require special handling as explained in Section 3.
5.Anytime a circuit board is removed or a component is replaced, the Model 2000
must be recalibrated.
Power-on test
During the power-on sequence, the Model 2000 will perform a checksum test on its EPROM
(U156 and U157) and test its RAM (U151 and U152). If one of these tests fails the instrument
will lock up.
▲
▲
2-4Troubleshooting
Front panel tests
There are two front panel tests: one to test the functionality of the front panel keys and one to
test the display . In the ev ent of a test failure, refer to “Display Board Checks” for details on troubleshooting the display board.
KEY test
The KEY test allows you to check the functionality of each front panel key. Perform the following steps to run the KEY test:
1.Press SHIFT and then TEST to access the self-test options.
2.Use the
3.Press ENTER to start the test. When a ke y is pressed, the label name for that key is displayed to indicate that it is functioning properly. When the key is released, the message
“NO KEY PRESS” is displayed.
4.Pressing EXIT tests the EXIT key . Ho we v er, the second consecutive press of EXIT
aborts the test and returns the instrument to normal operation.
or ▼ key to display “TEST: KEY”.
DISP test
cent display is working properly. Perform the following steps to run the display test:
The display test allows you to verify that each pixel and annunciator in the vacuum fluores-
1.Press SHIFT and then TEST to access the self-test options.
2.Use the
3.Press ENTER to start the test. There are four parts to the display test. Each time ENTER
is pressed, the next part of the test sequence is selected. The four parts of the test sequence are as follows:
A. All annunciators are displayed.
B. The pixels of each digit are sequentially displayed.
C. The 12 digits (and annunciators) are sequentially displayed.
D. The annunciators located at either end of the display are sequentially displayed.
4.When finished, abort the display test by pressing EXIT. The instrument returns to
normal operation.
or ▼ key to display “TEST: DISP”.
Principles of operation
The following information is provided to support the troubleshooting tests and procedures
covered in this section of the manual. Refer to the following block diagrams:
Block Diagrams:
Figure 2-1 — Power supply block diagram
Figure 2-2 — Digital circuitry block diagram
Figure 2-3 — Analog circuitry block diagram
Display board
Troubleshooting2-5
Microcontroller
U401 is the display board microcontroller that controls the display and interprets key data.
The microcontroller uses three internal, peripheral I/O ports for the various control and read
functions.
Display data is serially transmitted to the microcontroller from the digital section via the TXB
line to the microcontroller RDI terminal. In a similar manner, key data is serially sent back to
the digital section through the RXB line via TDO. The 4MHz clock for the microcontroller is
generated by crystal Y401.
Display
DS401 is the display module, which can display up to 12 alpha-numeric characters and the
various annunciators.
The display uses a common multiplexing scheme with each character refreshed in sequence.
U402 and U403 are the drivers for the display characters and annunciators. Note that data for
the drivers are serially transmitted from the microcontroller (MOSI and PC1).
Filament voltage for the display is derived from the power supply transformer (F1 and F2).
The display drivers require +37VDC and +5VDC, which are supplied by U144 (+5VD) and
U101 (+37V).
2-6Troubleshooting
Key matrix
The front panel keys (S401-S430) are organized into a row-column matrix to minimize the
number of microcontroller peripheral lines required to read the keyboard. A k ey is read by strobing the columns and reading all rows for each strobed column. K e y down data is interpreted by
the display microcontroller and sent back to the main microprocessor using proprietary encoding schemes.
Power supply
The following information provides some basic circuit theory that can be used as an aid to
troubleshoot the power supply. A block diagram of the power supply is shown in Figure 2-1.
Figure 2-1
Power supply
block diagram
+5VD
D Common
+37V
D Common
+15V
A Common
-15V
+5V, +5VRL
A Common
Fuse
Power
Switch
Line
Voltage
Switch
Power
Transformer
CR104
C128, C156
U144
CR116, CR117
C104, C108
U101
CR102
C131, C148
U119, U125
CR103
C146
U124
AC power is applied to the AC power module receptacle (J1009). Power is routed through the
line fuse and line voltage selection switch of the power module to the power transformer. The
power transformer has a total of four secondary windings for the various supplies.
AC voltage for the display fi laments is taken from a power transformer secondary at F1 and
F2, and then routed to the display board.
Each DC supply uses a bridge rectifier, a capaciti v e filter arrangement and a regulator . Table
2-1 summarizes rectifier, filter and regulator circuits for the various supplies.
Table 2-1
Power supply circuits
SupplyRectifierFilterRegulator
Troubleshooting2-7
Digital circuitry
Figure 2-2
Digital circuitry
block diagram
+5VD
+37V
+15V
-15V
+5V, +5VRL
CR104
CR116, CR117
CR102
CR102
CR103
C128, C156
C104, C108
C148
C131
C146
U144
U101
U125
U119
U124
Refer to Figure 2-2 for the following discussion on digital circuitry.
RAM
U151, U152
IN
OUT
Data IN
Data OUT
Analog
Circuitry
(See Figure 2-3)
XADTX
XADCLK
XADTS
XADRX
Scan Control
U146, U164
Trigger
O
P
T
O
I
S
O
AT101
U150
U155
NVRAM
U136
ADTX
ADCLK
ADTS
ADRXB
TRIG IN
TRIG OUT
ROM
U156, U157
68306
µP
U135
Display Board
Controller
U401
XTAL
Y101
RS-232
U159
GPIB
U158, U160,
U161
Keypad
RS-232
Port
Display
DS401
IEEE-488
Bus
Trigger
Link
2-8Troubleshooting
Microprocessor
U135 is a 68306 microprocessor that oversees all operating aspects of the instrument. The
MPU has a 16-bit data bus and provides an 18-bit address b us. It also has parallel and serial ports
for controlling various circuits. For example, the RXDA, TXDA, RXDB and TXDB lines are
used for the RS-232 interface.
The MPU clock frequency of 14.7456MHz is controlled by crystal Y101. MPU RESET is
performed momentarily (through C241) on power-up by the +5VD power supply.
Memory circuits
ROMs U156 and U157 store the firmware code for instrument operation. U157 stores the D0D7 bits of each data word, and U156 stores the D8-D15 bits.
RAMS U151 and U152 provide temporary operating storage. U152 stores the D0-D7 bits of
each data word, and U151 stores the D8-D15 bits.
Semi-permanent storage facilities include NVRAM U136. This IC stores such information as
instrument setup and calibration constants. Data transmission from this device is done in a serial
fashion.
RS-232 interface
Serial data transmission and reception is performed by the TXDB and RXDB lines of the
MPU. U159 provides the necessary voltage level conversion for the RS-232 interface port.
IEEE-488 interface
U158, U160 and U161 make up the IEEE-488 interface. U158, a 9914A GPIA, takes care of
routine bus overhead such as handshaking, while U160 and U161 provide the necessary buffering and drive capabilities.
T rigger circuits
Buffering for Trigger Link input and output is performed by U146. T rigger input and output
is controlled by the IRQ4 and PB3 lines of the MPU. U164 provides additional logic for the trigger input to minimize MPU control overhead.
At the factory, trigger output is connected to line 1 of the Trigger Link connector (resistor
R267 installed). Trigger input is connected to line 2 of the T rigger Link connector (resistor R270
installed).
Analog circuitry
Refer to Figure 2-3 for the following discussion on analog circuitry.
Ω
Ω
Troubleshooting2-9
Figure 2-3
Analog circuitry
block diagram
AMPS
DCA
ACA
AC Switching
K102, U102, U103, U105,
U112, U118, U111, U110
ACV,
FREQ
SSP*
Ohms I-Source
U133, Q123, Q125,
Q124, Q126, Q119,
Q120, U123
Scanner Control
Gain
&
DCV
OHMS
DCV & Ohms
Switching
K101, Q104, Q105,
Q108, Q113, U115
X1
Buffer
U113
BUFCOM
A/D
MUX &
Gain
U163, U166
U129, U132
ADC
U165
Digital
Circuitry
(See Figure 2-2)
INPUT
HI
R117, Q109,
Q114, Q136
SENSE
HI
SENSE
LO
Scanner Output
Scanner
Inputs
K103, R158, R205
Q101, Q102
DCV
Divider
DCV/100
Q121, U126
Scanner
Option
*Solid State Protection
Current
Shunts
X1 Buffer
INPUT HI
INPUT HI protection is provided by the SSP (solid state protection) circuit. The SSP is primarily made up of Q101 and Q102. An overload condition opens Q101 and Q102. This disconnects the analog input signal from the rest of the analog circuit.
Note that for the 100VDC and 1000VDC ranges, Q101 and Q102 of the SSP are open. The
DC voltage signal is routed through the DCV Divider (Q114 and Q136 on) to the DCV switching circuit.
AMPS input
The ACA or DCA input signal is applied to the Current Shunt circuit, which is made up of
K103, R158 and R205. For the 10mADC range, 10.1
put. Relay K103 is energized (on) to select the shunts. For all other DCA ranges, and all ACA
ranges, 0.1
(R158) is shunted across the input (K103 off).
The A CA signal is then sent to the A C Switching & Gain circuit, while the DCA signal is routed directly to the A/D MUX & Gain circuit.
(R158 + R205) is shunted across the in-
2-10Troubleshooting
Signal switching
Signal switching for DCV and OHMS is done by the DCV & Ohms Switching circuit. FETs
Q113, Q105, Q104 and Q108 connect the DCV or ohms signal to the
2-5 through 2-8 show the switching states of these FETs for the v arious DCV and OHMS ranges.)
Note that the reference current for OHMS is generated by the Ohms I-Source circuit. For 4wire ohms measurements, SENSE LO is connected to the circuit by turning on Q121.
Signal switching and gain for ACV, FREQ and ACA is done by the AC Switching & Gain
circuit, which is primarily made up of K102, U102, U103, U105, U112, U118, U111 and U110.
Tables 2-6 and 2-11 show the switching states for these AC signals. Note that U111 is used for
frequency adjustment. The states of these analog switches vary from unit to unit.
×
1 buffer (U113). (Tables
Multiplexer and A/D converter
All input signals, except FREQ, are routed to the A/D MUX & Gain circuit. The multiplex er
(U163) switches the various signals for measurement. In addition to the input signal, the multiplexer also switches among reference and zero signals at v arious phases of the measurement cycle.
When the input signal is selected by the MUX, it is amplified by U132 and U166. Tables 212 through 2-16 identify the input signal lines (S3, S4, S6 or S7) of the multiplexer for the various functions and ranges. These tables also provide the switch states of U129, which determine
the gain for U132 and U166.
The multiplexed signals of the measurement cycle are routed to the A/D Converter (U165)
where it converts the analog signals to digital form. The digital signals are then routed through
an opto-isolator to the MPU to calculate a reading.
Display board checks
If the front panel DISP test indicates that there is a problem on the display board, use Table
2-2. See “Principles of Operation” for display circuit theory.
Table 2-2
Display board checks
StepItem/componentRequired conditionRemarks
Troubleshooting2-11
Front panel DISP test.
1
P1005, pin 5
2
P1005, pin 9
3
U401, pin 1
4
U401, pin 43
5
U401, pin 32
6
U401, pin 33
7
Power supply checks
Power supply problems can be checked out using Table 2-3. See “Principles of Operation”
for circuit theory on the power supply.
Table 2-3
Power supply checks
StepItem/componentRequired conditionRemarks
1
Line fuse
2
Line voltage
3
Line power
4
U144, pin2
5
U101, pin 7
6
U125, pin 3
7
U119, pin 3
8
U124, pin 3
Verify that all pixels operate.
+5V +/-5%
+37V +/-5%
Goes low briefly on power up,
then goes low.
4MHz square wave.
Pulse train every 1msec.
Brief pulse train when front
panel key pressed.
Check continuity.
120V/240V as required.
Plugged into live receptacle,
power on.
+5V +/-5%
+37V +/-5%
+15V +/-5%
-15V +/-5%
+5V +/-5%
Use front panel display test.
Digital +5V supply.
Display +37V supply.
Microcontroller RESET.
Controller 4MHz clock.
Control from main processor.
Key down data sent to main
processor.
Remove to check.
Check power module position.
Check for correct power-up
sequence.
+5VD, referenced to Common D.
+37V, referenced to Common D.
+15V, referenced to Common A.
-15V, referenced to Common A.
+5VRL, referenced to Common A.
2-12Troubleshooting
Digital circuitry checks
Digital circuit problems can be checked out using Table 2-4. See “Principles of Operation”
for digital circuit.
Table 2-4
Digital circuitry checks
StepItem/componentRequired conditionRemarks
Power-on test
1
U152 pin 16
2
U152 pin 32
3
U135 pin 48
4
U135, lines A1 thru A23
5
U135, lines D1 thru D15
6
U135 pin 44
7
U159 pin 13
8
U159 pin 14
9
U158 pins 34-42
10
U158 pins 26-31
11
U158 pin 24
12
U158 pin 25
13
U135 pin 84
14
U135 pin 91
15
U135 pin 90
16
U135 pin 89
17
RAM OK, ROM OK.
Digital common.
+5V
Low on power-up, then goes
high.
Check for stuck bits.
Check for stuck bits.
14.7456MHz
Pulse train during RS-232 I/O.
Pulse train during RS-232 I/O.
Pulse train during IEEE-488 I/O.
Pulses during IEEE-488 I/O.
Low with remote enabled.
Low during interface clear.
Pulse train.
Pulse train.
Pulse train.
Pulse train.
Verify that RAM and
ROM are functional.
All signals referenced
to digital common.
Digital logic supply.
MPU RESET line.
Tables 2-5 through 2-11 provide switching states of the various relays, FETs and analog
switches for the basic measurement functions and ranges. These tables can be used to assist in
tracing an analog signal from the input to the A/D multiplexer.
T ables 2-12 through 2-16 can be used to trace the analog signal through the A/D multiplexer
(U163) to the final amplifier stage. These tables show the MUX lines (S3, S4, S6, S7) that are
selected for measurement during the SIGNAL phase of the multiplexing cycle. Also included
are switching states of analog switches (U129) that set up the gain for the final amplifier stage
(U166).
U105
pin 16
U105
pin 1
U111
pin 16
OFFONOFF
U105
pin 8
OFF
U103
pin 16
OFF
OFF
U103
pin 1
OFF
OFF
2-16Troubleshooting
Table 2-12
DCV signal multiplexing and gain
×
× 10 × 1 ×
Range
100mV
10V
100V
1000V
1V
Signal
(U163)
S4
S4
S4
S4
S4
U129
pin 1
OFF
OFF
ON
OFF
ON
U129
pin 8
OFF
ON
OFF
ON
OFF
U129
pin 9
ON
OFF
OFF
OFF
OFF
Table 2-13
ACV and ACA signal multiplexing and gain
Range
AllS3ONOFFOFF×1
Signal
(U163)
U129
pin 1
U129
pin 8
U129
pin 9
Table 2-14
DCA signal multiplexing and gain
Range
10mA
100mA
1A
3A
Signal
(U163)
S6
S6
S6
S6
U129
pin 1
OFF
OFF
OFF
OFF
U129
pin 8
OFF
OFF
OFF
ON
U129
pin 9
ON
ON
ON
OFF
Gain
(U166)
100
10
×1
Gain
(U166)
Gain
(U166)
×100
×100
×100
×10
Table 2-15
Ω
2 signal multiplexing and gain
Range
100Ω
1kΩ
10kΩ
100kΩ
1MΩ
10MΩ
100MΩ
Signal
(U163)
S4
S4
S4
S4
S4
S4
S4
U29 pin 1U129
OFF
OFF
OFF
OFF
ON
ON
ON
pin 8
OFF
ON
ON
ON
OFF
OFF
OFF
U129
pin 9
ON
OFF
OFF
OFF
OFF
OFF
OFF
Gain
(U166)
×100
×10
×10
×10
×1
×1
×1
Table 2-16
Ω
4 signal multiplexing and gain
Troubleshooting2-17
100Ω
1kΩ
10kΩ
1MΩ
Signal
(U163)
S4 then S7
S4 then S7
S4 then S7
S4 then S7
S4 then S7
S4 then S7
S4 then S7
Range
100kΩ
10MΩ
100MΩ
Figure 2-3 provides a block diagram of the analog circuitry. Table 2-17 is provided to show
where the various switching devices are located in the block diagram.
SSP (Solid State Protection)
DCV Divider
DCV & Ohms Switching
Sense LO
AC Switching & Gain
Ohms I-Source
Current Shunts
A/D Mux & Gain
2-18Troubleshooting
Built-In T est overview
Built-In Test is used to test and exercise v arious circuits and components. The Built-In Tests
are listed in Table 2-18. Many of the tests are actual pass/fail type tests, while others are circuit
exercises that are used for subsequent tests. Each Built-In Test can be run manually. After a test
is manually run, operation is “frozen” to allow the technician to troubleshoot the circuit.
Using Built-In T est
There are several ways to run the Built-In Test, including the following recommended sequence:
1.Run the AUTO bit test (see “AUTO Testing”) and note the first (lowest numbered) test
that has failed. Always address the lo west numbered test failure first because that f ailure
could cause subsequent tests to fail.
2.Familiarize yourself with the failed circuit. See “Built-In Test Documentation” for troubleshooting information. Be sure to read the documentation for the complete series. For
example, if test 202.4 fails, read the documentation for all 202 series tests.
3.Manually run the test that failed (see “MANUAL T esting”). Keep in mind that many of
the pass/fail type tests require that one or more circuit exercise tests be run first. Using
the manual step looping mode will “freeze” instrument operation after a test is run.
4.After manually running the test, use the test documentation and your troubleshooting expertise to locate the problem.
5.After repairing the instrument, start again at step 1 to check the integrity of the repair
and to see if there are any other failures.
Table 2-18
Built-In Test summary
TestCircuit tested
Troubleshooting2-19
Bank 100
100.1
100.2
101.1
101.2
101.3
Bank 200
200.1
200.2
201.1
201.2
Bank 300
300.1
301.1
301.2
302.1
302.2
303.1
303.2
304.1
Bank 400
400.1
400.2
400.3
401.1
401.2
401.3
402.1
402.2
402.3
403.1
403.2
403.3
Bank 500
500.1
500.2
Bank 600
600.1
600.2
601.1
601.2
601.3
A/D
A/D
A/D
TestCal
TestCal
TestCal
REF/MUX
Reference
Reference
A/D Mux Lo
A/D Mux Lo
DC/OHM
Front End Lo
Hi Ohms
Hi Ohms
2W Sense
2W Sense
Lo Ohm Path
Lo Ohm Path
Input /100
VAC
Non Inv Path
Non Inv Path
Non Inv Path
Invert Path
Invert Path
Invert Path
Non Inv /10
Non Inv /10
Non Inv /10
Non Inv Bex2
Non Inv Bex2
Non Inv Bex2
SENSE
4W Sense
4W Sense
AMP/OHM
Ohm/Amp
Ohm/Amp
Amp Shunt
Amp Shunt
Amp Shunt
2-20Troubleshooting
AUTO testing
1.Press SHIFT and then TEST to access the self-test options.
2.Use the ▲ or ▼ key to display “TEST: BUILT-IN” and press ENTER.
3.Use the ▲ or ▼ key to display “BIT: AUTO” and press ENTER.
4.Use the , , ▲ or ▼ key to display the bank of tests that you wish to run and press
5.Use the , , ▲ or ▼ key to display one of the following FAULT options:
6.Press ENTER and go to step A or B:
7.After the tests are finished, any failures are displayed. With the ”FAILS” message dis-
8.When finished, use the EXIT key to back out of the test menu structure.
ENTER. Test BANK selections include:
FULLPerform all tests.
A/DPerform tests on A/D converter.
REF/MUXPerform tests on reference and multiplexer circuitry.
DC/OHMPerform tests on DC and ohm circuitry.
VACPerform tests on AC volts circuitry.
SENSEPerform tests on sense circuitry.
AMP/OHMPerform tests on amp and ohm circuitry.
PAUSEThe tests will stop (pause) when a failure (FAULT) occurs.
CONTThe tests will not stop (continue) when a failure occurs.
A. If the PAUSE fault option was selected, the tests will start immediately. The tests
stop at a failure (F AULT) and displays the test number of the failure. Press ENTER
to continue the tests or press EXIT to abort the tests.
B. If the CONT fault option was selected, use the ▲ or ▼ key to display one of the
following REPEAT options and press ENTER to start the tests:
NOPerform the specified tests and stop.
YES Continuously repeat the specified tests.
When a failure occurs, the “FAULT” message will be displayed. If the YES repeat
option was selected, use the EXIT key when ready to stop the tests.
played, use the , , ▲ or ▼ key to scroll through the test numbers of the failures.
MANUAL testing
1.Press SHIFT and then TEST to access the self-test options.
2.Use the ▲ or ▼ key to display “TEST: BUILT-IN” and press ENTER.
3.Use the ▲ or ▼ key to display “BIT: MANUAL” and press ENTER.
4.Use the and keys, or the ▲ and ▼ keys to display the desired test series number.
For example, if you wish to run test 302.2, display the series 302 test number as shown:
MANUAL: 302
5.With the desired test series number displayed, press ENTER.
6.Use the , , ▲ or ▼ key to display one of the following looping modes and press
ENTER:
SINGLE — Performs all the tests in the specified series. The instrument displays the
number of the test being run. If a failure occurs, the “FAUL T” message appears and
stays on for the remainder of the tests in the series. This testing process automatically
stops after the last test in the series is completed. This test process can also be
stopped by pressing EXIT . When EXIT is pressed, any test in process will be allo wed
to finish before aborting the testing process.
CONTINUOUS — This looping mode continuously repeats all the tests in the specified
series until the testing process is manually stopped. If a failure occurs, the “FAUL T”
message appears and stays on for the remainder of the tests in the series. This test
process can be stopped by pressing EXIT . When EXIT is pressed, any test in process
will be allowed to finish before aborting the testing process.
STEP — Used to perform one test at a time. Each press of the ENTER key performs the
displayed test. If a failure occurs, the “FAULT” message appears for that test. The
instrument automatically aborts the testing process after the last test in the series is
run. If you do not wish to run all the tests in the series, simply press EXIT after the
desired test is run.
7.After the tests are finished, any failures are displayed. With the ”FAILS” message dis-
played, use the , , ▲ or ▼ key to scroll through the test numbers of the failures.
8.When finished, use the EXIT key to back out of the test menu structure.
Troubleshooting2-21
2-22Troubleshooting
Built-In T est documentation
The following paragraphs provide a detailed description of each Built-In Test. Refer to
“Built-In Test overvie w” for basic information on ho w to use Built-In T ests. The following documentation is provided for each test:
•Test Identification — Includes test bank, number and name.
•Input Requirements — Indicates the required state of the input terminals for the test.
Note that input requirements are displayed by the Model 2000 when Built-In Test is run.
•Expected Value and Limits — Provides the measurement or reading value (and limits)
that is expected for the test as explained in the “Description”.
•Fault Message — For pass/fail type tests, a message is pro vided to summarize the cause
of the failure.
•Description — Provides a description of circuit being tested. In general, all components
in the tested circuit could be the cause of a failure.
•Bit Patterns — Provides the logic states of key shift re gisters. After a test is manually
run, you can check the registers for the correct logic levels.
NOTEThe letter “v” in a bit pattern indicates a “don’t care” condition.
×
Troubleshooting2-23
TEST BANK: A/D
T est 100.1 — A/D
BankA/D
InputsOpen
Expected V alue153661550 counts
Limits1200000 counts
Fault MessageNO A/D COMM
Description
Bit patterns
This A/D test uses the def ault conditions of the ADC w ord and the ACDC
word. This sets up the front end of the instrument to a stable configuration.
The MUX word is applied to register U130 which sets lines A0, A1 and A2
of U163 high. This bit pattern selects the S8 input, which connects signal LO
to the D output.
Signal LO is then connected to op amp U166 which is configured for
gain with feedback through mux switch U129 pin 2 to 3. Signal LO is then
connected to the A/D at A/D_IN.
In the first tests the value is in the form of counts. Signal LO is converted
to counts in the A/D and then compared to a zero by-design value. This test
checks the functionality of the A/D converter. If the 100 series tests fail, all
other tests will be invalid. Measure 0V at A/D-IN. Failures could be the A/
D MUX U163, the A/D buffer U132 and associated circuitry, or almost any
component in the A/D section. Primary checks should be the references and
power supplies, then the control circuit U165.
Bit patternRegister
QQ
87654321
—U106—
110v1111
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
This test has the identical setup as the 100.1 test. Signal LO is connected
to the A/D circuit for ten readings and a min/max comparison is done to ensure that all readings are within 100 counts of each other . The test is to check
for noise. The failures are the same as in test 100.1.
Primary checks should be the references and power supplies. Secondary
tests are the op amps of the integrator (U138 and U137), gain op amp U142,
and the zero-cross comparator U145.
Bit patternRegister
QQ
87654321
—U106—
110v1111
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
QQ
87654321
—U109—
00101111
QQ
87654321
—U134—
1v10000v
—U130—
11111101
QQ
87654321
—U121—
01110010
ACDC_STB
MUX_STB
Troubleshooting2-25
T est 101.1 — TESTCAL
BankA/D
Expected V alue<none specified>
Limits<none specified>
InputsOpen
Description
Bit patterns
TESTCAL is a way to calibrate the unit with internal references so that
the remaining tests can be displayed in the form of voltages. Gi ven that there
are errors in the internal references and in the A/D circuitry, the voltages on
the display of the unit may vary from the value that is measured at A/D-IN
with a calibrated test meter. The values on the display of the unit under test
are values that are relative to the internal references.
This test has the same set up as the 100.1 and 100.2 tests. The A/D mak es
a conversion of the signal zero and stores the v alue in the form of A/D counts
to be used in the next phase of the test. There is no fault message for this test.
Measure 0V at A/D-IN.
Bit patternRegister
QQ
87654321
—U106—
110v1111
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
This A/D test uses the def ault conditions of the ADC w ord and the ACDC
word. This sets up the front end of the instrument to a stable configuration.
The MUX word is applied to register U130 which sets the lines of U163 as
follows; A0 and A1 lo w, A2 high. This bit pattern selects the S5 input, which
connects REFHI to the D output.
REFHI is then connected to op amp U166 which is configured for
with feedback through mux switch U129 pin 2 to 3. The buffered value of
REFHI is then connected to the A/D at A/D-IN.
A conversion is tak en in the form of A/D counts and compared to the v alue
taken in test 101.1. The value in counts of test 101.2 minus the value in
counts of test 101.1 yields a value that is compared to a v alue by-design for
REFHI. If this value is within the limits, the REFHI reference, which is 7
volts, is considered acceptable. Measure 7V at A/D-IN. Failures could be the
MUX (U163), or the reference circuit (U141) and the associated circuitry.
Bit patternRegister
QQ
87654321
—U106—
110v1111
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
QQ
87654321
—U109—
00101111
QQ
87654321
—U134—
1v10000v
—U130—
11001101
QQ
87654321
—U121—
01110010
1 gain
ACDC_STB
MUX_STB
×
Troubleshooting2-27
T est 101.3 — TESTCAL
BankA/D
InputsOpen
Expected V alue1.03 volts
Limits0.06 volts
Fault MessageNO 1V AT A/D
Description
Bit patterns
This test uses the default conditions of the ADC word and the ACDC
word. This sets up the front end of the instrument to a stable configuration.
The MUX word sets shift register U130 to disable U163 by setting line /EN
low. The /EN line is also connected to pin 16 of U129 which closes the mux
switch for pins 14 and 15. This connects the voltage between R189 and R185
(around 1.03 volts) to op amp U166, which is configured for
feedback through U129 (pin 2 to 3). The buf fered value of the signal is then
connected to the A/D at A/D-IN.
A conversion is tak en and compared to the calibration values in tests 101.1
and 101.2, and displayed as a voltage. Measure 1.03V at A/D-IN. Primary
tests are on the resistor divider (R189, R185, and R188), the MUX U163, and
the signal path from the resistor divider.
Bit patternRegister
QQ
87654321
—U106—
110v1111
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
QQ
87654321
—U109—
00101111
QQ
87654321
—U134—
1v10000v
—U130—
11111100
QQ
87654321
—U121—
01110010
1 gain with
ACDC_STB
MUX_STB
×
×
2-28Troubleshooting
TEST BANK: REF/MUX
T est 200.1 — REFERENCE
BankREF/MUX
InputsOpen
Expected V alue1 volt
Limits0.1 volts
Fault Message1VREF/AD X10
×
Description
Bit patterns
The 7V REFHI signal is routed through R189 and R185, which forms a
0.014/1 voltage divider with R188. The 0.1V result (0.014
then applied to S1 of U163. The A0, A1 and A2 bit pattern on U163 is set to
connect the S1 signal (0.1V) to the D output. The signal is then routed
through R159, Q117 and R166 to the non-inverting input of op amp U166.
A/D MUX (U166) is configured for
on U129 analog switch; pins 6 to 7). Feedback resistors R309 and R310 configure the
QQ
87654321
—U106—
110v1111
10 gain. Measure 1V at AD_IN.
Bit patternRegister
QQ
87654321
—U109—
00101111
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
10 gain (/ × 10 control line is low turning
QQ
87654321
—U134—
1v10000v
—U130—
10000111
QQ
87654321
—U121—
01110010
7V = 0.1V) is
ACDC_STB
MUX_STB
×
T est 200.2 — REFERENCE
BankREF/MUX
InputsOpen
Expected V alue10 volts
Limits1 volt
Fault MessageAD X100
Troubleshooting2-29
Description
Bit patterns
Same as test 200.1 except the A/D MUX is configured for × 100 gain (/
100 control line is low). The gain path is through U129 pin 10 to 11. Resis-
tor network R271 is used to configure the x100 gain. Measure 10V at AD_IN.
Bit patternRegister
QQ
87654321
—U106—
110v1111
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
QQ
87654321
—U109—
00101111
QQ
87654321
—U134—
1v10000v
—U130—
10001011
QQ
87654321
—U121—
01110010
ACDC_STB
MUX_STB
2-30Troubleshooting
T est 201.1 — A/D MUX LO
BankREF/MUX
InputsOpen
Expected V alue0 volts
Limits0.0001 volts
Fault MessageSENSE LO 0
×
Description
Bit patterns
Signal LO is routed through R181 and Q122 (/LOMUXA control line
high) into unity gain amp U126. Signal LO is then routed to S7 of U163. The
A0, A1 and A2 bit pattern on U163 connects S7 to the D output, which then
routes signal LO through Q117 to U166.
The A/D MUX (U166) is configured for
closing U129; pin 2 to 3. Measure 0V at AD_IN.
Bit patternRegister
QQ
87654321
—U106—
110v1111
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
QQ
87654321
—U109—
00101111
QQ
87654321
—U134—
1v10000v
—U130—
11011101
1 gain (/ × 1 control line low) by
QQ
87654321
—U121—
01110010
ACDC_STB
MUX_STB
×
T est 201.2 — A/D MUX LO
BankREF/MUX
InputsOpen
Expected V alue0 volts
Limits0.0001 volts
Fault MessageMUX LO
Troubleshooting2-31
Description
Bit patterns
This test is similar to test 201.1, except signal LO is routed through R274
to S8 of U163. Signal LO is then routed through Q117 to U166, which is configured for
QQ
87654321
—U106—
110v1111
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
1 gain. Measure 0V at AD_IN.
Bit patternRegister
QQ
87654321
—U109—
00101111
QQ
87654321
—U134—
1v10000v
—U130—
11111101
QQ
87654321
—U121—
01110010
ACDC_STB
MUX_STB
2-32Troubleshooting
TEST BANK: DC/OHM
T est 300.1 — FRONT END LO
BankDC/OHM
InputsOpen
Expected Value 0 volts
Limits0.01 volts
Fault MessageFRONT END LO
×
Description
Bit patterns
This test is for the DC volts front end LO path. Control line DIVLO is high
making the U120 comparator output (pin 2) open collector. Q114 is on due
to the gate being pulled low by R164. Signal LO is connected to SIG/100
through Q114 and divider R117.
The DIVT AP control line at U115 (pin 11) is pulled high to turn on Q108.
This routes SIG/100 LO through Q108 to the unity gain buffer U113. The
signal at the output of U113 is now called BUFCOM and goes through R314
to S4 of U163. It then goes to the A/D MUX which is confi gured for
Measure 0V at AD_IN.
Bit patternRegister
QQ
87654321
—U106—
110v1111
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
NOTE K101 and K102 are latching r elays. Any r eference to their contr ol line settings implies
that this setting, normally high (+5V), may be present for less than 100 milliseconds.
Remember this if attempting to troubleshoot these parts, especially when running the
BIT test in the MANUAL STEP mode.
+7V is generated by buffering REFHI with op amp U139. This +7V,
which is used by the ohms circuit as a voltage reference, is switched by U133
(/7V control line low) to op amp U123 which is a unity gain buffer.
The +7V reference, now labeled REFBOOT, is routed through R272,
Q109 (/HIOHM control line low), the 9.9M
K101 (RESETK2 control line high), R304, Q104 (LOV control line high) to
U113. The unity gain output of U113 (BUFCOM) then goes to the A/D MUX
as in test 300.1 with a gain of
1. Measure +7V at AD_IN.
half of R117, Q101, Q102,
Bit patterns
Bit patternRegister
QQ
87654321
—U106—
110v1111
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
This test is the same as 301.1 except that the +13.3V ohms reference is
tested. The +13.3V reference is generated by the same circuit as the +7V reference. 14V is routed through Q130 and then applied to a 1K/10K divider
which is part of R271. The +13.3V divider output is routed through analog
switch U133 (/.7V control line low) to op amp U123. The remainder of the
path is the same as test 300.1.
The expected voltage at AD_IN would be +13.3V except that at the source
lead of Q104 (labeled SOURCE) there is a clamping circuit. Back-to-back
11V zener diodes VR105 and VR106, and photo-coupler U107 clamp the
voltage at the SOURCE node to about +12.4V. Measure +12.4V at AD_IN.
Bit patternRegister
QQ
87654321
—U106—
110v1111
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
QQ
87654321
—U109—
00101111
QQ
87654321
—U134—
0v01001v
—U130—
10111101
QQ
87654321
—U121—
10000100
ACDC_STB
MUX_STB
T est 302.1 — 2W SENSE
BankDC/OHM
InputsOpen
Expected V alue7 volts
Limits0.7 volts
Fault Message2W SENSE 7V
Ω
×
Troubleshooting2-35
Description
Bit patterns
The +7V reference is again switched to REFBOOT, and routed through
R272, Q109, the 9.9M
R115, R324 and L109, and then through R113, R107, R103, R108, and
K101. At this point, the reference is labeled 2WSEN_I.
Reference 2WSEN_I is then routed through K102 (control line SETK1
high) to the 2WSEN_O node. This node then goes through Q105 (2W control
line high), to U113 (BUFCOM) and to the A/D MUX with
+7V at AD_IN.
QQ
87654321
—U106—
110v1111
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
half of divider R117, the parallel combination of
Bit patternRegister
QQ
87654321
—U109—
00011111
QQ
87654321
—U134—
0v10000v
—U130—
10111101
QQ
87654321
—U121—
10000010
1 gain. Measure
ACDC_STB
MUX_STB
2-36Troubleshooting
T est 302.2 — 2W SENSE
BankDC/OHM
InputsOpen
Expected V alue12.4 volts
Limits0.5 volts
Fault Message2W SENSE 13V
Description
Bit patterns
Same as test 302.1 except the +13.3V reference is used. This v oltage does
not go through the ohms zener clamp path but is clipped by the A/D circuit
itself at about 12.4V due to the fact that 13.3V approaches the power supply
limits of the op amps. Measure +12.4V at AD_IN.
Bit patternRegister
QQ
87654321
—U106—
110v1111
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
This test uses the ohms circuit. The +7V reference is switched to REFBOOT by closing U133 (/7V line lo w). Q123 and Q125 are turned on by setting the OHMA control line high. +14V is applied directly to R194. Since
Q123 is on, +7V appears on the other side of R194. As a result, the voltage
drop across R194 (7.06k
R194, Q125, Q119, CR114, and Q120 (/LOWOHM control line low).
The current (labeled OHM) then flows through R304, U107, VR106, and
VR105 to LO. The +7V reference is routed through Q104, to BUFCOM, and
on to the A/D MUX with a gain of
QQ
87654321
—U106—
110v1111
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
This test is similar to test 303.1. The +13.3V reference is switched to REFBOOT again by closing U133 pins 6 to 7. Q124 and Q126 are turned on by
setting the OHMA control line low . +14V is applied to R195, and since Q124
is on, +13.3V appears on the other end of R195. The voltage across R195
(70.6K
and Q120 (/LOWOHM control line low).
VR105 to LO. This is again the clamping circuit described in test 301.2. The
+12.4V reference is routed through Q104, to BUFCOM, and on to the A/D
MUX with a gain of
) is 0.7V. 10µA therefore flows through R195, Q126, Q119, CR114,
The current (labeled OHM) then flows through R304, U107, VR106, and
1. Measure +12.4V at AD_IN.
Bit patternRegister
QQ
87654321
—U106—
110v1111
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
The ohms circuit current is set up the same as test 303.1. A 1mA current
flows into the OHM node but instead of flowing into the clamping circuit, it
flows through K101 (RESETK2 control line high) through Q102, Q101,
R117, and Q114 to LO.
Resistor R117 is a 100 to 1 divider. Therefore, 0.07V (7V/100) is seen at
the SIG/100 node. Q108 is turned on to switch the 0.07V through U113
(BUFCOM) to the A/D MUX which is configured for
+7V at AD_IN.
Bit patternRegister
QQ
87654321
—U106—
110v1111
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
This test places the ACV front end in the non-inverting configuration.
Logic levels for this configuration are as follows:
K102: /SETK1 low, /RESETK1 high
U103: Pins 8 and 9 low
U105: Pin 9 high
The signal path is from A CIN through K102 to the plus input of U102. Resistors R117 (9.9M
feedback path for U102 is from the minus input through U103 (pins 6 and 7)
to node A CFE. Node ACFE is connected to U112 through U103 (pin 1 low).
Op amp U112 is configured for
through U105 (pin 1 low). The signal is then coupled across C115 to U118.
Analog switch U111 (pin 16 low) is closed to set up U118 for unity gain.
The output of U118 goes to U110 (TRMS conv erter) through the parallel
combination of R129, C113 and C114. The output of the TRMS converter
(OUT) is fed back through its own internal buffer. The buffer output signal
(BUFF OUT) is then labeled AC_MED. The AC_MED signal is selected at
U163 and fed to the A/D b uffer (U166) through Q117. The A/D buffer is set
up for
1 gain through U129 (/ × 1 low). This test is a setup phase for the ne xt
test.
) and R146 (1.1M Ω ) to form a ÷ 10 at the input. The
10 gain. The output of U112 is routed
Bit patternRegister
QQ
87654321
—U106—
110v1111
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
The previous test sets up the circuit for this test. There is a routine in software that generates a waveform for the ACV tests. This is done by selecting
the 13.3V reference by closing analog switch U133 (/.7V control line low).
The reference is buffered by U123 is labeled REFBOOT.
The REFBOOT signal is switched into the front end through Q109 via
U120 by toggling the /HIOHM line. This switching routine is done in firmware. Q114 and Q136 are turned ON (conducting to ground) by U120 (DIVLO control line low). The 100k
to clean up the switched signal REFBOOT.
The signal path continues through Q101, Q102 and K101 to ACIN. The
switched ACIN signal (coupled across C105) is applied to the circuit described in test 400.1 and the measurement is made.
The input signal switching stops while the A/D takes the reading. Signal
switching continues after the reading is done. There are delays before the
reading is taken to ensure that the ACV section and filters have enough time
to reach a charged full scale reading. In this phase, the switched signal can
be traced through the circuit described in test 400.1. Measure 5.6 volts DC at
A/D_IN.
Bit patternRegister
QQ
87654321
—U106—
110v1111
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
QQ
87654321
—U109—
10011111
leg of R117 acts as a pull-up and pull-down
QQ
87654321
—U134—
1v01000v
—U130—
10011101
QQ
87654321
—U121—
01110000
ACDC_STB
MUX_STB
2-42Troubleshooting
T est 400.3 — NON INV P A TH
BankVAC
InputsOpen
Expected V alue<none specified>
Limits<none specified>
Fault Message<none>
Description
Bit patterns
This phase resets the circuit to a known state and turns the waveform signal off. Subsequent tests require that the A/D be in the normal operating
mode.
Bit patternRegister
QQ
87654321
—U106—
101v0001
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
QQ
87654321
—U109—
10011111
QQ
87654321
—U134—
1v01000v
—U130—
10011101
QQ
87654321
—U121—
01110000
ACDC_STB
MUX_STB
Troubleshooting2-43
T est 401.1 — INVERT P A TH
BankVAC
InputsOpen
Expected V alue<none specified>
Limits<none specified>
Fault Message<none>
DescriptionThis test places the ACV front end in the inverting configuration. Logic
levels for this configuration are as follows:
K102: /SETK1 high, /RESETK1 low
U103: Pins 8 and 9 high
U105: Pin 9 low
Bit patterns
The signal path is from A CIN through C105, R104 and R105, which make
up a 1.1MΩ input resistance to the minus input of op amp U102. The plus
input of U102 is connected to AC common through R146. Feedback for
U102 is provided by R106 (11kΩ). The output gain for U102 (seen at A CFE)
is ×0.001 (R106/(R117+R104+R105)).
The output of U102 (ACFE) is routed through U103 (pin 1 low) to U112
which is configured for ×10 gain. The signal then goes through U105 (pin 1
low) and is coupled across C115 to U118 which is configured for ×2 gain.
The output of U118 goes to the TRMS converter (U110) through the parallel combination of R129, C113 and C114. The output of the TRMS converter (OUT) is fed back through its own internal buffer. The buffer output
signal (BUFF OUT) is then labeled AC_MED. The AC_MED signal is selected at U163 and fed to the A/D buffer (U166) through Q117. The A/D
buffer is set up for ×1 gain through U129 (/×1 lo w). This test is a setup phase
for the next test.
Bit patternRegister
QQ
87654321
—U106—
101v1101
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
DescriptionThe previous test sets up the circuit for this test. There is a routine in soft-
ware that generates a waveform for the ACV tests. This is done by selecting
the 13.3V reference by closing analog switch U133 (/.7V control line low).
The reference is buffered by U123 is labeled REFBOOT.
The REFBOOT signal is switched into the front end through Q109 via
U120 by toggling the /HIOHM line. This switching routine is done in firmware. Q114 and Q136 are turned ON (conducting to ground) by U120 (DIVLO control line low). The 100kΩ le g of R117 acts as a pull-up and pull-down
to clean up the switched signal REFBOOT.
The signal path continues through Q101, Q102 and K101 to ACIN. The
switched ACIN signal (coupled across C105) is applied to the circuit described in test 401.1 and the measurement is made.
Bit patterns
The input signal switching stops while the A/D takes the reading. Signal
switching continues after the reading is done. There are delays before the
reading is taken to ensure that the ACV section and filters have enough time
to reach a charged full scale reading. In this phase,the switched signal can be
traced through the circuit described in test 401.1. Measure 108mV DC at A/
D_IN.
Bit patternRegister
QQ
87654321
—U106—
101v1101
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
QQ
87654321
—U109—
01101111
QQ
87654321
—U134—
1v01000v
—U130—
10011101
QQ
87654321
—U121—
01110000
ACDC_STB
MUX_STB
Troubleshooting2-45
T est 401.3 — INVERT P A TH
BankVAC
InputsOpen
Expected V alue<none specified>
Limits<none specified>
Fault Message<none>
DescriptionThis phase resets the circuit to a known state and turns the waveform sig-
nal off. Subsequent tests require that the A/D be in the normal operating
mode.
Bit patterns
Bit patternRegister
QQ
87654321
—U106—
101v1101
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
QQ
87654321
—U109—
01101111
QQ
87654321
—U134—
1v01000v
—U130—
10011101
QQ
87654321
—U121—
01110000
ACDC_STB
MUX_STB
2-46Troubleshooting
T est 402.1 — NON INV /10
BankVAC
InputsOpen
Expected V alue<none specified>
Limits<none specified>
Fault Message<none>
DescriptionThis test places the ACV front end in the non-inverting configuration.
Logic levels for this configuration are as follows:
K102: /SETK1 low, /RESETK1 high
U103: Pins 8 and 9 low
U105: Pin 9 high
The signal path is from A CIN through K102 to the plus input of U102. Resistors R117 (9.9MÍ) and R146 (1.1MΩ) to form a ÷10 at the input. The feedback path for U102 is from the minus input through U103 (pins 6 and 7) to
node ACFE.
The signal at A CFE is di vided by 10 through R110 to make A CFE/10. The
ACFE/10 signal bypasses U112 through U105 (pin 8 set LO). The signal is
then coupled across C115 to U118 which is configured for ×2 gain.
Bit patterns
The output of U118 goes to U110 (TRMS conv erter) through the parallel
combination of R129, C113 and C114. The output of the TRMS converter
(OUT) is fed back through its own internal buffer. The buffer output signal
(BUFF OUT) is then labeled AC_MED. The AC_MED signal is selected at
U163 and fed to the A/D b uffer (U166) through Q117. The A/D buffer is set
up for ×1 gain through U129 (/×1 low). This test is a setup phase for the ne xt
test.
Bit patternRegister
QQ
87654321
—U106—
110v0011
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
DescriptionThe previous test sets up the circuit for this test. There is a routine in soft-
ware that generates a waveform for the ACV tests. This is done by selecting
the 13.3V reference by closing analog switch U133 (/.7V control line low).
The reference is buffered by U123 is labeled REFBOOT.
The REFBOOT signal is switched into the front end through Q109 via
U120 by toggling the /HIOHM line. This switching routine is done in firmware. Q114 and Q136 are turned ON (conducting to ground) by U120 (DIVLO control line low). The 100kΩ le g of R117 acts as a pull-up and pull-down
to clean up the switched signal REFBOOT.
The signal path continues through Q101, Q102 and K101 to ACIN. The
switched ACIN signal (coupled across C105) is applied to the circuit described in test 402.1 and the measurement is made.
Bit patterns
The input signal switching stops while the A/D takes the reading. Signal
switching continues after the reading is done. There are delays before the
reading is taken to ensure that the ACV section and filters have enough time
to reach a charged full scale reading. In this phase, the switched signal can
be traced through the circuit described in test 402.1. Measure 108mV DC at
A/D_IN.
Bit patternRegister
QQ
87654321
—U106—
110v0011
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
QQ
87654321
—U109—
11011111
QQ
87654321
—U134—
1v01000v
—U130—
10011101
QQ
87654321
—U121—
01110000
ACDC_STB
MUX_STB
2-48Troubleshooting
T est 402.3 — NON INV /10
BankVAC
InputsOpen
Expected V alue<none specified>
Limits<none specified>
Fault Message<none>
DescriptionThis phase resets the circuit to a known state and turns the waveform sig-
Bit patterns
nal off. Subsequent tests require that the A/D be in the normal operating
mode.
Bit patternRegister
QQ
87654321
—U106—
110v0011
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
QQ
87654321
—U109—
11011111
QQ
87654321
—U134—
1v01000v
—U130—
10011101
QQ
87654321
—U121—
01110000
ACDC_STB
MUX_STB
Troubleshooting2-49
T est 403.1 — NON INV BEX2
BankVAC
InputsOpen
Expected V alue<none specified>
Limits<none specified>
Fault Message<none>
DescriptionThis test places the ACV front end in the non-inverting configuration.
Logic levels for this configuration are as follows:
K102: /SETK1 low, /RESETK1 high
U103: Pins 8 and 9 low
U105: Pin 9 high
The signal path is from A CIN through K102 to the plus input of U102. Resistors R117 (9.9MΩ) and R146 (1.1MΩ) to form a ÷10 at the input. The
feedback path for U102 is from the minus input through U103 (pins 6 and 7)
to node A CFE. The A CFE signal bypasses U112 through U103 (pin 16 lo w).
The signal is then coupled across C115 to U118 which is configured for x2
gain.
Bit patterns
The output of U118 goes to U110 (TRMS conv erter) through the parallel
combination of R129, C113 and C114. The output of the TRMS converter
(OUT) is fed back through its own internal buffer. The buffer output signal
(BUFF OUT) is then labeled AC_MED. The AC_MED signal is selected at
U163 and fed to the A/D b uffer (U166) through Q117. The A/D buffer is set
up for ×1 gain through U129 (/×1 low). This test is a setup phase for the ne xt
test.
Bit patternRegister
QQ
87654321
—U106—
011v0011
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
DescriptionThe previous test sets up the circuit for this test. There is a routine in soft-
ware that generates a waveform for the ACV tests. This is done by selecting
the 13.3V reference by closing analog switch U133 (/.7V control line low).
The reference is buffered by U123 is labeled REFBOOT.
The REFBOOT signal is switched into the front end through Q109 via
U120 by toggling the /HIOHM line. This switching routine is done in firmware. Q114 and Q136 are turned ON (conducting to ground) by U120 (DIVLO control line low). The 100kΩ le g of R117 acts as a pull-up and pull-down
to clean up the switched signal REFBOOT.
The signal path continues through Q101, Q102 and K101 to ACIN. The
switched ACIN signal (coupled across C105) is applied to the circuit described in test 403.1 and the measurement is made.
Bit patterns
The input signal switching stops while the A/D takes the reading. Signal
switching continues after the reading is done. There are delays before the
reading is taken to ensure that the ACV section and filters have enough time
to reach a charged full scale reading. In this phase, the switched signal can
be traced through the circuit described in test 403.1. Measure 1.08V DC at
A/D_IN.
Bit patternRegister
QQ
87654321
—U106—
011v0011
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
QQ
87654321
—U109—
11011111
QQ
87654321
—U134—
1v01000v
—U130—
10011101
QQ
87654321
—U121—
01110000
ACDC_STB
MUX_STB
Troubleshooting2-51
T est 403.3 — NON INV BEX2
BankVAC
InputsOpen
Expected V alue<none specified>
Limits<none specified>
Fault Message<none>
DescriptionThis phase resets the circuit to a known state and turns the waveform sig-
nal off. Subsequent tests require that the A/D be in the normal operating
mode.
Bit patterns
Bit patternRegister
QQ
87654321
—U106—
011v0011
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
QQ
87654321
—U109—
11011111
QQ
87654321
—U134—
1v01000v
—U130—
10011101
QQ
87654321
—U121—
01110000
ACDC_STB
MUX_STB
2-52Troubleshooting
TEST BANK: SENSE
T est 500.1 — 4W SENSE
BankSENSE
Inputs4-wire short
Expected V alue0 volts
Limits0.0001 volts
Fault MessageSENSE LO
DescriptionThis test requires a 4-wire short at the input. The SLO node is the Sense
Bit patterns
LO jack on the front or rear panel. The 4-wire short connects SLO to LO. The
0V signal at SLO is routed through R132, R139, R148, R163, and Q121 to
U126, which is configured as a unity gain buffer. The 0V output of U126 is
routed to S7 of U163 where it is switched to the A/D MUX (×1 gain). Measure 0V at AD_IN.
Bit patternRegister
QQ
87654321
—U106—
110v1111
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
QQ
87654321
—U109—
00101111
QQ
87654321
—U134—
1v10000v
—U130—
01011101
QQ
87654321
—U121—
01110010
ACDC_STB
MUX_STB
Troubleshooting2-53
T est 500.2 — 4W SENSE
BankSENSE
Inputs4-wire short
Expected V alue0 volts
Limits0.0001 volts
Fault MessageSENSE HI
DescriptionThis test requires a 4-wire short at the input. The SHI node is the Sense HI
jack on the front or rear panel. The 4-wire short connects SHI to LO. The 0V
signal at SHI is routed through R120, R124, R121, R125 and Q113 (4W control line high) to U113 BUFCOM. As in previous tests, this signal goes to the
A/D MUX which is configured for ×1 gain. Measure 0V at AD_IN.
Bit patterns
Bit patternRegister
QQ
87654321
—U106—
110v1111
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
QQ
87654321
—U109—
00101111
QQ
87654321
—U134—
1v10000v
—U130—
10111101
QQ
87654321
—U121—
01101000
ACDC_STB
MUX_STB
2-54Troubleshooting
TEST BANK: AMP/OHM
T est 600.1 — OHM/AMP
BankAMP/OHM
InputsINPUT HI to AMPS Short
Expected V alue0.0095 volts
Limits0.001 volts
Fault Message1mA SOURCE
DescriptionThis test requires a jumper wire from the INPUT HI jack to the AMPS
jack on the front panel. The +7V reference is switched to the ohms circuit
through U133. Q123 and Q125 are turned on to generate a 1mA current that
is routed to the INPUT HI jack. The signal path for this 1mA current is from
the +14V node through R194, Q125, Q119, Q120, K101 (pins 3 to 4) Q102,
Q101, through the parallel combination of R115, L109, and R324, then to the
INPUT HI jack.
The jumper wire then routes the 1mA into the AMPS jack through K103
(SETK3 control line high so that pins 3 to 4 and 7 to 8 are closed). This puts
R205 in series with R158 for a total of 10.1Ω. The 1mA current through
10.1Ω generates around 10mV which is sensed through S101 and R142 to
the AMPSHUNT node. The AMPSHUNT signal is routed to S6 of U163
where it is switched to the A/D MUX. The A/D MUX is configured for ×1
gain. Measure 10mV at AD_IN.
Bit patterns
Bit patternRegister
QQ
87654321
—U106—
110v1111
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
QQ
87654321
—U109—
00101111
QQ
87654321
—U134—
1v10111v
—U130—
11101101
QQ
87654321
—U121—
10110010
ACDC_STB
MUX_STB
Troubleshooting2-55
T est 600.2 — OHM/AMP
BankAMP/OHM
Inputs INPUT HI to AMPS short
Expected V alue0.025 volts
Limits0.015 volts
Fault Message.1 OHM SHUNT
DescriptionThis test requires a jumper wire from the INPUT HI jack to the AMPS
jack on the front panel. The +7V reference is switched to the ohms circuit
through U133. Q123 and Q125 are turned on to generate a 1mA current that
is routed to the INPUT HI jack. The signal path for this 1mA current is from
the +14V node through R194, Q125, Q119, Q120, K101 (pins 3 to 4) Q102,
Q101, through the parallel combination of R115, L109, and R324, then to the
INPUT HI jack.
The jumper wire then routes the 1mA into the AMP jack and through
K103 (SETK3 control line low so that pins 2 to 3 and 8 to 9 are closed). This
bypasses R205 and routes the 1mA through the 0.1Ω ohm resistor (R158). A
1mA current through 0.1Ω generates around 100µV which is sensed through
S101 and R142 to the AMPSHUNT node.
Bit patterns
The AMPSHUNT signal is routed to S6 of U163 where it is switched to
the A/D MUX. The A/D MUX is configured for ×100 gain. Since this is a
very small voltage, trace resistance and circuit offsets greatly affect the expected voltage of 10mV. This test is useful to detect the presence of the proper component operation and not so much their precision. Measure
approximately 25mV at AD_IN.
Bit patternRegister
QQ
87654321
—U106—
110v1111
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
QQ
87654321
—U109—
00101111
QQ
87654321
—U134—
1v10011v
—U130—
11101011
QQ
87654321
—U121—
10110010
ACDC_STB
MUX_STB
2-56Troubleshooting
T est 601.1 — AMP SHUNT
BankAMP/OHM
InputsINPUT HI to AMPS short
Expected V alue<none specified>
Limits<none specified>
Fault Message<none>
DescriptionThis test requires an external jumper wire be installed from the INPUT HI
jack to the AMPS jack on the front panel. There is a routine in software that
generates a test signal current for the ACV AMP test. This signal generation
is described in test 601.2.
The test signal is routed through the front end circuit to the front panel INPUT HI jack. The jumper connects the test signal to the front panel AMPS
jack. The test signal is routed through K103 (pins 3 and 8 to pins 4 and 7. The
signal current then flows through the series combination of R205 (10Ω) and
R158 (0.1Ω) to ground. This generates an AC voltage that is connected to
AMPSHNT through S101 and R142.
The A CV front end is set up for the non-in verting configuration as follows:
K102: /SETK1 low, /RESETK1 high
U103: Pins 8 and 9 low
U105: Pin 9 high
The AMPSHNT signal is routed through U105 (pin 16 lo w) to the plus input of U112 which is configured for ×10 gain. The output signal of the op
amp is routed through U105 (pin 1 low) and coupled across C115 to U118
which is configured for ×2 gain.
The output of U118 goes to U110 the TRMS con verter through R129 and
the parallel C113 and C114. U110 OUT pin 11 is feed through its own inter nal buffer pin 1 to 16 and the signal out is AC_MED. AC_MED signal is selected at U163 pin 6 to 8 and fed to A/D buffer U166 through Q117. The A/
D buffer is set up for ×1 gain through U129 pin 3 to 2 with / ×1 lo w. This test
is the setup phase for the next test phase.
Bit patterns
Troubleshooting2-57
Bit patternRegister
QQ
87654321
—U106—
110v0010
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
QQ
87654321
—U109—
11011111
QQ
87654321
—U134—
1v10110v
—U130—
10011101
QQ
87654321
—U121—
10110000
ACDC_STB
MUX_STB
2-58Troubleshooting
T est 601.2 — AMP SHUNT
BankAMP/OHM
InputsINPUT HI to AMPS Short
Expected V alue0.084 volts
Limits0.02 volts
Fault MessageAC AMP SHUNT
DescriptionThe previous test sets up the circuit for this test. There is a routine in soft-
ware that generates a waveform for the ACV tests. This is done by selecting
the 7V reference by closing analog switch U133 (/7V controlline low). The
reference is buffered by U123.
Control line OHMA line is high turning Q123 and Q125 on which generates a 1mA current source with R195, op amp U123, Q119, and associated
circuitry. The /LOWOHM control line of U133 is switched to toggle Q120
on and off to generate the 1mA AC current to the OHM node.
This test current is then switched through K101 (pin 4 to 3). Control line
/SETK2 is high and /RESETK2 is low. The test current goes through Q102,
Q101, the parallel combination of R115, L109, and R324, then to the INPUT
HI jack.
Bit patterns
The switched current signal is applied to the circuit described in the previous test and a measurement is made. The input signal switching stops while
the A/D is taking the reading, then continues when the measurement is complete. There are delays before the reading is taken to ensure that the A CV section and filters have enough time to reach a charged stable reading. For this
test, the switched signal can be traced through the circuit described in the previous test. Measure 84mV DC at A/D_IN.
Bit patternRegister
QQ
87654321
—U106—
101v0010
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
QQ
87654321
—U109—
11011111
QQ
87654321
—U134—
1v10110v
—U130—
10011101
QQ
87654321
—U121—
10110000
ACDC_STB
MUX_STB
Troubleshooting2-59
T est 601.3 — AMP SHUNT
BankAMP/OHM
InputsINPUT HI to AMPS Short
Expected V alue<none specified>
Limits<none specified>
Fault Message<none>
DescriptionThis phase resets the circuit to a known state and turns the waveform sig-
nal off. Subsequent tests require that the A/D be in the normal operating
mode.
Bit patterns
Bit patternRegister
QQ
87654321
—U106—
101v0010
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
QQ
87654321
—U109—
11011111
QQ
87654321
—U134—
1v10110v
—U130—
10011101
QQ
87654321
—U121—
10110000
ACDC23
MUX_STB
_STB
3
Disassembly
3-2Disassembly
Introduction
This section explains how to handle, clean, and disassemble the Model 2000 Multimeter . This
section is organized as follows:
•Handling and cleaning — Describes how to properly handle, clean, and solder PC
boards.
•Static sensitive devices — Explains how to handle ICs and CMOS devices.
•Assembly drawings — Provides mechanical drawings to assist in the disassembly and
re-assembly of the Model 2000.
•Case cover removal — Provides the procedure for removing the case to gain access to
the internal components.
•Motherboard removal — Provides the procedure for removing the motherboard.
•Front panel disassembly — Provides the procedure for removing the display board and
front panel switch pad.
•Firmware replacement — Provides the procedure for removing and replacing the Model
2000 firmware.
•Removing power components — Explains how to remove the power transformer and
power module.
•Instrument re-assembly — Provides general guidelines for re-assembling the Model
2000.
Disassembly3-3
Handling and cleaning
T o avoid contaminating PC board traces with body oil or other foreign matter, avoid touching
the PC board traces while you are repairing the instrument. Motherboard areas covered by the
shield have high impedance devices or sensitive circuitry where contamination could cause degraded performance.
Handling PC boards
Observe the following precautions when handling PC boards:
•Wear cotton gloves.
•Only handle PC boards by the edges and shields.
•Do not touch any board traces or components not associated with repair.
•Do not touch areas adjacent to electrical contacts.
•Use dry nitrogen gas to clean dust off PC boards.
Solder repairs
Observe the following precautions when you must solder a circuit board:
•Use an OA-based (organic activated) flux, and take care not to spread the flux to other
areas of the circuit board.
•Remove the flux from the work area when you ha ve finished the repair by using pure water with clean, foam-tipped swabs or a clean, soft brush.
•Once you have remov ed the flux, only swab the repair area with methanol, then blo w dry
the board with dry nitrogen gas.
•After cleaning, allow the board to dry in a 50°C, low-humidity environment for several
hours.
3-4Disassembly
Static sensitive devices
CMOS devices operate at very high impedance levels for low power levels. Therefore, any
static that builds up on you or your clothing may be sufficient to destro y these devices if the y are
not handled properly. Use the following precautions to avoid damaging them:
CAUTIONMany CMOS devices are installed in the Model 2000. Handle all semicon-
ductor devices as static sensitive.
•Only transport and handle ICs in containers specially designed to prevent static b uild-up.
T ypically, you receive these parts in anti-static containers made of plastic or foam. Keep
these devices in their original containers until ready for installation.
•Remove the devices from their protective containers only at a properly grounded work
station. Also, ground yourself with a suitable wrist strap.
•Handle the devices only by the body; do not touch the pins.
•Also ground any printed circuit board into which a semiconductor device is to be inserted to the bench or table.
•Only use anti-static type solder sucker.
•Only use grounded tip solder irons.
•Once the device is installed in the PC board, it is normally adequately protected, and you
can handle the boards normally.
Assembly drawings
Use the following assembly drawings to assist you as you disassemble and re-assemble the
Model 2000. Also, refer to these drawings for information about the Keithley part numbers of
most mechanical parts in the unit. The drawings are located at the end of this section of the manual.
•Front Panel Assembly — 2000-040
•Chassis/Transformer Power Module Assembly — 2000-050
•Front Panel/Chassis Assembly — 2000-051
•Chassis Assembly — 2000-052
Disassembly3-5
Case cover removal
If you need to troubleshoot the instrument or replace a component, you must gain access to
the components by removing the case.
WARNINGBefore removing the case cover, disconnect the line cord and any test leads from the instru-
ment.
1.Remove Handle — The handle serves as an adjustable tilt-bail. Adjust its position by
gently pulling it away from the sides of the instrument case and swinging it up or do wn.
To remove the handle, swing the handle below the bottom surface of the case and back
until the orientation arrows on the handles line up with the orientation arrows on the
mounting ears. With the arrows lined up, pull the ends of the handle from the case.
2.Remove Mounting Ears — Remov e the screw that secures each mounting ear . Pull do wn
and out on each mounting ear.
NOTE When re-installing the mounting ears, make sure to mount the right ear to the right
side of the chassis, and the left ear to the left side of the chassis. Eac h ear is marked
“RIGHT” or “LEFT” on its inside surface.
3.Remove Rear Bezel — To remove the rear bezel, loosen the two captive screws that secure the rear bezel to the chassis. Pull the bezel away from the case.
4.Removing Grounding Screws — Remov e the two grounding scre ws that secure the case
to the chassis. They are located on the bottom of the case at the back.
5.Remove Chassis — To remove the case, grasp the front bezel of the instrument, and
carefully slide the chassis forward. Slide the chassis out of the metal case.
NOTE If you need to gain access to the components under the motherboard shield to trou-
bleshoot them, remove the shield. It is secured to the motherboard by a single screw.
3-6Routine Maintenance
Changing trigger link lines
The Model 2000 uses two lines of the T rigger Link rear panel connector as External Trigger
(EXT TRIG) input and Voltmeter Complete (VMC) output. At the factory, line 1 is configured
as VMC and line 2 as EXT TRIG.
NOTE Line 1, 3 or 5 of the T rig g er Link can be confi gured as VMC, while line 2, 4 or 6 can
be configured as EXT TRIG.
Trigger link line configurations are changed by moving the position of resistors inside the
unit. Perform the following steps to change trigger link lines:
WARNINGMake sure the instrument is disconnected from the power line and other equipment before
performing the following procedure.
Figure 3-1
Trigger link line
connections
1.Remove the cover from the instrument as explained in “Case Cover Removal”.
The resistors used to select the trigger link lines are located next to the T rigger Link con-
nector as shown in Figure 3-1. The “resistors” are actually solder beads that bridge pcboard pads. If the factory default lines are selected, the solder beads will be located at
R270 (line 2, EXT TRIG) and R267 (line 1, VMC).
2.To change a trigger link line:
A. Use a soldering iron and solder sucker to remove the appropriate solder bead.
B. Using a solder with OA-based flux, apply a solder bead to the appropriate resistor
location.
3.Replace the cover on the instrument.
Mother Board
(View from top)
Trigger Link Lines
Line 1 = VMC (R267)
Line 2 = EXT TRIG (R270)
Line 3 = VMC (R266)
Line 4 = EXT TRIG (R268)
Line 5 = VMC (R265)
Line 6 = EXT TRIG (R269)
Solder Bead
R270
R269
R268
R267
R265
R266
(Factory Default Configured)
Trigger
Link
Connector
Rear Panel
Motherboard removal
Perform the following steps to remove the motherboard. This procedure assumes that the case
cover is already removed.
1.Remove the IEEE-488 and RS-232 fasteners.
The IEEE-488 and the RS-232 connectors each have two nuts that secure the connectors
to the rear panel. Remove these nuts.
2.Remove the front/rear switch rod.
At the switch, place the edge of a flat-blade screw driver in the notch on the pushrod.
Gently twist the screw driver while pulling the rod from the shaft.
3.Disconnect the front and rear input terminals.
You must disconnect these input terminal connections for both the front and rear inputs:
• INPUT HI and LO
• SENSE HI and LO
• AMPS
Disassembly3-7
Remove all the connections except the front AMPS connection by pulling the wires off the
pin connectors. T o remov e the front panel AMPS input wire (white), first remove the AMPS fuse
holder, then use needle-nose pliers to grasp the AMP wire near fuse housing. Push the wire forward and down to snap the spring out of the fuse housing. Carefully pull the spring and contact
tip out of housing.
During re-assembly, use the following table to identify input terminals:
Front wire colorRear wire color
INPUT HI
INPUT LO
SENSE HI
SENSE LO
AMPS
4.Unplug cables.
C. Unplug the display board ribbon cable from connector J1014.
D. Unplug the transformer cables from connectors J1016 and J1015.
E. Unplug the scanner board ribbon cable from connector J1017.
5.Remove the fastening scre w that secures the main PC board to the chassis. This screw is
located along the left side of the unit towards the rear. It also holds down U144.
During re-assembly, replace the board, and start the IEEE-488 and RS-232 connector
nuts and the mounting screw. T ighten all the f asteners once they are all in place and the
board is correctly aligned.
Red
Black
Yellow
Gray
White
White/Red
White/Black
White/Yellow
White/Gray
—
6.Remove the motherboard, which is held in place by edge guides on each side, by
sliding it forward until the board edges clear the guides. Carefully pull the motherboard from the chassis.
3-8Disassembly
Front panel disassembly
Use the following procedures to remov e the display board and/or the pushbutton switch pad:
NOTE You must first remove the case cover, the front/rear input switch, and the front input
terminal wires as described in earlier in this section.
1.Unplug the display board ribbon cable from connector J1014.
2.Remove the front panel assembly.
This assembly has four retaining clips that snap onto the chassis over four pem nut studs.
Two retaining clips are located on each side of the front panel. Pull the retaining clips
outward and, at the same time, pull the front panel assembly forward until it separates
from the chassis.
3.Using a thin-bladed screw driv er , pry the plastic PC board stop (located at the bottom of
the display board) until the bar separates from the casing. Pull the display board from the
front panel.
4.Remove the switch pad by pulling it from the front panel.
Disassembly3-9
Main CPU firmware replacement
Changing the firmware may be necessary as upgrades become available. The firmware revision level for the main CPU is displayed during the power-on sequence. The firmware for the
main CPU is located in the EPROMs U156 (EVEN) and U157 (ODD), leadless ICs that resides
in chip carriers on the PC board.
To replace the CPU firmware, do the following:
WARNINGDisconnect the instrument from the power lines and remove the test leads before changing
the firmware.
1.Remove the case cover as described earlier in this section.
2.Locate U156 EVEN and U157 ODD (EPROMs) on the main PC board. The y are the
only devices installed in chip carriers (sockets).
CAUTIONEPROMs U156 and U157 are static sensitive devices. Be sure to follow the
handling precautions explained in the paragraph entitled “Static sensitive
devices.”
3.Using an appropriate chip extractor, remove U156 and U157 from its chip carrier.
4.Position the new U156 EPROM on the appropriate chip carrier. Make sure the notched
corner of the chip is aligned with the notch in the chip carrier.
5.With the EPROM properly positioned, push down on the chip until it completely seats
into the chip carrier.
6.Repeat steps 4 and 5 for EPROM U157.
3-10Disassembly
Removing power components
The following procedures to remove the po wer transformer and/or po wer module require that
the case cover and motherboard be removed, as previously explained.
Power transformer removal
Perform the following steps to remove the power transformer:
1.Remove motherboard.
2.Unplug the transformer wires that attach to the power module at the rear panel.
During re-assembly, use drawing 2000-050 as a reference and replace the wires as fol-
lows:
Top wire
Right top
Right bottom
Left top
Left bottom
3.Remove the two nuts that secure the transformer to the bottom of the chassis.
4.Pull the black ground wire off the threaded stud and remove the po wer transformer
from the chassis.
W ARNINGTo avoid electrical shock, which could result in injury or death, the black ground wire of the
transformer must be connected to chassis ground. When installing the power transformer, be
sure to re-connect the black ground wire to the mounting stud on bottom of the chassis.
Gray
Violet
White
Red
Blue
Power module removal
Perform the following steps to remove the power module:
1.Remove motherboard.
2.Unplug the transformer wires that attach to the power module at the rear panel.
During re-assembly, use drawing 2000-050 as a reference and replace the wires as fol-
lows:
Disassembly3-11
Top wire
Right top
Right bottom
Left top
Left bottom
3.Disconnect the power module's ground wire. This green and yellow wire connects to a
threaded stud on the chassis with a kep nut.
Gray
Violet
White
Red
Blue
4.Squeeze the latches on either side of the power module while pushing the module
from the access hole.
W ARNINGTo avoid electrical shock, which could result in injury or death, the ground wire of the power
module must be connected to chassis ground. When installing the power module, be sure to
re-connect the green and yellow ground wire to the threaded stud on the chassis.
3-12Disassembly
Instrument re-assembly
Re-assemble the instrument by reversing the previous disassembly procedures. Make sure
that all parts are properly seated and secured and that all connections are properly made. To ensure proper operation, replace and securely fasten the shield.
W ARNINGT o ensure continued protection against electrical shock, verify that power line ground (green
and yellow wire attached to the power module) and the power transformer ground (black
wire) are connected to the chassis.
4
Replaceable Parts
4-2Replaceable Parts
Introduction
Parts list
This section contains replacement parts information and component layout drawings for the
Model 2000.
The electrical parts lists for the Model 2000 are shown in Tables 4-1 to 4-3. For part numbers
to the various mechanical parts and assemblies, use the Miscellaneous parts list and the assembly drawings provided at the end of Section 3.
Ordering information
To place an order, or to obtain information concerning replacement parts, contact your Keithley representative or the f actory (see inside front cover for addresses). When ordering parts, be
sure to include the following information:
•Instrument model number (Model 2000)
•Instrument serial number
•Part description
•Component designation (if applicable)
•Keithley part number
Replaceable Parts4-3
Factory service
If the instrument is to be returned to Keithley Instruments for repair, perform the following:
1.Call the Repair Department at 1-800-552-1115 for a Return Material Authorization
(RMA) number.
2.Complete the service form at the back of this manual, and include it with the instrument.
3.Carefully pack the instrument in the original packing carton.
4.Write ATTENTION REP AIR DEPARTMENT and the RMA number on the shipping label.
Components layouts
The component layouts are provided in the following pages:
Motherboard: 2000-250, pages 1 and 2
Connector board: 2000-250, pages 1 and 2
Display board: 2000-250, pages 3 and 4
4-4Replaceable Parts
Table 4-1
Model 2000 connector board, parts list
Circuit desig.DescriptionKeithley part no.
C101
J1034
P1017
R196
CAP, .1UF, 10%, 25V, CERAMIC (0805)
CONN, MALE RT ANGLE, 32-PIN
CABLE ASSEMBL Y
RES, 2.21K, 1%, 100MW, THICK FILM (0805)
CRYSTAL, 14.7456MHZ
OSCILLATOR HIGH SPEED CMOS 12MHZ
VR-5
DZ-87
DZ-100
DZ-103
DZ-94
DZ-104
DZ-88
DZ-97
CR-39
CR-37
Table 4-4
Model 2000 mechanical, parts list
DescriptionKeithley part no.
2-56X5/8 PHILLIPS PAN HEAD SCREW SCANNER BOARD ASSEMBLY
4-40X1/4 PHIL FLAT HD UNDERCUT SR WRAP TO CHASSIS
4-40X5/16 PHILLIPS PAN HD SEMS MOTHER BOARD TO CHASSIS
6-32 KEP NUT SAFETY GROUND
6-32X1 PH PAN HD SEMS SCR FOR MOTHER BOARD SHIELD
6-32X1/4 PHIL. PAN HD SEMS CARD GUIDE TO CHASSIS
6-32X1/4 PHILLIPS FLAT HD FOR REAR FOOT
8-32 SMALL NUT FOR TRANSFORMER MOUNTING
#8 INTERNAL TOOTH LOCKWASHER FOR TRANSFORMER MOUNTING
BANANA JACK, PUSH-IN, BLACK
BANANA JACK, PUSH-IN, RED
BEZEL, REAR
BRACKET, REAR PANEL SCANNER COVER PLATE
CABLE CLAMP FOR DISPLAY CABLE & TR-299 WIRE
CABLE CLAMP TIE WRAP, NYLON, 4" LONG FOR FRONT/REAR WIRES
CAPTIVE PANEL SCREW FOR BEZEL
CARD GUIDE/SHIELD
CHASSIS ASSEMBL Y
CONNECTOR, HARDWARE KIT FOR IEEE
COVER
DISPLAY LENS
FASTENER FOR EARS
FOOT
FOOT, EXTRUDED
FOOT,RUBBER
FRONT PANEL OVERLAY
FRONT PANEL PRINTED
FRONT/REAR SWITCH ROD
FUSE HOLDER FOR PM-1-1
FUSE, 3A, 250 FOR CURRENT INPUT JACK
FUSE 0.25A FOR FH-35-1
JACK, CURRENT INPUT
LINE MODULE
LUG
LUG
MOTHERBOARD SHIELD
MOUNTING EAR, LEFT
MOUNTING EAR, RIGHT
PC BOARD STOP
PLASTIC PLUG FOR SCANNER COVER PLATE
POWER ROD
SCREWLOCK, FEMALE FOR RS-232
SWITCHPAD
TRANSFORMER
AMPS fuse replacement 1-4
Analog signal switching states 2-13
Assembly drawings 3-4
B
Built-in Test documentation 2-22
Built-in Test overview 2-18
C
Case cover removal 3-5
Changing trigger link lines 3-6
Components layouts 4-3
D
Digital circuitry checks 2-12
Disassembly 3-1
Display board checks 2-11
F
Factory service 4-3
Front panel disassembly 3-8
Front panel tests 2-4
H
Handling and cleaning 3-3
I
Instrument re-assembly 3-12
M
Main CPU firmware replacement 3-9
Motherboard removal 3-7
O
Ordering information 4-2
P
Parts list 4-2
Power supply checks 2-11
Power-on test 2-3
Principles of operation 2-5
R
Removing power components 3-10
Repair considerations 2-3
Replaceable parts 4-1
Routine maintenance 1-1
S
Setting line voltage and replacing fuse 1-2
Specifications A-1
Static sensitive devices 3-4
T
Troubleshooting 2-1
❑
❑
❑
❑
❑
❑
❑
❑
❑
❑
❑
❑
❑
❑
❑
❑
Service Form
Model No. _________________ Serial No. ______________________Date_________________
Name and T elephone No. ________________________________________________________
Company ______________________________________________________________________
List all control settings, describe problem and check boxes that apply to problem. _________________________
IEEE failure
Front panel operational ❑ All ranges or functions are bad
Analog output follows display
Obvious problem on power-up
Particular range or function bad; specify
_______________________________
Batteries and fuses are OK
Checked all cables
Display or output (check one)
Drifts
Overload
Calibration only
(attach any additional sheets as necessary)
Show a block diagram of your measurement including all instruments connected (whether power is turned on or
not). Also, describe signal source.
Where is the measurement being performed? (factory, controlled laboratory, out-of-doors, etc.)_______________
What power line voltage is used?___________________ Ambient temperature? ________________________°F
Relative humidity? ___________________________________________Other? ___________________________
Any additional information. (If special modifications have been made by the user, please describe.)