Intel MPCBL0001 User Manual
Intel NetStructure® MPCBL0001
High Performance Single Board
Computer
Technical Product Specification
July 2005
Order Number: 273817-007
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The Intel NetStructure
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Copyright © Intel Corporation, 2005. All rights reserved.
®
MPCBL0001 High Performance Single Board Computer may contain design defects or errors known as errata which may
2 Intel NetStructure
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MPCBL0001 High Performance Single Board Computer
Technical Product Specification
Contents
Contents
1 Introduction.................................................................................................................................... 11
1.1 Document Organization ...................................................................................................... 11
1.2 Glossary.............................................................................................................................. 12
2 Features Overview ........................................................................................................................14
2.1 Application ..........................................................................................................................14
2.2 Functional Description ........................................................................................................ 14
2.2.1 Low Voltage Intel
2.2.2 Chipset...................................................................................................................17
2.2.2.1 Intel
2.2.2.2 Intel
2.2.2.3 Intel
2.2.3 Memory (J8, J9, J10, J11) ..................................................................................... 19
2.2.3.1 Memory Ordering Rule for the MCH ...................................................... 20
2.2.4 I/O .......................................................................................................................... 20
2.2.4.1 Super I/O (U28)...................................................................................... 20
2.2.4.2 Real-Time Clock .................................................................................... 21
2.2.4.3 Timer0 Capabilities ................................................................................ 21
2.2.4.4 Gigabit Ethernet (U13) ........................................................................... 21
2.2.4.5 Fibre Channel* (U23) - Optional ............................................................22
2.2.5 PMC Connector (J25, J26, J27) ............................................................................ 23
2.2.6 Firmware Hub (U30, U33)...................................................................................... 23
2.2.6.1 FWH 0 (Main BIOS) ...............................................................................24
2.2.6.2 FWH 1 (Backup/Recovery BIOS)........................................................... 24
2.2.6.3 Flash ROM Backup Mechanism ............................................................24
2.2.7 Onboard Power Supplies ....................................................................................... 25
2.2.7.1 Power Feed Fuses.................................................................................25
2.2.7.2 ORing Diodes and Circuit Breaker Protection........................................ 25
2.2.7.3 -48 V to +12 V Converter ....................................................................... 25
2.2.7.4 -48 V to +5 V/+3.3 V Converter.............................................................. 25
2.2.7.5 Processor Voltage Regulator Module (VRM)......................................... 25
2.2.7.6 IPMB Standby Power.............................................................................26
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Xeon™ Processor CPU-0 (U35), CPU-1 (U36) .......................16
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E7501 Memory Controller Hub (U22)........................................... 17
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82801CA I/O Controller Hub 3 (U7) .............................................18
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82870P2 64-bit PCI/PCI-X Controller Hub 2 (U14, U24) .............19
3 Hardware Management Overview ................................................................................................. 27
3.1 Sensor Data Record (SDR) ................................................................................................ 28
3.2 System Event Log (SEL) .................................................................................................... 30
3.2.1 Temperature and Voltage Sensors ........................................................................ 34
3.2.2 Processor Events................................................................................................... 39
3.2.3 DIMM Memory Events ........................................................................................... 39
3.2.4 System Firmware Progress (POST Error) ............................................................. 39
3.2.5 Critical Interrupts.................................................................................................... 39
3.2.6 System ACPI Power State ..................................................................................... 41
3.2.7 IPMB Link Sensor .................................................................................................. 41
3.2.8 FRU Hot Swap....................................................................................................... 41
3.2.9 CPU Failure Detection ........................................................................................... 41
3.2.10 Port 80h POST Codes ........................................................................................... 42
3.3 Field Replaceable Unit (FRU) Information ..........................................................................43
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3.4 E-Keying ............................................................................................................................. 44
3.5 IPMC Firmware Code ......................................................................................................... 44
3.6 IPMC Firmware Upgrade Procedure .................................................................................. 45
3.6.1 IPMC Firmware Upgrade Using KCS Interface ..................................................... 45
3.6.2 IPMC Firmware Upgrade via the IPMB Interface (RMCP)..................................... 46
3.6.2.1 Updating MPCBL0001 Firmware ........................................................... 47
3.7 OEM IPMI Commands........................................................................................................ 47
3.7.1 Reset BIOS Flash Type ......................................................................................... 47
3.7.2 Set Fibre Channel Port Selection .......................................................................... 48
3.7.3 Get Fibre Channel Port Selection .......................................................................... 48
3.7.4 Get HW Fibre Channel Port Selection ................................................................... 49
3.7.5 Set Control State ................................................................................................... 49
3.7.6 Get Control State ................................................................................................... 50
3.7.7 Get Port80 Data..................................................................................................... 50
3.8 Controls Identifier Table...................................................................................................... 50
3.9 Hot-Swap Process .............................................................................................................. 51
3.9.1 Hot-Swap LED (DS10)........................................................................................... 52
3.9.2 Ejector Mechanism ................................................................................................ 52
3.10 Interrupts and Error Reporting ............................................................................................ 53
3.10.1 Device Interrupts.................................................................................................... 53
3.10.2 Error Reporting ...................................................................................................... 55
3.11 ACPI ................................................................................................................................... 56
3.11.1 System States and Power States .......................................................................... 56
3.12 Reset Types........................................................................................................................ 56
3.12.1 Reset Logic............................................................................................................ 57
3.12.2 Hard Reset Request .............................................................................................. 57
3.12.3 Soft Reset Request................................................................................................ 57
3.12.4 Warm Boot............................................................................................................. 58
3.12.5 Cold Boot............................................................................................................... 59
3.12.6 Power Good........................................................................................................... 59
3.13 Watchdog Timers (WDTs) .................................................................................................. 62
3.13.1 WDT #1.................................................................................................................. 62
3.13.2 WDT #2.................................................................................................................. 63
3.13.3 WDT #3.................................................................................................................. 63
3.14 LED Status.......................................................................................................................... 64
3.14.1 Health LED ............................................................................................................ 64
3.14.2 OOS (Out Of Service) LED.................................................................................... 64
3.14.3 Hot-Swap LED ....................................................................................................... 64
3.14.4 IDE Drive Activity LED ........................................................................................... 65
3.14.5 User Programmable LEDs..................................................................................... 65
3.14.6 Network Link/Speed LEDs..................................................................................... 66
3.14.7 Ethernet Controller Port State LEDs...................................................................... 66
3.14.8 Fibre Channel Port State LEDs ............................................................................. 67
3.15 FRU Payload Control.......................................................................................................... 67
3.15.1 Cold Reset ............................................................................................................. 68
3.15.2 Warm Reset........................................................................................................... 68
3.15.3 Graceful Reboot..................................................................................................... 68
3.15.4 Diagnostic Interrupt................................................................................................ 69
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Technical Product Specification
Contents
4 Connectors .................................................................................................................................... 70
4.1 Backplane Connectors........................................................................................................ 74
4.1.1 Power Distribution Connector (Zone 1)..................................................................74
4.1.2 Data Transport Connector (Zone 2)....................................................................... 75
4.1.3 Alignment Blocks ................................................................................................... 76
4.2 Front Panel Connectors......................................................................................................77
4.2.1 USB Connector (J12)............................................................................................. 77
4.2.2 Serial Port Connector (J17) ...................................................................................77
4.2.3 Fibre Channel Small Form-Factor Pluggable (SFP) Receptacle (J34 and J35) .... 80
4.2.4 Fibre Channel SFP Optical Transceiver Module.................................................... 80
4.2.5 PMC Connectors (J25, J26, J27)........................................................................... 81
4.3 On-board Connectors ......................................................................................................... 84
4.3.1 IDE Connector (J24) .............................................................................................. 84
5 Addressing.....................................................................................................................................85
5.1 Configuration Registers ......................................................................................................85
5.1.1 Configuration Address Register MCH CONFIG_ADDRESS ................................. 85
5.1.2 Configuration Data Register MCH CONFIG_ADDRESS .......................................85
5.2 I/O Address Assignments ................................................................................................... 86
5.3 Memory Map....................................................................................................................... 87
5.4 IPMC Addresses................................................................................................................. 88
6 Specifications ................................................................................................................................89
6.1 Mechanical Specifications .................................................................................................. 89
6.1.1 Board Outline......................................................................................................... 89
6.1.2 Backing Plate......................................................................................................... 92
6.1.3 Component Height ................................................................................................. 92
6.2 Environmental Specifications..............................................................................................97
6.3 Reliability Specifications ..................................................................................................... 97
6.3.1 Mean Time Between Failure (MTBF) Specifications.............................................. 97
6.3.1.1 Environmental Assumptions ..................................................................98
6.3.1.2 General Assumptions............................................................................. 98
6.3.1.3 General Notes........................................................................................ 98
6.3.2 Power Consumption .............................................................................................. 98
6.3.3 Cooling Requirements ........................................................................................... 99
6.4 Board Layer Specifications ................................................................................................. 99
6.5 Weight................................................................................................................................. 99
7 BIOS Features............................................................................................................................. 100
7.1 Introduction .......................................................................................................................100
7.2 BIOS Flash Memory Organization .................................................................................... 100
7.3 Complementary Metal-Oxide Semiconductor (CMOS) .....................................................100
7.3.1 Copying and Saving CMOS Settings ................................................................... 100
7.4 Redundant BIOS Functionality ......................................................................................... 101
7.5 System Management BIOS (SMBIOS) ............................................................................. 101
7.6 Legacy USB Support ........................................................................................................ 102
7.7 BIOS Updates................................................................................................................... 102
7.7.1 Language Support ............................................................................................... 103
7.8 Recovering BIOS Data ..................................................................................................... 103
7.9 Boot Options .....................................................................................................................103
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7.9.1 CD-ROM and Network Boot ................................................................................ 103
7.9.2 Booting without Attached Devices ....................................................................... 103
7.10 Fast Booting Systems....................................................................................................... 104
7.10.1 Quick Boot ........................................................................................................... 104
7.11 BIOS Security Features .................................................................................................... 104
7.12 Remote Access Configuration .......................................................................................... 105
8 BIOS Setup.................................................................................................................................. 106
8.1 Introduction ....................................................................................................................... 106
8.2 Main Menu........................................................................................................................ 106
8.3 Advanced Menu................................................................................................................107
8.3.1 CPU Configuration Submenu .............................................................................. 108
8.3.2 IDE Configuration Submenu ................................................................................ 109
8.3.2.1 Primary IDE Master/Slave Submenu ................................................... 110
8.3.3 Floppy Configuration Submenu ........................................................................... 112
8.3.4 SuperIO Configuration Submenu......................................................................... 113
8.3.5 ACPI Configuration Submenu.............................................................................. 114
8.3.5.1 Advanced ACPI Configuration Submenu............................................. 115
8.3.6 System Management Configuration Submenu .................................................... 116
8.3.7 Event Logging Configuration Submenu ............................................................... 117
8.3.8 Fibre Channel Routing (PICMG) Configuration Submenu................................... 118
8.3.9 Remote Access Configuration Submenu............................................................. 119
8.3.10 USB Configuration Submenu............................................................................... 120
8.3.10.1 USB Mass Storage Device Configuration............................................ 121
8.3.11 PCI Configuration ................................................................................................ 121
8.4 Boot Menu ........................................................................................................................ 122
8.4.1 Boot Settings Configuration Submenu................................................................. 122
8.4.2 Boot Device Priority Submenu............................................................................. 123
8.4.3 Hard Disk Drive Submenu ................................................................................... 124
8.4.4 OS Load Timeout Timer ...................................................................................... 124
8.5 Security Menu................................................................................................................... 125
8.6 Exit Menu.......................................................................................................................... 125
9 Error Messages ........................................................................................................................... 127
9.1 BIOS Error Messages....................................................................................................... 127
9.2 Port 80h POST Codes ...................................................................................................... 128
10 Operating the Unit ....................................................................................................................... 132
10.1 BIOS Configuration........................................................................................................... 132
10.2 BIOS Image Updates........................................................................................................ 132
10.3 Procedures to Copy and Save BIOS (Including CMOS Settings)..................................... 132
10.3.1 Copying BIOS.bin from the SBC.......................................................................... 132
10.3.2 Saving BIOS.bin to the SBC ................................................................................ 133
10.3.3 Error Messages ................................................................................................... 133
10.4 Jumpers ............................................................................................................................ 134
10.5 Digital Ground to Chassis Ground Connectivity ............................................................... 136
11 Maintenance ................................................................................................................................ 137
11.1 Supervision ....................................................................................................................... 137
11.2 Diagnostics ....................................................................................................................... 137
11.2.1 In-Target Probe (ITP)........................................................................................... 137
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Technical Product Specification
Contents
12 Thermals...................................................................................................................................... 138
13 Component Technology .............................................................................................................. 139
14 Warranty Information ................................................................................................................... 140
14.1 Intel NetStructure® Compute Boards and Platform Products Limited Warranty .............. 140
14.2 Returning a Defective Product (RMA) ..............................................................................140
14.3 For the Americas .............................................................................................................. 141
14.3.1 For Europe, Middle East, and Africa (EMEA) ...................................................... 141
14.3.2 For Asia and Pacific (APAC)................................................................................141
15 Customer Support ....................................................................................................................... 143
15.1 Customer Support.............................................................................................................143
15.2 Technical Support and Return for Service Assistance ..................................................... 143
15.3 Sales Assistance .............................................................................................................. 143
15.4 Product Code Summary ................................................................................................... 143
16 Certifications................................................................................................................................ 144
17 Agency Information—Class A......................................................................................................145
17.1 North America (FCC Class A)........................................................................................... 145
17.2 Canada – Industry Canada (ICES-003 Class A) (English and French-translated) ........... 145
17.3 Safety Instructions (English and French-translated) .........................................................145
17.3.1 English .................................................................................................................145
17.3.2 French.................................................................................................................. 146
17.4 Taiwan Class A Warning Statement ................................................................................. 146
17.5 Japan VCCI Class A .........................................................................................................147
17.6 Korean Class A................................................................................................................. 147
17.7 Australia, New Zealand..................................................................................................... 147
18 Agency Information—Class B......................................................................................................148
18.1 North America (FCC Class B)........................................................................................... 148
18.2 Canada – Industry Canada (ICES-003 Class B) (English and French-translated) ........... 148
18.3 Safety Instructions (English and French-translated) .........................................................148
18.3.1 English .................................................................................................................148
18.3.2 French.................................................................................................................. 149
18.4 Japan VCCI Class B .........................................................................................................149
18.5 Korean Class B................................................................................................................. 150
18.6 Australia, New Zealand..................................................................................................... 150
19 Safety Warnings .......................................................................................................................... 151
19.1 Mesures de Sécurité .........................................................................................................152
19.2 Sicherheitshinweise ..........................................................................................................154
19.3 Norme di Sicurezza ..........................................................................................................156
19.4 Instrucciones de Seguridad .............................................................................................. 158
19.5 Chinese Safety Warning ................................................................................................... 160
A Reference Documents................................................................................................................. 161
B List of Supported Commands (IPMI v1.5 and PICMG 3.0).......................................................... 163
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Technical Product Specification
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MPCBL0001 High Performance Single Board Computer 7
Contents
Tables
1 P64H2 Interfaces........................................................................................................................ 19
2 Hardware Sensors...................................................................................................................... 28
3 SEL Events Supported by the MPCBL0001 SBC....................................................................... 31
4 Sensor Thresholds for IPMC Firmware 1.0 ................................................................................ 35
5 Sensor Thresholds for IPMC Firmware 1.2 ................................................................................ 36
6 Sensor Thresholds for IPMC Firmware 1.7 and Above .............................................................. 37
7 Sensor Thresholds for IPMC Firmware 1.14 and Above ............................................................ 38
8 PCI Mapping for Hardware Component Subsystem................................................................... 40
9 CPU Failure Behavior................................................................................................................. 42
10 FRU Multirecord Data for CPU/RAM/PMC/BIOS Version Information ....................................... 43
11 PMC Data................................................................................................................................... 43
12 Link Descriptors for E-Keying..................................................................................................... 44
13 Reset BIOS Flash Type.............................................................................................................. 47
14 Set Fibre Channel Port Selection ............................................................................................... 48
15 Get Fibre Channel Port Selection............................................................................................... 48
16 Get HW Fibre Channel Port Selection........................................................................................ 49
17 Set Control State ........................................................................................................................ 49
18 Get Control State........................................................................................................................ 50
19 Get Port80 Data.......................................................................................................................... 50
20 Controls Identifier Table ............................................................................................................. 50
21 Hot-Swap LED (DS11) ............................................................................................................... 52
22 Interrupt Assignments................................................................................................................. 53
23 Power States and Targeted System Power................................................................................ 56
24 Reset Request............................................................................................................................ 58
25 Reset Actions ............................................................................................................................. 59
26 Health LED ................................................................................................................................. 64
27 OOS LED (DS9) ......................................................................................................................... 64
28 IDE Drive Activity LED................................................................................................................ 65
29 User Programmable LEDs.......................................................................................................... 65
30 GPIO Pin Connections ............................................................................................................... 65
31 Network Link LEDs..................................................................................................................... 66
32 Network Speed LEDs ................................................................................................................. 66
33 Ethernet Controller Port State LED ............................................................................................67
34 Fibre Channel Port State LED (DS2, DS3)................................................................................. 67
35 CMM Commands for FRU Control Options ................................................................................ 67
36 Returned Values from the Get Message Command................................................................... 69
37 LED Descriptions........................................................................................................................ 73
38 Connector Assignments ............................................................................................................. 73
39 Power Distribution Connector (Zone 1) P10 Pin Assignments ................................................... 74
40 Data Transport Connector (Zone 2) P23 Pin Assignments ........................................................ 76
41 USB Connector (J12) Pin Assignments...................................................................................... 77
42 Serial Port Connector (J17) Pin Assignments ............................................................................ 78
43 Fibre Channel SFP Copper Transceiver Module (AMP, J34, J35) ............................................. 80
44 Fibre Channel SFP Pin Assignments ......................................................................................... 81
45 PMC Connector Pin Assignments - 32 Bit.................................................................................. 82
46 PMC Connector Pin Assignments - 64 Bit.................................................................................. 83
47 IDE Connector Pin Assignments ................................................................................................ 84
48 Configuration Address Register Bit Assignments....................................................................... 85
49 Configuration Data Register Bit Assignments ............................................................................ 86
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50 I/O Address Cross-References................................................................................................... 86
51 Memory Map............................................................................................................................... 87
52 SMBus Addresses ...................................................................................................................... 88
53 Environmental Specifications......................................................................................................97
54 Reliability Estimate Data.............................................................................................................97
55 Total Measured Power................................................................................................................98
56 Supervisor and User Password Functions................................................................................ 105
57 Function Key Escape Code Equivalents................................................................................... 105
58 BIOS Setup Program Menu Bar ...............................................................................................106
59 BIOS Setup Program Function Keys ........................................................................................106
60 Main Menu ................................................................................................................................107
61 Advanced Menu........................................................................................................................ 108
62 CPU Configuration Submenu ...................................................................................................109
63 IDE Configuration Submenu .....................................................................................................109
64 Primary IDE Master/Slave Submenu ........................................................................................ 111
65 Floppy Configuration Submenu ................................................................................................112
66 SuperIO Configuration Submenu.............................................................................................. 113
67 ACPI Configuration Submenu...................................................................................................114
68 Advanced ACPI Configuration Submenu.................................................................................. 115
69 System Management Configuration Submenu ......................................................................... 116
70 Event Logging Configuration Submenu ....................................................................................117
71 Fibre Channel Routing (PICMG) Submenu .............................................................................. 118
72 Remote Access Configuration Submenu.................................................................................. 119
73 USB Configuration Submenu....................................................................................................120
74 USB Mass Storage Device Configuration................................................................................. 121
75 PCI Configuration Submenu .....................................................................................................122
76 Boot Menu ................................................................................................................................ 122
77 Boot Settings Configuration Submenu...................................................................................... 123
78 Boot Device Priority Submenu..................................................................................................124
79 Hard Disk Drive Priority Submenu ............................................................................................ 124
80 OS Load Timeout Timer Submenu ...........................................................................................125
81 Security Menu........................................................................................................................... 125
82 Exit Menu.................................................................................................................................. 126
83 BIOS Error Messages............................................................................................................... 127
84 Bootblock Initialization Code Checkpoints................................................................................ 128
85 POST Code Checkpoints..........................................................................................................129
87 ACPI Runtime Checkpoints ......................................................................................................131
86 DIM Code Checkpoints............................................................................................................. 131
88 BIOS Beep Codes ....................................................................................................................131
89 Error Message .......................................................................................................................... 133
90 J18 Pin Assignments ................................................................................................................ 135
91 J16 Jumper Assignments .........................................................................................................135
92 J37 Jumper assignments..........................................................................................................135
93 J40 Jumper Assignments .........................................................................................................136
94 Hardware Monitoring Components ........................................................................................... 137
95 Main Components..................................................................................................................... 139
96 MPCBL0001 Product Code Summary ......................................................................................143
97 IPMI 1.5 Supported Commands ............................................................................................... 163
98 PICMG 3.0 IPMI Supported Commands................................................................................... 165
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Contents
Figures
1 Intel NetStructure® MPCBL0001 SBC Block Diagram............................................................... 15
2 Memory Ordering........................................................................................................................ 20
3 Hardware Management Block Diagram...................................................................................... 27
4 IPMC Firmware Code Process ................................................................................................... 45
5 Upgrade via Remote Management Node ................................................................................... 46
6 Hot-Swap Process...................................................................................................................... 51
7 Interrupt Signals ......................................................................................................................... 54
8 Power Good Map........................................................................................................................ 59
9 Reset Chain................................................................................................................................ 61
10 Watchdog Timers ....................................................................................................................... 62
11 Flow Diagram for Graceful Reboot Command ........................................................................... 68
12 Diagnostic Interrupt Command Implementation ......................................................................... 69
13 MPCBL0001 SBC Connector Locations ..................................................................................... 70
14 MPCBL0001NXX SBC Front Panel ............................................................................................ 71
15 MPCBL0001FXX SBC Front Panel ............................................................................................ 72
16 Power Distribution Connector (Zone 1) P10 ............................................................................... 74
17 Data Transport Connector (Zone 2) J23..................................................................................... 75
18 Serial Port Connector (J17) ........................................................................................................ 78
19 DB9 to RJ-45 Pin Translation ..................................................................................................... 79
20 Intel NetStructure® MPCBL0001 Component Layout ................................................................ 90
21 Intel NetStructure® MPCBL0001 Component Layout ................................................................ 91
22 MPCBL0001 SBC Front Panel Dimensions – FC SKU (PMC and Connectors) ........................ 93
23 MPCBL0001 SBC Front Panel Dimensions – FC SKU (Screws and LEDs) .............................. 94
24 MPCBL0001 SBC Front Panel Dimensions – Non FC SKU (PMC and Connectors)................. 95
25 MPCBL0001 SBC Front Panel Dimensions – Non-FC SKU (Screws and LED) ........................ 96
26 Low Voltage Intel
27 Jumper/Connector Locations....................................................................................................134
28 Connecting Digital Ground to Chassis Ground......................................................................... 136
29 Power vs. Flow Rate................................................................................................................. 138
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Xeon™ Processor Heatsink......................................................................... 99
Revision History
Date Revision Description
July 2005 007 Added Table 7. Modified tables 3, 9, 13, 14, and 53; Fig. 21; and Section 10.5.
April 2005 006 New text in sections 3.2.9, 6.5, 10.3.1, and tables 2, 3, and 6.
February 2005 005 New text, figures; added Section 18, “Agency Information—Class B”.
November 2004 004
June 2004 003 SRA Release - changed from release 002 to current.
January 2004 002 Pre-SRA Release.
October 2003 001 Initial public release of this document
10 Intel NetStructure
Changes to figures 12, 13; changes to table 2, 3, 48, 77 and 81; added example
to Section 3.2.5.
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MPCBL0001 High Performance Single Board Computer
Technical Product Specification
Introduction
Introduction 1
1.1 Document Organization
This document gives technical specifications related to the Intel NetStructure® MPCBL0001 High
Performance Single Board Computer. The MPCBL0001 is designed following the standards of the
Advanced Telecommunications Compute Architecture (AdvancedTCA*) Design Guide for high
availability, switched network computing. This document is intended for support during system
product development and while sustaining a product. It specifies the architecture, design
requirements, external requirements, board functionality, and design limitations of the
MPCBL0001 Single Board Computer.
The following summarizes the focus of each chapter in this document.
Chapter 1, “Introduction” gives an overview of the information contained in the Intel
NetStructure
Specification as well as a glossary of acronyms and important terms.
Chapter 2, “Features Overview” introduces the key features of the MPCBL0001. It includes a
functional block diagram and a brief description of each block.
Chapter 3, “Hardware Management Overview”provides a high-level overview related to IPMI
implementation based on PICMG* 3.0 and IPMI v1.5 specifications in the MPCBL0001 SBC.
Chapter 4, “Connectors” includes an illustration of connector locations, connector descriptions,
and pinout tables.
Chapter 5, “Addressing” summarizes the information you need to configure the MPCBL0001.
Included are the PCI configuration map, Configuration Address register, Configuration Data
register, I/O address assignments, memory map, and IPMC addresses.
Chapter 6, “Specifications” contains the mechanical, environmental, and reliability specifications
for the MPCBL0001.
Chapter 7, “BIOS Features” provides an introduction to the Intel/AMI BIOS, and the System
Management BIOS, stored in flash memory on the MPCBL0001.
Chapter 8, “BIOS Setup” describes the interactive menu system of the BIOS Setup program. The
menu allows a user to configure the BIOS for a given system.
Chapter 9, “Error Messages” lists BIOS error messages, Port 80h POST codes, and bus
initialization checkpoints, and provides a brief description of each.
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MPCBL0001 High Performance Single Board Computer Technical Product
Chapter 10, “Operating the Unit” provides specifics for configuring the MPCBL0001, including
BIOS configuration and jumper settings.
Chapter 11, “Maintenance” includes supervision and diagnostics information.
Chapter 13, “Component Technology” lists the major components used on the MPCBL0001.
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MPCBL0001 High Performance Single Board Computer 11
Introduction
Chapter 14, “Warranty Information” provides warranty information for Intel® NetStructureTM
products.
Chapter 15, “Customer Support” provides informat ion on how to contact customer support.
Chapter 16, “Certifications” and Chapter 17, “Agency Information—Class A” document the
regulatory requirements the MPCBL0001 is designed to meet.
Appendix A, “Reference Documents” provides a list of data sheets, standards, and specifications
for the technology designed into the MPCBL0001.
Appendix B, “List of Supported Commands (IPMI v1.5 and PICMG 3.0)”provides lists of
commands supported by IPMI v1.5 and PICMG Specification 3.0.
1.2 Glossary
For ease of use, numeric entries are listed first with alpha entries following. Acronyms and terms
are then entered in their respective place.
ACPI Advanced Configuration and Power Interface.
AdvancedTCA Advanced Telecommunications Compute Architecture
BIOS Basic Input/Output Subsystem. ROM code that initializes the computer
and performs some basic functions.
Blade An assembled PCB card that plugs into a chassis.
DIMM Dual Inline Memory Module. Small card with memory on it used for
MPCBL0001.
DMI Desktop Management Interface
EEPROM Electrically Erasable Programmable Read-Only Memory
Fabric Board A board capable of moving packet data between Node Boards via the
ports of the backplane. This is sometimes referred to as a switch.
Fabric Slot A slot supporting a link port connection to/from each Node Slot and/or
out of the chassis.
Hyper-Threading Technology
†
HT T echnology allows a single (or dual) physical processor, to appear as
two (or quad) logical processors to a HT Technology-aware operating
system.
2
I
C* Inter-IC [Integrated Circuit]. 2-wire interface commonly used to carry
management data.
IBA Intel
®
Boot Agent. The Intel Boot Agent is a software product that
allows your networked client computer to boot using a program code
image supplied by a remote server.
IDE Integrated Device Electronics. Common, low-cost disk interface.
IPMB Intelligent Platform Management Bus. Physical 2-wire medium to carry
IPMI.
12 Intel NetStructure
®
MPCBL0001 High Performance Single Board Computer
Technical Product Specification
Introduction
IPMC Intelligent Platform Management Controller. ASIC in baseboard
responsible for low-level system management.
IPMI Intelligent Platform Management Interface. Programming model for
system management.
KCS Keyboard Controller Style interface.
LPC Bus Los Pin Count Bus. Legacy I/O bus that replaces ISA and X-bus. See the
Low Pin Count (LPC) Interface Specification.
MTBF Mean Time Between Failure. A reliability measure based on the
probability of failure.
NEBS National Equipment Building Standards. Telco standards for equipment
emissions, thermal, shock, contaminants, and fire suppression
requirements.
NMI Non-Maskable Interrupt. Low-level PC interrupt.
Node Board A board capable of providing and/or receiving packet data to/from a
Fabric Board via the ports of the networks. The term is used
interchangeably with SBC.
MPCBL0001 Single or dual processor Single Board Computer with Fibre Channel.
MPCBL0002 Single or dual processor Single Board Computer without Fibre Channel.
Node Slot A slot supporting port connections to/from Fabric Slot(s). A Node slot is
intended to accept a Node Board
Physical Port A port that physically exists. It is supported by one of many physical
(PHY) type components.
PMC PCI Mezzanine Card. IEEE1386 standard for embedded PCI cards. They
mount parallel to the SBC.
ROM Read-Only Memory.
SBC Single Board Computer. This term is used interchangeably with Node
Board.
SEL System Event Log. Action logged by management controller.
SFP Small Form Factor Pluggable receptacle for the front panel Fibre
Channel interfaces.
SMBus System Management Bus. Similar to I
2
C
SMI System Management Interrupt. Low-level PC interrupt which can be
initiated by chipset or management controller. Used to service IPMC or
handle things like memory errors.
SMS, SMSC Standard Microsystems Corporation*
USB Universal Serial Bus. General-purpose peripheral interconnect,
operating at 1-12 Mbps.
Intel NetStructure
Technical Product Specification
®
MPCBL0001 High Performance Single Board Computer 13
Features Overview
Features Overview 2
2.1 Application
The Advanced T elecommunications Compute Architecture (AdvancedTCA) standards define open
architecture modular computing components for carrier-grade, communications network
infrastructure. The goals of the standards are to enable blade-based modular platforms to be:
• cost effective
• high-density
• high-availability
• scalable
These systems use a fabric I/O network for connecting multiple, independent processor boards, I/O
nodes (e.g., line cards), and I/O devices (e.g., storage subsystem).
The MPCBL0001 SBC is designed per the AdvancedTCA Design Guide for High Availability,
Switched Network Computing. Bulk storage for the system is connected through optional dual
Fibre Channel interfaces. The MPCBL0001FXX SBC includes a Fibre Channel controller. The
MPCBL0001NXX SBC does not have the Fibre Channel controller.
2.2 Functional Description
This topic defines the architecture of the MPCBL0001 SBC through descriptions of functional
blocks. Figure 1, “Intel NetStructure® MPCBL0001 SBC Block Diagram” on page 15 shows the
functional blocks of the MPCBL0001 SBC. The MPCBL0001 SBC is a dual processor, hotswappable SBC with backplane connections to dual Gigabit Ethernet star networks and dual Fibre
Channel star arbitrated loops.
The SBC incorporates an Intelligent Platform Management Contro ller that monitors critical
functions of the board, responds to commands from the shelf manager, and reports events.
Power is supplied to the MPCBL0001 SBC through two redundant -48 V power supply
connections. Power for on-board hardware management circuitry is provided through a standby
converter on the power mezzanine. This converter, along with all the other converters on the power
mezzanine are fed by the diode OR'd -48 V supply from the backplane.
The SBC has provision for the addition of a PMC device and supports 32-bit and 64-bit transfers at
33 MHz and 66 MHz. The SBC also offers one USB and one service terminal interface. An
overview of each block follows.
14 Intel NetStructure
®
MPCBL0001 High Performance Single Board Computer
Technical Product Specification
Figure 1. Intel NetStructure® MPCBL0001 SBC Block Diagram
Features Overview
RJ-45
RJ-45
Serial
Serial
Port
Port
USB
USB
Port
Port
Optional
Third-
party
PMC
Front Panel
Optional 2.5”
Optional 2.5”
Hard Disk Drive
Hard Disk Drive
Standard
Microsystems Corp.
Microsystems Corp.
LPC47B272 Super I/O
LPC47B272 Super I/O
PCI
PCI
Mezzanine
Mezzanine
Card
Card
(PMC)
(PMC)
Connector
Connector
Intel®
Intel®
82546EB
82546EB
Dual Gb
Dual Gb
Ethernet
Ethernet
256K SRAM
256K SRAM
256K SRAM
256K SRAM
Dual FC Ports
Standard
528 MB/s
PCI 64/66
1066 MB/s
PCI-X
1066 MB/s
33/66/100
Intel®
Intel®
P64H2
P64H2
PCI
Bridge
Bridge
Intel®
Intel®
P64H2
P64H2
PCI
Bridge
Bridge
PCI-X
QLogic
QLogic
QLogic
QLogic
ISP2312
ISP2312
ISP2312
ISP2312
Fibre
Fibre
Channel
Channel
Channel
Channel
Controller
Controller
Controller
Controller
ATA
PCI
PCI
Fibre
Fibre
ADM
ADM
1026
1026
Sahalee
IPMC
Sahalee
IPMC
IPMC
(4MB/s)
33 MHz
LPC
Intel® ICH3
Intel® ICH3
266 MB/s HI 1.5
1066
MB/s
HI-2
1066
Intel® E7501
Intel® E7501
Intel® E7501
Intel® E7501
Intel® E7501
Intel® E7501
MB/s
HI-2
Controller Hub
Controller Hub
Controller Hub
Controller Hub
Controller Hub
Controller Hub
400MT/s 3.2GB/s
Intel
Intel
82802AC
82802AC
(FWH0)
(FWH0)
Memory
Memory
Memory
Memory
Memory
Memory
(MCH)
(MCH)
(MCH)
(MCH)
(MCH)
(MCH)
On-board Power
On-board Power
Supplies and Hot
Supplies and Hot
Swap Circuitry
Swap Circuitry
IPMB Isolators
IPMB Isolators
IPMB Isolators
IPMB Isolators
IPMB Isolators
IPMB Isolators
IPMB Isolators
IPMB Isolators
Intel
Intel
82802AC
82802AC
(FWH1)
(FWH1)
Four
Four
Four
Four
Four
Four
184-pin
184-pin
184-pin
184-pin
184-pin
184-pin
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
Sockets
Sockets
Sockets
Sockets
Sockets
Sockets
DDR-266
DDR-266
DDR-266
DDR-266
DDR-266
DDR-266
ECC
ECC
ECC
ECC
ECC
ECC
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
2.1 GB/s
DDR-266
2.1 GB/s
DDR-266
-48V
IPMB-A
IPMB-B
SMBUS
P10
Backplane
J23
MUX
MUX
Dual FC
Ports
Dual SFP
Dual SFP
Connectors
Connectors
MPCBL0001Fxx
products only
Intel NetStructure
®
MPCBL0001 High Performance Single Board Computer 15
Technical Product Specification
Low Voltage
Low Voltage
Intel® Xeon™
Intel® Xeon™
Processor
Processor
Low Voltage
Low Voltage
Intel® Xeon™
Intel® Xeon™
Processor
Processor
Dual Fibre Channel Ports to Fabric Interface
Dual Gigabit Ethernet Ports to Base Interface
Features Overview
2.2.1 Low Voltage Intel® Xeon
(U36)
The MPCBL0001 SBC supports up to two Low Voltage Intel® Xeon™ processors (see Figure 20,
“Intel NetStructure® MPCBL0001 Component Layout” on page 90 for locations). The Low
Voltage Xeon processor incorporates Intel
Front-Side Bus, allowing performance levels that are significantly higher than previous generations
of IA-32 family processors. The processors include the following features:
• 2.0 GHz with a 400 MHz system bus
• 512 Kbyte L2 cache
• Hyper-pipelined technology
• Advanced dynamic execution
• Execution trace cache
• Streaming SIMD (single instruction, multiple data) extensions 2
• Advanced transfer cache
• Enhanced floating point and multimedia engine
• Intel & OEM EEPROM and thermal sensor manageability features
• Supports single and dual processor configurations
• Throttling enabled for protection against high temperatures
™
Processor CPU-0 (U35), CPU-1
®
NetBurst™ microarchitecture and a high-bandwidth
The Low Voltage Xeon processor host bus utilizes a split-transaction, deferred-reply protocol. The
host bus uses source-synchronous transfer of address and data to improve throughput at the 100 or
133 MHz bus frequency (depending on processor model). Addresses are transferred at 2X the bus
frequency while data is transferred at 4X the bus frequency, resulting in peak data transfer rates up
to 3.2 or 4.3 GBytes/s.
In addition to the NetBurst microarchitecture, the Low Voltage Intel Xeon processor includes a
groundbreaking technology called Hyper-Threading Technology
Technology improves processor performance for multithreaded applications or multitasking
environments by supporting multiple software threads on each processor.
Low Voltage Intel Xeon processors require their package case temperatures to be operated below
an absolute maximum specification. If the chassis ambient temperature exceeds a level whereby
the processor thermal cooling subsystem can no longer maintain the specified case temperature, the
processors will automatically enter a mode called Thermal Monitor to reduce their case
temperatures. Thermal Monitor controls the processor temperature by modulating the internal
processor core clocks, thereby reducing internal power dissipation, and does not require any
interaction by the Operating System or Application. Once the case temperatures have reached a
safe operating level, the processor will return to its non-modulated operating frequency. See the
Low Voltage Intel Xeon processor datasheet, referenced in Appendix A, “Reference Documents”,
for further details.
An optional ITP700 port connection is included to facilitate debug and BIOS/software
development efforts. This JTAG connection to the processors utilizes voltage-signaling levels that
are specific to the Low Voltage Xeon processor family. These levels must not be exceeded or
processor damage may occur. Please refer to Intel document ITP700 Debug Port Design Guide,
order number 249679-005 for additional information on the ITP connector pin defi nitions.
†
(HT Te chnology). HT
16 Intel NetStructure
®
MPCBL0001 High Performance Single Board Computer
Technical Product Specification
2.2.2 Chipset
The Intel® E7501 chipset consists of three major components:
®
• Intel
• Intel
• Intel
See Figure 20, “Intel NetStructure® MPCBL0001 Component Layout” on page 90 for their
locations.
2.2.2.1 Intel® E7501 Memory Controller Hub (U22)
The Intel® E7501 Memory Controller Hub (MCH) interfaces between the processor system bus
and the memory and I/O subsystems.
Significant features are listed below:
• System/host bus features:
E7501 Memory Controller Hub (MCH)
®
82801CA I/O Controller Hub 3 (ICH3)
®
82870P2 64-bit PCI/PCI-X Controller Hub 2 (P64H2)
— Supports dual processors at either 400 or 533 MT/s or a bandwidth of 3.2 or 4.3 GBytes/s
— Supports a 36-bit system bus addressing model
— 12 deep in-order queue, two deep defer queue
Features Overview
Note: The current MPCBL0001 is designed to run with the Intel
processor frequency, the processor side bus (PSB) will run at 400 MT/s with a bandwidth of 3.2
GBytes/s.
• Memory subsystem features:
— 144-bit wide (72-bit x 2), DDR-266 memory interfaces with 3.2 or 4.3 GByte/s bandwidth
— Supports x72, registered DDR-266 ECC DIMMs using 64-, 128-, 256-, and 512-Mbit
SDRAMs
— Supports a maximum of 16 GBytes of memory (MPCBL0001 SBC implementation
supports a maximum of 8 Gbytes).
— Supports S4EC/D4ED ChipKill* ECC (x4 ChipKill)
• Corrects all bit errors within a single 4-bit nibble
• Detects all errors contained within two 4-bit nibbles
• Memory scrubbing supported
— Supports up to 32 simultaneous open pages
— Hardware support for auto-initialization of memory with valid ECC
• I/O features:
— Hub interface A provides HI 1.5 connection for ICH3
• 266 MB/s data bandwidth with parity protection
• 8 bits wide, 66 MHz clock, 4x data transfer (quad-pumped)
• Supports 64-bit inbound addressing, 32-bit outbound addressing
— Hub interfaces B and C provide HI2.0 connections for two P64H2s
• 1 GByte/s data bandwidth with ECC protection in each direction
®
LV Xeon® 2.0 GHz processor. At this
Intel NetStructure
Technical Product Specification
®
MPCBL0001 High Performance Single Board Computer 17
Features Overview
• 16-bits wide, 66 MHz clock, 8x data transfer (octal pumped)
• Supports 64-bit inbound, 32-bit outbound addressing
The MCH I/O subsystems interface incorporates four hub interfaces. Each Hub interface is a pointto-point connection between the MCH and an I/O bridge/device. The various components of the
chipset communicate via these connected hub interfaces:
• The first hub link connects the MCH to the ICH3.
• The next two hub link interfaces connect the MCH to P64H2 components.
• The remaining hub link is unused.
2.2.2.2 Intel® 82801CA I/O Controller Hub 3 (U7)
The Intel® 82801CA I/O Controller Hub 3 (IHC3) provides the legacy I/O subsystem and
integrates advanced I/O functions. ICH3 features are listed below:
• IDE interface controller
• Three Universal Host Controller Interface (UHCI)
• USB host controllers supporting up to 6 ports (MPCBL0001 SBC implementation supports
one port on the front panel)
• Integrated I/O APIC
• SMBus 2.0 controller
• LPC interface
• Watchdog timer #3 (see “Watchdog Timers (WDTs)” on page 62)
• PCI 2.2 bus interface supporting 32bit/33 MHz operation
• Connects to MCH through Hub Interface A (HI 1.5)
The MPCBL0001 SBC implements one USB port and does not use the ICH3 PCI connection.
2.2.2.2.1 PCI Bus Master IDE Interface (J24)
The ICH3 acts as a PCI based, enhanced IDE, 32-bit interface controller for intelligent disk drives
that have disk controller electronics onboard. The SBC includes a single 40-pin (2 x 20) IDE
connector (J24) that supports one master or one slave device. See Figure 20, “Intel NetStructure®
MPCBL0001 Component Layout” on page 90 drawing for its location. The IDE controller
provides support for an internally mounted 2.5” hard disk. The IDE control ler has the following
features:
• PIO and DMA transfer modes
• Mode 4 timings
• Supports Ultra ATA33/66/100 synchronous DMA
• Buffering for PCI/IDE burst transfers
• Master/slave IDE mode
• Support for up to two devices (Master/Slave) via a single primary IDE connector
(MPCBL0001 SBC implementation supports one optional physical 2.5" IDE device)
Note: Incorporating an optional IDE Hard Disk drive may significantly impact the Reliability
Specifications in Section 6.3.
18 Intel NetStructure
®
MPCBL0001 High Performance Single Board Computer
Technical Product Specification
Features Overview
Note: Performance of the IDE interface may be impacted by the DMA mode and type of DMA transfers
used. Even though the BIOS automatically sets the DMA mode/type, the OS could downgrade the
DMA transfer mode. Check the operating system documentation to see what DMA mode is used
by default and whether it is possible to change to a higher performance DMA mode.
2.2.2.3 Intel® 82870P2 64-bit PCI/PCI-X Controller Hub 2 (U14, U24)
The two P64H2 devices provide the system’s high-performance PCI bus support. See Figure 20,
“Intel NetStructure® MPCBL0001 Component Layout” on page 90 for their locations. Each
P64H2 component supports two independent, 64-bit, PCI/PCI-X interfaces. 32-bit/33 MHz and 64bit/66 MHz PCI bus modes are also supported. Each PCI bus interface features:
• PCI-X 1.0 Specification compliance
• PCI Specification 2.2 compliance
• PCI-PCI Bridge Rev 1.1 compliance
• PCI Hot Plug 1.0 compliance
• I/O APIC supporting up to 24 interrupts (16 external pins)
• PCI peer-to-peer write capability between PCI ports
• SMBus target for Out-of-Band access to all internal PCI registers
Each of the two P64H2 devices (U14, U24) included on the MPCBL0001 SBC provides the bridge
to two independent PCI bus connections, as shown in Table 1, “P64H2 Interfaces” on page 19.
Table 1. P64H2 Interfaces
P64H2 Device Interface
U24 PCI-X interface to the optional dual Fibre Channel controller
U14
The two high-speed communications interfaces (Gigabit Ethernet and Fibre Channel) are located in
separate P64H2 devices to maximize data throughput. A single HI-2 hub link connection from the
P64H2 to the MCH provides a >1 Gbyte/s bandw idth back to memory and the processor System
Bus.
• PCI-X interface to the dual Gigabit Ethernet controller
• 64-bit/66 MHz PCI bus for a plug-in PMC card
2.2.3 Memory (J8, J9, J10, J11)
Four DDR 266 DIMM sockets make up the memory subsystem. See Figure 20, “Intel
NetStructure® MPCBL0001 Component Layout” on page 90 for their locations. The MCH defines
two memory channels operating in parallel to logically create a 144-bit wide memory data path.
ECC is generated and checked across 128 bits of data, allowing for significant improvement in
error correction.
Due to this architecture, DDR DIMMs must be installed in matched pairs. Memory DIMM
configurations ranging from 512 MBytes to 8 GBytes in 512 MByte increments are supported.
Intel NetStructure
Technical Product Specification
®
MPCBL0001 High Performance Single Board Computer 19
Features Overview
2.2.3.1 Memory Ordering Rule for the MCH
Platforms based on the E7501 chipset require DDR DIMMs to be populated in matched pairs in a
specific order. Start with the two DIMMs furthest from the MCH in a “fill-farthest” approach (see
Figure 2). This requirement is based on the signal integrity requirements of the DDR interface.
Figure 2. Memory Ordering
MCH, U22
J8
Fill
Last
J9
Fill
First
J11
J10
2.2.4 I/O
2.2.4.1 Super I/O (U28)
The Super I/O device (SIO) is an SMSC LPC47B272 enhanced Super I/O controller. The SIO
connects to the ICH3 through its LPC bus connection. The SIO provides support for the front panel
serial port (J17, see page 70). There is no front-panel connection to the legacy keyboard and mouse
PS/2 ports. Keyboard and mouse support are provided by the USB connection (J12, see page 77).
See Figure 13 for connector locations.
20 Intel NetStructure
B0894-01
®
MPCBL0001 High Performance Single Board Computer
Technical Product Specification
To facilitate debug and BIOS development, SIO connections such as legacy (PS/2) keyboard/
mouse and floppy may be provided on initial board revisions. Software must not rely on the
presence of these connections on future board revisions.
2.2.4.2 Real-Time Clock
The MPCBL0001 SBC real-time clock is integrated into the ICH3. It is derived from a 32.768 KHz
crystal with the following specifications:
• Frequency tolerance @ 25 ºC: ±20ppm
• Frequency stability: maximum of -0.04ppm/(ΔºC)
• Aging ΔF/f (1
st
year @ 25 ºC): ±3ppm
• ±20ppm from 0-55 ºC and aging 1ppm/year
The real-time clock is powered by a 0.22F SuperCap* capacitor when main power is not applied to
the board. This capacitor powers the real-time clock for a minimum of two hours while external
power is removed from the MPCBL0001 SBC.
See Section 3.13, “Watchdog Timers (WDTs)” on page 62 for information about the real-time
clock timers.
Features Overview
2
2.2.4.3 Timer0 Capabilities
Timer0, integrated inside the ICH3, is an 8254 compatible timer. This timer is set up to generate a
periodic waveform that creates the edge for the timer0 interrupt. The interrupt is received by the
ICH3 APIC and communicated to the CPU(s).
MPCBL0001 provides a high-precision 14.318 MHz crystal clock source as the reference for the
timer0 counters. To improve timing accuracy, the crystal used is a low-PPM, high-stability
component with the following specifications:
• Frequency tolerance (25º C): ±10ppm
• Temperature characteristics (-10º C to +60º C): ±5ppm
• Aging: ±1ppm per year max
This timer does not operate when board power is removed.
2.2.4.4 Gigabit Ethernet (U13)
The MPCBL0001 SBC implements two Gigabit Ethernet interfaces, each of which is routed to the
fabric/switch slot through the backplane (J23, see page 75). There are no direct, external Ethernet
ports included on the SBC board. Each Ethernet connection utilizes an 82546 Dual Gigabit
Ethernet Controller, allowing support for 1000Mbits/s, 100Mbits/s and 10Mbits/s data rates.
The 82546 controller is optimized for designs using the PCI and the emerging PCI-X bus interface
extension. The MPCBL0001 SBC has a 133 MHz PCI-X bus connection. The integrated physical
layer circuitry (PHY) provides an IEEE 802.3 Ethernet Interface for 1000Base-T, 100Base-TX,
and 10Base-T applications.
Features include:
• 32/64-bit 33/66 MHz, PCI Rev 2.2 compliant interface
Intel NetStructure
Technical Product Specification
®
MPCBL0001 High Performance Single Board Computer 21
Features Overview
• Host interface also compliant with the PCI-X addendum, Rev 1.0a, from 50 to 133 MHz
• Supports 64-bit addressing
• Efficient PCI bus master operation, supported by optimized internal DMA controller
• Supports advanced PCI commands such as MWI, MRM, and MRL, and PCI-X commands
such as MRD, MRB, and MWB
• Full IEEE 802.3ab auto-negotiation of speed, duplex, and flow-control configuration
• Complete full duplex and half duplex support
• Automatic MDI crossover operation for 100Base-TX and 10Base-T modes
• Automatic polarity correction
• Digital implementation of adaptive equalizer and canceller for echo and crosstalk
2.2.4.5 Fibre Channel* (U23) - Optional
The QLogic* ISP2312 dual Fibre Channel controller is used for access to high-speed storage
subsystems. It is routed through backplane connector P23.
See Figure 20, “Intel NetStructure® MPCBL0001 Component Layout” on page 90 for its location.
This controller supports PCI and PCI-X bus interfaces. Burst mode master DMA transfers are
utilized for efficient usage of bus bandwidth during data transfers, and 8, 16, and 32-bit accesses
are supported as a PCI target. The controller appears as two independent Fibre Channel ports. A
PCI function is assigned to each port in the device’s PCI configuration space. Functions 0 and 1 are
used to configure FC ports 1 and 2, respectively.
ISP2312 features include:
• 32/64-bit 33/66 MHz, PCI Rev 2.2 compliant interface.
• Host interface compliant with the PCI-X addendum, Rev 1.0a, from 50 to 133 MHz.
• Supports 64-bit addressing (addresses >32 bit initiate use of DAC address cycle).
• Efficient PCI bus master operation, supported by optimized internal DMA controller.
• Supports advanced PCI commands such as MWI, MRM, and MRL, and PCI-X commands
such as MRD, MRB, and MWB.
• Automatically negotiates Fibre Channel bit rate 1.06 Gbits/s (through backplane or front
panel) or 2.12 Gbits/s (through front-panel Fibre Channel ports only)
• Supports up to 533 MBytes sustained FC data transfer rate (combined bandwidth of both
directions transmitting simultaneously).
• Supports Fibre Channel-arbitrated loop (FC-AL), FC-AL-2, point-to-point, and switched
fabric topologies.
• Maxim MAX3840 2x2 crosspoint switch for switching Fibre Channel between the front ports
and the backplane, either via the BIOS Setup Menu by electronic keying.
• Each FC port includes:
— Internal RISC processor
— Receive DMA sequencer
—Frame buffer
22 Intel NetStructure
®
MPCBL0001 High Performance Single Board Computer
Technical Product Specification
— DMA channels (transmit, receive, command, auto-request, and auto-response)
• Support for JTAG boundary scan.
• Supports IP as well as other protocols; however there are currently no plans to validate
protocols other than SCSI_FCP.
Each Fibre Channel interface of the ISP2312 includes its own internal 16-bit RISC processor and
external 7.5 ns synchronous SRAM memory for instruction code and data. Parity protection is
provided on accesses to this memory. The SBC utilizes two 256 KByte (128Kx18) SRAMs, one for
each port, for the ISP2312 memory requirements.
An external 256 x 16 non-volatile EEPROM is used to store system configuration parameters and
PCI subsystem and subsystem vendor IDs. The first 128 bytes are used fo r function 0 parameters
and the second 128 bytes are used for function 1.
2.2.5 PMC Connector (J25, J26, J27)
The MPCBL0001 SBC supports one 64-bit, 66 MHz PMC slot. The PMC slot is connected to the
second of two P64H2 hub controllers via PMC Connectors J25-J27. The PMC slot has an opening
in the front panel of the SBC that exposes the I/O connectors of the add-in PMC card. PMC cards
can only be added to or removed from this slot when the board is outside the system chassis. See
Figure 20, “Intel NetStructure® MPCBL0001 Compo nent Layou t” on page 90 for its location.
Features Overview
The PCI bus specification provides the means for backward compatibility with slower PMC cards
(32-bit or 33 MHz) through the use of the M66EN pin. A PMC card that does not support 66 MHz
operation grounds the M66EN pin when installed to inform the SBC hardware to provide a 33
MHz clock to this interface. Support for 32-bit only PMC cards is accomplished through the use of
the REQ64#/ACK64# PCI bus protocol.
The PMC slot provided by the SBC connects the PCI VI/O voltage pins to +3.3 V. This requires
use of PMC plug-in cards that support +3.3 V I/O signal levels. Only PM C plug-in cards
designated “+3.3 V only” or “univ e rsal” voltage I/O are supported. The PMC plug-in location
provides a key pin to prevent insertion of cards that do not meet this requirement. Note that +5 V
power is still supplied to the PMC pins designated for +5 V connections. The PMC is allotted 1.5 A
of current.
2.2.6 Firmware Hub (U30, U33)
The MPCBL0001 SBC supports two 8Mbit (1 MByte) BIOS flash ROMs:
• Primary BIOS flash ROM (FWH0)
• Recovery BIOS flash ROM (FWH1)
The flash is allocated for BIOS and Firmware usage.
The SBC boots from the primary flash ROM under normal circumstances. During the boot process,
if the BIOS (or IPMC) determines that the contents of the primary flash ROM are corrupted, a
hardware mechanism is available to change the flash device select logic to the recovery flash
ROM. See Section 2.2.6.3, “Flash ROM Backup Mechanism” on page 24 for more information.
Each flash component has a separately write-protected boot block that prevents erasure when the
device is upgraded.
Intel NetStructure
Technical Product Specification
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MPCBL0001 High Performance Single Board Computer 23
Features Overview
Flash ROM BIOS updates can be performed by an end user or a network administrator over the
LAN. The system should complete booting to an OS, MS-DOS* or logon to Linux* as root user.
The system should have a local copy of the flash program and the BIOS data files or have the
capability to copy the flash program and BIOS data files onto a local drive via the network. The
flash program has a command line interface to specify the path and the file name of the BIOS data
files. After completing the BIOS ROM update the user should shutdown and reset the system to let
the new BIOS ROM take effect. See Section 7.7, “BIOS Updates” on page 102 for more
information.
2.2.6.1 FWH 0 (Main BIOS)
BIOS execute code off this flash and perform checksum validation of its operational code. This
checksum occurs in the boot block of the BIOS. The BIOS image is also stored in FWH0. When
user performs BIOS update, the BIOS image will be stored in FWH 0 only. FWH0 will also store
the factory default CMOS settings user configured CMOS settings.
1. When user "Load optimal defaults" from the BIOS setup screen, it restores the factory default
by copying the "Factory Default" settings from FWH0 to ICH3 (CMOS).
2. When user "Save custom defaults" from the BIOS setup screen, the changes will be made to
the CMOS settings on ICH3 and then copied from ICH3 to FWH0.
3. When user "Load custom defaults" from the BIOS setup screen, the "custom" CMOS settings
are copied from FWH0 to ICH3.
2.2.6.2 FWH 1 (Backup/Recovery BIOS)
FWH 1 stores the recovery BIOS. In the event of checksum failure on the Main BIOS operational
code, BIOS will request BMC to switch FWH, so that the board will be able to boot up from FWH1
for recovery.
User is able to boot up the board from FWH1 by executing an OEM IPMI command as well (see
Section 3.7.1, “Reset BIOS Flash Type” on page 47 ).
2.2.6.3 Flash ROM Backup Mechanism
The on-board Intelligent Platform Management Controller (IPMC) manages which of the two
BIOS flash ROMs is used during the boot process. The IPMC mon itors the boot progress and can
change the flash ROM selection and reset the processor.
The default state of this control configures the primary Firmware Hub (FWH) ROM device ID to
be the boot device; the secondary FWH is assigned the next ID. The secondary FWH responds to
the address range just below the primary FWH ROM in high memory.
The Intelligent Platform Management Controller sets the ID for both FWH devices. Boot accesses
are directed to the FWH with ID = 0; unconnected ID pins are pulled low by the FWH device. In
this way the IPMC may select which flash ROM is used for the boot process.
Refer to Section 3.7.1, “Reset BIOS Flash Type” on page 47 for a description of how to do this
manually.
24 Intel NetStructure
®
MPCBL0001 High Performance Single Board Computer
Technical Product Specification
2.2.7 Onboard Power Supplies
The main power supply rails on the MPCBL0001 SBC are powered from dual-redundant -48 V
power supply inputs from the backplane power connector (P10). There are also dual redundant,
limited current, make-last-break-first (MLBF) power connections. See Figure 20, “Intel
NetStructure® MPCBL0001 Component Layout” on page 90 for their location.
2.2.7.1 Power Feed Fuses
As required by the PICMG 3.0 Specification, the MPCBL0001 SBC provides fuses on each of the
-48V power feeds and on the RTN connections as well . The fuses on the return feeds are critical to
prevent overcurrent situations if an ORing diode in the return path fails and there is a voltage
potential difference between the A and B return paths.
2.2.7.2 ORing Diodes and Circuit Breaker Protection
The two -48 V power connectors are OR’d together. A current limiting FET switch is connected
between the OR’d -48 V and the primary DC-DC converters. The FET switch provides three
functions:
• A mechanism to electrically connect/disconnect the SBC to/from the two -48 V inputs.
• A soft-on function.
Features Overview
• An over-current circuit breaker feature.
2.2.7.3 -48 V to +12 V Converter
This converter provides DC isolation between the -48 V and -48 V return connections and all of the
derived DC power on the MPCBL0001 SBC. Its output is connected to the SBC’s +12 V power
rail. The converter supplies a maximum of 9 A of current. The converter is enabled/disabled by the
onboard IPMC.
2.2.7.4 -48 V to +5 V/+3.3 V Converter
This converter provides DC isolation between the -48 V and -48 V return connections and all of the
derived DC power on the MPCBL0001 SBC. Its output is connected to the SBC’s +5 V and 3.3 V
power rails. The converter supplies a maximum of 9 A of +5 V current and 9 A of +3.3 V current.
The converter is enabled/disabled by the onboard IPMC.
2.2.7.5 Processor Voltage Regulator Module (VRM)
The Voltage Regulator Module (VRM) provides core power to the two Low Voltage Xeon
processors. The input to the VRM is connected to the +12 V power rail.
See Figure 20, “Intel NetStructure® MPCBL0001 Component Layout” on page 90 for its location.
Intel NetStructure
Technical Product Specification
®
MPCBL0001 High Performance Single Board Computer 25
Features Overview
The VRM controller is designed to support multiple processor core voltages selected by the voltage
identification (VID) pins on the processor. Logic provided on the SBC ensures that the VRM is not
enabled if the two processors request different VID codes. In addition, the VRM is disabled until
all other voltage converters indicate “power good.” The voltage regulator module is designed to
support up to two 43 W (TDP - Thermal Design Power) processors.
Note: The +5 VSB power rail only needs to supply at least 4.0 V to properly power any circuitry that uses
the +5 VSB rail when the payload power (i.e., processors, ethernet controller, etc.) is not turned on.
Any alerts from the +5 VSB sensor when the system is not in the M4, M5, or M6 states should be
ignored.
2.2.7.6 IPMB Standby Power
This converter provides DC isolation between the -48 V and -48 V return connections and all of the
derived DC power on the MPCBL0001. Its output is connected to the IPMB and standby +5 V
power rail of the SBC. The converter supplies a maximum of 1.5 A of +5 V current. A +3.3 V
management voltage is derived from the IPMB power by means of a linear regulator circuit and is
used to power most of the IPMC functions. Standby power is derived from the -48 V rails and is
always available on the SBC unless the overall system power rail (-48 V) is shut down.
26 Intel NetStructure
®
MPCBL0001 High Performance Single Board Computer
Technical Product Specification
Hardware Management Overview
Hardware Management Overview 3
The Intelligent Platform Management Controller (IPMC) is an Intel-designed baseboard
management controller device manufactured by Philips Semiconductor* for Intel.
The high-level architecture of the baseboard management for MPCBL0001 is represented in the
block diagram below.
Figure 3. Hardware Management Block Diagram
ADM 1026
Wat chdog Tim er
CPU
(Low Voltage Int el
Xeon™)
Intel® E7501 Memory
Controller H ub (MCH)
ICH3
Intelligent Platform
Management Controller
(IPMC)
Flash
Mem ory
SRAM
®
NOT E:
IPMB A
I
P
M
B
B
I2C Bus
KCS interf ace
Logic C onnect ion
Back plane
(P10)
The main processors communicate with the IPMC using the Keyboard Controller Style (KCS)
interface. T wo KCS interfaces are available for the BIOS to communicate to the IPMC. BIOS uses
SMS interface for normal communication and SMM interface when executing code under systems
management mode (SMM). The base address of the LPC interface for SMS is 0xCA2 and 0xCA4
for SMM operation. Besides that, the BIOS is able to communicate with the IPMC for POST error
logging purposes, fault resilient purposes, and critical interrupts via the KCS interface.
The memory subsystem of the IPMC consists of a flash memory to hold the IPMC operation code,
firmware update code, system event log (SEL), and a sensor data record (SDR) repository. RAM is
used for data and occasionally as a storage area for code when flash programming is under
execution. The field replacement unit (FRU) inventory information is stored in the nonvolatile
memory on ADM1026. The flash memory can store up to 64 KBytes of SEL events and SDR
information, while the ADM1026 can store up to 512 bytes of FRU information. Having the SEL
and logging functions managed by the IPMC helps ensure that ‘post-mortem’ logging information
is available even if the system processor becomes disabled.
Intel NetStructure
Technical Product Specification
®
MPCBL0001 High Performance Single Board Computer 27
Hardware Management Overview
The IPMC provides six I2C bus connections. Two are used as the redundant IPMB bus connections
to the backplane while another one is used for communication with the ADM1026. The remaining
buses are unused. If an IPMB bus fault or IPMC failure occurs, IPMB isolators are used to switch
and isolate the backplane/system IPMB bus from the faulted SBC board. Where possible, the
IPMC activates the redundant IPMB bus to re-establish system management communication to
report the fault.
The onboard DC voltages are monitored by the ADM1026 device, manufactured by Analog
Devices. The IPMC queries the ADM1026 over a local system management I
ADM1026 includes voltage threshold settings that can be configured to generate an interrupt to the
IPMC if any of the thresholds are exceeded.
To increase the reliability of the MPCBL0001 SBC, a watchdog timer is implemented, whereby it
strobes an external watchdog timer at two-second intervals to ensure continuity of operation of the
board’s management subsystem. If the IPMC ceases to strobe the watchdog timer, the watchdog
timer isolates the IPMC from the IPMBs and resets the IPMC. The watchdog timer expires after six
seconds if strobes are not generated, and it resets the IPMC. Detailed information on the watchdog
timer configuration can be queried using standard IPMI v1.5 watchdog timer commands. The
watchdog timer does not reset the payload power.
3.1 Sensor Data Record (SDR)
Sensor Data Records contain information about the t ype and number of sensors in the baseboard,
sensor threshold support, event generation capabilities, and the types of sensor readings handled by
system management firmware.
The MPCBL0001 management controller is set up as a satellite management controller (SMC). It
does support sensor devices, whose population is static by nature. SDRs can be queried using
Device SDR commands to the firmware. Refer to Section B, “List of Supported Commands (IPMI
v1.5 and PICMG 3.0)” on page 163 for the list of supported IPMI commands for SDRs. Hardware
sensors that have been implemented are listed below.
Table 2. Hardware Sensors (Sheet 1 of 3)
2
C bus. The
Sensor
Number
03h Watchdog Timer IPMC Watchdog
06h System Firmware
07h CPU Critical
08h Memory Error ECC Multiple Bit
09h Power Unit Payload Power IPMC Power On Soft power control
Sensor Type
Progress
Interrupt
Volt age/Signals
Monitored
Timer timeout
PCI SERR IPMC Power On PCI SERR signal
PCI PERR IPMC Power On PCI PERR signal
error
ECC Single Bit error IPMC Power On No change
28 Intel NetStructure
Monitored
via
IPMC Power On/
IPMC Power On No change
IPMC Power On Multiple Bit Error or
®
MPCBL0001 High Performance Single Board Computer
Scanning
Enabled
under Power
State
Off
Health LED
(Green to Red)
No change
asserted
asserted
Uncorrectable ECC
occurred
failure (Offset Bit 05h
asserted
Technical Product Specification
Table 2. Hardware Sensors (Sheet 2 of 3)
Hardware Management Overview
Sensor
Number
Sensor Type
Voltage/Signals
Monitored
Monitored
via
10h Voltage 3.3 VSB ADM 1026 Power On/
11h Voltage +5 VSB ADM 1026 Power On/
12h +1.8 VSB ADM 1026 Power On/
13h V BAT ADM 1026 Power On/
Scanning
Enabled
under Power
State
Off
Off
Off
Off
Health LED
(Green to Red)
Exceeds critical
threshold
Exceeds critical
threshold
Exceeds critical
threshold
Exceeds critical
threshold
14h +1.2 V ADM 1026 Power On Exceeds critical
threshold
15h VTT DDR (+1.25 V) ADM 1026 Power On Exceeds critical
threshold
16h +1.8 V ADM 1026 Power On Exceeds critical
threshold
17h +2.5 V ADM 1026 Power On Exceeds critical
threshold
18h +3.3 V ADM 1026 Power On Exceeds critical
threshold
19h +5 V ADM 1026 Power On Exceeds critical
threshold
30h Temperature Board Temperature ADM 1026 Power On/
Off
Exceeds critical
threshold
37h CPU 0 Temperature ADM 1026 Power On Exceeds critical
threshold
38h CPU 1 Temperature ADM 1026 Power On Exceeds critical
threshold
50h Processor CPU 0 Presence ADM 1026 Power On/
IERR signal asserted
Off
50h CPU 0 IERR IPMC Power On No change
50h CPU 0 Thermtrip IPMC Power On ThermTrip signal
asserted
50h CPU 0 Non-
Presence
51h CPU 1 Presence ADM 1026 Power On/
ADM 1026 Power On/
Off
CPU 0 is detected as
missing
IERR signal asserted
Off
51h CPU 1 IERR IPMC Power On No change
51h CPU 1 Thermtrip IPMC Power On ThermTrip signal
asserted
54h Boot Error BIOS Main Flash IPMC Power On No change
55h BIOS FRED Flash IPMC Power On No change
56h CPU 0 ProcHot
57h CPU1 ProcHot
82h ACPI State ACPI State IPMC Power On/
1
IPMC Power On ProcHot signal asserted
1
IPMC Power On ProcHot signal asserted
No change
Off
Intel NetStructure
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MPCBL0001 High Performance Single Board Computer 29
Technical Product Specification
Hardware Management Overview
Table 2. Hardware Sensors (Sheet 3 of 3)
Sensor
Number
83h System Event System Event IPMC Power On No change
1Ah +12 V ADM 1026 Power On Exceeds critical
1Bh -12 V ADM 1026 Power On Exceeds critical
1Ch CPU Core Voltage ADM 1026 Power On Exceeds critical
1Dh Voltage +1.5 V ADM 1026 Power On Exceeds critical
8Ah FRU Hot Swap FRU State IPMC Power On/
8Bh IPMB Link Sensor Operational state of
E0h SMI Timeout Steady state
NOTE: The PROCHOT signal is a discrete signal but it is treated as a threshold sensor so that it can have a
Sensor Type
Sensor Type of Temperature. IPMI does not have a discrete sensor type for temperatures. The
advantage of the PROCHOT sensor acting as a temperature sensor is that the CMM can recognize
events from this sensor as temperature events and adjust fan speed accordingly.
Volt age/Signals
Monitored
IPMB-0
assertion of the SMI
line
Monitored
via
Logical Power On/
IPMC Power On SMI Line asserted
Scanning
Enabled
under Power
State
Off
Off
Health LED
(Green to Red)
threshold
threshold
threshold
threshold
No change
No change
(Offset bit 01h asserted)
3.2 System Event Log (SEL)
The SEL is the collection of events that are generated by the IPMC. Event logs are stored in nonvolatile memory. This resides on the board and allows better tracking of error conditions on the
baseboard when it is moved from chassis to chassis. Having the SEL and logging functions
managed by the IPMC helps ensure that post-mortem logging information is available should a
failure occur that disables the systems processor(s). In the MPCBL0001, flash memory for IPMI
firmware can store up to 3276 SEL entries. Management software running on the host processor is
responsible for ensuring that SEL storage has sufficient space for SEL logging. Events are
normally forwarded to shelf manager and logged to SEL on the board. If SEL storage on the board
is full, new events are forwarded to the Shelf Manager but are not logged in to SEL on the board.
A set of IPMI commands (see T able 97, “IPMI 1.5 Supported Commands” on page 163) allows the
SEL to be read and cleared and allows events to be added to the SEL. The IPMI commands used
for adding events to the SEL are Platform Event Message, Add SEL entry, and Partial Add Entry.
T able 3, “SEL Events Supported by the MPCBL0001 SBC” on page 31 lists supported SEL events.
Event Messages can be sent to the IPMC via the IPMB. This provides the mechanism for satellite
controllers to detect events and log them into the SEL.
30 Intel NetStructure
®
MPCBL0001 High Performance Single Board Computer
Technical Product Specification
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