Intel L- and H-Tile Transceiver PHY User Manual

L- and H-Tile Transceiver PHY User

Guide

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	Contents
Contents
1. Overview........................................................................................................................	7
1.1. L-Tile/H-Tile Layout in Intel Stratix 10 Device Variants................................................	8
1.1.1. Intel Stratix 10 GX/SX H-Tile Configurations..................................................	8
1.1.2. Intel Stratix 10 TX H-Tile and E-Tile Configurations.......................................	10
1.1.3. Intel Stratix 10 MX H-Tile and E-Tile Configurations......................................	12
1.2. L-Tile/H-Tile Counts in Intel Stratix 10 Devices and Package Variants..........................	14
1.3. L-Tile/H-Tile Building Blocks...................................................................................	16
1.3.1. Transceiver Bank Architecture....................................................................	17
1.3.2. Transceiver Channel Types........................................................................	17
1.3.3. GX and GXT Channel Placement Guidelines..................................................	19
1.3.4. GXT Channel Usage..................................................................................	19
1.3.5. PLL and Clock Networks............................................................................	20
1.3.6. Ethernet Hard IP......................................................................................	23
1.3.7. PCIe Gen1/Gen2/Gen3 Hard IP Block..........................................................	25
1.4. Overview Revision History.....................................................................................	28
2. Implementing the Transceiver PHY Layer in L-Tile/H-Tile............................................	30
2.1. Transceiver Design IP Blocks.................................................................................	30
2.2. Transceiver Design Flow........................................................................................	31
2.2.1. Select the PLL IP Core..............................................................................	31
2.2.2. Reset Controller ......................................................................................	32
2.2.3. Create Reconfiguration Logic.....................................................................	32
2.2.4. Connect the Native PHY IP Core to the PLL IP Core and Reset Controller..........	32
2.2.5. Connect Datapath ...................................................................................	33
2.2.6. Modify Native PHY IP Core SDC..................................................................	33
2.2.7. Compile the Design..................................................................................	33
2.2.8. Verify Design Functionality........................................................................	33
2.3. Configuring the Native PHY IP Core........................................................................	34
2.3.1. Protocol Presets.......................................................................................	35
2.3.2. GXT Channels..........................................................................................	36
2.3.3. General and Datapath Parameters .............................................................	36
2.3.4. PMA Parameters......................................................................................	39
2.3.5. PCS-Core Interface Parameters..................................................................	42
2.3.6. Analog PMA Settings Parameters................................................................	47
2.3.7. Enhanced PCS Parameters ........................................................................	53
2.3.8. Standard PCS Parameters.........................................................................	57
2.3.9. PCS Direct Datapath Parameters...............................................................	61
2.3.10. Dynamic Reconfiguration Parameters........................................................	61
2.3.11. Generation Options Parameters................................................................	64
2.3.12. PMA, Calibration, and Reset Ports.............................................................	64
2.3.13. PCS-Core Interface Ports.........................................................................	67
2.3.14. Enhanced PCS Ports...............................................................................	74
2.3.15. Standard PCS Ports................................................................................	80
2.3.16. Transceiver PHY PCS-to-Core Interface Reference Port Mapping....................	86
2.3.17. IP Core File Locations............................................................................	104
2.4. Using the Intel Stratix 10 L-Tile/H-Tile Transceiver Native PHY Intel Stratix 10 FPGA
IP Core..........................................................................................................	106

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2.4.1. PMA Functions.......................................................................................	108
2.4.2. PCS Functions........................................................................................	110
2.4.3. Deterministic Latency Use Model..............................................................	145
2.4.4. Debug Functions....................................................................................	153
2.5. Implementing the PHY Layer for Transceiver Protocols.............................................	163
2.5.1. PCI Express (PIPE)................................................................................	163
2.5.2. Interlaken............................................................................................	213
2.5.3. Ethernet...............................................................................................	220
2.5.4. CPRI....................................................................................................	226
2.6. Unused or Idle Transceiver Channels.....................................................................	232
2.7. Simulating the Native PHY IP Core........................................................................	235
2.7.1. How to Specify Third-Party RTL Simulators ...............................................	235
2.7.2. Scripting IP Simulation............................................................................	237
2.7.3. Custom Simulation Flow..........................................................................	239
2.8. Implementing the Transceiver Native PHY Layer in L-Tile/H-Tile Revision History.........	242
3. PLLs and Clock Networks............................................................................................	249
3.1. PLLs.................................................................................................................	251
3.1.1. ATX PLL................................................................................................	251
3.1.2. fPLL......................................................................................................	266
3.1.3. CMU PLL...............................................................................................	273
3.2. Input Reference Clock Sources............................................................................	278
3.2.1. Dedicated Reference Clock Pins...............................................................	279
3.2.2. Receiver Input Pins.................................................................................	281
3.2.3. PLL Cascading as an Input Reference Clock Source.....................................	282
3.2.4. Reference Clock Network.........................................................................	282
3.2.5. Core Clock as an Input Reference Clock.....................................................	282
3.3. Transmitter Clock Network...................................................................................	283
3.3.1. x1 Clock Lines.......................................................................................	283
3.3.2. x6 Clock Lines.......................................................................................	284
3.3.3. x24 Clock Lines......................................................................................	286
3.3.4. GXT Clock Network.................................................................................	289
3.3.5. HCLK Network.......................................................................................	291
3.4. Clock Generation Block.......................................................................................	292
3.5. FPGA Fabric-Transceiver Interface Clocking............................................................	294
3.6. Double Rate Transfer Mode..................................................................................	295
3.7. Transmitter Data Path Interface Clocking...............................................................	295
3.8. Receiver Data Path Interface Clocking...................................................................	297
3.9. Channel Bonding................................................................................................	299
3.9.1. PMA Bonding.........................................................................................	299
3.9.2. PMA and PCS Bonding.............................................................................	300
3.9.3. Selecting Channel Bonding Schemes.........................................................	301
3.9.4. Skew Calculations..................................................................................	302
3.10. PLL Cascading Clock Network.............................................................................	302
3.11. Using PLLs and Clock Networks..........................................................................	304
3.11.1. Non-bonded Configurations....................................................................	304
3.11.2. Bonded Configurations..........................................................................	308
3.11.3. Implementing PLL Cascading..................................................................	311
3.11.4. Mix and Match Example.........................................................................	312
3.12. PLLs and Clock Networks Revision History............................................................	315

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4. Resetting Transceiver Channels..................................................................................		319
4.1. When Is Reset Required? ...................................................................................		319
4.2. Transceiver PHY Reset Controller Intel Stratix 10 FPGA IP Implementation.................		320
4.3. How Do I Reset?................................................................................................		321
4.3.1. Recommended Reset Sequence................................................................		321
4.3.2. Transceiver Blocks Affected by Reset and Power-down Signals......................		332
4.4. Using PCS Reset Status Port................................................................................		332
4.5. Using Transceiver PHY Reset Controller Intel Stratix 10 FPGA IP...............................		332
4.5.1. Parameterizing Transceiver PHY Reset Controller Intel Stratix 10 FPGA IP		.......334
4.5.2. Transceiver PHY Reset Controller Intel Stratix 10 FPGA IP Parameters............		334
4.5.3. Transceiver PHY Reset Controller Intel Stratix 10 FPGA IP Interfaces.............		336
4.5.4. Transceiver PHY Reset Controller Intel Stratix 10 FPGA IP Resource Utilization 340
4.6. Using a User-Coded Reset Controller.....................................................................		340
4.6.1. User-Coded Reset Controller Signals.........................................................		341
4.7. Combining Status or PLL Lock Signals with User Coded Reset Controller....................		342
4.8. Resetting Transceiver Channels Revision History.....................................................		343
5. Intel Stratix 10 L-Tile/H-Tile Transceiver PHY Architecture........................................		344
5.1. PMA Architecture................................................................................................		344
5.1.1. Transmitter PMA.....................................................................................		344
5.1.2. Receiver PMA.........................................................................................		346
5.2. Enhanced PCS Architecture..................................................................................		354
5.2.1. Transmitter Datapath..............................................................................		354
5.2.2. Receiver Datapath..................................................................................		361
5.2.3. RX KR FEC Blocks...................................................................................		367
5.3. Intel Stratix 10 Standard PCS Architecture............................................................		367
5.3.1. Transmitter Datapath..............................................................................		368
5.3.2. Receiver Datapath..................................................................................		373
5.4. Intel Stratix 10 PCI Express Gen3 PCS Architecture................................................		387
5.4.1. Transmitter Datapath..............................................................................		388
5.4.2. Receiver Datapath..................................................................................		389
5.4.3. PIPE Interface........................................................................................		390
5.5. PCS Support for GXT Channels.............................................................................		390
5.6. Square Wave Generator......................................................................................		390
5.7. PRBS Pattern Generator......................................................................................		391
5.8. PRBS Pattern Verifier..........................................................................................		392
5.9. Loopback Modes................................................................................................		392
5.10. Intel Stratix 10 L-Tile/H-Tile Transceiver PHY Architecture Revision History...............		394
6. Reconfiguration Interface and Dynamic Reconfiguration............................................		396
6.1. Reconfiguring Channel and PLL Blocks...................................................................		397
6.2. Interacting with the Reconfiguration Interface........................................................		397
6.2.1. Reading from the Reconfiguration Interface...............................................		399
6.2.2. Writing to the Reconfiguration Interface....................................................		399
6.3. Multiple Reconfiguration Profiles...........................................................................		400
6.3.1. Configuration Files..................................................................................		401
6.3.2. Embedded Reconfiguration Streamer........................................................		403
6.4. Arbitration.........................................................................................................		405
6.5. Recommendations for Dynamic Reconfiguration......................................................		407
6.6. Steps to Perform Dynamic Reconfiguration............................................................		407
6.6.1. Channel Reconfiguration..........................................................................		409
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6.6.2. PLL Reconfiguration................................................................................		410
6.7. Direct Reconfiguration Flow.................................................................................		411
6.8. Native PHY IP or PLL IP Core Guided Reconfiguration Flow.......................................		412
6.9. Reconfiguration Flow for Special Cases..................................................................		413
6.9.1. Switching Transmitter PLL.......................................................................		414
6.9.2. Switching Reference Clocks.....................................................................		416
6.9.3. Reconfiguring Between GX and GXT Channels............................................		420
6.10. Changing Analog PMA Settings..........................................................................		420
6.11. Ports and Parameters........................................................................................		421
6.12. Dynamic Reconfiguration Interface Merging Across Multiple IP Blocks......................		426
6.13. Embedded Debug Features................................................................................		428
6.13.1. Native PHY Debug Master Endpoint (NPDME)............................................		428
6.13.2. Optional Reconfiguration Logic...............................................................		429
6.14. Timing Closure Recommendations......................................................................		430
6.15. Unsupported Features.......................................................................................		432
6.16. Transceiver Register Map...................................................................................		433
6.17. Reconfiguration Interface and Dynamic Revision History........................................		433
7. Calibration..................................................................................................................		435
7.1. Reconfiguration Interface and Arbitration with PreSICE (Precision Signal Integrity
Calibration Engine)..........................................................................................		437
7.2. Calibration Registers...........................................................................................		438
7.2.1. Avalon Memory-Mapped Interface Arbitration Registers...............................		438
7.2.2. User Recalibration Enable Registers..........................................................		438
7.2.3. Capability Registers................................................................................		439
7.2.4. Rate Switch Flag Register........................................................................		442
7.3. Power-up Calibration..........................................................................................		443
7.4. Background Calibration.......................................................................................		444
7.5. User Recalibration..............................................................................................		446
7.5.1. Recalibrating a Duplex Channel (Both PMA TX and PMA RX).........................		446
7.5.2. Recalibrating the PMA RX Only in a Duplex Channel....................................		447
7.5.3. Recalibrating the PMA TX Only in a Duplex Channel.....................................		447
7.5.4. Recalibrating a PMA Simplex RX Without a Simplex TX Merged into the
Same Physical Channel...........................................................................		448
7.5.5. Recalibrating a PMA Simplex TX Without a Simplex RX Merged into the
Same Physical Channel...........................................................................		448
7.5.6. Recalibrating Only a PMA Simplex RX in a Simplex TX Merged Physical
Channel................................................................................................		449
7.5.7. Recalibrating Only a PMA Simplex TX in a Simplex RX Merged Physical
Channel................................................................................................		449
7.5.8. Recalibrating the fPLL.............................................................................		450
7.5.9. Recalibrating the ATX PLL........................................................................		450
7.5.10. Recalibrating the CMU PLL When it is Used as a TX PLL..............................		450
7.6. Calibration Revision History.................................................................................		451
A. Logical View of the L-Tile/H-Tile Transceiver Registers..............................................		452
A.1. ATX_PLL Logical Register Map..............................................................................		452
A.1.1. ATX PLL Calibration................................................................................		452
A.1.2. Optional Reconfiguration Logic ATX PLLCapability.....................................		453
A.1.3. Optional Reconfiguration Logic ATX PLLControl & Status............................		453
A.1.4. Embedded Streamer (ATX PLL)................................................................		453
A.1.5. Updating ATX PLL Fractional Multiply Factor (K) Value.................................		454
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A.2. CMU_PLL Logical Register Map.............................................................................	454
A.2.1. CDR/CMU and PMA Calibration.................................................................	455
A.2.2. Optional Reconfiguration Logic CMU PLLCapability.....................................	455
A.2.3. Optional Reconfiguration Logic CMU PLLControl & Status...........................	456
A.2.4. Embedded Streamer (CMU PLL)...............................................................	456
A.3. FPLL Logical Register Map...................................................................................	457
A.3.1. fPLL Calibration......................................................................................	457
A.3.2. Optional Reconfiguration Logic fPLL-Capability............................................	458
A.3.3. Optional Reconfiguration Logic fPLL-Control & Status...................................	458
A.3.4. Embedded Streamer (fPLL)......................................................................	458
A.4. Channel Logical Register Map..............................................................................	459
A.4.1. Transmitter PMA Logical Register Map.......................................................	460
A.4.2. Receiver PMA Logical Register Map...........................................................	461
A.4.3. Pattern Generators and Checkers.............................................................	466
A.4.4. Loopback..............................................................................................	469
A.4.5. Optional Reconfiguration Logic PHYCapability...........................................	469
A.4.6. Optional Reconfiguration Logic PHYControl & Status..................................	470
A.4.7. Embedded Streamer (Native PHY)............................................................	471
A.4.8. Static Polarity Inversion..........................................................................	472
A.4.9. Reset...................................................................................................	472
A.4.10. CDR/CMU and PMA Calibration...............................................................	473
A.5. Logical View Register Map of the L-Tile/H-Tile Transceiver Registers Revision History...	474

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1. Overview

Intel® Stratix® 10 devices offer up to 144 transceivers with integrated advanced highspeed analog signal conditioning and clock data recovery circuits for chip-to-chip, chip-to-module, and backplane applications.

The Intel Stratix 10 devices contain a combination of GX, GXT, or GXE channels, in addition to the hardened IP blocks for PCI Express* and Ethernet applications.

The Intel Stratix 10 device introduces several transceiver tile variants to support a wide variety of protocol implementations. These transceiver tile variants are L-tiles, H- tiles, and E-tiles. This user guide describes both the L- and H-tile transceivers. For Intel Stratix 10 devices that only contain E-tiles, refer to the E-Tile Transceiver PHY User Guide.

Table 1.		Transceiver Tile Variants—Comparison of Transceiver Capabilities
		Feature	L-Tile	H-Tile	E-Tile
	Maximum Transceiver		GX (1)—17.4 Gbps
	Data Rate (Chip-to-		GXT (1)—26.6 Gbps		GXE (2)—57.8 Gbps Pulse Amplitude
		chip)		GX—17.4 Gbps
					Modulation 4 (PAM4)/28.9 Gbps Non-
	Maximum Transceiver			GXT—28.3 Gbps
			GX—12.5 Gbps		return to zero (NRZ)
	Data Rate
			GXT—12.5 Gbps
	(Backplane)
			GX—16 per tile	GX—8 per tile
	Number of		GXT—8 per tile
				GXT—16 per tile
	Transceiver Channels		Total—24 per tile (4		GXE—24 individual channels per tile
				Total—24 per tile (4 banks, 6
		(per tile)	banks, 6 channels per
			bank)	channels per bank)
					Ethernet—100GbE MAC and RS (528,
				PCIe—Gen3 x16, SR-IOV (4	514)-FEC, 4 per tile
	Hard IP (per tile)		PCIe*—Gen3 x16	PF, 2K VF)	Ethernet—KP-FEC, 4 per tile
				Ethernet—100GbE MAC	Ethernet—10/25GbE MAC and RS
					(528, 514)-FEC, 24 per tile

In all Intel Stratix 10 devices, the various transceiver tiles connect to the FPGA fabric using Intel EMIB (Embedded Multi-Die Interconnect Bridge) technology.

Related Information

•L-Tile/H-Tile Building Blocks on page 16

•See AN 778: Intel Stratix 10 Transceiver Usage for transceiver channel placement guidelines for L-tiles and H-tiles.

(1)Refer to the L-Tile/H-Tile Building Blocks section for further descriptions of GX and GXT channels.

(2)Refer to the E-Tile Transceiver PHY User Guide for a full description of GXE channels.

	Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, eASIC, Intel, the Intel logo, MAX, Nios,
	Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or	ISO
	other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
		9001:2015
	accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
		Registered
	at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
	information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
	customers are advised to obtain the latest version of device specifications before relying on any published
	information and before placing orders for products or services.
	*Other names and brands may be claimed as the property of others.

1. Overview

UG-20055 | 2021.03.29

•Intel Stratix 10 GX/SX Device Overview

•Intel Stratix 10 MX (DRAM System-in-Package) Device Overview

•Intel Stratix 10 TX Device Overview

•Intel Stratix 10 DX Device Overview

•E-Tile Transceiver PHY User Guide

•Intel FPGA IP for Transceiver PHY—Support Center

1.1.L-Tile/H-Tile Layout in Intel Stratix 10 Device Variants

Intel Stratix 10 GX/SX device variants support both L- and H-Tiles. Intel Stratix 10 TX and MX device variants support both H- and E-Tiles.

Intel Stratix 10 devices are offered in a number of different configurations based on layout. There is a maximum of six possible locations for a tile. The following figure maps these layouts to the corresponding transceiver tiles and banks.

Figure 1. Intel Stratix 10 Tile Layout

	Channel	Bank
	5
	4
	3	1N
	2
	1
	0
	5
	4
	3	1M
	2
	1
	0
	5
	4
	3	1L
	2
	1
	0
	5
	4
	3	1K
	2
	1
	0

	Package Substrate
	Tile 1K-N	<![if ! IE]> <![endif]>EMIB		<![if ! IE]> <![endif]>EMIB	Tile 4K-N
	HSSI_2_0				HSSI_2_1
	Tile 1G-J	<![if ! IE]> <![endif]>EMIB	®	<![if ! IE]> <![endif]>EMIB	Tile 4G-J
	HSSI_1_0				HSSI_1_1
	Tile 1C-F	<![if ! IE]> <![endif]>EMIB	Core Fabric	<![if ! IE]> <![endif]>EMIB	Tile 4C-F
	HSSI_0_0				HSSI_0_1

1.1.1. Intel Stratix 10 GX/SX H-Tile Configurations

The Intel Stratix 10 GX FPGAs meet the high-performance demands of highthroughput systems with up to 10 teraflops (TFLOPs) of floating-point performance. Intel Stratix 10 GX FPGAs also provide transceiver support up to 28.3 Gbps for chipmodule, chip-to-chip, and backplane applications.

The Intel Stratix 10 SX SoCs features a hard processor system with 64 bit quad-core ARM* Cortex*-A53 processor available in all densities, in addition to all the features of Intel Stratix 10 GX devices.

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1. Overview

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Figure 2. Intel Stratix 10 GX/SX Device with 1 H-Tile (24 Transceiver Channels)

Package Substrate

L-Tile/H-Tile

(24 Channels)

HSSI_0_0

GX/SX 400 HF35 (F1152)

GX/SX 650 HF35 (F1152)

GX/SX 2500 HF55 (F2912E)

GX/SX 2800 HF55 (F2912E)

®

Core Fabric

<![if ! IE]>

<![endif]>EMIB

Figure 3. Intel Stratix 10 GX/SX Device with 2 H-Tiles (48 Transceiver Channels)

Package Substrate

	L-Tile/H-Tile
		<![if ! IE]> <![endif]>EMIB
	(24 Channels)
	HSSI_2_0

	L-Tile/H-Tile
		<![if ! IE]> <![endif]>EMIB
	(24 Channels)
	HSSI_0_0

GX/SX 850 NF43 (F1760A) GX/SX 1100 NF43 (F1760A) GX/SX 1650 NF43 (F1760A) GX/SX 2100 NF43 (F1760A) GX/SX 2500 NF43 (F1760A) GX/SX 2800 NF43 (F1760A)

GX 1660 NF43 (F1760A) GX 2110 NF43 (F1760A)

®

Core Fabric

Figure 4. Intel Stratix 10 GX/SX Device with 4 H-Tiles (96 Transceiver Channels)

	Package Substrate
	L-Tile/H-Tile	<![if ! IE]> <![endif]>EMIB	GX/SX 1650 UF50 (F2397B)	<![if ! IE]> <![endif]>EMIB	L-Tile/H-Tile
	(24 Channels)		GX/SX 2100 UF50 (F2397B)		(24 Channels)
			GX/SX 2500 UF50 (F2397B)
	HSSI_2_0		GX/SX 2800 UF50 (F2397B)		HSSI_2_1
				®
	L-Tile/H-Tile	<![if ! IE]> <![endif]>EMIB		<![if ! IE]> <![endif]>EMIB	L-Tile/H-Tile
	(24 Channels)		Core Fabric		(24 Channels)
	HSSI_0_0				HSSI_0_1

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1. Overview

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Figure 5. Intel Stratix 10 GX 10M Device with 4 H-Tiles (48 Transceiver Channels)

Dedicated	Channel Bank	Dedicated	Channel Bank
REFCLK		REFCLK

refclk1	4									refclk1	4
	3	1MU12									3	1MU22
refclk0	1									refclk0	1
	0										0
refclk1										refclk1
	1	1LU12	Package Substrate		GX 10200 NF74 (F4938)						1	1LU22
refclk0	0									refclk0	0
refclk1	5		H-tile	<![if ! IE]> <![endif]>EMIB		<![if ! IE]> <![endif]>EMIB		<![if ! IE]> <![endif]>EMIB	H-tile	refclk1	5
	4										4
			(12 Channels)						(12 Channels)
	3	1KU12									3	1KU22
refclk0	2		T2						T4	refclk0	2
	1										1
	0					<![if ! IE]> <![endif]>EMIB					0
Dedicated										Dedicated
	Channel	Bank									Channel	Bank
REFCLK										REFCLK
refclk1	4		H-tile	<![if ! IE]> <![endif]>EMIB		<![if ! IE]> <![endif]>EMIB		<![if ! IE]> <![endif]>EMIB	H-tile	refclk1	4
	3	1EU10	(12 Channels)						(12 Channels)		3	1EU20
refclk0	1				Core Fabric		Core Fabric			refclk0	1
	0		T1						T3		0
refclk1										refclk1
	1	1DU10									1	1DU20
refclk0	0									refclk0	0
refclk1	5									refclk1	5
	4										4
	3	1CU10									3	1CU20
	2										2
refclk0										refclk0
	1										1
	0										0

1.1.2. Intel Stratix 10 TX H-Tile and E-Tile Configurations

The Intel Stratix 10 TX FPGAs deliver the most advanced transceiver capabilities in the industry by combining H-Tile and E-Tile transceivers.

Figure 6. Intel Stratix 10 TX Device with 1 E-Tile and 1 H-Tile (48 Transceiver Channels)

Channel	Bank	Package Substrate					Channel
5							23
4							22
3	1F			TX 850 NF43 (F1760C)			21
2							20
				TX 1100 NF43 (F1760C)
1							19
0							18
5							17
4							16
3	1E						15
2							14
1					®		13
0							12
5							11
4	1D	H-Tile				E-Tile	10
3			<![if ! IE]> <![endif]>EMIB		<![if ! IE]> <![endif]>EMIB		9
2		(24 Channels)				(24 Channels)	8
1				Core Fabric			7
0		HSSI_0_0				HSSI_0_1	6
5							5
4							4
3	1C						3
2							2
1							1
0							0

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1. Overview

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Figure 7. Intel Stratix 10 TX Device with 2 E-Tiles and 1 H-Tile (72 Transceiver Channels)

Package Substrate
E-Tile	<![if ! IE]> <![endif]>EMIB	TX 850 SF50 (F2397C)	<![if ! IE]> <![endif]>EMIB	E-Tile
(24 Channels)		TX 1100 SF50 (F2397C)		(24 Channels)
HSSI_2_0				HSSI_2_1
			®
H-Tile	<![if ! IE]> <![endif]>EMIB
(24 Channels)		Core Fabric
HSSI_0_0

Figure 8. Intel Stratix 10 TX Device with 3 E-Tiles and 1 H-Tile (96 Transceiver Channels)

	Package Substrate
	E-Tile	<![if ! IE]> <![endif]>EMIB	TX 1650 UF50 (F2397C)	<![if ! IE]> <![endif]>EMIB	E-Tile
	(24 Channels)		TX 2100 UF50 (F2397C)		(24 Channels)
			TX 2500 UF50 (F2397C)
	HSSI_2_0		TX 2800 UF50 (F2397C)		HSSI_2_1
				®
	H-Tile	<![if ! IE]> <![endif]>EMIB		<![if ! IE]> <![endif]>EMIB	E-Tile
	(24 Channels)		Core Fabric		(24 Channels)
	HSSI_0_0				HSSI_0_1

Figure 9. Intel Stratix 10 TX Device with 5 E-Tiles and 1 H-Tile (144 Transceiver Channels)

Package Substrate

E-Tile

(24 Channels)

HSSI_2_0

E-Tile

(24 Channels)

HSSI_1_0

H-Tile

(24 Channels)

HSSI_0_0

<![if ! IE]>

<![endif]>EMIB EMIB EMIB

	TX 2500	YF55 (F2912B)
			<![if ! IE]> <![endif]>EMIB
	TX 2800	YF55 (F2912B)
			<![if ! IE]> <![endif]>EMIB
	Core Fabric		<![if ! IE]> <![endif]>EMIB

E-Tile

(24 Channels)

HSSI_2_1

E-Tile

(24 Channels)

HSSI_1_1

E-Tile

(24 Channels)

HSSI_0_1

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Note: 1. No package migration available between GX/SX and TX device families (H-Tile and E-Tile)

2.Migration available within GX/SX from L-Tile to H-Tile variants

1.1.3.Intel Stratix 10 MX H-Tile and E-Tile Configurations

The Intel Stratix 10 MX devices combine the programmability and flexibility of Intel Stratix 10 FPGAs and SoCs with 3D stacked high-bandwidth memory 2 (HBM2). The DRAM memory tile physically connects to the FPGA using Intel Embedded Multi-Die Interconnect Bridge (EMIB) technology.

Figure 10. Intel Stratix 10 MX Device with 2 H-Tiles (48 Transceiver Channels) and 2 HBM2

Package Substrate

H-Tile

(24 Channels)

HSSI_2_0

H-Tile

(24 Channels)

HSSI_0_0

<![if ! IE]>

<![endif]>EMIB

<![if ! IE]>

<![endif]>EMIB

HBM2 4 GByte

MX 2100 NF53 (F2597B)

®

Core Fabric

HBM2 4 GByte

Figure 11. Intel Stratix 10 MX Device with 4 H-Tiles (96 Transceiver Channels) and Two 4 GB HBM2

Package Substrate		HBM2	4 GByte
H-Tile	<![if ! IE]> <![endif]>EMIB	MX 1650 UF53 (F2597A)		<![if ! IE]> <![endif]>EMIB	H-Tile
(24 Channels)		MX 2100 UF53 (F2597A)			(24 Channels)
HSSI_2_0					HSSI_2_1
				®
H-Tile	<![if ! IE]> <![endif]>EMIB			<![if ! IE]> <![endif]>EMIB	H-Tile
(24 Channels)		Core Fabric			(24 Channels)
HSSI_0_0					HSSI_0_1
		HBM2	4 GByte

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Figure 12. Intel Stratix 10 MX Device with 4 H-Tiles (96 Transceiver Channels) and Two 8 GB HBM2

Package Substrate		HBM2	8 GByte
H-Tile	<![if ! IE]> <![endif]>EMIB	MX 1650 UF53 (F2597C)		<![if ! IE]> <![endif]>EMIB	H-Tile
(24 Channels)		MX 2100 UF53 (F2597C)			(24 Channels)
HSSI_2_0					HSSI_2_1
				®
H-Tile	<![if ! IE]> <![endif]>EMIB			<![if ! IE]> <![endif]>EMIB	H-Tile
(24 Channels)		Core Fabric			(24 Channels)
HSSI_0_0					HSSI_0_1
		HBM2	8 GByte

Figure 13. Intel Stratix 10 MX Device with 3 E-Tiles, 1 H-Tile (96 Transceiver Channels) and 2 HBM2

Package Substrate		HBM2	4 GByte
E-Tile	<![if ! IE]> <![endif]>EMIB	MX 1650 UF55 (F2912)		<![if ! IE]> <![endif]>EMIB	E-Tile
(24 Channels)		MX 2100 UF55 (F2912)			(24 Channels)
HSSI_2_0					HSSI_2_1
				®
H-Tile	<![if ! IE]> <![endif]>EMIB			<![if ! IE]> <![endif]>EMIB	E-Tile
(24 Channels)		Core Fabric			(24 Channels)
HSSI_0_0					HSSI_0_1
		HBM2	4 GByte

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1.2. L-Tile/H-Tile Counts in Intel Stratix 10 Devices and Package

Variants

Table 2. L-Tile/H-Tile Counts in Intel Stratix 10 GX/SX Devices (HF35, NF43, UF50, HF55, NF74)

The number in the Intel Stratix 10 GX/SX Device Name column indicates the device's Logic Element (LE) count (in thousands LEs).

			F1152	F1760A	F2397B	F2912E	F4938
	Intel Stratix 10 GX/SX			NF43
			HF35		UF50	HF55	NF74
	Device Name			(42.5x42.5
			(35x35 mm2)		(50x50 mm2)	(55x55 mm2)	(70x74 mm2)
				mm2)
	GX 400/ SX	400	1
	GX 650/ SX	650	1
	GX 850/ SX	850		2
	GX 1100/ SX	1100		2
	GX 1650/ SX	1650		2	4
	GX 2100/ SX	2100		2	4
	GX 2500/ SX	2500		2	4	1
	GX 2800/ SX	2800		2	4	1
	GX 1660			2
	GX 2110			2
	GX 10200						4

Table 3. H- and E-Tile Counts in Intel Stratix 10 TX Devices (HF35, NF43, SF50, UF50, YF55)

The number in the Intel Stratix 10 TX Device Name column indicates the device's Logic Element (LE) count (in thousands LEs).

Cell legend: H-Tile count, E-Tile count

	Intel Stratix 10 TX Device	F1152	F1760C	F2397C	F2912B
		HF35	NF43	SF50, UF50	YF55
	Name
		(35x42.5 mm2)	(42.5x42.5 mm2)	(50x50 mm2)	(55x55 mm2)
	TX 850	—	1, 1	1, 2	—
	TX 1100	—	1, 1	1, 2	—
	TX 1650	—	—	1, 3	—
	TX 2100	—	—	1, 3	—
	TX 2500	—	—	1, 3	1, 5
	TX 2800	—	—	1, 3	1, 5

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Table 4. H- and E-Tile Counts in Intel Stratix 10 MX Devices (NF53, UF53, UF55)

The number in the Intel Stratix 10 MX Device Name column indicates the device's Logic Element (LE) count (in thousands LEs).

Cell legend: H-Tile count, E-Tile count

	Intel Stratix 10 MX Device	F2597A	F2597B	F2597C	F2912
		UF53	NF53	UF53	UF55
	Name
		(52.5x52.5 mm2)	(52.5x52.5 mm2)	(52.5x52.5 mm2)	(55x55 mm2)
	MX 1650	4, 0	—	4, 0	1, 3
	MX 2100	4, 0	2, 0	4, 0	1, 3

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1.3. L-Tile/H-Tile Building Blocks

Figure 14. High Level Block Diagram of L-Tile/H-Tile in Intel Stratix 10 Devices

Transceiver Bank 3 (2)	x6 Clock	x24 Clock
	Network	Network

refclk1	fPLL 1	PMA Ch 5	PCS Ch 5
	ATX PLL 1	PMA Ch 4	PCS Ch 4
		PMA Ch 3	PCS Ch 3
	fPLL 0	PMA Ch 2	PCS Ch 2
	ATX PLL 0	PMA Ch 1	PCS Ch 1
refclk0		PMA Ch 0	PCS Ch 0
Transceiver Bank 2		x6 Clock
		Network
refclk1	fPLL 1	PMA Ch 5	PCS Ch 5
	ATX PLL 1	PMA Ch 4	PCS Ch 4
		PMA Ch 3	PCS Ch 3
	fPLL 0	PMA Ch 2	PCS Ch 2
	ATX PLL 0	PMA Ch 1	PCS Ch 1
refclk0		PMA Ch 0	PCS Ch 0
Transceiver Bank 1 (2)		x6 Clock
		Network
refclk1	fPLL 1	PMA Ch 5	PCS Ch 5
	ATX PLL 1	PMA Ch 4	PCS Ch 4
		PMA Ch 3	PCS Ch 3
	fPLL 0	PMA Ch 2	PCS Ch 2
	ATX PLL 0	PMA Ch 1	PCS Ch 1
refclk0		PMA Ch 0	PCS Ch 0
Transceiver Bank 0		x6 Clock
		Network
refclk1	fPLL 1	PMA Ch 5	PCS Ch 5
	ATX PLL 1	PMA Ch 4	PCS Ch 4
		PMA Ch 3	PCS Ch 3
	fPLL 0	PMA Ch 2	PCS Ch 2
	ATX PLL 0	PMA Ch 1	PCS Ch 1
refclk0		PMA Ch 0	PCS Ch 0

Ethernet 100G

Hard IP (1)

PCIe Gen3

x16 Hard IP

	L-Tile/H-Tile	EMIB		FPGA Fabric
	PCS Core Interface
	Ch5 PCS FIFO			Ch5 Core FIFO
	Ch4 PCS FIFO			Ch4 Core FIFO
	Ch3 PCS FIFO			Ch3 Core FIFO
	Ch2 PCS FIFO			Ch2 Core FIFO
	Ch1 PCS FIFO			Ch1 Core FIFO
	Ch0 PCS FIFO			Ch0 Core FIFO
	Ch5 PCS FIFO			Ch5 Core FIFO
	Ch4 PCS FIFO			Ch4 Core FIFO
	Ch3 PCS FIFO			Ch3 Core FIFO
	Ch2 PCS FIFO			Ch2 Core FIFO
	Ch1 PCS FIFO			Ch1 Core FIFO
	Ch0 PCS FIFO			Ch0 Core FIFO
	Ch5 PCS FIFO			Ch5 Core FIFO
	Ch4 PCS FIFO			Ch4 Core FIFO
	Ch3 PCS FIFO			Ch3 Core FIFO
	Ch2 PCS FIFO			Ch2 Core FIFO
	Ch1 PCS FIFO			Ch1 Core FIFO
	Ch0 PCS FIFO			Ch0 Core FIFO
	Ch5 PCS FIFO			Ch5 Core FIFO
	Ch4 PCS FIFO			Ch4 Core FIFO
	Ch3 PCS FIFO			Ch3 Core FIFO
	Ch2 PCS FIFO			Ch2 Core FIFO
	Ch1 PCS FIFO			Ch1 Core FIFO
	Ch0 PCS FIFO			Ch0 Core FIFO

Note:	Legend
1. The Ethernet Hard IP is only for H-Tile devices.		= GXT clock network
2. GXT channels for L-Tile devices are only in Banks 1 or 3.

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1.3.1. Transceiver Bank Architecture

Each L-Tile/H-tile transceiver tile contains four transceiver banks. The transceiver channels are grouped into transceiver banks, where each bank has six channels. These six channels are a combination of GX and GXT channels which you can configure in the following ways:

•All six channels as GX channels

•Channels 0, 1, 3, and 4 as GXT channels. L-Tile supports GXT channels in banks 1 and 3. H-Tile supports GXT channels in banks 0, 1, 2, and 3.

•All six channels as a mix of GX and GXT channels; for example, two GX channels and four GXT channels on H-Tile Devices. On L-Tile devices, you can use a maximum of four channels in a bank when any channel is configured as a GXT channel.

Each channel can also run in any of the following operational modes:

•Duplex (default)—Specifies a single channel that supports both transmission and reception

•Transmitter (TX) Simplex—Specifies a single channel that supports only transmission

•Receiver (RX) Simplex—Specifies a single channel that supports only reception

Each transceiver bank contains two Advanced Transmit (ATX) PLLs, two fractional PLLs (fPLL), and two Clock Multiplier Unit (CMU) PLLs.

Figure 15. Transceiver Banks in the L-Tile/H-Tile

	fPLL	GX - Channel 5
	ATX	GXT Channel 4
		GXT Channel 3
	fPLL	GX Channel 2
	ATX	GXT Channel 1
		GXT Channel 0

Related Information

PLLs and Clock Networks on page 249

1.3.2. Transceiver Channel Types

Each transceiver has a Physical Coding Sublayer (PCS) and a Physical Medium Attachment (PMA). Additionally, each transceiver has loopback modes and internal pattern generator and verifier blocks for debugging.

1.3.2.1. GX Channel

Each GX transceiver channel has four types of PCS blocks that together support continuous datarates up to 17.4 Gbps. The various PCS blocks contain data processing functions such as encoding or decoding, scrambling or descrambling, word alignment, frame synchronization, FEC, and so on.

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Figure 16. GX Transceiver Channel in TX/RX Duplex Mode

	Transmitter PMA		Transmitter PCS	Transceiver
			Standard PCS	Tile
		Serializer	PCIe Gen3 PCS	TX
				PCS
			Enhanced PCS	FIFO
			PCS Direct
	Receiver PMA		Receiver PCS
			Standard PCS	RX
	CDR	Deserializer	PCIe Gen3 PCS
				PCS
			Enhanced PCS	FIFO
			PCS Direct

from FPGA fabric

to FPGA fabric

Table 5.		PCS Types Supported by GX Transceiver Channels
	PCS Type		L-Tile Production			H-Tile Production
			-2 Speed Grade	-3 Speed Grade	-1 Speed Grade	-2 Speed Grades	-3 Speed Grade
	Standard PCS		12 Gbps(3) or	9.8304 Gbps(4)	12 Gbps(3) or	12 Gbps(3) or	9.8304 Gbps(4)
			10.81344 Gbps(4)		10.81344 Gbps(4)	10.81344 Gbps(4)
	Enhanced				17.4 Gbps
	PCS
	PCIe Gen3				8 Gbps
	PCS
	PCS Direct				17.4 Gbps

Note: Use the L-Tile/H-Tile Transceiver Native PHY Intel Stratix 10FPGA IP Parameter Editor to determine the datarate limitations of your selected PCS configuration.

Refer to Table 12 on page 38 for a definition of the PCS Direct mode.

1.3.2.2. GXT Channel

Each GXT transceiver channel has two types of PCS blocks that together support continuous datarates up to 28.3 Gbps for H-Tile and 26.6 Gbps for L-Tile. Use PCS Direct or Enhanced PCS to implement a GXT channel.

Refer to the Intel Stratix 10 Device Datasheet for more details on transceiver specifications.

(3)The 12 Gbps data rate at the receiver is only supported when the RX word aligner mode parameter is set to Manual.

(4)This data rate is only supported when Byte Serializer and Deserializer mode is enabled.

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Figure 17. GXT Transceiver Channel in TX/RX Duplex Mode

	Transmitter PMA		Transmitter PCS	Transceiver
			Standard PCS	Tile
				TX
		Serializer	PCIe Gen3 PCS
				PCS
			Enhanced PCS	FIFO
			PCS Direct
	Receiver PMA		Receiver PCS
			Standard PCS	RX
	CDR	Deserializer	PCIe Gen3 PCS
				PCS
			Enhanced PCS	FIFO
			PCS Direct

from FPGA fabric

to FPGA fabric

Table 6.		PCS Types Supported by GXT Transceiver Channels
	PCS Type		L-Tile Production			H-Tile Production
			-2 Speed Grade	-3 Speed Grade	-1 Speed Grade	-2 Speed Grades	-3 Speed Grade
	Enhanced		26.6 Gbps	No GXT	28.3 Gbps	26.6 Gbps	No GXT
	PCS
	PCS Direct		26.6 Gbps	No GXT	28.3 Gbps	26.6 Gbps	No GXT

Note: Use the Native PHY IP Parameter Editor to determine the datarate limitations of your selected PCS configuration.

Related Information

Intel Stratix 10 Device Datasheet

1.3.3. GX and GXT Channel Placement Guidelines

Refer to AN 778: Intel Stratix 10 Transceiver Usage for detailed information on this section.

Related Information

AN 778: Intel Stratix 10 Transceiver Usage

1.3.4. GXT Channel Usage

Intel Stratix 10 L-Tile/H-Tile transceivers support GXT channels.

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Table 7. Channel Types

There are a total of 24 channels available per tile. You can configure them as either GX channels or as a combination of GX and (up to 16) GXT channels provided that the total does not exceed 24. You can use GXT channels as a GX channel, but they are subject to all of the GX channel placement constraints.

Tile	Channel Type	Number of Channels	Channel Capability
		per Tile	Chip-to-Chip		Backplane
L-Tile	GX	Up to 24	17.4 Gbps		12.5 Gbps
	GXT (5)	Up to 8	26.6 Gbps		12.5 Gbps
H-Tile	GX	Up to 24		17.4 Gbps
	GXT (5)	Up to 16	28.3 Gbps		28.3 Gbps

An ATX PLL can serve as the transmit PLL for up to six GXT channels.

Refer to AN 778: Intel Stratix 10 Transceiver Usage for detailed information about this section.

Related Information

•Intel Stratix 10 Device Datasheet

•AN 778: Intel Stratix 10 Transceiver Usage

1.3.5.PLL and Clock Networks

There are two different types of clock networks to distribute the high speed serial clock to the channels:

•Transceiver clock network that supports GX channels and allows a single TX PLL to drive up to 24 bonded channels in a tile.

•High Performance clock network that allows a single ATX PLL to drive up to 6 GXT channels in unbonded configurations.

Table 8.		Channel Type Supported by Different Clock Networks
		Clock Network	Clock Lines		Channel Type Support
		Standard	x1, x6, x24		GX
		High Performance	PLL Direct Connect		GXT

1.3.5.1. PLLs

1.3.5.1.1. Transceiver Phase-Locked Loops

Each transceiver channel in Intel Stratix 10 devices has direct access to three types of high performance PLLs:

•Advanced Transmit (ATX) PLL

•Fractional PLL (fPLL)

•Channel PLL / Clock Multiplier Unit (CMU) PLL.

(5)If you use GXT channel data rates, the VCCR_GXB and VCCT_GXB voltages must be set to 1.12 V.

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These transceiver PLLs along with the Master or Local Clock Generation Blocks (CGB) drive the transceiver channels.

Related Information

PLLs on page 251

For more information about transceiver PLLs in Stratix 10 devices.

Advanced Transmit (ATX) PLL

The ATX PLL is the transceiver channel’s primary transmit PLL. It can operate over the full range of supported datarates required for high datarate applications. An ATX PLL supports both integer frequency synthesis and coarse resolution fractional frequency synthesis (when configured as a cascade source).

Fractional PLL (fPLL)

A fractional PLL (fPLL) is an alternate transmit PLL used for generating lower clock frequencies for lower datarate applications. fPLLs support both integer frequency synthesis and fine resolution fractional frequency synthesis. Unlike the ATX PLL, you can also use the fPLL to synthesize frequencies that can drive the core through the FPGA fabric clock networks.

Channel PLL (CMU/CDR PLL)

A channel PLL is located within each transceiver channel. The channel's primary function is clock and data recovery in the transceiver channel when you use the PLL in clock data recovery (CDR) mode. You can use the channel PLLs of channel 1 and 4 as transmit PLLs when configured in clock multiplier unit (CMU) mode. You cannot configure the channel PLLs of channel 0, 2, 3, and 5 in CMU mode; therefore, you cannot use them as transmit PLLs. You cannot use the receiver channel when you use it as a Channel PLL/CMU.

1.3.5.1.2. Clock Generation Block (CGB)

Intel Stratix 10 devices include the following types of clock generation blocks (CGBs):

•Master CGB

•Local CGB

Transceiver banks have two master CGBs. The master CGB divides and distributes bonded clocks to a bonded channel group. The master CGB also distributes nonbonded clocks to non-bonded channels across the x6/x24 clock network.

Each transceiver channel has a local CGB. The local CGB divides and distributes nonbonded clocks to the corresponding PCS and PMA blocks.

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1.3.5.2.Input Reference Clock Sources

•Eight dedicated reference clocks available per transceiver tile

—Two reference clocks per transceiver bank

—You must route multiple copies of reference clocks on the PCB to span beyond a transceiver tile

•Reference clock network

—Reference clock network does not span beyond the transceiver tile

—There are two regulated reference clock networks for better performance per tile that any reference clock pin can access

•You can use unused receiver pins as additional reference clocks

Note: Unused receiver pins used as reference clocks can only be used within the same tile.

Figure 18. Reference Clock Network

	8 reference	Tile 2
	clock pins	Transceiver Bank 3
	per tile
		Transceiver Bank 2
		Transceiver Bank 1
	8 reference	Transceiver Bank 0
		Tile 1
	clock pins	Transceiver Bank 3
	per tile
		Transceiver Bank 2
		Transceiver Bank 1
	8 reference	Transceiver Bank 0
		Tile 0
	clock pins	Transceiver Bank 3
	per tile	Transceiver Bank 2
		Transceiver Bank 1
		Transceiver Bank 0

For the best jitter performance, place the reference clock as close as possible to the transmit PLL. Use the reference clock in the same triplet of the bank as the transmit PLL.

1.3.5.3. Transceiver Clock Network

1.3.5.3.1. x1 Clock Lines

The ATX PLL, fPLL, or CMU PLL can access the x1 clock lines. The x1 clock lines allow the TX PLL to drive multiple transmit channels in the same bank in non-bonded mode.

For more information, refer to the x1 Clock Lines section.

Related Information

x1 Clock Lines on page 283

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1.3.5.3.2. x6 Clock Lines

The ATX PLL or fPLL can access the x6 clock lines through the master CGB. The x6 clock lines allow the TX PLL to drive multiple bonded or non-bonded transmit channels in the same bank.

For more information, refer to the x6 Clock Lines section.

Related Information

x6 Clock Lines on page 284

1.3.5.3.3. x24 Clock Lines

Route the x6 clock lines onto x24 clock lines to allow a single ATX PLL or fPLL to drive multiple bonded or non-bonded transmit channels in multiple banks in an L-/H-Tile.

1.3.5.3.4. GXT Clock Network

The GXT Clock Network allows the ATX PLL to drive up to six GXT channels in nonbonded mode.

The top ATX PLL in a bank can drive:

•Channels 0, 1, 3, 4 in the bank

•Channels 0, 1 in the bank above in the same H-Tile

The bottom ATX PLL in a bank can drive:

•Channels 0, 1, 3, 4 in the bank

•Channels 3, 4 in the bank below in the same H-Tile

Related Information

GXT Clock Network on page 289

1.3.6. Ethernet Hard IP

1.3.6.1. 100G Ethernet MAC Hard IP

The 100G Ethernet MAC Hard IP block implements an Ethernet stack with MAC and PCS layers, as defined in the www.ieee802.org/3/.

Note: This Hard IP only apples to Intel Stratix 10 H-Tile devices.

•Supported Protocols

—100G MAC + PCS Ethernet x4 lanes

•Modes

—MAC + PCS

—PCS only

—PCS66 (encoder/scrambler bypass)

—Loopbacks

—AN/LT with soft logic: dynamic switching

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•Requires a soft Auto Negotiation / Link Training (AN/LT) logic implemented in the core fabric. Implement the AN/LT logic, or use a MAC IP.

Note: Auto negotiation (AN) is an exchange in which link partners to determine the highest performance datarate that they both support. Link training (LT) is the process that defines how a receiver (RX) and a transmitter (TX) on a high-speed serial link communicate with each other to tune their PMA settings.

The protocol specifies how to request the link partner TX driver to adjust TX deemphasis, but the standard does not state how or when to adjust receiver equalization. The manufacturer determines how they adjust their receiver equalization. The algorithm for RX settings is different between tiles.

1.3.6.2. 100G Configuration

The Ethernet Hard IP uses 5 channels in the top transceiver bank of the tile. Channels 0, 1, 3 and 4 send or receive data at 25 Gbps. Channel 2 bonds the 4 transceiver channels and it cannot be used for other purposes.

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Figure 19.	100G Configuration
		fPLL	GX Channel 5		EMIB GX Channel 5
		ATXPLL	GXT Channel 4	GXT Channel 3	EMIB GXT Channel 4
			GXT Channel 3	GXT Channel 2	EMIB GXT Channel 3
		fPLL	GX Channel 2	100G Ethernet HIP	EMIB GX Channel 2
		ATXPLL	GXT Channel 1	GXT Channel 1	EMIB GXT Channel 1
			GXT Channel 0	GXT Channel 0	EMIB GXT Channel 0
		fPLL	GX Channel 5		EMIB GX Channel 5
		ATXPLL	GXT Channel 4		EMIB GXT Channel 4
			GXT Channel 3		EMIB GXT Channel 3
		fPLL	GX Channel 2		EMIB GX Channel 2
		ATXPLL	GXT Channel 1		EMIB GXT Channel 1
			GXT Channel 0		EMIB GXT Channel 0
		fPLL	GX Channel 5		EMIB GX Channel 5
		ATXPLL	GXT Channel 4		EMIB GXT Channel 4
			GXT Channel 3		EMIB GXT Channel 3
		fPLL	GX Channel 2		EMIB GX Channel 2
		ATXPLL	GXT Channel 1		EMIB GXT Channel 1
			GXT Channel 0		EMIB GXT Channel 0
		fPLL	GX Channel 5		EMIB GX Channel 5
		ATXPLL	GXT Channel 4		EMIB GXT Channel 4
			GXT Channel 3		EMIB GXT Channel 3
		fPLL	GX Channel 2		EMIB GX Channel 2
		ATXPLL	GXT Channel 1		EMIB GXT Channel 1
			GXT Channel 0		EMIB GXT Channel 0

1.3.7. PCIe Gen1/Gen2/Gen3 Hard IP Block

The PCIe Hard IP is an IP block that provides multiple layers of the protocol stack for PCI Express. The Intel Stratix 10 Hard IP for PCIe is a complete PCIe solution that includes the Transaction, Data Link, and PHY/MAC layers. The Hard IP solution contains dedicated hard logic that connects to the transceiver PHY interface. Each transceiver tile contains a PCIe Hard IP block supporting PCIe Gen1, Gen2, or Gen3 protocols with x1, x2, x4, x8, and x16 configurations. x1, x2, and x4 configurations result in unusable channels. The Hard IP resides at the bottom of the tile, and is 16 channels high. Additionally, the block includes extensible VF (Virtual Functions)

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interface to enable implementation of up to 2K VFs via the SRIOV-w (Single-Root I/O Virtualization) bridge. The following table and figure show the possible PCIe Hard IP channel configurations, the number of unusable channels, and the number of channels available for other protocols.

Table 9.		PCIe Hard IP Channel Configurations Per Transceiver Tile
	PCIe Hard IP Configuration		Number of Unusable Channels	Number of Channels Available for
				Other Protocols
		PCIe x1	7	16
		PCIe x2	6	16
		PCIe x4	4	16
		PCIe x8	0	16
		PCIe x16	0	8

Figure 20.

PCIe Hard IP Channel Configurations Per Transceiver Tile

PCIe x1

PCIe x2

PCIe x4

PCIe x8

PCIe x16

23

23

23

23

23

8 Channels

Usable

16 Channels

16 Channels

16 Channels

16 Channels

16

Usable

Usable

Usable

Usable

15

8

8

8

8

PCIe Hard IP x16

7

6 Channels

7

4 Channels

7

7

7 Channels

Unusable

Unusable

4

PCIe Hard IP x8

Unusable

2

3

1

PCIe Hard IP x4

PCIe Hard IP x2

1

PCIe Hard IP x1 0

0

0

0

0

Transceiver Tile

Transceiver Tile

Transceiver Tile

Transceiver Tile

Transceiver Tile

The table below maps all transceiver channels to PCIe Hard IP channels in available

tiles.

Table 10.

PCIe Hard IP Channel Mapping Across all Tiles

Tile Channel

PCIe Hard IP

Index within

Bottom Left

Top Left Tile

Bottom Right

Top Right Tile

Tile Bank

Tile Bank

Sequence

Channel

I/O Bank

Bank Number

Bank Number

Number

Number

23

—

5

1F

1N

4F

4N

22

—

4

1F

1N

4F

4N

21

—

3

1F

1N

4F

4N

20

—

2

1F

1N

4F

4N

19

—

1

1F

1N

4F

4N

18

—

0

1F

1N

4F

4N

continued...

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	Tile Channel	PCIe Hard IP	Index within	Bottom Left	Top Left Tile	Bottom Right	Top Right Tile
				Tile Bank		Tile Bank
	Sequence	Channel	I/O Bank		Bank Number		Bank Number
				Number		Number
	17	—	5	1E	1M	4E	4M
	16	—	4	1E	1M	4E	4M
	15	15	3	1E	1M	4E	4M
	14	14	2	1E	1M	4E	4M
	13	13	1	1E	1M	4E	4M
	12	12	0	1E	1M	4E	4M
	11	11	5	1D	1L	4D	4L
	10	10	4	1D	1L	4D	4L
	9	9	3	1D	1L	4D	4L
	8	8	2	1D	1L	4D	4L
	7	7	1	1D	1L	4D	4L
	6	6	0	1D	1L	4D	4L
	5	5	5	1C	1K	4C	4K
	4	4	4	1C	1K	4C	4K
	3	3	3	1C	1K	4C	4K
	2	2	2	1C	1K	4C	4K
	1	1	1	1C	1K	4C	4K
	0	0	0	1C	1K	4C	4K

The PCIe Hard IP block includes extensible VF (Virtual Functions) interface to enable the implementation of up to 2K VFs via the SRIOV-2 (Single-Root I/O Virtualization) bridge.

In network virtualization, single root input/output virtualization or SR-IOV is a network interface that allows the isolation of the PCI Express resources for manageability and performance reasons. A single physical PCI Express is shared on a virtual environment using the SR-IOV specification. The SR-IOV specification offers different virtual functions to different virtual components, such as a network adapter, on a physical server machine.

Related Information http://www.design-reuse.com/articles/32998/single-root-i-o-virtualization.html

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				1. Overview
			UG-20055 | 2021.03.29
1.4. Overview Revision History
		Document	Changes
		Version
		2021.03.29	• Removed H-tile information for Intel Agilex™ devices in the Overview section.
			• Removed the footnote to PCIe—Gen3 x16 for H-tile in the Transceiver Tile Variants—Comparison of
			Transceiver Capabilities table.
			• Removed the H-Tile in Intel Agilex Devices section.
		2020.10.22	Made the following change:
			• Clarified that H-tiles in Intel Agilex devices do not support speed grade -1 and thus have a
			maximum GXT transceiver data rate of 26.6 Gbps.
		2020.10.05	Made the following changes:
			• Added the "Intel Stratix 10 GX 10M Device with 4 H-Tiles (48 Transceiver Channels)" figure.
			• Added the Intel Stratix 10 GX 10M Device to the "L-Tile/H-Tile Counts in Intel Stratix 10 GX/SX
			Devices (HF35, NF43, UF50, HF55, NF74)" table.
			• Added H-Tile in Intel Agilex Devices.
			• Removed the H-tile hard IP 50G variant.
		2020.03.03	Made the following changes:
			• Updated the Intel Stratix 10 TX devices in the "Intel Stratix 10 TX Device with 1 E-Tile and 1 H-Tile
			(48 Transceiver Channels)" figure and the "H- and E-Tile Counts in Intel Stratix 10 TX Devices
			(HF35, NF43, SF50, UF50, YF55)" table.
			• For GX Standard PCS data rates in GX Channel, added 12 Gbps and the note, "The 12 Gbps data
			rate at the receiver is only supported when the RX word aligner mode parameter is set to
			Manual.
		2019.03.22	Made the following change:
			• Changed the data rate for E-tile Non-Return to Zero (NRZ) to 28.9 Gbps.
			• Changed 60 GXE channels/device for PAM-4 to 57.8 Gbps.
			• Updated plan of record devices.
			• Updated device configuration drawings.
		2018.07.06	Made the following changes:
			• Changed the GXT data rate limit for L-Tile to 26.6 Gbps in the "Channel Types" table.
			• Changed the data rate limit for -2 speed grades on both L-Tile and H-Tile to 26.6 Gbps in the "PCS
			Types Supported by GXT Type Transceiver Channels" table.
			• Clarified the number of reference clocks pins in the "Reference Clock Network" figure.
			• Changed the standard PCS data rates for L-Tile and H-Tile devices in the "PCS Types Supported by
			GX Transceiver Channels" table.
			• Changed the backplane data rate for L-Tile GX channels in the "Channel Types" table.
		2018.03.16	Made the following changes:
			• Added the operational modes description for channels in the "Transceiver Bank Architecture"
			section.
			• Added PCS Direct to the "GX Transceiver Channel in TX/RX Duplex Mode" figure.
			• Added a cross-reference to the "General and Datapath Parameters" table in the "GX Channel"
			section.
			• Added PCS Direct to the "PCS Types Supported by GX Type Transceiver Channels" table.
			• Changed the description in the "GXT Channel" section.
			• Added PCS Direct to the "GXT Transceiver Channel in TX/RX Duplex Mode" figure.
			• Updated ATX PLL description stating "An ATX PLL supports both integer frequency synthesis and
			coarse resolution fractional frequency synthesis (when configured as a cascade source)".
			• Removed the NF48 package from the "L-Tile/H-Tile Counts in Intel Stratix 10 GX/SX Devices (HF35,
			NF43, UF50, HF55)" table.
		2017.08.11	Made the following changes:
			• Added the "Transceiver Tile Variants—Comparison of Transceiver Capabilities" table.
			• Removed the "H-Tile Transceivers" section.
			• Added description to the "L-Tile/H-Tile Layout in Stratix 10 Device Variants" section.
				continued...
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Document	Changes
Version
	• Added the "Stratix 10 Tile Layout" figure.
	• Changed the package and tile counts in the "H- and E-Tile Counts in Intel Stratix 10 MX Devices
	(NF43, UF53, UF55)" table.
	• Added separate datarate support for L-Tile and H-Tile in the "PCS Types Supported by GX Type
	Transceiver Channels" table.
2017.06.06	Made the following changes:
	• Removed CEI 56G support from the "Stratix 10 Transceiver Protocols, Features, and IP Core
	Support" table.
	• Added tile names based on the thermal models to the figures in the "Stratix 10 GX/SX H-Tile
	Configurations" section.
	• Added tile names based on the thermal models to the figures in the "Stratix 10 TX H-Tile and E-Tile
	Configurations" section.
	• Added tile names based on the thermal models to the figures in the "Stratix 10 MX H-Tile and E-Tile
	Configurations" section.
	• Changed the number of GXT channels that the ATX PLL can support as a transmit PLL in the "GXT
	Channel Usage" section.
	• Changed the number of GXT channels an ATX PLL can support in the "GXT Channel Usage" section.
	• Removed a note in the "Input Reference Clock Sources" section.
2017.03.08	Made the following changes:
	• Changed all the notes in the "GXT Channel Usage" section.
	• Changed all the notes in the "PLL Direct Connect Clock Network" section.
2017.02.17	Made the following changes:
	• Completely updated the "GXT Channel Usage" section.
2016.12.21	Initial release.

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2. Implementing the Transceiver PHY Layer in L-Tile/H-

Tile

2.1. Transceiver Design IP Blocks

The following figure shows all the design blocks involved in designing and using Intel Stratix 10 transceivers.

Figure 21. Intel Stratix 10 Transceiver Design Fundamental Building Blocks

Resets the transceiver channels

Provides a clock source to clock networks that drive the transceiver channels. In Intel Stratix 10 devices, the PLL IP Core is seperate from the Native PHY IP Core

This block can be either a MAC IP core, or a frame generator/ analyzer or a data generator/analyzer

	Transceiver PHY Reset			Analog and Digital
				Reset Bus	Reset Ports
	Controller Intel Stratix 10
	FPGA IP (1)
	Transceiver
			Master/Local
	PLL IP Core		Clock
			Generation	Non-Bonded and	L-Tile/H-Tile Transceiver
			Block
				Bonded Clocks	Native PHY Intel Stratix 10
					FPGA IP

MAC IP Core /	Parallel Data Bus
Data Generator /
Data Analyzer

Controls the PCS and PMA

configurations and transceiver channels functions for all communication protocols

Note:

(1) You can either design your own reset controller or use the Transceiver PHY Reset Controller Intel Stratix 10 FPGA IP core.

Legend:

Intel generated IP block

User created IP block

Related Information

Resetting Transceiver Channels on page 319

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