Intel IXP12xx User Manual

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IXP12xx ATM OC12/Ethernet IP

Router Example Design

Performance and Headroom Analysis

April, 2002

Document Number: 301144-001

Version 1.0, 4/10/02

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The IXP12xx ATM OC12/Ethernet IP Router Example Design may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

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IXP12xx ATM OC12/Ethernet IP Router Example Design

Performance and Headroom Analysis

OVERVIEW

This documents details the performance and headroom analysis done on the IXP12xx ATM OC12 / Ethernet IP Router Example Design. It covers the general performance aspects of the protocols; cycle and instruction budgets; testing under different workloads; and performance measurements in both, simulation and hardware environments.

This document also attempts to analyze the amount of headroom available in this design for customers to add additional features by providing microengine and memory utilization metrics.

Three different configurations are supported:

One ATM OC-12 port &

For use with the IXP1240/1250 with hardware CRC capability

eight 100Mbps Ethernet ports

 

Four ATM OC-3 ports &

Similar to the above configuration (requires the IXP1240/50), except

eight 100Mbps Ethernet ports

that it uses four OC-3 ports.

Two ATM OC-3 ports &

For use with the IXP1200 (which does not have hardware CRC

capability). Instead, CRC computation is performed by two

four 100Mbps Ethernet ports

microengines (thus the reduced data rates).

 

Since in each configuration aggregate Ethernet port bandwidth exceeds aggregate ATM port bandwidth, ATM port bandwidth is the limiting external factor. This example design supports full-duplex, full-bandwidth ATM communication on all available ATM ports.

The design is able to simultaneously transmit and receive any traffic pattern on all available ATM ports at line rate. Line rate means that no idle cells should appear on the ATM links. Furthermore, no ATM PHY FIFO overflows or Ethernet MAC FIFO overflows or underflows should occur.

MEASUREMENT ENVIRONMENT

Simulation and hardware performance testing was performed under the following conditions:

o232 MHz IXP1240 with an 80 MHz IX Bus

(IXP1200 measurements do not use the hardware-CRC on the IXP1240)

o133 MHz SDRAM – ‘-75’ speed-grade

(some results for 143 MHz (‘-7E’ speed-grade) are also provided where indicated)

Alternate DRAM Timing

The project ships with two FLASH files for two different DRAM speed grades. atm_ether\tools\flash contains files for 133MHz (-75) and 143 MHz (-7E) DRAM. Most measurements were repeated with both settings to illustrate the sensitivity of the design to DRAM performance. Where not specifically mentioned in this document, the slower 133MHz settings were used.

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KEY WORKLOADS & APPROACHES TO TESTING THE EXAMPLE DESIGN

Protocol Performance of IP over ATM vs. Ethernet

Figure 1 details the protocol processing required to carry an IP packet over ATM and Ethernet. .

Figure 1 – Protocol Processing

Figures 2 and 3 show that as the size of the IP packet varies so do the efficiencies of ATM and Ethernet. This section details those efficiencies and the resulting performance implications

Single Cell PDU Workload

Single-cell PDUs result from IP packets of size 20 to 32 bytes – for example UDP packets with up to 4 payload bytes (8 bytes of LLC/SNAP plus 8 bytes of AAL5 trailer are included with the IP packet in the 48-byte cell payload). Adding a 4-byte ATM cell header plus 1-byte HEC results in a 53-byte cell. SONET overhead transparently adds about another 2 bytes/cell to the wire-time such that its total cost is 55-bytes in terms of a 155 or 622 Mbps ATM link.

When the same packet is carried over Ethernet, it expands to consume a minimum-sized 64-byte frame. Ethernet then adds at least 960ns of inter-packet gap (12-bytes), plus a preamble (8- bytes). The total packet cost is 84-bytes on a 100Mbps Ethernet link.

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The result is that ATM is significantly more efficient that Ethernet in terms of Mbps for carrying very small PDUs. Every Mbps of single-cell-PDUs on the ATM link requires (84/55) Mbps on the matching Ethernet link(s).

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Figure 2 – Frame and PDU Length versus IP Packet Length

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OC12 Input

OC- 3 Input

Figure 3 – Expected Ethernet Transmit Bandwidth

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