The KU440EX motherboard may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized
errata are documented in the KU440EX Motherboard Specification Update.
Revision History
RevisionRevision HistoryDate
001Final release of the KU440EX Motherboard Technical Product
Specification.
This product specification applies only to standard KU440EX motherboards with BIOS identifier
4K4UE0X0.86A.000X.P0X.
Changes to this specification will be published in the KU440EX Motherboard Specification
Update before being incorporated into a revision of this document.
April 1998
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and
Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied
warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular
purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel retains the right to make changes to specifications and product descriptions at any time, without notice.
The KU440EX motherboard may contain design defects or errors known as errata which may cause the product to deviate
from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777,
Germany 44-0-1793-421-333, other Countries 708-296-9333.
†
Brand, name or trademark owned by another company.
Copyright 1998, Intel Corporation. All rights reserved.
59.Compliance with Specifications ..................................................................................77
vi
1 Motherboard Description
1.1 Overview
The KU440EX motherboard is a versatile platform that offers a wide variety of features. Many of
the options, however, are implemented – at least in part – on the riser. Throughout this manual,
‡
symbol is used to indicate such an option. Because there is no standard riser, no detailed
the
description of an implementation can be given. See Section 6.1 to obtain the reference design for
the NLX riser.
The KU440EX motherboard uses the NLX form factor (8.25 x 10.0 inches) and has the following
features:
Microprocessor:
• Single Pentium
• Intel
• 66 MHz host bus speed
• Slot 1 connector which provides an upgrade path that includes higher performance processors
Main memory:
• Two 168-pin DIMM sockets
• Supports from 8 MB up to 256 MB of synchronous DRAM (SDRAM) memory
Intel
• Intel 82443EX PCI/A.G.P. controller (PAC)
• Intel 82371EB PCI ISA IDE Xcelerator (PIIX4E)
Celeron processor operating at 266 MHz
82440EX AGPset and PCI/IDE Interface
Integrated PCI bus mastering controller
Integrated Accelerated Graphics Port (A.G.P.) controller
Supports up to four IDE drives or devices
Multifunction PCI-to-ISA bridge
Universal Serial Bus (USB) and DMA controllers
Two fast IDE interfaces
Power management logic
Real-time clock
II processor operating at 233, 266, 300, or 333 MHz
I/O features:
• SMC FDC37M707QFP I/O controller
Integrates standard I/O functions
• Advanced Configuration and Power Management Interface (ACPI) ready
• Support for WfM 1.1a
• Support for Management Level 3.0
1.2 Manufacturing Options
The following is a list of manufacturing options. Not all manufacturing options are available in all
marketing channels. Please contact your Intel representative to determine which options are
available to you.
The motherboard is designed to fit into a or a full NLX form-factor chassis. The outer dimensions
are 8.25 x 10.0 inches. (Full NLX dimensions are 9.0 x 13.0 inches.) Figure 2 shows that the
mechanical form factor, the I/O connector locations, and the mounting hole locations are in
compliance with the NLX specification (see Section 6.2).
0.00
0.60
0.00
0.349
0.509
2.975
9.40
9.20
8.05
7.60
4.20
Figure 2. Motherboard Dimensions
5.159
9.234
0.20
OM07103
10
Motherboard Description
1.5 I/O Shield
The back panel I/O shield for the motherboard must meet specific dimension and material
requirements. Systems based on this motherboard need the back panel I/O shield to pass
certification testing. Figure 3 shows the critical dimensions of the chassis-dependent I/O shield.
The figure indicate the position of each cutout. Additional design considerations for I/O shields
relative to chassis requirements are described in the NLX specification. See Section 6.2 for
information about the NLX specification.
NOTE
✏
A chassis-independent I/O shield designed to be compliant with the NLX specification 1.2 is
available from Intel.
The motherboard supports a single Pentium II or Celeron processor. The processor’s VID pins
automatically program the voltage regulator on the motherboard to the required processor voltage.
In addition, the 66 MHz host bus speed is automatically selected.
The motherboard will support either the low cost cartridge retention mechanism (LC-RM) or the
retention mechanism specifically designed for the Celeron processor (C-RM).
NOTE
✏
The motherboard has 0.159” mounting holes to accommodate the new plastic studs. The older
style studs are too small and can not be used.
The motherboard supports the following processor configurations:
Processor TypeProcessor SpeedHost Bus SpeedRetention Module
Pentium II233 MHz
266 MHz
300 MHz
333 MHz
Celeron266 MHz66 MHzC-RM
66 MHzLC-RM
1.6.1 Microprocessor Packaging
The Pentium II processor is packaged in a Single Edge Contact (S.E.C.) cartridge. The cartridge
includes the processor core, second-level cache subsystem, thermal plate, and back cover.
The Celeron processor is packaged in a Single Edge Processor (S.E.P.) package that includes the
processor core only.
The processor connects to the motherboard through the Slot 1 connector, a 242-pin edge connector.
When mounted in Slot 1, the processor is secured by a retention mechanism attached to the
motherboard. A passive heatsink is stabilized by the heatsink support.
1.6.2 Second Level Cache
The Pentium II second-level cache is located on the substrate of the S.E.C. cartridge. The cache
includes 512 KB of burst pipelined synchronous static RAM (BSRAM) and tag RAM. All
supported onboard memory can be cached.
The Celeron processor does not have second level cache.
1.6.3 Microprocessor Upgrades
The motherboard can be upgraded with future steppings of the Pentium II or Celeron processor
that run at higher speeds. When upgrading the processor, use the BIOS configure mode to change
the processor speed (see Section 1.18).
12
Motherboard Description
1.7 Main Memory
The motherboard has two dual inline memory module (DIMM) sockets. Synchronous DRAM
(SDRAM) can be installed in one or both sockets. In addition, the motherboard supports both
serial presence detect (SPD) and non-SPD data structures.
2
Using the SPD data structure, programmed into an E
determine the SDRAM's size and speed. Using the non-SPD data structure, the BIOS will
dynamically determine SDRAM size and speed. Minimum memory size is 8 MB; maximum
memory size is 256 MB. Memory size and speed can vary between sockets.
The motherboard supports the following memory features:
• 168-pin DIMMs with gold-plated contacts
• 66 MHz unbuffered SDRAM
• Non-ECC (64-bit) memory
• 3.3 V memory only
• Single- or double-sided DIMMs in the following sizes:
DIMM SizeNon-ECC Configuration
8 MB1 Mbit x 64
16 MB2 Mbit x 64
32 MB4 Mbit x 64
64 MB8 Mbit x 64
PROM on the DIMM, the BIOS can
128 MB16 Mbit x 64
NOTE
✏
All memory components and DIMMs used with the KU440EX motherboard must comply with the
PC Unbuffered DIMM Specification. You can access this document through the Internet at:
http://www.intel.com/design/pcisets/memory/.
See Section 6.2 for information about this specification.
1.8 Chipset
The Intel 440EX AGPset includes a Host-PCI bridge integrated with both an optimized DRAM
controller and an Accelerated Graphics Port (A.G.P.) interface. The I/O subsystem of the 440EX
is based on the PIIX4E, which is a highly integrated PCI-ISA/IDE Accelerator Bridge. This
chipset consists of the Intel 82443EX PCI/A.G.P. controller (PAC) and the Intel 82371EB PCI/ISA
IDE Xccelerator (PIIX4E) bridge chip.
The PAC provides bus-control signals, address paths, and data paths for transfers between the
processor’s host bus, the PCI bus, the A.G.P., and main memory. The PAC features:
• Processor interface control
Support for processor host bus frequencies of 66 MHz
32-bit addressing
Desktop Optimized GTL+ compliant host bus interface
• Integrated DRAM controller, with support for:
+3.3 V only DIMM DRAM configurations
Up to two double sided DIMMs
Synchronous 66-MHz SDRAM
DIMM serial presence detect via the SMBus interface
16- and 64-Mbit devices with 2 K, 4 K, and 8 K page sizes
4, x 8, x 16, and x 32 DRAM widths
x
SDRAM 64-bit data interface
Symmetrical and asymmetrical DRAM addressing
• A.G.P. interface
Complies with the A.G.P. specification Rev 1.0 (see Section 6.2 for specification
information)
Support for +3.3 V PCI devices, A.G.P.-66/133 devices
Synchronous coupling to the host-bus frequency
• PCI bus interface
Complies with the PCI specification Rev 2.1, +5 V 33 MHz interface (see Section 6.2 for
specification information)
Asynchronous coupling to the host-bus frequency
PCI parity generation support
Data streaming support for PCI-to-DRAM
Support for three PCI bus masters in addition to the host and PCI-to-ISA I/O bridge
Support for concurrent host, A.G.P., and PCI transactions to main memory
• Data buffering
DRAM write buffer with read-around-write capability
Dedicated host-to-DRAM, PCI0-to-DRAM, and PCI1/A.G.P.-to-DRAM read buffers
A.G.P. dedicated inbound/outbound FIFOs (133/66 MHz), used for temporary data storage
• Power management functions
Support for system suspend/resume
Compliant with ACPI power management
• SMBus support for desktop management functions
• Support for system management mode (SMM)
14
1.8.2 Intel 82371EB PCI ISA IDE Xcelerator (PIIX4E)
The PIIX4E is a multifunction PCI device implementing the PCI-to-ISA bridge, PCI IDE
functionality, Universal Serial Bus (USB) host/hub functionality, and enhanced power
management. The PIIX4E features:
• Multifunction PCI-to-ISA bridge
Support for the PCI bus at 33 MHz
Complies with the PCI specification (see Section 6.2 for specification information)
Full ISA bus support
• USB controller
Two USB ports (see Section 6.2 for specification information)
Support for legacy keyboard and mouse
Support for the Universal Host Controller Interface (UHCI) Design Guide, revision 1.1,
interface
• Integrated dual-channel enhanced IDE interface
Support for up to four IDE devices
PIO Mode 4 transfers up to 16 MB/sec
Support for Ultra DMA/33 synchronous DMA mode transfers up to 33 MB/sec
Bus master mode with an 8 x 32-bit buffer for bus master PCI IDE burst transfers
• Enhanced DMA controller
Two 8237-based DMA controllers
Support for PCI DMA with three PC/PCI channels and distributed DMA protocols
• Interrupt controller based on 82C59
Support for 15 interrupts
Programmable for edge/level sensitivity
• Power management logic
Sleep/resume logic
†
Support for Wake on LAN
Support for ACPI (see Section 6.2 for specification information)
• Real-Time Clock
256-byte battery-backed CMOS SRAM
Includes date alarm
• 16-bit counters/timers based on 82C54
technology
Motherboard Description
1.8.2.1 Universal Serial Bus (USB)
The motherboard has two USB ports; one USB peripheral can be connected to each port. For more
than two USB devices, an external hub can be connected to either port. The motherboard fully
supports the universal host controller interface (UHCI) and uses UHCI-compatible software
drivers. See Section 6.2 for information about the USB specification. USB features include:
• Self-identifying peripherals that can be plugged in while the computer is running
• Automatic mapping of function to driver and configuration
• Support for isochronous and asynchronous transfer types over the same set of wires
• Guaranteed bandwidth and low latencies appropriate for telephony, audio, and other
applications
• Error-handling and fault-recovery mechanisms built into the protocol
NOTE
✏
Computer systems that have an unshielded cable attached to a USB port may not meet FCC
Class B requirements, even if no device or a low-speed USB device is attached to the cable. Use
shielded cable that meets the requirements for full-speed devices.
1.8.2.2 IDE Support
The motherboard has two independent bus-mastering PCI IDE interfaces. These interfaces support
PIO Mode 3, PIO Mode 4, ATAPI devices (such as CD-ROM), and Ultra DMA/33 synchronousDMA mode transfers. The BIOS supports logical block addressing (LBA) and extended cylinder
head sector (ECHS) translation modes. The BIOS automatically detects the IDE device transfer
rate and translation mode.
Programmed I/O operations usually require a substantial amount of processor bandwidth.
However, in multitasking operating systems, the bandwidth freed by bus mastering IDE can be
devoted to other tasks while disk transfers are occurring.
1.8.2.3 Real-Time Clock, CMOS SRAM, and Battery
The real-time clock is compatible with DS1287 and MC146818 components. The clock provides a
time-of-day clock and a multicentury calendar with alarm features and century rollover. The realtime clock supports 256 bytes of battery-backed CMOS SRAM in two banks that are reserved for
BIOS use.
The time, date, and CMOS values can be specified in the Setup program. The CMOS values can
be returned to their defaults by using the Setup program.
16
Motherboard Description
NOTE
✏
The recommended method of accessing the date in systems with Intel motherboards is indirectly
from the Real Time Clock (RTC) via the BIOS. The BIOS on Intel motherboards and baseboards
contains a century checking and maintenance feature that checks the least two significant digits of
the year stored in the RTC during each BIOS request (INT 1Ah) to read the date and, if less than
80 (i.e., 1980 is the first year supported by the PC), updates the century byte to 20. This feature
enables operating systems and applications using the BIOS date/time services to reliably
manipulate the year as a four-digit value.
For more information on proper date access in systems with Intel motherboards please see
http://support.intel.com/support/year2000/motherboard.htm
A coin-cell battery powers the real-time clock and CMOS memory. When the computer is not
plugged into a wall socket, the battery has an estimated life of three years. When the computer is
plugged in, the 3.3 V standby current from the power supply extends the life of the battery. The
clock is accurate to ± 13 minutes/year at 25 ºC with 3.3 V applied.
1.9 I/O Interface Controller
The motherboard uses the SMC FDC37M707QFP I/O controller which features:
• Single diskette drive interface
• ISA Plug-and-Play compatible register set
• Two serial ports
• FIFO support on both serial and floppy interfaces
• One parallel port with ECP and EPP support
†
• PS/2
• PCI PME interface to PIIX4E
• Intelligent auto power management, including:
The Setup program provides configuration options for the I/O controller.
1.9.1 Serial Ports
The motherboard has two serial ports. COM1 is a 9-pin D-Sub serial port connector located on the
back panel, and COM2 is a header located at J5J1. Both serial ports have NS16C550-compatible
UARTs that support data transfers at speeds up to 115.2 Kbits/sec with BIOS support.
style mouse and keyboard interfaces
Shadowed write-only registers for ACPI compliance
Programmable wake-up event interface
Wake on Modem support is available on the riser
Support for Wake on Ring through an external modem connected to COM1
There is no infrared header on the motherboard; however, the edge connector does accommodate
†
infrared signals from the riser. If an IrDA
connector is available on the riser, use the BIOS
Peripheral Configuration Submenu to change the mode for Serial Port B from COM2 to infrared
applications. You will no longer be able to use Serial Port B.
1.9.3 Parallel Port
The connector for the multimode bi-directional parallel port is a 25-pin D-Sub connector located
on the back panel of the motherboard. In the Setup program, there are four options for parallel
port operation:
• Output only (standard mode)
• Bi-directional (PS/2 compatible)
• Bi-directional Enhanced Parallel Port (EPP). A driver from the peripheral manufacturer is
required for operation. See Section 6.2 for EPP compatibility
• Bi-directional high-speed Extended Capabilities Port (ECP)
1.9.4 Diskette Drive Controller
The I/O controller is software compatible with the 82077 diskette drive controller and supports a
†
single diskette drive in either PC-AT
interface can be configured for the following diskette drive capacities and sizes:
• 360 KB, 5.25-inch
• 1.2 MB, 5.25-inch
• 720 KB, 3.5-inch
• 1.2 MB, 3.5-inch (driver required)
• 1.25/1.44 MB, 3.5-inch
• 2.88 MB, 3.5-inch
and PS/2 modes. In the Setup program, the diskette drive
18
Motherboard Description
1.9.5 PS/2 Keyboard and Mouse Interface
PS/2 keyboard and mouse connectors are located on the back panel of the motherboard. The +5 V
†
lines to these connectors are protected with a PolySwitch
reestablishes the connection after an over-current condition is removed.
NOTE
✏
The mouse and keyboard can be plugged into either PS/2 connector. Power to the computer
should be turned off before a keyboard or mouse is connected or disconnected.
The keyboard controller contains code which provides the traditional keyboard and mouse control
functions and also supports Power On/Reset password protection. A Power On/Reset password
can be specified in the BIOS Setup program.
The keyboard controller also supports the hot-key sequence <Ctrl><Alt><Del>, software reset.
This key sequence resets the computer’s software by jumping to the beginning of the BIOS code
and running the Power On Self Test (POST).
circuit that, like a self-healing fuse,
1.10 Audio Subsystem
The audio subsystem consists of the following:
• Crystal Semiconductor CS4235 audio codec
• Back panel and onboard audio connectors
1.10.1 Crystal Semiconductor CS4235 Audio Codec
The CS4235 audio codec’s features include:
†
• Compatibility with Roland MPU-401, Sound Blaster
Sound System
• Advanced MPC3-compliant input and output mixer
1.10.2 Audio Connectors
The audio connectors include the following:
• Back panel connectors: stereo line-level output (Line-out) and Mic-in
• CD-ROM (2 mm) audio header
1.10.3 Audio Drivers and Utilities
Audio software and utilities are available from Intel’s World Wide Web site (see Section 6.1).
Audio driver support is provided for Microsoft Windows
†
Microsoft Windows NT
operating systems.
, Sound Blaster Pro†, and Windows
†
3.1, Microsoft Windows 95, and
Audio software and utilities are available from Intel’s World Wide Web site (see Section 6.1).
• Enhanced line buffer allows vertical filtering of native MPEG-2 size (720 x 480) images
• DVD/MPEG-2 decode assist
• Filter circuitry that eliminates video artifacts caused by displaying interlaced video on
noninterlaced displays
• Hardware mirroring for flipping video images in video conferencing systems
• Bi-directional bus mastering engine with planar YUV-to-packed format converter
• YUV-to-RGB color space converter with support for both packed and planar YUV:
YUV 4:2:2, YUV 4:1:0, and YUV 4:2:0
RGB 32, RGB 16/15, RGB 8, and monochrome
1.12 LAN Subsystem
The Intel® EtherExpress PRO/100 Wired for Management (WfM) PCI LAN subsystem is an
†
Ethernet
include:
• 32-bit direct bus mastering on the PCI bus
• Shared memory structure in the host memory that copies data directly to/from host memory
• 10Base-T and 100Base-TX capability using a single RJ-45 connector with connection and
• IEEE 802.3µ Auto-Negotiation for the fastest available connection
• Jumperless configuration; the LAN subsystem is completely software configurable
LAN interface that provides both 10Base-T and 100Base-TX connectivity. Features
activity status LEDs
20
Motherboard Description
1.12.1 Intel® 82558 LAN Controller
The Intel® 82558 LAN Controller provides the following functions:
• CSMA/CD Protocol Engine
• PCI bus interface (Rev 2.1 compliant)
• DMA engine for movement of commands, status, and network data across the PCI bus
• Integrated physical layer interface, including:
Complete functionality necessary for the 10Base-T and 100Base-TX interfaces; when in
10 Mbit/sec mode, the interface drives the cable directly
A complete set of MII management registers for control and status reporting
802.3µ Auto-Negotiation for automatically establishing the best operating mode when
connected to other 10Base-T or 100Base-TX devices
• Integrated power management features, including:
Support for ACPI
Support for Wake on LAN technology
• Digitally controlled adaptive equalizations and transmission
1.13 Wake on LAN Technology
Wake on LAN technology enables remote wakeup of the computer through a network. Wake on
LAN technology requires a PCI add-in network interface card (NIC) with remote wakeup
capabilities. The remote wakeup connector on the NIC must be connected to the onboard Wake on
LAN technology connector. The NIC monitors network traffic at the Media Independent Interface
†
(MII); upon detecting a Magic Packet
computer.
This feature is available on the riser. See Section 1.17 for the location and pinouts of the NLX
edge connector.
CAUTION
For Wake on LAN, the +5 V standby line for the power supply must be capable of delivering
+5 V
Wake on LAN, can damage the power supply.
5% at 720 mA. Failure to provide adequate standby current when implementing
±
, the NIC asserts a wakeup signal that powers up the
The hardware monitor subsystem provides low-cost instrumentation capabilities. The features of
the hardware monitor subsystem include:
• Support for an optional chassis intrusion connector
• An integrated ambient temperature sensor
• Fan speed sensors (see Figure 4 for the location of fan connector on the motherboard)
• Power supply voltage monitoring to detect levels above or below acceptable values
When suggested ratings for temperature, fan speed, or voltage are exceeded, an interrupt is
activated. The hardware monitor component connects to the SMBus.
‡
1.15 Fan Speed Control
The motherboard includes two independent circuits for controlling various system cooling fans:
one on the motherboard and the other on the riser.
1.15.1 Fan Header
The processor fan header (J1A1) on the motherboard is intended to drive a processor-mounted fan
either full-speed or off, depending on the operating state of the system.
1.15.2 Fan Control Signal on the Riser
The fan control (FAN_CTL) signal is defined by the NLX specification as a means to control the
speeds of fans connected to an NLX riser or power supply. The KU440EX motherboard is capable
of driving FAN_CTL at different output levels, depending on the operating state of the system.
Initially, two levels are defined for high and low fan speed operation. Based on the cooling needs
and capabilities of a given system platform, the system OEM can redefine these output levels (by
means of the SMBIOS table entries) to achieve a better balance of acoustic and thermal
performance.
22
Motherboard Description
1.15.3 System Management Support
While the system is running an APM OS, the BIOS controls both fan circuits as shown in Table 1.
With an ACPI OS, the voltage to both circuits is dependent on the system state, as shown in
Table 2.
Table 1.Fan Speed Control under APM OS
APM system statesProcessor fan voltageFAN_CTL signal to riser
Full on APM Enabled/Standby+12 V (default)OEM-definable “High speed”
(default = +12 V)
APM Suspend off0 V (default)OEM-definable “Low speed”
(default = 8 V)
Table 2.Fan Speed Control under ACPI OS
ACPI System StatesProcessor Fan VoltageFAN_CTL Signal to Riser
S0+12V+12 V
S1OS ControlACPI software/Operating System
S2No supportNo support
S3No supportNo support
S4Future Upgrade (+0 V)(+0 V)