The KU440EX motherboard may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized
errata are documented in the KU440EX Motherboard Specification Update.
Revision History
RevisionRevision HistoryDate
001Final release of the KU440EX Motherboard Technical Product
Specification.
This product specification applies only to standard KU440EX motherboards with BIOS identifier
4K4UE0X0.86A.000X.P0X.
Changes to this specification will be published in the KU440EX Motherboard Specification
Update before being incorporated into a revision of this document.
April 1998
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and
Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied
warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular
purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel retains the right to make changes to specifications and product descriptions at any time, without notice.
The KU440EX motherboard may contain design defects or errors known as errata which may cause the product to deviate
from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777,
Germany 44-0-1793-421-333, other Countries 708-296-9333.
†
Brand, name or trademark owned by another company.
Copyright 1998, Intel Corporation. All rights reserved.
59.Compliance with Specifications ..................................................................................77
vi
1 Motherboard Description
1.1 Overview
The KU440EX motherboard is a versatile platform that offers a wide variety of features. Many of
the options, however, are implemented – at least in part – on the riser. Throughout this manual,
‡
symbol is used to indicate such an option. Because there is no standard riser, no detailed
the
description of an implementation can be given. See Section 6.1 to obtain the reference design for
the NLX riser.
The KU440EX motherboard uses the NLX form factor (8.25 x 10.0 inches) and has the following
features:
Microprocessor:
• Single Pentium
• Intel
• 66 MHz host bus speed
• Slot 1 connector which provides an upgrade path that includes higher performance processors
Main memory:
• Two 168-pin DIMM sockets
• Supports from 8 MB up to 256 MB of synchronous DRAM (SDRAM) memory
Intel
• Intel 82443EX PCI/A.G.P. controller (PAC)
• Intel 82371EB PCI ISA IDE Xcelerator (PIIX4E)
Celeron processor operating at 266 MHz
82440EX AGPset and PCI/IDE Interface
Integrated PCI bus mastering controller
Integrated Accelerated Graphics Port (A.G.P.) controller
Supports up to four IDE drives or devices
Multifunction PCI-to-ISA bridge
Universal Serial Bus (USB) and DMA controllers
Two fast IDE interfaces
Power management logic
Real-time clock
II processor operating at 233, 266, 300, or 333 MHz
I/O features:
• SMC FDC37M707QFP I/O controller
Integrates standard I/O functions
• Advanced Configuration and Power Management Interface (ACPI) ready
• Support for WfM 1.1a
• Support for Management Level 3.0
1.2 Manufacturing Options
The following is a list of manufacturing options. Not all manufacturing options are available in all
marketing channels. Please contact your Intel representative to determine which options are
available to you.
The motherboard is designed to fit into a or a full NLX form-factor chassis. The outer dimensions
are 8.25 x 10.0 inches. (Full NLX dimensions are 9.0 x 13.0 inches.) Figure 2 shows that the
mechanical form factor, the I/O connector locations, and the mounting hole locations are in
compliance with the NLX specification (see Section 6.2).
0.00
0.60
0.00
0.349
0.509
2.975
9.40
9.20
8.05
7.60
4.20
Figure 2. Motherboard Dimensions
5.159
9.234
0.20
OM07103
10
Motherboard Description
1.5 I/O Shield
The back panel I/O shield for the motherboard must meet specific dimension and material
requirements. Systems based on this motherboard need the back panel I/O shield to pass
certification testing. Figure 3 shows the critical dimensions of the chassis-dependent I/O shield.
The figure indicate the position of each cutout. Additional design considerations for I/O shields
relative to chassis requirements are described in the NLX specification. See Section 6.2 for
information about the NLX specification.
NOTE
✏
A chassis-independent I/O shield designed to be compliant with the NLX specification 1.2 is
available from Intel.
The motherboard supports a single Pentium II or Celeron processor. The processor’s VID pins
automatically program the voltage regulator on the motherboard to the required processor voltage.
In addition, the 66 MHz host bus speed is automatically selected.
The motherboard will support either the low cost cartridge retention mechanism (LC-RM) or the
retention mechanism specifically designed for the Celeron processor (C-RM).
NOTE
✏
The motherboard has 0.159” mounting holes to accommodate the new plastic studs. The older
style studs are too small and can not be used.
The motherboard supports the following processor configurations:
Processor TypeProcessor SpeedHost Bus SpeedRetention Module
Pentium II233 MHz
266 MHz
300 MHz
333 MHz
Celeron266 MHz66 MHzC-RM
66 MHzLC-RM
1.6.1 Microprocessor Packaging
The Pentium II processor is packaged in a Single Edge Contact (S.E.C.) cartridge. The cartridge
includes the processor core, second-level cache subsystem, thermal plate, and back cover.
The Celeron processor is packaged in a Single Edge Processor (S.E.P.) package that includes the
processor core only.
The processor connects to the motherboard through the Slot 1 connector, a 242-pin edge connector.
When mounted in Slot 1, the processor is secured by a retention mechanism attached to the
motherboard. A passive heatsink is stabilized by the heatsink support.
1.6.2 Second Level Cache
The Pentium II second-level cache is located on the substrate of the S.E.C. cartridge. The cache
includes 512 KB of burst pipelined synchronous static RAM (BSRAM) and tag RAM. All
supported onboard memory can be cached.
The Celeron processor does not have second level cache.
1.6.3 Microprocessor Upgrades
The motherboard can be upgraded with future steppings of the Pentium II or Celeron processor
that run at higher speeds. When upgrading the processor, use the BIOS configure mode to change
the processor speed (see Section 1.18).
12
Motherboard Description
1.7 Main Memory
The motherboard has two dual inline memory module (DIMM) sockets. Synchronous DRAM
(SDRAM) can be installed in one or both sockets. In addition, the motherboard supports both
serial presence detect (SPD) and non-SPD data structures.
2
Using the SPD data structure, programmed into an E
determine the SDRAM's size and speed. Using the non-SPD data structure, the BIOS will
dynamically determine SDRAM size and speed. Minimum memory size is 8 MB; maximum
memory size is 256 MB. Memory size and speed can vary between sockets.
The motherboard supports the following memory features:
• 168-pin DIMMs with gold-plated contacts
• 66 MHz unbuffered SDRAM
• Non-ECC (64-bit) memory
• 3.3 V memory only
• Single- or double-sided DIMMs in the following sizes:
DIMM SizeNon-ECC Configuration
8 MB1 Mbit x 64
16 MB2 Mbit x 64
32 MB4 Mbit x 64
64 MB8 Mbit x 64
PROM on the DIMM, the BIOS can
128 MB16 Mbit x 64
NOTE
✏
All memory components and DIMMs used with the KU440EX motherboard must comply with the
PC Unbuffered DIMM Specification. You can access this document through the Internet at:
http://www.intel.com/design/pcisets/memory/.
See Section 6.2 for information about this specification.
1.8 Chipset
The Intel 440EX AGPset includes a Host-PCI bridge integrated with both an optimized DRAM
controller and an Accelerated Graphics Port (A.G.P.) interface. The I/O subsystem of the 440EX
is based on the PIIX4E, which is a highly integrated PCI-ISA/IDE Accelerator Bridge. This
chipset consists of the Intel 82443EX PCI/A.G.P. controller (PAC) and the Intel 82371EB PCI/ISA
IDE Xccelerator (PIIX4E) bridge chip.
The PAC provides bus-control signals, address paths, and data paths for transfers between the
processor’s host bus, the PCI bus, the A.G.P., and main memory. The PAC features:
• Processor interface control
Support for processor host bus frequencies of 66 MHz
32-bit addressing
Desktop Optimized GTL+ compliant host bus interface
• Integrated DRAM controller, with support for:
+3.3 V only DIMM DRAM configurations
Up to two double sided DIMMs
Synchronous 66-MHz SDRAM
DIMM serial presence detect via the SMBus interface
16- and 64-Mbit devices with 2 K, 4 K, and 8 K page sizes
4, x 8, x 16, and x 32 DRAM widths
x
SDRAM 64-bit data interface
Symmetrical and asymmetrical DRAM addressing
• A.G.P. interface
Complies with the A.G.P. specification Rev 1.0 (see Section 6.2 for specification
information)
Support for +3.3 V PCI devices, A.G.P.-66/133 devices
Synchronous coupling to the host-bus frequency
• PCI bus interface
Complies with the PCI specification Rev 2.1, +5 V 33 MHz interface (see Section 6.2 for
specification information)
Asynchronous coupling to the host-bus frequency
PCI parity generation support
Data streaming support for PCI-to-DRAM
Support for three PCI bus masters in addition to the host and PCI-to-ISA I/O bridge
Support for concurrent host, A.G.P., and PCI transactions to main memory
• Data buffering
DRAM write buffer with read-around-write capability
Dedicated host-to-DRAM, PCI0-to-DRAM, and PCI1/A.G.P.-to-DRAM read buffers
A.G.P. dedicated inbound/outbound FIFOs (133/66 MHz), used for temporary data storage
• Power management functions
Support for system suspend/resume
Compliant with ACPI power management
• SMBus support for desktop management functions
• Support for system management mode (SMM)
14
1.8.2 Intel 82371EB PCI ISA IDE Xcelerator (PIIX4E)
The PIIX4E is a multifunction PCI device implementing the PCI-to-ISA bridge, PCI IDE
functionality, Universal Serial Bus (USB) host/hub functionality, and enhanced power
management. The PIIX4E features:
• Multifunction PCI-to-ISA bridge
Support for the PCI bus at 33 MHz
Complies with the PCI specification (see Section 6.2 for specification information)
Full ISA bus support
• USB controller
Two USB ports (see Section 6.2 for specification information)
Support for legacy keyboard and mouse
Support for the Universal Host Controller Interface (UHCI) Design Guide, revision 1.1,
interface
• Integrated dual-channel enhanced IDE interface
Support for up to four IDE devices
PIO Mode 4 transfers up to 16 MB/sec
Support for Ultra DMA/33 synchronous DMA mode transfers up to 33 MB/sec
Bus master mode with an 8 x 32-bit buffer for bus master PCI IDE burst transfers
• Enhanced DMA controller
Two 8237-based DMA controllers
Support for PCI DMA with three PC/PCI channels and distributed DMA protocols
• Interrupt controller based on 82C59
Support for 15 interrupts
Programmable for edge/level sensitivity
• Power management logic
Sleep/resume logic
†
Support for Wake on LAN
Support for ACPI (see Section 6.2 for specification information)
• Real-Time Clock
256-byte battery-backed CMOS SRAM
Includes date alarm
• 16-bit counters/timers based on 82C54
technology
Motherboard Description
1.8.2.1 Universal Serial Bus (USB)
The motherboard has two USB ports; one USB peripheral can be connected to each port. For more
than two USB devices, an external hub can be connected to either port. The motherboard fully
supports the universal host controller interface (UHCI) and uses UHCI-compatible software
drivers. See Section 6.2 for information about the USB specification. USB features include:
• Self-identifying peripherals that can be plugged in while the computer is running
• Automatic mapping of function to driver and configuration
• Support for isochronous and asynchronous transfer types over the same set of wires
• Guaranteed bandwidth and low latencies appropriate for telephony, audio, and other
applications
• Error-handling and fault-recovery mechanisms built into the protocol
NOTE
✏
Computer systems that have an unshielded cable attached to a USB port may not meet FCC
Class B requirements, even if no device or a low-speed USB device is attached to the cable. Use
shielded cable that meets the requirements for full-speed devices.
1.8.2.2 IDE Support
The motherboard has two independent bus-mastering PCI IDE interfaces. These interfaces support
PIO Mode 3, PIO Mode 4, ATAPI devices (such as CD-ROM), and Ultra DMA/33 synchronousDMA mode transfers. The BIOS supports logical block addressing (LBA) and extended cylinder
head sector (ECHS) translation modes. The BIOS automatically detects the IDE device transfer
rate and translation mode.
Programmed I/O operations usually require a substantial amount of processor bandwidth.
However, in multitasking operating systems, the bandwidth freed by bus mastering IDE can be
devoted to other tasks while disk transfers are occurring.
1.8.2.3 Real-Time Clock, CMOS SRAM, and Battery
The real-time clock is compatible with DS1287 and MC146818 components. The clock provides a
time-of-day clock and a multicentury calendar with alarm features and century rollover. The realtime clock supports 256 bytes of battery-backed CMOS SRAM in two banks that are reserved for
BIOS use.
The time, date, and CMOS values can be specified in the Setup program. The CMOS values can
be returned to their defaults by using the Setup program.
16
Motherboard Description
NOTE
✏
The recommended method of accessing the date in systems with Intel motherboards is indirectly
from the Real Time Clock (RTC) via the BIOS. The BIOS on Intel motherboards and baseboards
contains a century checking and maintenance feature that checks the least two significant digits of
the year stored in the RTC during each BIOS request (INT 1Ah) to read the date and, if less than
80 (i.e., 1980 is the first year supported by the PC), updates the century byte to 20. This feature
enables operating systems and applications using the BIOS date/time services to reliably
manipulate the year as a four-digit value.
For more information on proper date access in systems with Intel motherboards please see
http://support.intel.com/support/year2000/motherboard.htm
A coin-cell battery powers the real-time clock and CMOS memory. When the computer is not
plugged into a wall socket, the battery has an estimated life of three years. When the computer is
plugged in, the 3.3 V standby current from the power supply extends the life of the battery. The
clock is accurate to ± 13 minutes/year at 25 ºC with 3.3 V applied.
1.9 I/O Interface Controller
The motherboard uses the SMC FDC37M707QFP I/O controller which features:
• Single diskette drive interface
• ISA Plug-and-Play compatible register set
• Two serial ports
• FIFO support on both serial and floppy interfaces
• One parallel port with ECP and EPP support
†
• PS/2
• PCI PME interface to PIIX4E
• Intelligent auto power management, including:
The Setup program provides configuration options for the I/O controller.
1.9.1 Serial Ports
The motherboard has two serial ports. COM1 is a 9-pin D-Sub serial port connector located on the
back panel, and COM2 is a header located at J5J1. Both serial ports have NS16C550-compatible
UARTs that support data transfers at speeds up to 115.2 Kbits/sec with BIOS support.
style mouse and keyboard interfaces
Shadowed write-only registers for ACPI compliance
Programmable wake-up event interface
Wake on Modem support is available on the riser
Support for Wake on Ring through an external modem connected to COM1
There is no infrared header on the motherboard; however, the edge connector does accommodate
†
infrared signals from the riser. If an IrDA
connector is available on the riser, use the BIOS
Peripheral Configuration Submenu to change the mode for Serial Port B from COM2 to infrared
applications. You will no longer be able to use Serial Port B.
1.9.3 Parallel Port
The connector for the multimode bi-directional parallel port is a 25-pin D-Sub connector located
on the back panel of the motherboard. In the Setup program, there are four options for parallel
port operation:
• Output only (standard mode)
• Bi-directional (PS/2 compatible)
• Bi-directional Enhanced Parallel Port (EPP). A driver from the peripheral manufacturer is
required for operation. See Section 6.2 for EPP compatibility
• Bi-directional high-speed Extended Capabilities Port (ECP)
1.9.4 Diskette Drive Controller
The I/O controller is software compatible with the 82077 diskette drive controller and supports a
†
single diskette drive in either PC-AT
interface can be configured for the following diskette drive capacities and sizes:
• 360 KB, 5.25-inch
• 1.2 MB, 5.25-inch
• 720 KB, 3.5-inch
• 1.2 MB, 3.5-inch (driver required)
• 1.25/1.44 MB, 3.5-inch
• 2.88 MB, 3.5-inch
and PS/2 modes. In the Setup program, the diskette drive
18
Motherboard Description
1.9.5 PS/2 Keyboard and Mouse Interface
PS/2 keyboard and mouse connectors are located on the back panel of the motherboard. The +5 V
†
lines to these connectors are protected with a PolySwitch
reestablishes the connection after an over-current condition is removed.
NOTE
✏
The mouse and keyboard can be plugged into either PS/2 connector. Power to the computer
should be turned off before a keyboard or mouse is connected or disconnected.
The keyboard controller contains code which provides the traditional keyboard and mouse control
functions and also supports Power On/Reset password protection. A Power On/Reset password
can be specified in the BIOS Setup program.
The keyboard controller also supports the hot-key sequence <Ctrl><Alt><Del>, software reset.
This key sequence resets the computer’s software by jumping to the beginning of the BIOS code
and running the Power On Self Test (POST).
circuit that, like a self-healing fuse,
1.10 Audio Subsystem
The audio subsystem consists of the following:
• Crystal Semiconductor CS4235 audio codec
• Back panel and onboard audio connectors
1.10.1 Crystal Semiconductor CS4235 Audio Codec
The CS4235 audio codec’s features include:
†
• Compatibility with Roland MPU-401, Sound Blaster
Sound System
• Advanced MPC3-compliant input and output mixer
1.10.2 Audio Connectors
The audio connectors include the following:
• Back panel connectors: stereo line-level output (Line-out) and Mic-in
• CD-ROM (2 mm) audio header
1.10.3 Audio Drivers and Utilities
Audio software and utilities are available from Intel’s World Wide Web site (see Section 6.1).
Audio driver support is provided for Microsoft Windows
†
Microsoft Windows NT
operating systems.
, Sound Blaster Pro†, and Windows
†
3.1, Microsoft Windows 95, and
Audio software and utilities are available from Intel’s World Wide Web site (see Section 6.1).
• Enhanced line buffer allows vertical filtering of native MPEG-2 size (720 x 480) images
• DVD/MPEG-2 decode assist
• Filter circuitry that eliminates video artifacts caused by displaying interlaced video on
noninterlaced displays
• Hardware mirroring for flipping video images in video conferencing systems
• Bi-directional bus mastering engine with planar YUV-to-packed format converter
• YUV-to-RGB color space converter with support for both packed and planar YUV:
YUV 4:2:2, YUV 4:1:0, and YUV 4:2:0
RGB 32, RGB 16/15, RGB 8, and monochrome
1.12 LAN Subsystem
The Intel® EtherExpress PRO/100 Wired for Management (WfM) PCI LAN subsystem is an
†
Ethernet
include:
• 32-bit direct bus mastering on the PCI bus
• Shared memory structure in the host memory that copies data directly to/from host memory
• 10Base-T and 100Base-TX capability using a single RJ-45 connector with connection and
• IEEE 802.3µ Auto-Negotiation for the fastest available connection
• Jumperless configuration; the LAN subsystem is completely software configurable
LAN interface that provides both 10Base-T and 100Base-TX connectivity. Features
activity status LEDs
20
Motherboard Description
1.12.1 Intel® 82558 LAN Controller
The Intel® 82558 LAN Controller provides the following functions:
• CSMA/CD Protocol Engine
• PCI bus interface (Rev 2.1 compliant)
• DMA engine for movement of commands, status, and network data across the PCI bus
• Integrated physical layer interface, including:
Complete functionality necessary for the 10Base-T and 100Base-TX interfaces; when in
10 Mbit/sec mode, the interface drives the cable directly
A complete set of MII management registers for control and status reporting
802.3µ Auto-Negotiation for automatically establishing the best operating mode when
connected to other 10Base-T or 100Base-TX devices
• Integrated power management features, including:
Support for ACPI
Support for Wake on LAN technology
• Digitally controlled adaptive equalizations and transmission
1.13 Wake on LAN Technology
Wake on LAN technology enables remote wakeup of the computer through a network. Wake on
LAN technology requires a PCI add-in network interface card (NIC) with remote wakeup
capabilities. The remote wakeup connector on the NIC must be connected to the onboard Wake on
LAN technology connector. The NIC monitors network traffic at the Media Independent Interface
†
(MII); upon detecting a Magic Packet
computer.
This feature is available on the riser. See Section 1.17 for the location and pinouts of the NLX
edge connector.
CAUTION
For Wake on LAN, the +5 V standby line for the power supply must be capable of delivering
+5 V
Wake on LAN, can damage the power supply.
5% at 720 mA. Failure to provide adequate standby current when implementing
±
, the NIC asserts a wakeup signal that powers up the
The hardware monitor subsystem provides low-cost instrumentation capabilities. The features of
the hardware monitor subsystem include:
• Support for an optional chassis intrusion connector
• An integrated ambient temperature sensor
• Fan speed sensors (see Figure 4 for the location of fan connector on the motherboard)
• Power supply voltage monitoring to detect levels above or below acceptable values
When suggested ratings for temperature, fan speed, or voltage are exceeded, an interrupt is
activated. The hardware monitor component connects to the SMBus.
‡
1.15 Fan Speed Control
The motherboard includes two independent circuits for controlling various system cooling fans:
one on the motherboard and the other on the riser.
1.15.1 Fan Header
The processor fan header (J1A1) on the motherboard is intended to drive a processor-mounted fan
either full-speed or off, depending on the operating state of the system.
1.15.2 Fan Control Signal on the Riser
The fan control (FAN_CTL) signal is defined by the NLX specification as a means to control the
speeds of fans connected to an NLX riser or power supply. The KU440EX motherboard is capable
of driving FAN_CTL at different output levels, depending on the operating state of the system.
Initially, two levels are defined for high and low fan speed operation. Based on the cooling needs
and capabilities of a given system platform, the system OEM can redefine these output levels (by
means of the SMBIOS table entries) to achieve a better balance of acoustic and thermal
performance.
22
Motherboard Description
1.15.3 System Management Support
While the system is running an APM OS, the BIOS controls both fan circuits as shown in Table 1.
With an ACPI OS, the voltage to both circuits is dependent on the system state, as shown in
Table 2.
Table 1.Fan Speed Control under APM OS
APM system statesProcessor fan voltageFAN_CTL signal to riser
Full on APM Enabled/Standby+12 V (default)OEM-definable “High speed”
(default = +12 V)
APM Suspend off0 V (default)OEM-definable “Low speed”
(default = 8 V)
Table 2.Fan Speed Control under ACPI OS
ACPI System StatesProcessor Fan VoltageFAN_CTL Signal to Riser
S0+12V+12 V
S1OS ControlACPI software/Operating System
S2No supportNo support
S3No supportNo support
S4Future Upgrade (+0 V)(+0 V)
When used with an NLX-compliant power supply that supports remote power on/off, the
motherboard can turn off the system power through software control. See Section 6.2 for
information about the NLX specification.
To enable soft-off control in software, advanced power management must be enabled in the Setup
program and in the operating system. When the system BIOS receives the correct APM command
from the operating system, the BIOS turns off power to the computer.
With soft-off enabled, if power to the computer is interrupted by a power outage or a disconnected
power cord, when power resumes, the computer returns to the power state it was in before power
was interrupted (on or off).
Table 7.Power Supply Connector
PinSignal Name
1+3.3 V
2+3.3 V
3Ground
4+5 V
5Ground
6+5 V
7Ground
8PWRGD (Power Good)
9+5 V (STANDBY)
10+12 V
11+3.3 V
12-12 V
13Ground
14PS-ON# (power supply remote
on/off control)
15Ground
16Ground
17Ground
18-5 V
19+5 V
20+5 V
26
1.16.2 Back Panel Connectors
Figure 5 shows the location of the back panel I/O connectors, which include:
• External audio jacks: Mic In and Line Out
• Two USB connectors (stacked)
• PS/2-keyboard and mouse connectors
• RJ-45 LAN connector
• One serial port
• One video port
• One parallel port
Motherboard Description
C
EFJ
D
BA
AMic InFPS/2 Keyboard/Mouse
BLine OutGRJ-45 LAN
CUSB Port 1HSerial Port A
DUSB Port 0IParallel Port
EPS/2 Keyboard/MouseJVideo
1Strobe#14Auto Feed#
2Data bit 015Fault#
3Data bit 116INIT#
4Data bit 217SLCT IN#
5Data bit 318Ground
6Data bit 419Ground
7Data bit 520Ground
8Data bit 621Ground
9Data bit 722Ground
10ACK#23Ground
11Busy24Ground
12Error25Ground
13Select
30
Motherboard Description
1.17 NLX Card Edge Connector
The NLX riser connector on the motherboard consists of a 340 (2 x 170) position and a
supplemental 26 (2 x 13) position gold finger contact. All edge connector pin definitions are
defined in the NLX specification, version 1.2.
According to the NLX specification, the motherboard edge connector provides the following:
• PCI signals (the motherboard supports up to four PCI devices)
• ISA signals
• Two IDE channels
• One diskette drive interface
• Infrared signals
• Miscellaneous front panel signals
• Power connection for the motherboard
See Section 6.2 for information about the NLX Specification.
Table 16, Table 17, and Table 18 specify the pinouts located on the primary connector; Table 19
specifies the pinouts located on the supplemental connector.
A114IDEA_IORDYIDEIMBB114IDEA_CSELIDEOMB
A115IDEA_DMACK# IDEOMBB115IDEA_INTRQIDEIMB
A116RESERVEDRESNANAB1165VDCPWRNANA
A117IDEA_DA2IDEOMBB117IDEA_DA1IDEOMB
A118IDEA_CS0#IDEOMBB118IDEA_DA0IDEOMB
A1195VDCPWRNANAB119IDEA_CS1#IDEOMB
A120IDEA_DASP#IDEIRISB120IDEB_DD8IDEI/OMB
A121IDEB_RESET#IDEOMBB121IDEB_DD7IDEI/OMB
A122IDEB_DD9IDEI/OMBB122GNDPWRNANA
A123IDEB_DD6IDEI/OMBB123IDEB_DD10IDEI/OMB
A124IDEB_DD5IDEI/OMBB1245VDCPWRNANA
A125IDEB_DD11IDEI/OMBB125IDEB_DD4IDEI/OMB
A126IDEB_DD12IDEI/OMBB126IDEB_DD3IDEI/OMB
A127GNDPWRNANAB127IDEB_DD13IDEI/OMB
A128IDEB_DD2IDEI/OMBB128IDEB_DD14IDEI/OMB
A129IDEB_DD15IDEI/OMBB129IDEB_DD1IDEI/OMB
A130IDEB_DIOW#IDEI/OMBB130IDEB_DD0IDEI/OMB
A131IDEB_DMARQIDEIMBB131IDEB_DIOR#IDEOMB
A132IDEB_IORDYIDEIMBB132IDEB_CSELIDEOMB
A133GNDPWRNANAB133IDEB_INTRQIDEIMB
A134IDEB_DMACK# IDEOMBB134IDEB_DA1IDEOMB
A135RESERVEDRESNANAB135IDEB_DA2IDEOMB
A136IDEB_DA0IDEOMBB136IDEB_CS1#IDEOMB
A137IDEB_CS0#IDEOMBB137IDEB_DASP#IDEIRIS
A138DRV2#FLOPPYGNDNAB138GNDPWRNANA
A1395VDCPWRNANAB139DRATE0FLOPPY ONA
A140RESERVEDRESNANAB140FDS1#FLOPPY ONA
A141DENSELFLOPPYONAB141FDS0#FLOPPY ONA
A142FDME0#FLOPPYONAB142DIR#FLOPPY ONA
A143INDX#FLOPPYIRISB143MSEN1FLOPPY INA
(continued)
A144FDME1#FLOPPYONAB144GNDPWRNANA
A145GNDPWRNANAB145WRDATA#FLOPPY ONA
A146WE#FLOPPYONAB146TRK0#FLOPPY IRIS
A147STEP#FLOPPYONAB147MSEN0FLOPPY INA
A148WP#FLOPPYIRISB148RDDATA#FLOPPY IRIS
X5FP_SPKR_ENAUDIOIThis signal indicates if headphones have
been plugged into the front panel LINE-OUT
jack. The signal is connected to one of the
wipers on the audio jack and is HIGH when
the headphones are plugged into the front
audio jack and LOW when they are not. The
signal is pulled low through a pull-down on
the motherboard (Typically 100K).
X6VOL_DN# **AUDIOIConnects to Volume Down switch on front
panel, appropriate pull-up resistor on
motherboard. The motherboard provides
debounce protection and a pull-up resistor.
X7GNDPWRNAGroundNA
X8SMI# **SYSISystem Management Interrupt that is an input
to the motherboard.
X9RESERVEDRESNAReservedNA
X10RESERVEDRESNAReservedNA
X11RESERVEDRESNAReservedNA
X12AGNDPWRNALow pass filtered ground for audio circuitry on
the riser.
X13MODEM_MICAUDIOOPre-amplified microphone mono output signal
Table 19.Signals, NLX Riser with Supplemental Connector
(continued)
PinSignal NameTypeI/O *DescriptionSignal Type
Y5FP_MIC_EN **AUDIOIThis signal indicates if a microphone has
TTL
been plugged into the front panel MIC_IN
jack. The signal is connected to a wiper on
the MIC_IN jack and is LOW when the
microphone is plugged in and HIGH when it
is not. The signal is pulled LOW through a
pull down on the motherboard (Typically
100K).
Y6VOL_UP# **AUDIOIConnects to Volume Up switch on front
TTL
panel, appropriate pull-up resistor on
motherboard. The motherboard provides
debounce protection and a pull-up resistor.
TTL
stream to the motherboard from the codec on
the riser (output from the codec).
Y9GROUNDPWRNADigital (main motherboard) ground plane.NA
Y10AC_SD_OUT **AC’97OA84MEMCS16#
Y11AC_SYNC **AC’97OA85IRQ11
Y12AC_BIT_CLK **AC’97I
Y13MODEM_SPKRAUDIOOAnalog mono output signal from telephony
* I/O column: relative to motherboard
“O” = output, from motherboard to riser
“I” = input, from riser to motherboard.
** These signals are not supported.
A86IRQ10
Analog
device to motherboard.
1 V RMS
38
Motherboard Description
1.18 Jumper Settings
The motherboard has a single, 3-pin configuration jumper block at location (J6C1). Figure 6
shows the location of the configuration jumper block. Table 20 describes the jumper settings for
the three modes.
3
C
1
J6C1
OM07106
Figure 6. Location of the Configuration Jumper Block
Table 20.Configuration Jumper Settings
FunctionJumper J6C1Configuration
Normal1-2The BIOS uses current configuration information and passwords for booting.
Configure2-3After the POST runs, Setup runs automatically. The maintenance menu is
displayed.
RecoverynoneThe BIOS attempts to recover the BIOS configuration. A recovery diskette is
required.
CAUTION
Do not move the jumper with the power on. Always turn off the power and unplug the power cord
from the computer before changing the jumper.
The mean time between failures (MTBF) prediction is calculated using component and
subassembly random failure rates. The calculation is based on the Bellcore Reliability Prediction
Procedure, TR-NWT-000332, Issue 4, September 1991. The MTBF prediction is for estimating
repair rates and spare parts requirements.
MTBF data is calculated from predicted data @ 55 °C.
The MTBF prediction for the motherboard is 136,338 hours.
1.20 Environmental Specifications
Table 21.Environmental Specifications
ParameterSpecification
Temperature
Nonoperating-40 °C to +70 °C
Operating0 °C to +55 °C
Shock
Unpackaged50 G trapezoidal waveform
Velocity change of 170 inches/sec
PackagedHalf sine 2 millisecond
Product Weight
(lbs)
<2036167
21-4030152
41-8024136
81-10018118
Vibration
Unpackaged5 Hz to 20 Hz : 0.01g² Hz sloping up to 0.02 g² Hz
20 Hz to 500 Hz : 0.02g² Hz (flat)
Packaged10 Hz to 40 Hz : 0.015g² Hz (flat)
40 Hz to 500 Hz : 0.015g² Hz sloping down to 0.00015 g² Hz
Humidity
Non-operating95% RH at 30° C non-condensing
Free Fall (inches)Velocity Change (inches/sec)
40
Motherboard Description
1.21 Power Consumption
Table 22 lists the power usage for a computer that contains a motherboard with a 266 MHz
Celeron processor, 32 MB RAM, 0 KB cache, 3.5-inch floppy drive, 2.1 GB IDE hard drive,
16X IDE CD-ROM and integrated Rage IIC with 4 MB of video memory. This information is
provided only as a guide for calculating approximate power usage with additional resources added.
Values for the Windows 95 desktop mode are measured at 65K colors and 75 Hz refresh rate. AC
watts are measured with a typical 145 W supply, nominal input voltage and frequency, and with a
true RMS wattmeter at the line input.
Table 22.Power Usage
DC (amps) at:
ModeAC (watts) +3.3 V+5 V+12 V-12 V+5 V SB
DOS prompt, APM disabled49.01.78 A2.92 A.444 A.032 A.38 A
Windows 95 desktop, APM disabled49.51.63 A2.88 A.452 A.032 A.38 A
Windows 95 desktop, APM enabled, in
System Management Mode (SMM)
35.62.176 A 2.488 A.302 A.032 A.38 A
For typical configurations, the motherboard is designed to operate with a 90 to 200 W power
supply. A higher-wattage power supply should be used for heavily-loaded configurations. The
power supply must comply with the following recommendations found in the indicated sections of
the NLX form factor specification (see Section 6.2).
• The potential relation between 3.3VDC and +5VDC power rails
• The current capability of the +5V (standby) line
• All timing parameters
• All voltage tolerances
1.22 Thermal Considerations
Table 23 lists maximum component case temperatures for motherboard components that could be
sensitive to thermal changes. Case temperatures could be affected by factors such as the operating
temperature, current load, or operating frequency. Maximum case temperatures are important
when considering proper airflow to cool the motherboard.
CAUTION
An ambient temperature that exceeds the board’s maximum operating temperature by 5 oC to 10 oC
might cause components to exceed their maximum case temperature. For information about the
maximum operating temperature, see the environmental specifications in Section 1.20.
Figure 7 shows motherboard components that may be sensitive to thermal changes.
AProcessor (in Slot 1 connector)
BIntel 82443EX
CIntel 82371EB
Figure 7. Thermally-Sensitive Components
A
B
C
OM07102
42
Motherboard Description
Table 24 shows the DC power requirements for systems in either Sleep or Normal operating
modes. Power consumption is independent of the operating system used and other variables.
Table 24.Processor Fan Voltage (J1A1)
ModeVoltage
Sleep0
Normal12
1.23 Regulatory Compliance
This motherboard complies with the following safety and EMC regulations when correctly
installed in a compatible host system.
This motherboard has the following product certification markings:
• European CE Marking: Consists of a marking on the board and shipping container.
• UL Recognition Mark: Consists of the UL File No. E139761 on the component side of the
board and the PB No. on the solder side of the board. Board material flammability is 94V-1
or -0.
• Each board will be marked with an FCC Declaration of Conformity.
• Canadian Compliance: Consists of small c followed by a stylized backward UR on component
side of the board.
44
2 Motherboard Resources
2.1 Memory Map
Table 27.Memory Map
Address Range (decimal)Address Range (hex) SizeDescription
1024 K - 292144 K100000 - 10000000256 MBExtended memory
896 K - 1024 KE8000 - FFFFF96 KBSystem BIOS
800 K - 896 KC8000 - DFFFF96 KBAvailable high DOS memory (open to ISA and
640 K - 800 KA0000 - C7FFF160 KBVideo memory and BIOS
0 K - 640 K00000 - 9FFFF640 KBConventional memory
2.2 DMA Channels
Table 28.DMA Channels
PCI buses)
DMA Channel NumberData WidthSystem Resource
08- or 16-bitsAudio
18- or 16-bitsAudio / parallel port
28- or 16-bitsFloppy drive
38- or 16-bitsParallel port (for ECP)/audio
4Reserved - cascade channel
516-bitsOpen
616-bitsOpen
716-bitsOpen
000000Intel® 82443EX (PAC)
000100Intel 82443EX (PAC) A.G.P. bus
000700Intel 82371EB (PIIX4E) PCI/ISA bridge
000701Intel 82371EB (PIIX4E) IDE bus master
000702Intel 82371EB (PIIX4E) USB
000703Intel 82371EB (PIIX4E) power management
000600Intel 83558 Ethernet controller (if present)
010000ATI Rage II C
0012
0014
2.5 Interrupts
Table 31.Interrupts
IRQSystem Resource
NMII/O channel check
0Reserved, interval timer
1Reserved, keyboard controller
2Reserved, cascade interrupt from slave PIC
3COM2 (User available if COM2 is not present)
4COM1*
5LPT2 (Plug and Play option) / audio / user available
6Diskette Drive controller
7LPT1*
8Real time clock
9Reserved
10USB/User available
11Windows Sound System* / user available
12PS/2 mouse port (if present, else user available)
13Reserved, numeric processor
14Primary IDE (if present, else user available)
This section describes interrupt sharing and how the interrupt signals are connected between the
‡
PCI expansion slots
be shared between devices attached to the PCI bus. In most cases, the small amount of latency
added by interrupt sharing does not affect the operation or throughput of the devices. In some
special cases where maximum performance is needed from a device, a PCI device should not share
an interrupt with other PCI devices. Use the following information to avoid sharing an interrupt
with a PCI add-in card.
PCI devices are categorized as follows to specify their interrupt grouping:
• INTA: By default, all add-in cards that require only one interrupt are in this category. For
almost all cards that require more than one interrupt, the first interrupt on the card is also
classified as INTA.
• INTB: Generally, the second interrupt on add-in cards that require two or more interrupts is
classified as INTB. (This is not an absolute requirement.)
• INTC and INTD: Generally, a third interrupt on add-in cards is classified as INTC and a
fourth interrupt is classified as INTD.
and onboard PCI devices. The PCI specification specifies how interrupts can
The PIIX4E PCI-to-ISA bridge has four programmable interrupt request (PIRQ) input signals.
Any PCI interrupt source (either onboard or from a PCI add-in card) connects to one of these PIRQ
signals. Because there are only four signals, some PCI interrupt sources are mechanically tied
together on the motherboard and therefore share the same interrupt. Table 32 lists the PIRQ
‡
signals and shows how the signals are connected to the PCI expansion slots
For example, assume an add-in card has one interrupt (group INTD) into the second PCI slot. In
this slot, an interrupt source from group INTA connects to the PIRQD signal, which is already
connected to the onboard video and USB PCI sources. The add-in card shares an interrupt with
these onboard interrupt sources.
NOTE
✏
The PIIX4E can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 7, 11, 14, 15).
Typically, a device that does not share a PIRQ line will have a unique interrupt. However, in
certain interrupt-constrained situations, it is possible for two or more of the PIRQ lines to be
connected to the same IRQ signal.
48
3 Overview of BIOS Features
The motherboard uses an Intel/Phoenix BIOS, which is stored in flash memory and can be
upgraded using a disk-based program. In addition to the BIOS, the flash memory contains the
Setup program, Power-On Self Test (POST), Advanced Power Management (APM), the PCI autoconfiguration utility, and Windows 95-ready Plug and Play. See Section 6.2 for the supported
versions of these specifications.
This motherboard supports system BIOS shadowing, allowing the BIOS to execute from 64-bit
onboard write-protected DRAM.
The BIOS displays a message during POST identifying the type of BIOS and a revision code. The
initial production BIOS is identified as 4K4UE0X0.86A.xxxx.P01.
3.1 BIOS Upgrades
The BIOS can be upgraded from a diskette using the Intel Flash Memory Update utility that is
available from Intel. This utility upgrades the BIOS as follows:
• Updates the flash BIOS from a file on a disk
• Updates the language section of the BIOS
• Makes sure that the upgrade BIOS matches the target system to prevent accidentally installing
a BIOS for a different type of system.
BIOS upgrades and the Intel Flash Memory Update utility are available from Intel through the
Intel World Wide Web site. See Section 6.1 for information about this site.
NOTE
✏
Please review the instructions distributed with the upgrade utility before attempting a BIOS
upgrade.
The Intel 28F002 2-Mbit flash component is organized as 256 KB x 8 bits and is divided into
areas as described in Table 33. The table shows the addresses in the ROM image in normal mode
(the addresses change in BIOS Recovery Mode).
Table 33.Flash Memory Organization
Address (Hex)SizeDescription
FFFFC000 - FFFFFFFF16 KBBoot Block
FFFFA000 - FFFFBFFF8 KBVital Product Data (VPD) Extended System Configuration Data
(ESCD) (SMBIOS configuration data / Plug and Play data)
FFFF9000 - FFFF9FFF4 KBUsed by BIOS (for activities such as Event Logging)
FFFF8000 - FFFF8FFF4 KBOEM logo or Scan Flash Area
FFFC0000 - FFFF7FFF224 KBMain BIOS Block
3.3 Plug and Play: PCI Autoconfiguration
The BIOS can automatically configure PCI devices and Plug and Play devices. PCI devices may
be onboard or add-in cards. Plug and Play devices are ISA devices built to meet the Plug and Play
specification. Autoconfiguration lets a user insert or remove PCI or Plug and Play cards without
having to configure the system. When a user turns on the system after adding a PCI or Plug and
Play card, the BIOS automatically configures interrupts, the I/O space, and other system resources.
Any interrupts set to Available in Setup are considered to be available for use by the add-in card.
PCI interrupts are distributed to available ISA interrupts that have not been assigned to an ISA
card or to system resources. The assignment of PCI interrupts to ISA IRQs is nondeterministic.
PCI devices can share an interrupt, but an ISA device cannot share an interrupt allocated to PCI or
to another ISA device. Autoconfiguration information is stored in the extended system
configuration data (ESCD) format.
For information about the versions of PCI and Plug and Play supported by this BIOS, see
Section 6.2. Copies of the specifications can be obtained from the Intel World Wide Web site (see
Section 6.2).
50
Overview of BIOS Features
3.4 PCI IDE Support
If you select Auto in Setup, the BIOS automatically sets up the two PCI IDE connectors with
independent I/O channel support. The IDE interface supports hard drives up to PIO Mode 4 and
recognizes any ATAPI devices, including CD-ROM drives, tape drives and Ultra DMA drives (see
Section 6.2 for the supported version of ATAPI). Add-in ISA IDE controllers are not supported.
The BIOS determines the capabilities of each drive and configures them to optimize capacity and
performance. To take advantage of the high capacities typically available today, hard drives are
automatically configured for Logical Block Addressing (LBA) and to PIO Mode 3 or 4, depending
on the capability of the drive. You can override the auto-configuration options by specifying
manual configuration in Setup. The ATAPI Specification recommends that ATAPI devices be
configured as shown in Table 34.
Table 34.Recommendations for Configuring an ATAPI Device
Primary CableSecondary Cable
Configuration
Normal, no ATAPIATA
Disk and CD-ROM for enhanced IDE systemsATAATAPI
Legacy IDE system with only one cableATAATAPI
Enhanced IDE with CD-ROM and a tape or two CD-ROMsATAATAPIATAPI
Drive 0Drive 1Drive 0Drive 1
3.5 ISA Plug and Play
If Plug and Play O/S (see Section 4.3) is selected in Setup, the BIOS autoconfigures only ISA Plug
and Play cards that are required for booting (IPL devices). If Plug and Play O/S is not selected in
Setup, the BIOS autoconfigures all Plug and Play ISA cards.
3.6 ISA Legacy Devices
Since ISA legacy devices are not autoconfigurable, the resources for them must be reserved.
Resources can be reserved in the Setup program or with an ISA configuration utility. The ISA
configuration utility can be downloaded from the Intel World Wide Web site (see Section 6.1).
System Management BIOS (SMBIOS) is an interface for managing computers in an enterprise
environment. The main component of SMBIOS is the management information format (MIF)
database, which contains information about the computing system and its components. Using
SMBIOS, a system administrator can obtain the system types, capabilities, operational status, and
installation dates for system components. The MIF database defines the data and provides the
method for accessing this information. The BIOS enables applications such as Intel
Client Manager to use SMBIOS. The BIOS stores and reports the following SMBIOS information:
• BIOS data, such as the BIOS revision level
• Fixed-system data, such as peripherals, serial numbers, and asset tags
• Resource data, such as memory size, cache size, and processor speed
• Dynamic data, such as event detection and error logging
OEMs can use a utility that programs flash memory so the BIOS can report on system and chassis
information. This utility is available through Intel sales offices. See Section 6.1 for information
about contacting a local Intel sales office. See Section 6.2 for information about the latest
SMBIOS specification.
®
LANDesk
®
SMBIOS does not work directly under non-Plug and Play operating systems (such as
Windows NT). However, the BIOS supports a SMBIOS table interface for such operating
systems. Using this support, a SMBIOS service-level application running on a non-Plug and Play
OS can access the SMBIOS BIOS information.
3.8 Advanced Power Management (APM)
See Section 6.2 for the version of the APM specification that is supported. The energy saving
standby mode can be initiated in the following ways:
• Time-out period specified in Setup
• Suspend/resume switch connected to the front panel sleep connector
• From the operating system, such as the Suspend menu item in Windows 95
In standby mode, the motherboard can reduce power consumption by spinning down hard drives,
†
and reducing power to or turning off VESA
DPMS-compliant monitors. Power-management
mode can be enabled or disabled in Setup (see Section 4.5).
While in standby mode, the system retains the ability to respond to external interrupts and service
requests, such as incoming faxes or network messages. Any keyboard or mouse activity brings the
system out of standby mode and immediately restores power to the monitor.
The BIOS enables APM by default; but the operating system must support an APM driver for the
power-management features to work. For example, Windows 95 supports the power-management
features upon detecting that APM is enabled in the BIOS.
‡
52
Overview of BIOS Features
3.9 Advanced Configuration and Power Interface (ACPI)
ACPI gives the operating system direct control over the power management and Plug and Play
functions of a computer. ACPI requires an ACPI-aware operating system. ACPI features include:
• Plug and Play (including bus and device enumeration) and Advanced Power Management
(APM) functionality normally contained in the BIOS
• Power management control of individual devices, add-in boards (some add-in boards may
require an ACPI-aware driver), video displays, and hard disk drives
• Methods for achieving less than 30-watt system operation in the Power On Suspend sleeping
state, and less than 5-watt system operation in the Soft Off sleeping state
• A Soft-off feature that enables the operating system to power off the computer
• Support for multiple wake up events (see Table 37)
• Support for a front panel power and sleep mode switch. Table 35 describes the system states
based on how long the switch is pressed
Table 35. Effects of Pressing the Power Switch
…and the power switch is
If the system is in this state…
OffLess than four secondsPower on
OnLess than four secondsSleep
OnMore than four secondsPower off
SleepLess than four secondsWake up
pressed for…the system enters this state
‡
3.9.1 System States and Power States
Under ACPI, the operating system directs all system and device power state transitions. The
operating system puts devices in and out of low-power states based on user preferences and
knowledge of how devices are being used by applications. Devices that are not being used can be
turned off. The operating system uses information from applications and user settings to put the
system as a whole into a low-power state.
Table 36 lists the power states supported by the motherboard along with the associated system
power targets. See the ACPI specification for a complete description of the various system and
power states.
In addition to power management, ACPI provides controls and information so that the operating
system can facilitate Plug and Play device enumeration and configuration. ACPI is used only to
enumerate and configure motherboard devices that do not have other hardware standards for
enumeration and configuration. PCI devices on the motherboard, for example, are not enumerated
by ACPI.
54
Overview of BIOS Features
3.9.4 BIOS Support
The BIOS supports both APM and ACPI. If the board is used with an ACPI-aware operating
system, the BIOS provides ACPI support. Otherwise, it defaults to APM support.
3.10 Language Support
The Setup program and help messages can be supported in 32 languages. Five languages are
available: American English, German, Italian, French, and Spanish. The default language is
American English, which is present unless another language is programmed into the BIOS using
the flash memory update utility. See Section 3.1 for information about the BIOS update utility.
3.11 Boot Options
In the Setup program, the user can choose to boot from a floppy drive, hard drive, CD-ROM,
network, or any BIOS boot specification (BBS) compliant device. The default setting is for the
floppy drive to be the primary boot device and the hard drive to be the secondary boot device. By
default the third and fourth devices are disabled.
Booting from CD-ROM is supported in compliance to the El Torito bootable CD-ROM format
specification. See Section 6.2 for information about the El Torito specification. Under the Boot
menu in the Setup program, CD-ROM is listed as a boot device. Boot devices are defined in
priority order. If the CD-ROM is selected as the boot device, it must be the first device.
The network can be selected as a boot device. This selection allows booting from a network add-in
card with a remote boot ROM installed.
3.12 OEM Logo or Scan Area
A 4 KB flash-memory user area at memory location FFFF8000h-FFFF8FFFh is for displaying a
custom OEM logo during POST. A utility is available from Intel to assist with installing a logo
into the flash memory. Contact Intel customer support for further information. See Section 6.1 for
information on contacting Intel customer support.
USB legacy support enables USB keyboards and mice to be used even when no operating system
USB drivers are in place. By default, USB legacy support is disabled. USB legacy support is only
intended to be used in accessing BIOS Setup and installing an operating system that supports USB.
This sequence describes how USB legacy support operates in the default (disabled) mode.
1. When you power up the computer, USB legacy support is disabled.
2. POST begins.
3. USB legacy support is temporarily enabled by the BIOS. This allows you to use a USB
keyboard to enter the Setup program or the maintenance mode.
4. POST completes and disables USB legacy support (unless it was set to Enabled while in
Setup).
5. The operating system loads. While the operating system is loading, USB keyboards and mice
are not recognized. After the operating system loads the USB drivers, the USB devices are
recognized.
To install an operating system that supports USB, enable USB Legacy support in BIOS Setup and
follow the operating system’s installation instructions. Once the operating system is installed and
the USB drivers configured, USB legacy support is no longer used. USB Legacy Support can be
left enabled in BIOS Setup if needed.
Notes on using USB legacy support:
• If USB legacy support is enabled, don't mix USB and PS/2 keyboards and mice. For example,
do not use a PS/2 keyboard with a USB mouse, or a USB keyboard and a PS/2 mouse.
• Do not use USB devices with an operating system that does not support USB. USB legacy is
not intended to support the use of USB devices in a non USB operating system.
• USB legacy support is for keyboards and mice only. Hubs and other USB devices are not
supported.
3.14 BIOS Setup Access
Access to the Setup program can be restricted using passwords. User and administrative
passwords can be set using the Security menu in Setup. The default is no passwords enabled. See
Section 4.4 for information about setting user and administrative passwords.
3.15 Recovering BIOS Data
Some types of failure can destroy the BIOS. For example, the data can be lost if a power outage
occurs while the BIOS is being updated in flash memory. The BIOS can be recovered from a
diskette using the BIOS recovery mode.
To create a BIOS recovery diskette, a bootable diskette must be created and the recovery files
copied to it. The recovery files are available from Intel, contact Intel customer support for further
information. See Section 6.1 for information on contacting Intel customer support.
56
4 BIOS Setup Program
The Setup program is for viewing and changing the BIOS settings for a computer. Setup is
accessed by pressing the <F2> key after the Power-On Self Test (POST) memory test begins and
before the operating system boot begins.
Table 38 shows the menus available from the menu bar at the top of the Setup screen.
Table 38.Setup Menu Bar
Setup Menu ScreenDescription
MaintenanceSpecifies the processor speed and clears the Setup passwords. This
menu is only available in configure mode. Refer to Section 1.18 for
information about configure mode.
MainAllocates resources for hardware components.
AdvancedSpecifies advanced features available through the chipset.
SecuritySpecifies passwords and security features.
PowerSpecifies power management features.
BootSpecifies boot options and power supply controls.
ExitSaves or discards changes to the Setup program options.
Table 39 shows the function keys available for menu screens.
Table 39.Setup Function Keys
Setup KeyDescription
<F1> or <Alt-H>Brings up a help screen for the current item.
<Esc>Exits the menu.
<←> or <→>Selects a different menu screen.
<↑> or <↓>Moves cursor up or down.
<Home> or <End>Moves cursor to top or bottom of the window.
<PgUp> or <PgDn>Moves cursor to top or bottom of the window.
<F5> or <->Selects the previous value for a field.
<F6> or <+> or <Space>Selects the next value for a field.
<F9>Load the default configuration values for the current menu.
<F10>Save the current values and exit Setup.
<Enter>Executes command or selects the submenu.
The maintenance menu is for setting the processor speed and clearing the Setup passwords. Setup
only displays this menu in configure mode. See Section 1.18 for information about setting
configure mode.
Table 40.Maintenance Menu
FeatureOptionsDescription
Processor Speed• 233
• 266
• 300
• 333
Clear All PasswordsNo optionsClears the user and administrative passwords.
Specifies the processor speed in megahertz. This setup
screen will only show speeds up to and including the
maximum speed of the processor installed on the
motherboard.
With a host bus operating at 66 MHz, the board supports
processors at the following speeds: 266, 300, and
333 MHz.
4.2 Main Menu
This menu reports processor and memory information and is for configuring the system date and
system time.
Table 41.Main Menu
FeatureOptionsDescription
BIOS VersionNo optionsDisplays the version of the BIOS.
Processor TypeNo optionsDisplays processor type.
Processor SpeedNo optionsDisplays processor speed.
Cache RAMNo optionsDisplays size of second-level cache, if present.
System MemoryNo optionsDisplays the total amount of RAM on the motherboard.
Memory Bank 0
Memory Bank 1
Language• English (US)
System TimeHour, minute,
System DateMonth, day, and
No optionsDisplays size and type of DIMM installed in each memory bank.
Displays the default language used by the BIOS.
(default)
• Italian
• Francais
• Deutsch
• Espanol
Specifies the current time.
and second
Specifies the current date.
year
58
4.3 Advanced Menu
This menu is for setting advanced features that are available through the chipset.
Table 42.Advanced Menu
FeatureOptionsDescription
Plug & Play O/S• No (default)
• Yes
Reset Configuration Data• No (default)
• Yes
Numloc• Auto (default)
• On
• Off
Peripheral ConfigurationNo optionsConfigures peripheral ports and devices. When
Primary IDE Master,
submenu
Floppy Configuration,
submenu
SMBIOS Events LoggingNo optionsConfigures SMBIOS Events Logging. When selected,
Video ConfigurationNo optionsConfigures video features. When selected, displays
Resource ConfigurationNo optionsConfigures memory blocks and IRQs for legacy ISA
No optionsSpecifies Reports type of connected IDE device.
No optionsWhen selected, displays the Floppy Options
Specifies if a Plug and Play operating system is being
used.
No
lets the BIOS configure all devices.
Yes
lets the operating system configure Plug and Play
devices. Not required with a Plug and Play operating
system.
Clears the BIOS configuration data on the next boot.
Specifies the power on state of the Num Lock feature
on the numeric keypad of the keyboard.
selected, displays the Peripheral Configuration
submenu.
When selected, displays the Primary IDE Master
submenu.
submenu.
displays the SMBIOS Events Logging submenu.
the Video Configuration submenu.
devices. When selected, displays the Resource
Configuration submenu.
This submenu is for configuring IDE devices, including:
• Primary IDE master
• Primary IDE slave
• Secondary IDE master
• Secondary IDE slave
Table 45.IDE Configuration Submenus
FeatureOptionsDescription
Type• None
• ATAPI Removable
• Other ATAPI
• CD-ROM
• User
• IDE Removable
• Auto (default)
Maximum CapacityNo optionsReports the maximum capacity for the hard disk.
Multi-Sector Transfers• Disabled (default)
• 2 Sectors
• 4 Sectors
• 8 Sectors
• 16 Sectors
LBA Mode Control• Disabled (default)
• Enabled
Transfer Mode• Standard (default)
• Fast PIO 1
• Fast PIO 2
• Fast PIO 3
• Fast PIO 4
• FPIO 3 / DMA 1
• FPIO 4 / DMA 2
Ultra DMA• Disabled (default)
• Mode 0
• Mode 1
• Mode 2
Specifies the IDE configuration mode for IDE
devices.
User
allows the cylinders, heads, and sectors
fields to be changed.
Auto
automatically fills in the values for the
cylinders, heads, and sectors fields.
Specifies number of sectors per block for
transfers from the hard drive to memory.
Check the hard drive’s specifications for optimum
setting.
Enables or disables the LBA mode control.
Specifies the method for moving data to/from the
drive.
Specifies the Ultra DMA mode for the drive.
62
4.3.4 Floppy Options Submenu
This submenu is for configuring the floppy drive.
Table 46.Floppy Options Submenu
FeatureOptionsDescription
Floppy Disk Controller• Auto
• Disabled
• Enabled (default)
Diskette A:• Disabled
• 360 KB, 5¼″
• 1.2 MB, 5¼″
• 720 KB, 3½″
• 1.44/1.25 MB, 3½″ (default)
• 2.88 MB, 3½″
Floppy Write Protect• Disabled (default)
• Enabled
BIOS Setup Program
Disables or enables the integrated floppy
disk controller.
Specifies the capacity and physical size
of diskette drive A.
Disables or enables write protect for the
diskette drive.
4.3.5 DMI Event Logging
This submenu is for configuring the DMI event logging features.
Table 47.DMI Event Logging Submenu
FeatureOptionsDescription
Event log capacityNo optionsIndicates if there is space available in the event log.
Event log validityNo optionsIndicates if the contents of the event log are valid.
View DMI event logNo optionsEnables viewing of SMBIOS event log.
Clear all DMI event logs• No (default)
• Yes
Event Logging• Disabled
• Enabled (default)
Mark DMI events as readNo optionsMarks all SMBIOS events as read.
4.3.6 Video Configuration Submenu
This submenu is for configuring video features.
Table 48.Video Configuration Submenu
FeatureOptionsDescription
Palette Snooping• Disabled (default)
• Enabled
AGP Aperture Size• 64 MB (default)
• 256 MB
Controls the ability of a primary PCI graphics controller to
share a common palette with an ISA add-in video card.
Specifies the aperture size for the A.G.P. video controller.
This submenu is for configuring the memory and interrupts.
Table 49.Resource Configuration Submenu
FeatureOptionsDescription
Memory
Reservation
IRQ
Reservation
• C800 - CBFFAvailable (default) | Reserved
• CC00- CFFFAvailable (default) | Reserved
• D000 - D3FFAvailable (default) | Reserved
• D400 - D7FFAvailable (default) | Reserved
• D800 - DBFFAvailable (default) | Reserved
• DC00 - DFFFAvailable (default) | Reserved
• IRQ3Available (default) | Reserved
• IRQ4 Available (default) | Reserved
• IRQ5 Available (default) | Reserved
• IRQ7 Available (default) | Reserved
• IRQ10 Available (default) | Reserved
• IRQ11 Available (default) | Reserved
Reserves specific
upper memory blocks
for use by legacy ISA
devices.
Reserves specific
IRQs for use by legacy
ISA devices.
An * (asterisk)
displayed next to an
IRQ indicates an IRQ
conflict.
4.4 Security Menu
This menu is for setting passwords and security features.
Table 50.Security Menu
FeatureOptionsDescription
User Password IsNo optionsReports if there is a user password set.
Administrative Password Is No optionsReports if there is a administrative password
Set User PasswordPassword can be up to seven
alphanumeric characters.
Set Administrative
Password
Clear UserNo OptionsClears the user password.
User Setup Access• Disabled
Unattended Start• Disabled (default)
Password can be up to seven
alphanumeric characters.
• View only (default)
• Limited access
• Enabled
• Enabled
set.
Specifies the user password.
Specifies the administrative password.
Enables or disables User Setup Access.
Disabled
Setup. View only and limited access options
are available only when the administrative
password is set.
Enables the unattended start feature. When
enabled, the computer boots, but the
keyboard is locked. The user must enter a
password to unlock the computer or boot
from a floppy diskette.
prevents the user from accessing
64
4.5 Power Menu
This menu is for setting power management features.
Table 51.Power Menu
FeatureOptionsDescription
Power Management• Disabled
• Enabled (default)
Fan always on• Yes
• No (default)
Inactivity Timer• Off (default) (default)
• 1 Minute
• 5 Minutes
• 10 Minutes
• 20 Minutes
• 30 Minutes
• 60 Minutes
• 120 Minutes
Hard Drive• Disabled
• Enabled (default)
VESA Video Power Down• Disabled
• Standby (default)
• Suspend
• Sleep
BIOS Setup Program
Enables or disables the BIOS power
management feature.
If enabled, the fan will continue to run when
the system has been powered off.
Specifies the amount of time before the
computer enters standby mode.
Enables power management for hard disks
during standby and suspend modes.
Specifies power management for video during
standby and suspend modes.
4.6 Boot Menu
This menu is for setting the boot features and the boot sequence.
Table 52.Boot Menu
FeatureOptionsDescription
Quick Boot Mode• Disabled
• Enabled (default)
Scan User Flash
Area
After Power Failure• Power On
On Modem Ring• Stay Off
On LAN• Stay Off
• Disabled (default)
• Enabled
• Stay Off
• Last State (default)
• Power On (default)
• Power On (default)
Enables the computer to boot without running certain
POST tests.
Enables the BIOS to scan the flash memory for user
binary files that are executed at boot time.
Specifies the mode of operation if an AC/Power loss
occurs.
Power On
Stay Off
pressed.
Last State
loss occurred.
Specifies how the computer responds to an incoming call
on an installed modem when the system is off.
Specifies how the computer responds to a LAN wakeup
First Boot Device
Second Boot Device
Third Boot Device
Fourth Boot Device
Fifth Boot Device
Hard DriveNo optionsLists available hard drives. When selected, displays the
Removable DevicesNo optionsLists available removable devices. When selected,
(continued)
• Power On
• Removable devices
• Hard Drive
• ATAPI CD-ROM
Drive
• Network Boot
• LSA
Specifies how the computer responds to a PME wakeup
event when the power is off.
Specifies the boot sequence from the available devices.
To specify boot sequence:
1. Select the boot device with <↑> or <↓>.
2. Press <+> to move the device up the list or <-> to
move the device down the list.
The operating system assigns a drive letter to each boot
device in the order listed. Changing the order of the
devices changes the drive lettering.
LSA option is available only if LAN is present.
Hard Drive submenu.
displays the Removable Devices submenu.
4.6.1 Hard Drive Submenu
This submenu is for configuring the boot sequence for hard drives.
Table 53.Hard Drive Submenu
OptionsDescription
• Bootable Add in CardSpecifies the boot sequence for the hard drives attached to the computer. To
specify boot sequence:
1. Select the boot device with <↑> or <↓>.
2. Press <+> to move the device up the list or <-> to move the device down
the list.
The operating system assigns a drive letter to each device in the order listed.
Changing the order of the devices changes the drive lettering.
4.6.2 Removable Devices Submenu
This submenu is for configuring the boot sequence for removable devices.
Table 54.Removable Devices Submenu
OptionsDescription
• Legacy Floppy DrivesSpecifies the boot sequence for the removable devices attached to the
computer. To specify boot sequence:
1. Select the boot device with <↑> or <↓>.
2. Press <+> to move the device up the list or <-> to move the device down
the list.
The operating system assigns a drive letter to each device in the order listed.
Changing the order of the devices changes the drive lettering.
66
4.7 Exit Menu
This menu is for exiting the Setup program, saving changes, and loading and saving defaults.
Table 55.Exit Menu
FeatureDescription
Exit Saving ChangesExits and saves the changes in CMOS RAM.
Exit Discarding ChangesExits without saving any changes made in Setup.
Load Setup DefaultsLoads the factory default values for all the Setup options.
Load Custom DefaultsLoads the custom defaults for Setup options.
Save Custom DefaultsSaves the current values as custom defaults. Normally, the BIOS reads the
Setup values from flash memory. If this memory is corrupted, the BIOS reads
the custom defaults. If no custom defaults are set, the BIOS reads the factory
defaults.
Discard ChangesDiscards changes without exiting Setup. The option values present when the
Diskette drive A errorDrive A is present but fails the POST diskette tests. Check that the drive
is defined with the proper diskette type in Setup and that the diskette drive
is installed correctly.
Extended RAM Failed at offset:
nnnn
Failing Bits:
Fixed Disk 0 Failure or
Fixed Disk 1 Failure or
Fixed Disk Controller Failure
Incorrect Drive A type - run
SETUP
Invalid NVRAM media typeProblem with NVRAM (CMOS) access.
Keyboard controller errorThe keyboard controller failed test. Try replacing the keyboard.
Keyboard errorKeyboard not working.
Keyboard error nnBIOS discovered a stuck key and displays the scan code nn for the stuck
Keyboard locked - Unlock key
switch
Monitor type does not match
CMOS - Run SETUP
Operating system not foundOperating system cannot be located on either drive A or drive C. Enter
Parity Check 1Parity error found in the system bus. BIOS attempts to locate the address
Parity Check 2Parity error found in the I/O bus. BIOS attempts to locate the address and
Press <F1> to resume, <F2> to
Setup
Real time clock errorReal-time clock fails BIOS test. May require motherboard repair.
nnnn
Extended memory not working or not configured properly at offset
The hexadecimal number
(System, Extended, or Shadow memory) that failed the memory test.
Each 1 in the map indicates a failed bit.
Fixed disk is not working or not configured properly. Check to see if fixed
disk is installed properly. Run Setup be sure the fixed-disk type is
correctly identified.
Type of diskette drive for drive A not correctly identified in Setup.
key.
Unlock the system to proceed.
Monitor type not correctly identified in Setup.
Setup and see if fixed disk and drive A are properly identified.
and display it on the screen. If it cannot locate the address, it displays
????.
display it on the screen. If it cannot locate the address, it displays ????.
Displayed after any recoverable error message. Press <F1> to start the
boot process or <F2> to enter Setup and change any settings.
System timer errorThe timer test failed. Requires repair of system motherboard.
nnnn = hexadecimal number
(continued)
Shadow RAM failed at offset
was detected.
The CMOS clock battery indicator shows the battery is dead. Replace the
battery and run Setup to reconfigure the system.
RAM cache failed the BIOS test. BIOS disabled the cache.
System CMOS RAM has been corrupted or modified incorrectly, perhaps
by an application program that changes data stored in CMOS. Run Setup
and reconfigure the system either by getting the default values and/or
making your own selections.
System RAM failed at offset
was detected.
nnnn
of the 64 KB block at which the error
nnnn
of the 64 KB block at which the error
70
Error Messages and Beep Codes
5.2 Port 80h POST Codes
During the POST, the BIOS generates diagnostic progress codes (POST codes) to I/O port 80h. If
the POST fails, execution stops and the last POST code generated is left at port 80h. This code is
useful for determining the point where an error occurred.
Displaying the POST codes requires an add-in card (often called a POST card). The POST card
can decode the port and display the contents on a medium such as a seven-segment display. These
cards can be purchased from JDR Microdevices or other sources.
The following table provides the POST codes that can be generated by the BIOS. Some codes are
repeated in the table because that code applies to more than one operation.
Table 57.Port 80h Codes
CodeDescription of POST Operation
02hVerify real mode
03hDisable non-maskable interrupt (NMI)
04hGet processor type
06hInitialize system hardware
08hInitialize chipset with initial POST values
09hSet IN POST flag
0AhInitialize processor registers
0BhEnable processor cache
0ChInitialize caches to initial POST values
0EhInitialize I/O component
0FhInitialize the local bus IDE
10hInitialize power management
11hLoad alternate registers with initial POST
12hRestore processor control word during warm boot
13hInitialize PCI bus mastering devices
14hInitialize keyboard controller
16hBIOS ROM checksum
17hInitialize cache before memory autosize
18h8254 timer initialization
1Ah8237 DMA controller initialization
1ChReset programmable interrupt controller
20hTest DRAM refresh
22hTest keyboard controller
24hSet ES segment register to 4 GB
26hEnable A20 line
28hAutosize DRAM
CodeDescription of POST Operation Currently In Progress
29hInitialize POST memory manager
2AhClear 512 KB base RAM
2ChRAM failure on address line
2EhRAM failure on data bits
2FhEnable cache before system BIOS shadow
30hRAM failure on data bits
32hTest processor bus-clock frequency
33hInitialize POST dispatch manager
34hTest CMOS RAM
35hInitialize alternate chipset registers
36hWarm start shut down
37hReinitialize the chipset (motherboard only)
38hShadow system BIOS ROM
39hReinitialize the cache (motherboard only)
3AhAutosize cache
3ChConfigure advanced chipset registers
3DhLoad alternate registers with CMOS
40hSet Initial processor speed new
42hInitialize interrupt vectors
44hInitialize BIOS interrupts
45hPOST device initialization
46hCheck ROM copyright notice
47hInitialize manager for PCI option ROMs
48hCheck video configuration against CMOS RAM data
49hInitialize PCI bus and devices
4AhInitialize all video adapters in system
4BhDisplay QuietBoot screen
4ChShadow video BIOS ROM
4EhDisplay BIOS copyright notice
50hDisplay processor type and speed
51hInitialize EISA motherboard
52hTest keyboard
54hSet key click if enabled
56hEnable keyboard
58hTest for unexpected interrupts
59hInitialize POST display service
5AhDisplay prompt "Press F2 to enter SETUP"
5BhDisable processor cache
(continued)
xxxx*
xxxx*
of low byte of memory bus
xxxx*
of high byte of memory bus
valuesnew
72
continued
Error Messages and Beep Codes
Table 57.Port 80h Codes
CodeDescription of POST Operation Currently In Progress
5ChTest RAM between 512 and 640 KB
60hTest extended memory
62hTest extended memory address lines
64hJump to UserPatch1
66hConfigure advanced cache registers
67hInitialize multiprocessor APIC
68hEnable external and processor caches
69hSetup System Management Mode (SMM) area
6AhDisplay external L2 cache size
6ChDisplay shadow-area message
6EhDisplay possible high address for UMB recovery
70hDisplay error messages
72hCheck for configuration errors
74hTest real-time clock
76hCheck for keyboard errors
7AhTest for key lock on
7ChSet up hardware interrupt vectors
7EhInitialize coprocessor if present
80hDisable onboard Super I/O ports and IRQs
81hLate POST device initialization
82hDetect and install external RS232 ports
83hConfigure non-MCD IDE controllers
84hDetect and install external parallel ports
85hInitialize PC-compatible PnP ISA devices
86hRe-initialize onboard I/O ports
87hConfigure motherboard configurable devices
88hInitialize BIOS Data Area
89hEnable Non-Maskable Interrupts (NMIs)
8AhInitialize extended BIOS data area
8BhTest and initialize PS/2 mouse
8ChInitialize diskette controller
8FhDetermine number of ATA drives
90hInitialize hard-disk controllers
91hInitialize local-bus hard-disk controllers
92hJump to UserPatch2
93hBuild MPTABLE for multiprocessor boards
94hDisable A20 address line (Rel. 5.1 and earlier)
95hInstall CD-ROM for boot
CodeDescription of POST Operation Currently In Progress
96hClear huge ES segment register
97hFix up multiprocessor table
98hSearch for option ROMs
99hCheck for SMART Drive
9AhShadow option ROMs
9ChSet up power management
9EhEnable hardware interrupts
9FhDetermine number of ATA and SCSI drives
A0hSet time of day
A2hCheck key lock
A4hInitialize typematic rate
A8hErase F2 prompt
AahScan for F2 key stroke
AchEnter SETUP
AehClear IN POST flag
B0hCheck for errors
B2hPOST done - prepare to boot operating system
B4hOne short beep before boot
B5hTerminate QuietBoot
B6hCheck password (optional)
B8hClear global descriptor table
B9hClean up all graphics
BahInitialize SMBIOS parameters
BBhInitialize PnP Option ROMs
BChClear parity checkers
BDhDisplay MultiBoot menu
BehClear screen (optional)
BFhCheck virus and backup reminders
C0hTry to boot with INT 19h
C1hInitialize POST Error Manager (PEM)
C2hInitialize error logging
C3hInitialize error display function
C4hInitialize system error handler
E0hInitialize the chipset
E1hInitialize the bridge
E2hInitialize the processor
(continued)
74
continued
Error Messages and Beep Codes
Table 57.Port 80h Codes
(continued)
CodeDescription of POST Operation (The following are for boot block in flash ROM)
E3hInitialize system timer
E4hInitialize system I/O
E5hCheck force recovery boot
E6hChecksum BIOS ROM
E7hGo to BIOS
E8hSet huge segment
E9hInitialize multiprocessor
EahInitialize OEM special code
EbhInitialize PIC and DMA
EchInitialize memory type
EdhInitialize memory size
EehShadow boot block
EfhSystem memory test
F0hInitialize interrupt vectors
F1hInitialize runtime clock
F2hInitialize video
F3hInitialize beeper
F4hInitialize boot
F5hClear huge segment
F6hBoot to mini-DOS
F7hBoot to full DOS
* If the BIOS detects error 2Ch, 2Eh, or 30h (base 512 K RAM error), it displays an additional word-bitmap (xxxx) indicating
the address line or bits that failed. For example, "2C 0002" means address line 1 (bit one set) has failed. "2E 1020"
means data bits 12 and 5 (bits 12 and 5 set) have failed in the lower 16 bits. The BIOS also sends the bitmap to the port80 LED display. It first displays the check point code, followed by a delay, the high-order byte, another delay, and then
the low-order byte of the error. It repeats this sequence continuously.
Whenever a recoverable error occurs during Power-On Self Test (POST), the BIOS displays an
error message describing the problem. The BIOS also issues a beep code (one long tone followed
by two short tones) during POST if the video configuration fails (no card installed or faulty) or if
an external ROM module does not properly checksum to zero.
An external ROM module (such as video BIOS) can also issue audible errors, usually consisting of
one long tone followed by a series of short tones. For more information on the beep codes issued,
check the documentation for that external device.
There are several POST routines that issue a POST Terminal Error and shut down the system if
they fail. Before shutting down the system, the terminal-error handler issues a beep code
signifying the test point error, writes the error to I/O port 80h, attempts to initialize the video, and
writes the error in the upper left corner of the screen (using both monochrome and color adapters).
If POST completes normally, the BIOS issues one short beep before passing control to the
operating system.
Table 58.Beep Codes
BeepsPort 80h CodeExplanation
1-2-2-316hBIOS ROM checksum
1-3-1-120hTest DRAM refresh
1-3-1-322hTest keyboard controller
1-3-3-128hAutosize DRAM
1-3-3-229hInitialize POST memory manager
1-3-3-32AhClear 512 KB base RAM
1-3-4-12ChRAM failure on address line xxxx
1-3-4-32EhRAM failure on data bits xxxx of low byte of memory bus
1-4-1-130hRAM failure on data bits xxxx of high byte of memory bus
2-1-2-245hPOST device initialization
2-1-2-346hCheck ROM copyright notice
2-2-3-158hTest for unexpected interrupts
2-2-4-15ChTest RAM between 512 and 640 KB
1-298hSearch for option ROMs. One long, two short beeps on checksum failure
76
6 Specifications and Customer Support
6.1 Online Support
Find information about Intel boards under “Product Info” or “Customer Support” at this World
Wide Web site:
http://www.intel.com/
6.2 Specifications
The motherboard complies with the following specifications:
Table 59.Compliance with Specifications
SpecificationDescriptionRevision Level
A.G.P.Accelerated Graphics Port
Interface Specification
APMAdvanced Power Management
BIOS interface specification
ACPIAdvanced Configuration and
Power Interface specification
ATA-3Information Technology - AT
Attachment-3 Interface
ATAPIATA Packet Interface for CD-
ROMs
Revision 1.0, July, 1996, Intel Corporation.
The specification is available through the
Accelerated Graphics Implementers Forum at:
http://www.agpforum.org/.
Revision 1.2, February, 1996
Intel Corporation, Microsoft Corporation
Revision 1.0, December 22, 1996
Intel Corporation, Microsoft Corporation, and Toshiba
Corporation
X3T10/2008D Revision 6
ATA Anonymous FTP Site: fission.dt.wdc.com
NLXNLX form factor specificationRevision 2.01, February 1997
Intel Corporation, The specification is available at:
http://www.intel.com/
NLXNLX form factor specificationVersion 1.0, December, 1997
Intel Corporation
SMBIOSSMBIOS specificationVersion 2.1 - 16 June 1997
Award Software International Inc.,
Dell Computer Corporation,
Hewlett-Packard Company,
Intel Corporation,
International Business Machines Corporation,
Phoenix Technologies Limited,
SystemSoft Corporation.
El ToritoBootable CD-ROM format
specification
Version 1.0, January 25, 1995
Phoenix Technologies Ltd., IBM Corporation. The El
Torito specification is available on the Phoenix Web site
http://www.ptltd.com/techs/specs.html.
Revision 1.0, January 15, 1996
Compaq Computer Corporation, Digital Equipment
Corporation, IBM PC Company, Intel Corporation,
Microsoft Corporation, NEC, Northern Telecom
78
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