The JN440BX motherboard may contain design defects or errors known as errata. Characterized errata that may cause the JN440BX motherboard’s behavior to deviate from
published specifications are documented in the JN440BX Motherboard Specification Update.
699414-001
Revision History
RevisionRevision HistoryDate
-001First released versionApril 1998
This product specification applies only to standard JN440BX motherboards with BIOS identifier
4J4NB0X1
Changes to this specification will be published in the JN440BX Motherboard Specification Update
before being incorporated into a revision of this document.
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and
Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied
warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular
purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel retains the right to make changes to specifications and product descriptions at any time, without notice.
The JN440BX motherboard may contain design defects or errors known as errata which may cause the product to deviate
from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777,
Germany 44-0-1793-421-333, other Countries 708-296-9333.
†
Brand, name or trademark owned by another company.
The JN440BX motherboard is a versatile platform that offers a wide variety of features. Some of
the options, however, are implemented – at least in part – on the riser. Throughout this manual,
‡
symbol is used to indicate such an option. Because there is no standard riser, no detailed
the
description of an implementation can be given. See Section 6.1 to obtain the reference design for
the NLX riser.
Microprocessor
£
x
Single Pentium
x
66 MHz and 100 MHz host bus speeds
x
Integrated 512 KB or 1 MB of second level cache
x
Slot 1 connector
NOTE
✏
Pentium II processors with 100 MHz front-side bus should be paired only with 100 MHz SDRAM.
Processors with 66 MHz front side bus can be paired with either 66 MHz or 100 MHz SDRAM.
II processor
The motherboard features:
x
NLX v1.2 form factor
x
Minimal jumper design
Main Memory
x
Three 168-pin DIMM sockets
x
Support for up to 384 MB of synchronous DRAM (SDRAM)
x
Support for 66 MHz and 100 MHz SDRAM
x
Support for ECC and non-ECC memory
Chipset and PCI/IDE Interface
®
xxxxxx
82440BX AGPset PCI/A.G.P. Controller (PAC)
Intel
Integrated PCI bus mastering controller using PIIX4E
Dual channel EIDE interface
Real-time clock
PCI Slots
Automatic detection of Host Bus speed
The motherboard is designed to fit into a standard NLX form factor chassis. Figure 3 illustrates
the mechanical form factor for the motherboard. Location of the I/O connectors, riser slot, and
mounting holes are in strict compliance with the NLX specification (see Section 6.2). Dimensions
are given in inches.
The back panel I/O shield for the JN440BX motherboard must meet specific dimensional and
material requirements. Systems based on this motherboard need the back panel I/O shield in order
to pass emission certification testing. Figure 4 shows the critical dimensions of the I/O shield, and
indicates the position of each cutout. Dimensions are given in inches.
7.458
3.1461.6530.507
1.080
0.009.00
2.479
5.728
8.1826.7504.706
NLX Motherboard Shield
Figure 4. Back Panel I/O Shield Dimensions
OM07100
12
Motherboard Description
1.5 Microprocessor
The motherboard supports a single Pentium II processor. The processor’s VID pins automatically
program the motherboard’s voltage regulator to the required processor voltage. In addition, the
host bus speeds (66 MHz and 100 MHz) is automatically selected. The motherboard supports all
current processor speeds, voltages, and bus frequencies.
1.5.1 Microprocessor Packaging
The processor is packaged in a Single Edge Contact (S.E.C.) cartridge. The S.E.C. cartridge
includes the processor core, the second-level cache, a thermal plate, and a back cover.
The processor connects to the motherboard through the Slot 1 processor connector, a 242-pin edge
connector. When the processor is mounted in Slot 1, it is secured by a retention mechanism
attached to the motherboard. The processor’s heatsink is stabilized by a heatsink support that is
attached to the motherboard.
1.5.2 Second-Level Cache
The second-level cache is located on the substrate of the S.E.C. cartridge. The cache includes
pipelined burst synchronous static RAM (PBSRAM) and tag RAM. There can be two or four
PBSRAM components totaling 512 KB or 1024 KB in size. All supported onboard memory can be
cached.
1.5.3 Microprocessor Upgrades
The motherboard can be upgraded with Pentium II processors that run at higher processor speeds.
After upgrading the processor, use the BIOS configuration mode to set the proper speed for the
processor. See Section 1.15.2 for information about configuration mode.
The motherboard has three, dual inline memory module (DIMM) sockets. Minimum memory size
is 16 MB; maximum memory size is 384 MB. The BIOS automatically detects memory type, size,
and speed.
The motherboard supports the following memory features:
x
168-pin DIMMs with gold-plated contacts
x
66 and 100 MHz (matching Host Bus speed) unbuffered SDRAM only
x
Non-ECC (64-bit) and ECC (72-bit) memory
x
3.3 V memory only
x
Single- or double-sided DIMMs in the following sizes:
DIMM SizeNon-ECC ConfigurationECC Configuration
16 MB2 Mbit x 642 Mbit x 72
32 MB4 Mbit x 644 Mbit x 72
64 MB8 Mbit x 648 Mbit x 72
128 MB16 Mbit x 6416 Mbit x 72
Memory can be installed in one, two, or three sockets. Memory size can vary between sockets.
1.6.1 SDRAM
Synchronous DRAM (SDRAM) improves memory performance through memory access that is
synchronous with the memory clock. This simplifies the timing design and increases memory
speed because all timing is dependent on the number of memory clock cycles.
NOTE
✏
All memory components and DIMMs used with the JN440BX motherboard must comply with the
PC SDRAM Specifications. These include: the PC SDRAM Specification (memory component
specific), the PC unbuffered SDRAM Specifications, and the PC Serial Presence Detect
Specification. Customers can access these document through the Internet at:
http://www.intel.com/design/pcisets/memory
See Section 6.2 for information about these specifications.
14
Motherboard Description
1.6.2 ECC Memory
Error checking and correcting (ECC) memory detects multiple-bit errors and corrects single-bit
errors. When ECC memory is installed, the BIOS supports both ECC and non-ECC mode. ECC
mode is enabled in the Setup program. The BIOS automatically detects if ECC memory is
installed and provides the Setup option for selecting ECC mode. If non-ECC memory is installed,
the Setup option for ECC mode does not appear.
The following table describes the effect of using Setup to put each memory type in each supported
mode. Whenever ECC mode is selected in Setup, some performance loss occurs.
Memory Error Detection Mode Established in Setup Program
ECC DisabledECC Enabled
The Intel 440BX AGPset includes a Host-PCI bridge integrated with both an optimized DRAM
controller and an Accelerated Graphics Port (A.G.P.) interface. The I/O subsystem of the 440BX
is based on the PIIX4E, which is a highly integrated PCI-ISA/IDE Accelerator Bridge. This
®
chipset consists of the Intel
PCI/ISA IDE Xccelerator (PIIX4E) bridge chip.
1.7.1 Intel® 82443BX PCI/A.G.P. Controller (PAC)
The PAC provides bus-control signals, address paths, and data paths for transfers between the
processor’s host bus, PCI bus, the A.G.P., and main memory. The PAC features:
x
Processor interface control
Support for processor host bus frequencies of 100 MHz or 66 MHz
32-bit addressing
Desktop Optimized GTL+ compliant host bus interface
x
Integrated DRAM controller, with support for:
+3.3 V only DIMM DRAM configurations
Up to three double sided DIMMs
Synchronous 100-MHz or 66-MHz SDRAM
DIMM serial presence detect via SMBus interface
16- and 64-Mbit devices with 2 K, 4 K, and 8 K page sizes
4, x 8, x 16, and x 32 DRAM widths
x
SDRAM 64-bit data interface with ECC support
Symmetrical and asymmetrical DRAM addressing
x
A.G.P. interface
Complies with the A.G.P. specification (see Section 6.2 for specification information)
Support for +3.3 V A.G.P. 66/133 devices
Synchronous coupling to the host-bus frequency
x
PCI bus interface
Complies with the PCI specification, +5 V 33 MHz interface (see Section 6.2 for
specification information)
Asynchronous coupling to the host-bus frequency
PCI parity generation support
Data streaming support from PCI-to-DRAM
Support for four PCI bus masters in addition to the host and PCI-to-ISA I/O bridge
Support for concurrent host, A.G.P., and PCI transactions to main memory
82443BX PCI/A.G.P. controller (PAC) and the Intel® 82371EB
16
x
Data buffering
DRAM write buffer with read-around-write capability
Dedicated host-to-DRAM, PCI0-to-DRAM, and PCI1/A.G.P.-to-DRAM read buffers
A.G.P. dedicated inbound/outbound FIFOs (133/66 MHz), used for temporary data storage
x
Power management functions
Support for system suspend/resume (DRAM and power-on suspend)
Compliant with ACPI power management
x
SMBus support for desktop management functions
x
Support for system management mode (SMM)
1.7.2 Intel® 82371EB PCI ISA IDE Xcelerator (PIIX4E)
The PIIX4E is a multifunction PCI device implementing the PCI-to-ISA bridge, PCI IDE
functionality, Universal Serial Bus (USB) host/hub functionality, and enhanced power
management. The PIIX4E features:
x
Multifunction PCI-to-ISA bridge
Support for the PCI bus at 33 MHz
Complies with the PCI specification (see Section 6.2 for specification information)
Full ISA bus support
x
USB controller
Two USB ports (see Section 6.2 for specification information)
Support for legacy keyboard and mouse
Support for UHCI interface
x
Integrated dual-channel enhanced IDE interface
Support for up to four IDE devices
PIO Mode 4 transfers at up to 16 MB/sec
Support for Ultra DMA/33 synchronous DMA mode transfers up to 33 MB/sec
Bus master mode with an 8 x 32-bit buffer for bus master PCI IDE burst transfers
x
Enhanced DMA controller
Two 8237-based DMA controllers
Support for PCI DMA with three PC/PCI channels and distributed DMA protocols
Fast type-F DMA for reduced PCI bus usage
x
Interrupt controller based on 82C59
Support for 15 interrupts
Programmable for edge/level sensitivity
x
Power management logic
Sleep/resume logic
†
Support for wake on modem and Wake on LAN
Support for ACPI (see Section 6.2 for specification information)
The Accelerated Graphics Port (A.G.P.) is a high-performance interconnect for graphic-intensive
applications, such as 3D applications. A.G.P. is independent of the PCI bus and is intended for
exclusive use with graphical-display devices. A.G.P. provides these performance features:
x
Pipelined-memory read and write operations that hide memory access latency
x
Demultiplexing of address and data on the bus for near 100 percent bus efficiency
x
AC timing for 133 MHz data transfer rates, allowing data throughput of 500 MB/sec
A.G.P. complies with the 66 MHz PCI specification. See Section 6.2 for information about the
A.G.P. and PCI specifications.
NOTE
✏
Only half-length NLX A.G.P. cards are supported.
1.7.4 Universal Serial Bus (USB)
The motherboard can support two‡ USB ports; however, it is shipped with only one port installed.
The second port must be supported through the NLX riser. If you need to connect more than one
USB device, you can connect an external hub to the USB port. The motherboard fully supports the
universal host controller interface (UHCI) and uses UHCI-compatible software drivers. See
Section 6.2 for information about the USB specification. USB features include:
x
Self-identifying peripherals that can be plugged in while the computer is running
x
Automatic mapping of function to driver and configuration
x
Supports isochronous and asynchronous transfer types over the same set of wires
x
Bandwidth and low latencies appropriate for telephony, audio, and other applications
x
Error-handling and fault-recovery mechanisms built into the protocol
NOTE
✏
Computer systems that have an unshielded cable attached to a USB port may not meet FCC
Class B or other regulatory EMI requirements, even if no device or a low-speed USB device is
attached to the cable. Use shielded cable that meets the requirements for full-speed devices.
18
Motherboard Description
1.7.5 IDE Support
The motherboard has two independent bus-mastering capable PCI IDE interfaces. These interfaces
support PIO Mode 3, PIO Mode 4, ATAPI devices (such as CD-ROM), and Ultra DMA/33
synchronous-DMA mode transfers. The BIOS supports logical block addressing (LBA) and
extended cylinder head sector (ECHS) translation modes. The BIOS automatically detects the IDE
device transfer rate.
The motherboard also supports laser servo (LS-120) drives. LS-120 technology allows the user to
perform read/write operations to LS-120 (120 MB) and conventional 1.44 MB and 720 KB
diskettes. LS-120 drives are ATAPI-compatible and connect to the motherboard's IDE interface.
†
Some versions of Windows 95 and Windows NT
a bootable device in both 120 MB and 1.44 MB mode.
Connection of an LS-120 drive and a standard 3.5-inch diskette drive is allowed. The LS-120
drive can be configured as a boot device if selected in the Setup program.
Bus master IDE drivers are available from Intel at the following web location:
http://developer.intel.com/design/pcisets/busmastr/
operating systems recognize the LS-120 drive as
1.7.6 Real-Time Clock, CMOS SRAM, and Battery
The real-time clock is compatible with DS1287 and MC146818 components. The clock provides a
time-of-day clock and a multicentury calendar with alarm features and century rollover. The realtime clock supports 256 bytes of battery-backed SRAM in two banks that are reserved for BIOS
use.
The time, date, and SRAM values can be specified in the Setup program. The SRAM values can
be returned to their defaults by using the Setup program.
An external coin-cell battery powers the real-time clock and SRAM. When the computer is not
plugged into a wall socket, the battery has an estimated life of three years. When the computer is
plugged in, the 5 V standby current from the power supply extends the life of the battery. The
clock is accurate to r 13 minutes/year at 25 ºC with 5 V applied.
NOTE
✏
The recommended method of accessing the date in systems with Intel motherboards is indirectly
from the Real Time Clock (RTC) via the BIOS. The BIOS on Intel motherboards and baseboards
contains a century checking and maintenance feature that checks the least two significant digits of
the year stored in the RTC during each BIOS request (INT 1Ah) to read the date and, if less
than 80 (i.e., 1980 is the first year supported by the PC), updates the century byte to 20. This
feature enables operating systems and applications using the BIOS date/time services to reliably
manipulate the year as a four-digit value.
For more information on proper date access in systems with Intel motherboards please see
The motherboard uses the SMC FDC37C777 I/O controller which features:
x
5 Volt operation
x
ISA Plug-and-Play compatible register set
x
Two serial ports or one serial port and one infrared port
x
Single diskette drive interface
x
FIFO support on both serial and diskette interfaces
x
One parallel port with ECP and EPP support
†
xx
The Setup program provides configuration options for the I/O controller.
style mouse and keyboard interfaces
PS/2
Intelligent auto power management, including:
Shadowed write-only registers for ACPI compliance
Programmable wake-up event interface
1.8.1 Keyboard and Mouse Interface
‡
PS/2 keyboard and mouse connectors are located on the back panel of the motherboard. The +5 V
†
lines to these connectors are protected with a PolySwitch
reestablishes the connection after an over-current condition is removed. While this device
eliminates the possibility of having to replace a fuse, power to the computer should be turned off
before connecting or disconnecting a keyboard or mouse.
NOTE
✏
You can plug a mouse or keyboard into either connector.
The keyboard controller contains code which provides the traditional keyboard and mouse control
functions, and also supports Power On/Reset password protection. A Power On/Reset password
can be specified in the Setup program.
The controller supports the <Ctrl><Alt><Del> key sequence to reset the computer’s software by
jumping to the beginning of the BIOS code and running the Power-On Self Test (POST).
circuit that, like a self-healing fuse,
1.8.2 Parallel Port
The connector for the multimode bi-directional parallel port is a 25-pin D-Sub connector located
on the back panel of the motherboard. In the Setup program, there are four options for parallel
port operation:
x
Compatible (standard mode)
x
Bi-directional (PS/2 compatible)
x
Bi-directional Enhanced Parallel Port (EPP). A driver from the peripheral manufacturer is
required for operation. See Section 6.2 for EPP compatibility
x
Bi-directional high-speed Extended Capabilities Port (ECP)
20
Motherboard Description
1.8.3 Diskette Drive Controller
The I/O controller is software compatible with the 82077 diskette drive controller. The diskette
drive connector is located on the riser card. In the Setup program, the interface can be configured
for the following drive capacities and sizes:
The motherboard has two 9-pin D-Sub serial port connectors located on the back panel. The
NS16C550-compatible UARTs allow data transfers at speeds up to 115.2 Kbits/sec using BIOS
support.
1.8.5 Optional Infrared
There is no infrared header on the motherboard; however, the edge connector does accommodate
†
infrared signals from the riser. If an IrDA
Peripheral Configuration Submenu to change the mode for Serial Port B from COM2 to infrared
applications. You will no longer be able to use Serial Port B.
connector is available on the riser, use the BIOS
1.9 Audio Subsystem
The audio subsystem consists of the following:
x
Crystal Semiconductor CS4235 audio codec
x
Back panel and onboard audio connectors
1.9.1 Crystal Semiconductor CS4235 Audio Codec
The CS4235 audio codec’s features include:
†
x
Compatibility with Sound Blaster, Sound Blaster Pro
Back panel connectors: stereo line-level output (Line-out), stereo line-level input (Line-in),
and Mic-in
x
CD-ROM audio header (Creative Labs style)
CAUTION
The LINE-OUT connector, following convention, is designed to power headphones or amplified
speakers ONLY. Do not connect passive (non-amplified) speakers to this output, as poor audio
quality and/or damage to the motherboard may occur.
1.9.3 Audio Drivers and Utilities
Audio software and utilities are available from Intel’s World Wide Web site (see Section 6.1).
Audio driver support is provided for Microsoft Windows 3.1, Microsoft Windows 95, and
Microsoft Windows NT operating systems.
22
Motherboard Description
1.10 Graphics Subsystem
The graphics subsystem features the ATI Rage† Pro Turbo 2X graphics controller. See Intel’s
World Wide Web site (see Section 6.1) for graphics drivers.
1.10.1 ATI Rage Pro Turbo 2X Graphics Controller
The ATI Rage Pro Turbo 2X Graphics Controller provides the following features:
x
Comprehensive A.G.P. support, including 1X (66 MHz) and 2X (133 MHz) fully pipelined
operation and sideband support
x
Full bus mastering support
x
Triple 8-bit palette DAC with gamma correction. Pixel rates up to 230 MHz
x
Supports DDC1 and DDC2B+ for Plug and Play monitors
†
x
Game acceleration including support for Microsoft’s DirectDraw
sprites, transparent blit, masked blit, and context chaining
x
4 KB on-chip texture cache
†
x
Direct3D
x
4 MB of 100 MHz SGRAM on the motherboard
texture lighting
: double buffering, virtual
1.10.1.1 Motion Video Acceleration
The ATI Rage Pro Turbo 2X supports motion video acceleration by providing:
Enhanced line buffer allows vertical filtering of native MPEG-2 size (720 x 480) images
x
DVD/MPEG-2 decode assist
x
Filter circuitry that eliminates video artifacts caused by displaying interlaced video on
noninterlaced displays
x
Hardware mirroring for flipping video images in video conferencing systems
x
Bidirectional bus mastering engine with planar YUV-to-packed format converter
x
YUV to RGB color space converter with support for both packed and planar YUV:
YUV 4:2:2, YUV 4:1:0, and YUV 4:2:0
RGB 32, RGB 16/15, RGB 8, and monochrome
1.10.1.2 Disabling On-Board A.G.P.
To provide an upgrade path, the on-board A.G.P. is disabled if an A.G.P. add-in card is used. Only
half-length NLX A.G.P. cards can be used with this motherboard.
The management extension hardware provides low-cost instrumentation capabilities on a chip.
The features include:
x
Integrated temperature sensor
x
Fan speed sensors
x
Power supply voltage monitoring to detect levels above or below acceptable values
£
x
Remote reset capabilities from a remote peer or server through LANDesk
Version 3.3 and service layers
Client Manager,
1.12 Onboard Networking
The onboard networking subsystem is an Ethernet† LAN interface that provides both 10Base-T and
100Base-TX connectivity. Onboard LAN can be enabled or disabled in the Setup program.
Features include:
x
32-bit direct bus mastering on the PCI bus
x
Shared memory structure in the host memory that copies data directly to/from host memory
x
10Base-T and 100Base-TX capability using a single RJ-45 connector
x
IEEE 802.3P Auto-Negotiation for the fastest available connection
x
Jumperless configuration; the LAN subsystem is completely software configurable
x
Remote wake up controller
1.12.1 Intel® 82558 LAN Controller
This device is the heart of the LAN subsystem. It provides the following functions:
x
CSMA/CD protocol engine
x
PCI compatibility
x
DMA engine for movement of commands, status, and network data across the PCI bus
x
Standard MII interface for access to IEEE 802.3P -compliant physical layer devices
24
Motherboard Description
1.12.2 Alert On LAN Component
The Alert on LAN component is a companion device to the Intel® 82558 LAN controller.
Together, these devices provide a management interface between a remote management console
(or management server) and a client system monitoring instrumentation. When an alert input is
asserted, the Alert on LAN component transmits Ethernet packets to the 82558 through an 8-bit
dedicated data path. Examples of events that can trigger alert messages to a management server
include:
x
Chassis intrusion
x
System BIOS hang (transmits POST code error)
x
LAN leash (transmits an alert that the LAN cable was disconnected)
x
Processor missing signal
x
Sensing an interrupt from the hardware monitor
1.12.3 LAN Software
The software for the LAN subsystem, including setup/diagnostic software and a readme file viewer
that lists supported drivers, is available on the Intel web site. See Section 6.1.