The JN440BX motherboard may contain design defects or errors known as errata. Characterized errata that may cause the JN440BX motherboard’s behavior to deviate from
published specifications are documented in the JN440BX Motherboard Specification Update.
699414-001
Revision History
RevisionRevision HistoryDate
-001First released versionApril 1998
This product specification applies only to standard JN440BX motherboards with BIOS identifier
4J4NB0X1
Changes to this specification will be published in the JN440BX Motherboard Specification Update
before being incorporated into a revision of this document.
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and
Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied
warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular
purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel retains the right to make changes to specifications and product descriptions at any time, without notice.
The JN440BX motherboard may contain design defects or errors known as errata which may cause the product to deviate
from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777,
Germany 44-0-1793-421-333, other Countries 708-296-9333.
†
Brand, name or trademark owned by another company.
The JN440BX motherboard is a versatile platform that offers a wide variety of features. Some of
the options, however, are implemented – at least in part – on the riser. Throughout this manual,
‡
symbol is used to indicate such an option. Because there is no standard riser, no detailed
the
description of an implementation can be given. See Section 6.1 to obtain the reference design for
the NLX riser.
Microprocessor
£
x
Single Pentium
x
66 MHz and 100 MHz host bus speeds
x
Integrated 512 KB or 1 MB of second level cache
x
Slot 1 connector
NOTE
✏
Pentium II processors with 100 MHz front-side bus should be paired only with 100 MHz SDRAM.
Processors with 66 MHz front side bus can be paired with either 66 MHz or 100 MHz SDRAM.
II processor
The motherboard features:
x
NLX v1.2 form factor
x
Minimal jumper design
Main Memory
x
Three 168-pin DIMM sockets
x
Support for up to 384 MB of synchronous DRAM (SDRAM)
x
Support for 66 MHz and 100 MHz SDRAM
x
Support for ECC and non-ECC memory
Chipset and PCI/IDE Interface
®
xxxxxx
82440BX AGPset PCI/A.G.P. Controller (PAC)
Intel
Integrated PCI bus mastering controller using PIIX4E
Dual channel EIDE interface
Real-time clock
PCI Slots
Automatic detection of Host Bus speed
The motherboard is designed to fit into a standard NLX form factor chassis. Figure 3 illustrates
the mechanical form factor for the motherboard. Location of the I/O connectors, riser slot, and
mounting holes are in strict compliance with the NLX specification (see Section 6.2). Dimensions
are given in inches.
The back panel I/O shield for the JN440BX motherboard must meet specific dimensional and
material requirements. Systems based on this motherboard need the back panel I/O shield in order
to pass emission certification testing. Figure 4 shows the critical dimensions of the I/O shield, and
indicates the position of each cutout. Dimensions are given in inches.
7.458
3.1461.6530.507
1.080
0.009.00
2.479
5.728
8.1826.7504.706
NLX Motherboard Shield
Figure 4. Back Panel I/O Shield Dimensions
OM07100
12
Motherboard Description
1.5 Microprocessor
The motherboard supports a single Pentium II processor. The processor’s VID pins automatically
program the motherboard’s voltage regulator to the required processor voltage. In addition, the
host bus speeds (66 MHz and 100 MHz) is automatically selected. The motherboard supports all
current processor speeds, voltages, and bus frequencies.
1.5.1 Microprocessor Packaging
The processor is packaged in a Single Edge Contact (S.E.C.) cartridge. The S.E.C. cartridge
includes the processor core, the second-level cache, a thermal plate, and a back cover.
The processor connects to the motherboard through the Slot 1 processor connector, a 242-pin edge
connector. When the processor is mounted in Slot 1, it is secured by a retention mechanism
attached to the motherboard. The processor’s heatsink is stabilized by a heatsink support that is
attached to the motherboard.
1.5.2 Second-Level Cache
The second-level cache is located on the substrate of the S.E.C. cartridge. The cache includes
pipelined burst synchronous static RAM (PBSRAM) and tag RAM. There can be two or four
PBSRAM components totaling 512 KB or 1024 KB in size. All supported onboard memory can be
cached.
1.5.3 Microprocessor Upgrades
The motherboard can be upgraded with Pentium II processors that run at higher processor speeds.
After upgrading the processor, use the BIOS configuration mode to set the proper speed for the
processor. See Section 1.15.2 for information about configuration mode.
The motherboard has three, dual inline memory module (DIMM) sockets. Minimum memory size
is 16 MB; maximum memory size is 384 MB. The BIOS automatically detects memory type, size,
and speed.
The motherboard supports the following memory features:
x
168-pin DIMMs with gold-plated contacts
x
66 and 100 MHz (matching Host Bus speed) unbuffered SDRAM only
x
Non-ECC (64-bit) and ECC (72-bit) memory
x
3.3 V memory only
x
Single- or double-sided DIMMs in the following sizes:
DIMM SizeNon-ECC ConfigurationECC Configuration
16 MB2 Mbit x 642 Mbit x 72
32 MB4 Mbit x 644 Mbit x 72
64 MB8 Mbit x 648 Mbit x 72
128 MB16 Mbit x 6416 Mbit x 72
Memory can be installed in one, two, or three sockets. Memory size can vary between sockets.
1.6.1 SDRAM
Synchronous DRAM (SDRAM) improves memory performance through memory access that is
synchronous with the memory clock. This simplifies the timing design and increases memory
speed because all timing is dependent on the number of memory clock cycles.
NOTE
✏
All memory components and DIMMs used with the JN440BX motherboard must comply with the
PC SDRAM Specifications. These include: the PC SDRAM Specification (memory component
specific), the PC unbuffered SDRAM Specifications, and the PC Serial Presence Detect
Specification. Customers can access these document through the Internet at:
http://www.intel.com/design/pcisets/memory
See Section 6.2 for information about these specifications.
14
Motherboard Description
1.6.2 ECC Memory
Error checking and correcting (ECC) memory detects multiple-bit errors and corrects single-bit
errors. When ECC memory is installed, the BIOS supports both ECC and non-ECC mode. ECC
mode is enabled in the Setup program. The BIOS automatically detects if ECC memory is
installed and provides the Setup option for selecting ECC mode. If non-ECC memory is installed,
the Setup option for ECC mode does not appear.
The following table describes the effect of using Setup to put each memory type in each supported
mode. Whenever ECC mode is selected in Setup, some performance loss occurs.
Memory Error Detection Mode Established in Setup Program
ECC DisabledECC Enabled
The Intel 440BX AGPset includes a Host-PCI bridge integrated with both an optimized DRAM
controller and an Accelerated Graphics Port (A.G.P.) interface. The I/O subsystem of the 440BX
is based on the PIIX4E, which is a highly integrated PCI-ISA/IDE Accelerator Bridge. This
®
chipset consists of the Intel
PCI/ISA IDE Xccelerator (PIIX4E) bridge chip.
1.7.1 Intel® 82443BX PCI/A.G.P. Controller (PAC)
The PAC provides bus-control signals, address paths, and data paths for transfers between the
processor’s host bus, PCI bus, the A.G.P., and main memory. The PAC features:
x
Processor interface control
Support for processor host bus frequencies of 100 MHz or 66 MHz
32-bit addressing
Desktop Optimized GTL+ compliant host bus interface
x
Integrated DRAM controller, with support for:
+3.3 V only DIMM DRAM configurations
Up to three double sided DIMMs
Synchronous 100-MHz or 66-MHz SDRAM
DIMM serial presence detect via SMBus interface
16- and 64-Mbit devices with 2 K, 4 K, and 8 K page sizes
4, x 8, x 16, and x 32 DRAM widths
x
SDRAM 64-bit data interface with ECC support
Symmetrical and asymmetrical DRAM addressing
x
A.G.P. interface
Complies with the A.G.P. specification (see Section 6.2 for specification information)
Support for +3.3 V A.G.P. 66/133 devices
Synchronous coupling to the host-bus frequency
x
PCI bus interface
Complies with the PCI specification, +5 V 33 MHz interface (see Section 6.2 for
specification information)
Asynchronous coupling to the host-bus frequency
PCI parity generation support
Data streaming support from PCI-to-DRAM
Support for four PCI bus masters in addition to the host and PCI-to-ISA I/O bridge
Support for concurrent host, A.G.P., and PCI transactions to main memory
82443BX PCI/A.G.P. controller (PAC) and the Intel® 82371EB
16
x
Data buffering
DRAM write buffer with read-around-write capability
Dedicated host-to-DRAM, PCI0-to-DRAM, and PCI1/A.G.P.-to-DRAM read buffers
A.G.P. dedicated inbound/outbound FIFOs (133/66 MHz), used for temporary data storage
x
Power management functions
Support for system suspend/resume (DRAM and power-on suspend)
Compliant with ACPI power management
x
SMBus support for desktop management functions
x
Support for system management mode (SMM)
1.7.2 Intel® 82371EB PCI ISA IDE Xcelerator (PIIX4E)
The PIIX4E is a multifunction PCI device implementing the PCI-to-ISA bridge, PCI IDE
functionality, Universal Serial Bus (USB) host/hub functionality, and enhanced power
management. The PIIX4E features:
x
Multifunction PCI-to-ISA bridge
Support for the PCI bus at 33 MHz
Complies with the PCI specification (see Section 6.2 for specification information)
Full ISA bus support
x
USB controller
Two USB ports (see Section 6.2 for specification information)
Support for legacy keyboard and mouse
Support for UHCI interface
x
Integrated dual-channel enhanced IDE interface
Support for up to four IDE devices
PIO Mode 4 transfers at up to 16 MB/sec
Support for Ultra DMA/33 synchronous DMA mode transfers up to 33 MB/sec
Bus master mode with an 8 x 32-bit buffer for bus master PCI IDE burst transfers
x
Enhanced DMA controller
Two 8237-based DMA controllers
Support for PCI DMA with three PC/PCI channels and distributed DMA protocols
Fast type-F DMA for reduced PCI bus usage
x
Interrupt controller based on 82C59
Support for 15 interrupts
Programmable for edge/level sensitivity
x
Power management logic
Sleep/resume logic
†
Support for wake on modem and Wake on LAN
Support for ACPI (see Section 6.2 for specification information)
The Accelerated Graphics Port (A.G.P.) is a high-performance interconnect for graphic-intensive
applications, such as 3D applications. A.G.P. is independent of the PCI bus and is intended for
exclusive use with graphical-display devices. A.G.P. provides these performance features:
x
Pipelined-memory read and write operations that hide memory access latency
x
Demultiplexing of address and data on the bus for near 100 percent bus efficiency
x
AC timing for 133 MHz data transfer rates, allowing data throughput of 500 MB/sec
A.G.P. complies with the 66 MHz PCI specification. See Section 6.2 for information about the
A.G.P. and PCI specifications.
NOTE
✏
Only half-length NLX A.G.P. cards are supported.
1.7.4 Universal Serial Bus (USB)
The motherboard can support two‡ USB ports; however, it is shipped with only one port installed.
The second port must be supported through the NLX riser. If you need to connect more than one
USB device, you can connect an external hub to the USB port. The motherboard fully supports the
universal host controller interface (UHCI) and uses UHCI-compatible software drivers. See
Section 6.2 for information about the USB specification. USB features include:
x
Self-identifying peripherals that can be plugged in while the computer is running
x
Automatic mapping of function to driver and configuration
x
Supports isochronous and asynchronous transfer types over the same set of wires
x
Bandwidth and low latencies appropriate for telephony, audio, and other applications
x
Error-handling and fault-recovery mechanisms built into the protocol
NOTE
✏
Computer systems that have an unshielded cable attached to a USB port may not meet FCC
Class B or other regulatory EMI requirements, even if no device or a low-speed USB device is
attached to the cable. Use shielded cable that meets the requirements for full-speed devices.
18
Motherboard Description
1.7.5 IDE Support
The motherboard has two independent bus-mastering capable PCI IDE interfaces. These interfaces
support PIO Mode 3, PIO Mode 4, ATAPI devices (such as CD-ROM), and Ultra DMA/33
synchronous-DMA mode transfers. The BIOS supports logical block addressing (LBA) and
extended cylinder head sector (ECHS) translation modes. The BIOS automatically detects the IDE
device transfer rate.
The motherboard also supports laser servo (LS-120) drives. LS-120 technology allows the user to
perform read/write operations to LS-120 (120 MB) and conventional 1.44 MB and 720 KB
diskettes. LS-120 drives are ATAPI-compatible and connect to the motherboard's IDE interface.
†
Some versions of Windows 95 and Windows NT
a bootable device in both 120 MB and 1.44 MB mode.
Connection of an LS-120 drive and a standard 3.5-inch diskette drive is allowed. The LS-120
drive can be configured as a boot device if selected in the Setup program.
Bus master IDE drivers are available from Intel at the following web location:
http://developer.intel.com/design/pcisets/busmastr/
operating systems recognize the LS-120 drive as
1.7.6 Real-Time Clock, CMOS SRAM, and Battery
The real-time clock is compatible with DS1287 and MC146818 components. The clock provides a
time-of-day clock and a multicentury calendar with alarm features and century rollover. The realtime clock supports 256 bytes of battery-backed SRAM in two banks that are reserved for BIOS
use.
The time, date, and SRAM values can be specified in the Setup program. The SRAM values can
be returned to their defaults by using the Setup program.
An external coin-cell battery powers the real-time clock and SRAM. When the computer is not
plugged into a wall socket, the battery has an estimated life of three years. When the computer is
plugged in, the 5 V standby current from the power supply extends the life of the battery. The
clock is accurate to r 13 minutes/year at 25 ºC with 5 V applied.
NOTE
✏
The recommended method of accessing the date in systems with Intel motherboards is indirectly
from the Real Time Clock (RTC) via the BIOS. The BIOS on Intel motherboards and baseboards
contains a century checking and maintenance feature that checks the least two significant digits of
the year stored in the RTC during each BIOS request (INT 1Ah) to read the date and, if less
than 80 (i.e., 1980 is the first year supported by the PC), updates the century byte to 20. This
feature enables operating systems and applications using the BIOS date/time services to reliably
manipulate the year as a four-digit value.
For more information on proper date access in systems with Intel motherboards please see
The motherboard uses the SMC FDC37C777 I/O controller which features:
x
5 Volt operation
x
ISA Plug-and-Play compatible register set
x
Two serial ports or one serial port and one infrared port
x
Single diskette drive interface
x
FIFO support on both serial and diskette interfaces
x
One parallel port with ECP and EPP support
†
xx
The Setup program provides configuration options for the I/O controller.
style mouse and keyboard interfaces
PS/2
Intelligent auto power management, including:
Shadowed write-only registers for ACPI compliance
Programmable wake-up event interface
1.8.1 Keyboard and Mouse Interface
‡
PS/2 keyboard and mouse connectors are located on the back panel of the motherboard. The +5 V
†
lines to these connectors are protected with a PolySwitch
reestablishes the connection after an over-current condition is removed. While this device
eliminates the possibility of having to replace a fuse, power to the computer should be turned off
before connecting or disconnecting a keyboard or mouse.
NOTE
✏
You can plug a mouse or keyboard into either connector.
The keyboard controller contains code which provides the traditional keyboard and mouse control
functions, and also supports Power On/Reset password protection. A Power On/Reset password
can be specified in the Setup program.
The controller supports the <Ctrl><Alt><Del> key sequence to reset the computer’s software by
jumping to the beginning of the BIOS code and running the Power-On Self Test (POST).
circuit that, like a self-healing fuse,
1.8.2 Parallel Port
The connector for the multimode bi-directional parallel port is a 25-pin D-Sub connector located
on the back panel of the motherboard. In the Setup program, there are four options for parallel
port operation:
x
Compatible (standard mode)
x
Bi-directional (PS/2 compatible)
x
Bi-directional Enhanced Parallel Port (EPP). A driver from the peripheral manufacturer is
required for operation. See Section 6.2 for EPP compatibility
x
Bi-directional high-speed Extended Capabilities Port (ECP)
20
Motherboard Description
1.8.3 Diskette Drive Controller
The I/O controller is software compatible with the 82077 diskette drive controller. The diskette
drive connector is located on the riser card. In the Setup program, the interface can be configured
for the following drive capacities and sizes:
The motherboard has two 9-pin D-Sub serial port connectors located on the back panel. The
NS16C550-compatible UARTs allow data transfers at speeds up to 115.2 Kbits/sec using BIOS
support.
1.8.5 Optional Infrared
There is no infrared header on the motherboard; however, the edge connector does accommodate
†
infrared signals from the riser. If an IrDA
Peripheral Configuration Submenu to change the mode for Serial Port B from COM2 to infrared
applications. You will no longer be able to use Serial Port B.
connector is available on the riser, use the BIOS
1.9 Audio Subsystem
The audio subsystem consists of the following:
x
Crystal Semiconductor CS4235 audio codec
x
Back panel and onboard audio connectors
1.9.1 Crystal Semiconductor CS4235 Audio Codec
The CS4235 audio codec’s features include:
†
x
Compatibility with Sound Blaster, Sound Blaster Pro
Back panel connectors: stereo line-level output (Line-out), stereo line-level input (Line-in),
and Mic-in
x
CD-ROM audio header (Creative Labs style)
CAUTION
The LINE-OUT connector, following convention, is designed to power headphones or amplified
speakers ONLY. Do not connect passive (non-amplified) speakers to this output, as poor audio
quality and/or damage to the motherboard may occur.
1.9.3 Audio Drivers and Utilities
Audio software and utilities are available from Intel’s World Wide Web site (see Section 6.1).
Audio driver support is provided for Microsoft Windows 3.1, Microsoft Windows 95, and
Microsoft Windows NT operating systems.
22
Motherboard Description
1.10 Graphics Subsystem
The graphics subsystem features the ATI Rage† Pro Turbo 2X graphics controller. See Intel’s
World Wide Web site (see Section 6.1) for graphics drivers.
1.10.1 ATI Rage Pro Turbo 2X Graphics Controller
The ATI Rage Pro Turbo 2X Graphics Controller provides the following features:
x
Comprehensive A.G.P. support, including 1X (66 MHz) and 2X (133 MHz) fully pipelined
operation and sideband support
x
Full bus mastering support
x
Triple 8-bit palette DAC with gamma correction. Pixel rates up to 230 MHz
x
Supports DDC1 and DDC2B+ for Plug and Play monitors
†
x
Game acceleration including support for Microsoft’s DirectDraw
sprites, transparent blit, masked blit, and context chaining
x
4 KB on-chip texture cache
†
x
Direct3D
x
4 MB of 100 MHz SGRAM on the motherboard
texture lighting
: double buffering, virtual
1.10.1.1 Motion Video Acceleration
The ATI Rage Pro Turbo 2X supports motion video acceleration by providing:
Enhanced line buffer allows vertical filtering of native MPEG-2 size (720 x 480) images
x
DVD/MPEG-2 decode assist
x
Filter circuitry that eliminates video artifacts caused by displaying interlaced video on
noninterlaced displays
x
Hardware mirroring for flipping video images in video conferencing systems
x
Bidirectional bus mastering engine with planar YUV-to-packed format converter
x
YUV to RGB color space converter with support for both packed and planar YUV:
YUV 4:2:2, YUV 4:1:0, and YUV 4:2:0
RGB 32, RGB 16/15, RGB 8, and monochrome
1.10.1.2 Disabling On-Board A.G.P.
To provide an upgrade path, the on-board A.G.P. is disabled if an A.G.P. add-in card is used. Only
half-length NLX A.G.P. cards can be used with this motherboard.
The management extension hardware provides low-cost instrumentation capabilities on a chip.
The features include:
x
Integrated temperature sensor
x
Fan speed sensors
x
Power supply voltage monitoring to detect levels above or below acceptable values
£
x
Remote reset capabilities from a remote peer or server through LANDesk
Version 3.3 and service layers
Client Manager,
1.12 Onboard Networking
The onboard networking subsystem is an Ethernet† LAN interface that provides both 10Base-T and
100Base-TX connectivity. Onboard LAN can be enabled or disabled in the Setup program.
Features include:
x
32-bit direct bus mastering on the PCI bus
x
Shared memory structure in the host memory that copies data directly to/from host memory
x
10Base-T and 100Base-TX capability using a single RJ-45 connector
x
IEEE 802.3P Auto-Negotiation for the fastest available connection
x
Jumperless configuration; the LAN subsystem is completely software configurable
x
Remote wake up controller
1.12.1 Intel® 82558 LAN Controller
This device is the heart of the LAN subsystem. It provides the following functions:
x
CSMA/CD protocol engine
x
PCI compatibility
x
DMA engine for movement of commands, status, and network data across the PCI bus
x
Standard MII interface for access to IEEE 802.3P -compliant physical layer devices
24
Motherboard Description
1.12.2 Alert On LAN Component
The Alert on LAN component is a companion device to the Intel® 82558 LAN controller.
Together, these devices provide a management interface between a remote management console
(or management server) and a client system monitoring instrumentation. When an alert input is
asserted, the Alert on LAN component transmits Ethernet packets to the 82558 through an 8-bit
dedicated data path. Examples of events that can trigger alert messages to a management server
include:
x
Chassis intrusion
x
System BIOS hang (transmits POST code error)
x
LAN leash (transmits an alert that the LAN cable was disconnected)
x
Processor missing signal
x
Sensing an interrupt from the hardware monitor
1.12.3 LAN Software
The software for the LAN subsystem, including setup/diagnostic software and a readme file viewer
that lists supported drivers, is available on the Intel web site. See Section 6.1.
1+5VOFused +5V
2USB_D-I/O3.3V differential USB signal D3USB_D+I/O3.3V differential USB signal D+
4GND-Ground
Table 9.Serial Port A and B Connectors (J3P1 and J5P1)
PinSignalI/ODescription
1DCDICarrier Detect
2SINISerial Data In
3SOUTOSerial Data Out
4DTROData Terminal Ready
5GND-Ground
6DSRIData Set Ready
7RTSORequest to Send
8CTSIClear to Send
9RIIRing Indicator
Table 10.Keyboard/Mouse Connectors (J4P1)
PinSignalI/ODescription
1DATAI/OKeyboard/mouse data signal
2Not connected-Not connected
3GND-Ground
4+5VOFused +5V power
5CLOCKI/OKeyboard/mouse clock signal
6Not connected-Not connected
1REDIAnalog RED
2GREENIAnalog GREEN
3BLUEIAnalog BLUE
4Not connected-Not connected
5GND-Return for RED
6GND-Return for GREEN
7GND-Return for BLUE
8GND9FUSED_+5VOFused +5V
10GND11Not connected-Not connected
12DDC_DATI/O DDC Data signal / MON_ID1
13HSYNCOHorizontal Sync signal
14VSYNCOVertical Sync signal
15DDC_CLKI/O DDC clock signal / MON_ID2
Figure 7 shows the location of the configuration jumper block on the motherboard. Table 13
summarizes the settings.
Config
Select
3
1
J5G1
OM07093
Figure 7. Configuration Jumper Block
Table 13.Configuration Jumper Settings (J5G1)
FunctionJumperConfiguration
Normal1-2The BIOS uses current configuration information and passwords for booting.
Configure2-3After the POST runs, Setup is run automatically, using BIOS defaults. The
maintenance menu is displayed.
RecoverynoneThe BIOS attempts to recover the BIOS configuration. A recovery diskette
is required.
CAUTION
Moving the jumper with the power on can damage your computer. Always turn off the power and
unplug the power cord from the computer before changing the jumper.
32
Motherboard Description
1.15.1 Normal Mode
This mode is for normal computer booting and operations. To enable this mode, pins 1 and 2 must
be connected on the configuration jumper (J5G1). Access to the Setup program can be restricted
using a supervisor or user password.
1.15.2 Configuration Mode
This mode is for configuring special BIOS settings, including processor speed and special
maintenance options. This mode is used when upgrading the BIOS, upgrading the processor, or
clearing the passwords. To enable this mode, pins 2 and 3 must be connected on the configuration
jumper (J5G1). In this mode, Setup automatically executes after the POST runs. No password is
required, and this mode overrides any passwords that are set. The Maintenance menu is the first
menu displayed. This menu provides options for setting the processor speed and clearing
passwords. User and supervisor settings are preserved and used when the computer is rebooted.
For the configuration changes to take effect after exiting the Setup program, power down the
computer, set the configuration jumper to normal mode (see Section 1.15.1), and boot the
computer.
1.15.3 Recovery Mode
This mode is for recovering BIOS data. To enable this mode, no pins are connected on the
configuration jumper (J5G1). After the computer is powered-on, the BIOS attempts to upgrade or
recover the BIOS data from a diskette in the drive. If a diskette is not in the boot drive, the BIOS
runs the POST, does not boot the operating system, and sounds a 4 - 4 - 2 - 4 beep code.
Continuos beeps indicate failed recovery attempt. For a full list of beep codes please refer to
Section 5.3.
For the configuration changes to take effect after a successful recovery, power down the computer,
set the configuration jumper to normal mode (see Section 1.15.1), and boot the computer.
The NLX riser connector on the motherboard consists of a 340 (2 x 170) position and a
supplemental 26 (2 x 13) position gold finger contact. All edge connector pin definitions are
defined in the NLX specification, version 1.2.
According to the NLX specification, the motherboard edge connector provides the following:
x
PCI signals (the motherboard supports up to four PCI devices)
x
ISA signals
x
Two IDE channels
x
One diskette drive interface
x
Infrared signals
x
Miscellaneous front panel signals
x
Power connection for the motherboard
See Section 6.2 for information about the NLX Specification.
Table 14, Table 15, and Table 16 specify the pinouts located on the primary connector; Table 17
specifies the pinouts located on the supplemental connector. All edge connector pin definitions are
defined in the NLX specification, version 1.2.
X5FP_SPKR_EN **AUDIOIThis signal indicates if headphones have
been plugged into the front panel LINE-OUT
jack. The signal is connected to one of the
wipers on the audio jack and is HIGH when
the headphones are plugged into the front
audio jack and LOW when they are not. The
signal is pulled high through a pull-up on the
motherboard (Typically 100K).
X6VOL_DN# **AUDIOIConnects to Volume Down switch on front
panel, appropriate pull-up resistor on
motherboard. The motherboard provides
debounce protection and a pull-up resistor.
X7GNDPWRNAGroundNA
X8SMI# **SYSISystem Management Interrupt that is an input
to the motherboard.
X9RESERVEDRESNAReservedNA
X10RESERVEDRESNAReservedNA
X11RESERVEDRESNAReservedNA
X12AGNDPWRNALow pass filtered ground for audio circuitry on
the riser.
X13MODEM_MICAUDIOOPre-amplified microphone mono output signal
Table 17.Signals, NLX Riser with Supplemental Connector
PinSignal NameTypeI/O *DescriptionSignal Type
Y5FP_MIC_EN **AUDIOIThis signal indicates if a microphone has
been plugged into the front panel MIC_IN
jack. The signal is connected to a wiper on
the MIC_IN jack and is LOW when the
microphone is plugged in and HIGH when it
is not. The signal is pulled LOW through a
pull down on the motherboard (Typically
100K).
Y6VOL_UP# **AUDIOIConnects to Volume Up switch on front
panel, appropriate pull-up resistor on
motherboard. The motherboard provides
debounce protection and a pull-up resistor.
Y7AC_RST# **AC’97OAC’97 master H/W reset.TTL
Y8AC_SD_IN **AC’97ISerial, time division, multiplexed, AC’97 input
stream to the motherboard from the codec on
the riser (output from the codec).
Y9GROUNDPWRNADigital (main motherboard) ground plane.NA
Y10AC_SD_OUT **AC’97OSerial, time division, multiplexed, AC’97
output from the motherboard to the codec on
the riser (input to the codec).
Y11AC_SYNC **AC’97O48 KHz fixed rate sample sync signal from
the motherboard to the codec on the riser.
Y12AC_BIT_CLK **AC’97I12.288 MHz serial data clock.TTL
Y13MODEM_SPKRAUDIOOAnalog mono output signal from telephony
device to motherboard.
*I/O column: relative to motherboard, “O” = output, from motherboard to riser; “I” = input, from riser to motherboard.
**These signals are not supported.
(continued)
TTL
TTL
TTL
TTL
TTL
Analog
1 V RMS
1.17 Reliability
The mean time between failures (MTBF) prediction is calculated using component and
subassembly random failure rates. The calculation is based on the Bellcore Reliability Prediction
Procedure, TR-NWT-000332, Issue 4, September 1991. The MTBF prediction is for estimating
repair rates and spare parts requirements.
The Mean Time Between Failures (MTBF) data is calculated from predicted data at 55 ºC.
Motherboard MTBF: 173,814 hours
81-100 lbs.18118
Vibration
Unpackaged5 Hz to 20 Hz : 0.01g² Hz sloping up to 0.02 g² Hz
20 Hz to 500 Hz : 0.02g² Hz (flat)
Packaged10 Hz to 40 Hz : 0.015g² Hz (flat)
40 Hz to 500 Hz : 0.015g² Hz sloping down to 0.00015 g² Hz
42
Motherboard Description
1.19 Power Consumption
Tables 19 and 20 list voltage and current specifications for a computer that contains the
motherboard, a 350 MHz Pentium II processor, 32 MB SDRAM, 512 KB cache, 3.5-inch diskette
drive, 2.1 GB IDE hard disk drive, and a 6X IDE CD-ROM drive. This information is provided
only as a guide for calculating approximate power usage with additional resources added.
Values for the Windows 95 desktop mode are measured at 640 x 480 x 256 colors and 60 Hz
refresh rate. AC watts are measured with a typical 145 W supply, nominal input voltage and
frequency, with true RMS wattmeter at the line input.
Table 19.DC Voltage
VoltageAcceptable ToleranceWattageCurrent
+3.3V± 5%46W=13.94A
+5V± 5%40W=8A
-5V± 5%0W=0A
+12V± 5%9W=750mA
-12V± 5%3W=250mA
5V SB (Stand By)± 5%3.6W=720mA
Table 20.Power Usage
DC (amps) at:
ModeAC (watts) +3.3 V+5 V+12 V-12 V
DOS prompt, APM disabled461.64 A3.16 A178 mA16.55 mA
Windows 95 desktop, APM disabled471.59 A3.17 A190.5 mA32.83 mA
Windows 95 desktop, APM enabled, in
System Management Mode (SMM)
291.58 A85 mA156 mA32.64 mA
For typical configurations, the motherboard is designed to operate with at least a 200 W NLX
power supply (see Section 6.2 for the specification). Use a higher wattage supply for heavily
loaded configurations. The power supply must comply with the NLX power supply
recommendations.
Table 21 shows the max DC power requirements for systems in either Sleep or Normal operating
modes. Power consumption is independent of the operating system used and other variables.
Table 21.Processor Fan DC Power Requirements (J2A1)
EMKO-TSE (74-SEC) 207/94Summary of Nordic deviations to EN 60 950. (Norway, Sweden,
The Standard for Safety of Information Technology Equipment
including Electrical Business Equipment. (USA & Canada)
The Standard for Safety of Information Technology Equipment
including Electrical Business Equipment. (European Union)
The Standard for Safety of Information Technology Equipment
including Electrical Business Equipment. (International)
Denmark & Finland)
Table 23.EMC Regulations
RegulationTitle
FCC Class BTitle 47 of the Code of Federal Regulations, Parts 2 & 15, Subpart B,
pertaining to unintentional radiators. (USA)
CISPR 22, 2nd Edition, 1993Limits and methods of measurement of Radio Interference
Characteristics of Information Technology Equipment. (International)
EN 55 022, 1995Limits and methods of measurement of Radio Interference
Characteristics of Information Technology Equipment. (Europe)
EN 50 082-1 (1992)Generic Immunity Standard; Currently compliance is determined via
testing to IEC 801-2, -3, and -4. (Europe)
VCCI Class B (ITE)Implementation Regulations for Voluntary Control of Radio Interference
by Data Processing Equipment and Electronic Office Machines. (Japan)
ICES-003, Issue 2Interference-Causing Equipment Standard, Digital Apparatus. (Canada)
1.20.1 Product Certification Markings
This motherboard has the following product certification markings:
x
European CE Marking: Consists of a marking on the board and shipping container.
x
UL Recognition Mark: Consists of the UL File No. E139761 on the component side of the
board and the PB No. on the solder side of the board. Board material flammability is 94V-1
or -0.
x
Each board will be marked with an FCC Declaration of Conformity.
x
Canadian Compliance: Consists of small c followed by a stylized backward UR on component
side of the board.
44
2 Motherboard Resources
2.1 Memory Map
Table 24.System Memory Map
Address Range (decimal) Address Range (hex)SizeDescription
1024 K - 393216 K100000 - 18000000383 MB Extended memory
1008 K - 1024 KFC000 - FFFFF16 KBBoot block
1000 K - 1008 KFA000 - FBFFF8 KBESCD (Plug and Play configuration and
996 K - 1000 KF9000 - F9FFF4 KBReserved for BIOS
992 K - 996 KF8000 - F8FFF4 KBOEM Logo or Scan User Flash
928 K - 992 KE8000 - F7FFF64 KBPOST BIOS
896 K - 928 KE0000 - E7FFF32 KBPOST BIOS (Available as UMB)
800 K - 896 KC8000 - DFFFF96 KBAvailable high DOS memory (open to ISA
640 K - 800 KA0000 - C7FFF160 KBVideo memory and BIOS
639 K - 640 K9FC00 - 9FFFF1 KBExtended BIOS data (movable by memory
512 K - 639 K80000 - 9FBFF127 KBExtended conventional memory
0 K - 512 K00000 - 7FFFF512 KBConventional memory
DMI)
and PCI bus)
manager software)
2.2 DMA Channels
Table 25.DMA Channels
DMA Channel NumberData WidthSystem Resource
08- or 16-bitsAudio
18- or 16-bitsAudio / Parallel Port
28- or 16-bitsDiskette Drive
38- or 16-bitsParallel Port (for ECP or EPP) / Audio
4Reserved - Cascade Channel
516-bitsOpen
616-bitsOpen
716-bitsOpen
NMII/O Channel Check
0Reserved, Interval Timer
1Reserved, Keyboard Buffer Full
2Reserved, Cascade Interrupt From Slave PIC
3COM2*
4COM1*
5LPT2 (Plug and Play option) / Audio / User available
6Diskette Drive
7LPT1*
8Real Time Clock
9Reserved for PIIX4E system management bus
10User available
11Windows Sound System* / User available
12Onboard Mouse Port (if present, else user available)
13Reserved, Math Coprocessor
14Primary IDE (if present, else user available)
15Secondary IDE (if present, else user available)
*Default, but can be changed to another IRQ
Function
Number (hex)Description
‡
‡
‡
‡
48
Motherboard Resources
2.6 PCI Interrupt Routing Map
This section describes interrupt sharing and how the interrupt signals are connected between the
‡
PCI expansion slots
be shared between devices attached to the PCI bus. In most cases, the small amount of latency
added by interrupt sharing does not affect the operation or throughput of the devices. In some
special cases where maximum performance is needed from a device, a PCI device should not share
an interrupt with other PCI devices. Use the following information to avoid sharing an interrupt
with a PCI add-in card.
PCI devices are categorized as follows to specify their interrupt grouping:
x
INTA: By default, all add-in cards that require only one interrupt are in this category. For
almost all cards that require more than one interrupt, the first interrupt on the card is also
classified as INTA.
x
INTB: Generally, the second interrupt on add-in cards that require two or more interrupts is
classified as INTB. (This is not an absolute requirement.)
x
INTC and INTD: Generally, a third interrupt on add-in cards is classified as INTC and a
fourth interrupt is classified as INTD.
and onboard PCI devices. The PCI specification specifies how interrupts can
The PIIX4E PCI-to-ISA bridge has four programmable interrupt request (PIRQ) input signals.
Any PCI interrupt source (either onboard or from a PCI add-in card) connects to one of these PIRQ
signals. Because there are only four signals, some PCI interrupt sources are mechanically tied
together on the motherboard and therefore share the same interrupt. Table 29 lists the PIRQ
‡
signals and shows how the signals are connected to the PCI expansion slots
For example, assume an add-in card has one interrupt (group INTD) into the second PCI slot. In
this slot, an interrupt source from group INTA connects to the PIRQD signal, which is already
connected to the onboard video and USB PCI sources. The add-in card shares an interrupt with
these onboard interrupt sources.
NOTE
✏
The PIIX4E can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 7, 11, 14, 15).
Typically, a device that does not share a PIRQ line will have a unique interrupt. However, in
certain interrupt-constrained situations, it is possible for two or more of the PIRQ lines to be
connected to the same IRQ signal.
The motherboard uses an Intel/Phoenix BIOS, which is stored in flash memory and can be
upgraded using a disk-based program. In addition to the BIOS, the flash memory contains the
Setup program, Power-On Self Test (POST), Advanced Power Management (APM) software, the
PCI auto-configuration utility, and Windows 95-ready Plug and Play. See Section 6.2 for the
supported versions of these specifications.
This motherboard supports system BIOS shadowing, allowing the BIOS to execute from 64-bit
onboard write-protected DRAM.
The BIOS displays a message during POST identifying the type of BIOS and a the revision code.
The initial production BIOS is identified as 4J4NB0X1.
3.1 BIOS Upgrades
A new version of the BIOS can be upgraded from a diskette using the Intel® Flash Memory Update
utility that is available from Intel. This utility does BIOS upgrades as follows:
x
Updates the flash BIOS from a file on a disk
x
Updates the language section of the BIOS
x
Makes sure that the upgrade BIOS matches the target system to prevent accidentally installing
a BIOS for a different type of system
BIOS upgrades and the update utility are available from Intel through the Intel World Wide Web
site. See Section 6.1 for information about this site.
NOTE
✏
Please review the instructions distributed with the update utility before attempting a BIOS
upgrade.
The Intel® E28F004S5 is a high performance 4 Mbit (512 KB) symmetrical flash memory device.
Internally, the device is grouped into eight 64-KB blocks that are individually erasable, lockable,
and unlockable. Figure 8 shows the organization of the flash memory.
Symmetrical flash memory allows both the boot and the fault tolerance blocks to increase in size
from 16 KB to 64 KB. This increase allows the addition of features such as flash memory
manager (FMM), dynamic memory detection, LS-120 recovery code, and extended security
features.
The first two 8 KB blocks of the fault tolerance area are the parameter blocks. These blocks
contain data such as microcode patches, vital product data (VPD), logo, SMBIOS interface, and
ESCD information. The backup block contains a copy of the fault tolerance block.
The 4-Mbit flash component is organized as 512 KB x 8 bits and is divided into areas as described
in Table 30. The table shows the addresses in the ROM image in normal mode.
Table 30.Flash Memory Organization
Address (Hex)SizeDescription
FFFF0000 - FFFFFFFF64 KBBoot Block
FFFA0000 - FFFEFFFF256 KBMain BIOS Block
FFF9F000 - FFF9FFFF8 KBUsed by BIOS (for Event Logging, as an example)
FFF9E000 - FFF9EFFF8 KBOEM logo or Scan Flash Area
FFF9C000 - FFF9DFFF16 KBVital Product Data (VPD) Extended System Configuration Data
(ESCD) (DMI configuration data/Plug and Play Data)
FFF90000 - FFF9BFFF96 KBFault Tolerant Storage
FFF80000 - FFF8FFFF64 KBFault Tolerant Backup Block
52
Overview of BIOS Features
3.3 Plug and Play: PCI Autoconfiguration
The BIOS automatically configures PCI devices and Plug and Play devices. PCI devices may be
onboard or add-in cards. Plug and Play devices are ISA add-in cards built to meet the Plug and
Play specification. Autoconfiguration lets a user insert or remove PCI or Plug and Play cards
without having to configure the system. When a user turns on the system after adding a PCI or
Plug and Play card, the BIOS automatically configures interrupts, the I/O space, and other system
resources. Any interrupts set to Available in Setup are considered to be available for use by the
add-in card.
PCI interrupts are distributed to available ISA interrupts that have not been assigned to an ISA
card or to system resources. The assignment of PCI interrupts to ISA IRQs is non-deterministic.
PCI devices can share an interrupt, but an ISA device cannot share an interrupt allocated to PCI or
to another ISA device. Autoconfiguration information is stored in the extended system
configuration data (ESCD) format.
For information about the versions of PCI and Plug and Play supported by this BIOS, see
Section 6.2. Copies of the specifications can be obtained from the Intel World Wide Web site (see
Section 6.1).
3.4 PCI IDE Support
If Auto is selected as a primary or secondary IDE device (see Section 4.3.2) in Setup, the BIOS
automatically sets up the two local-bus IDE connectors with independent I/O channel support. The
IDE interface supports hard disk drives up to PIO Mode 4 and recognizes any ATAPI devices,
including CD-ROM drives and tape drives (see Section 6.2 for the supported version of ATAPI).
The BIOS determines the capabilities of each drive and configures them so as to optimize capacity
and performance. To take advantage of the high-capacity storage devices, hard disk drives are
automatically configured for logical block addressing (LBA) and to PIO Mode 3 or 4, depending
on the capability of the drive. To override the autoconfiguration options, use the specific IDE
device options in Setup. The ATAPI specification recommends that ATAPI devices be configured
as shown in Table 31.
Table 31.Recommendations for Configuring an ATAPI Device
Primary CableSecondary Cable
ConfigurationDrive 0Drive 1Drive 0Drive 1
Normal, no ATAPIATA
Disk and CD-ROM for enhanced IDE systemsATAATAPI
Legacy IDE system with only one cableATAATAPI
Enhanced IDE with CD-ROM and a tape or two CD-ROMsATAATAPIATAPI
If Plug and Play operating system (see Section 4.3) is selected in Setup, the BIOS autoconfigures
only ISA Plug and Play cards that are required for booting (IPL devices). If Plug and Play
operating system is not selected in Setup, the BIOS autoconfigures all Plug and Play ISA cards.
3.6 ISA Legacy Devices
Since ISA legacy devices are not autoconfigurable, the resources for them must be reserved.
Resources can be reserved in the Setup program.
3.7 Desktop Management Interface (DMI)
Desktop Management Interface (DMI) is an interface for managing computers in an enterprise
environment. The main component of DMI is the management information format (MIF)
database, which contains information about the computing system and its components. Using
DMI, a system administrator can obtain the system types, capabilities, operational status, and
installation dates for system components. The MIF database defines the data and provides the
method for accessing this information. The BIOS enables applications such as Intel
Client Manager to use DMI. The BIOS stores and reports the following DMI information:
x
BIOS data, such as the BIOS revision level
x
Fixed-system data, such as peripherals, serial numbers, and asset tags
x
Resource data, such as memory size, cache size, and processor speed
x
Dynamic data, such as event detection and error logging
®
LANDesk
OEMs can use a utility that programs flash memory so the BIOS can report on system and chassis
information. This utility is available through Intel sales offices. See Section 6.1 for information
about contacting a local Intel sales office. See Section 6.2 for information about the latest DMI
specification.
DMI does not work directly under non-Plug and Play operating systems (for example,
Windows NT). However, the BIOS supports a DMI table interface for such operating systems.
Using this support, a DMI service-level application running on a non-Plug and Play operating
systems can access the DMI BIOS information.
54
Overview of BIOS Features
3.8 Advanced Power Management (APM)
The BIOS supports APM and standby mode. See Section 6.2 for the version of the APM
specification that is supported. The energy saving standby mode can be initiated in the following
ways:
x
Time-out period specified in Setup
x
Suspend/resume switch connected to the front panel sleep connector
x
From the operating system, such as the Suspend menu item in Windows 95
In standby mode, the motherboard reduces power consumption by using SMM capabilities,
†
spinning down hard disk drives, and reducing power to, or turning off, VESA
monitors. Power-management mode can be enabled or disabled in Setup (see Section 4).
While in standby mode, the system retains the ability to respond to external interrupts and service
requests, such as incoming faxes or network messages. Any keyboard or mouse activity brings the
system out of standby mode and immediately restores power to the monitor.
The BIOS enables APM by default; but the operating system must support an APM driver for the
power-management features to work. For example, Windows 95 supports the power-management
features upon detecting that APM is enabled in the BIOS.
DPMS-compliant
3.9 Advanced Configuration and Power Interface (ACPI)
ACPI gives the operating system direct control over the power management and Plug and Play
functions of a computer. ACPI requires an ACPI-aware operating system such as
Windows NT 5.0 or Windows 98. ACPI features include:
x
Plug and Play (including bus and device enumeration) and Advanced Power Management
(APM) functionality normally contained in the BIOS
x
Power management control of individual devices, add-in boards (some add-in boards may
require an ACPI-aware driver), video displays, and hard disk drives
x
Methods for achieving less than 30-watt system operation in the Power On Suspend sleeping
state, and less than 5-watt system operation in the Suspend to Disk sleeping state
x
A Soft-off feature that enables the operating system to power off the computer
x
Support for multiple wake up events (see Table 34)
x
Support for a front panel power and sleep mode switch. Table 32 describes the system states
based on how long the switch is pressed
Table 32. Effects of Pressing the Power Switch
…and the power switch is
If the system is in this state…
OffLess than four secondsPower on to G0 state
OnLess than four secondsPower off to G2 state
OnMore than four secondsPower off to G2 state
SleepLess than four secondsWake up to G0 state
Under ACPI, the operating system directs all system and device power state transitions. The
operating system puts devices in and out of low-power states based on user preferences and
knowledge of how devices are being used by applications. Devices that are not being used can be
turned off. The operating system uses information from applications and user settings to put the
system as a whole into a low-power state. Table 33 lists the power states supported by the
motherboard along with the associated system power targets. See the ACPI specification for a
complete description of the various system and power states.
Table 33. Power States and Targeted System Power
Global StatesSleeping StatesProcessor StatesDevice StatesTargeted System Power *
G0 - working
state
G1 - sleeping
state
G1 - sleeping
state
G1 - sleeping
state
G1 - sleeping
state
G2/S5S5 - Soft off.
G3 -mechanical
off.
The power
supply switch is
off.
*Total system power is dependent on the system configuration, including add-in boards and peripherals powered by the
system chassis’ power supply.
**Dependent on the standby power consumption of wake-up devices used in the system.
*** S3 and S4BIOS states are entered at the same time to preserve system context. In normal operation, the system
restores context from RAM. In case of power failure, the system restores context from disk.
S0 - workingC0 - workingD0 - working
state
S1 - Processor
stopped
S2 - power on
suspend
S3 - suspend to
RAM. Not
supported.
S4BIOS suspend to
disk***. Not
supported.
Context not
saved. Cold
boot is required.
No power to the
system.
C1 - stop grantD1, D2, D3-
device
specification
specific
C2 - clock
stopped
No powerD3 - no power
No powerD3 - no power
No powerD3 - no power
No powerD3 - no power
D2, D3- device
specification
specific
except for wake
up logic
except for wake
up logic
except for wake
up logic
for wake up
logic, except
when provided
by battery or
external source
Full power > 60 W
5 W < power < 30 W
5 W < power < 30 W
power < 5 W **
power < 5 W **
power < 5 W **
No power to the system so
that service can be
performed.
56
Overview of BIOS Features
3.9.2 Wake Up Devices and Events
The table below describes which devices or specific events can wake the computer from specific
states. Sleeping states S3, S4BIOS, and S5 are the same for the wake up events.
Table 34. Wake Up Devices and Events
These devices/events can
wake up the computer……from this state
In addition to power management, ACPI provides controls and information so that the operating
system can facilitate Plug and Play device enumeration and configuration. ACPI is used only to
enumerate and configure motherboard devices that do not have other hardware standards for
enumeration and configuration. PCI devices on the motherboard, for example, are not enumerated
by ACPI.
3.9.4 BIOS Support
The BIOS supports both APM and ACPI. If the board is used with an ACPI-aware operating, the
BIOS provides ACPI support. Otherwise, it defaults to APM support.
3.10 Language Support
Five languages will be available: American English, German, Italian, French, and Spanish. The
BIOS includes extensions to support the Kanji character set and other non-ASCII character sets.
Translations of other languages may become available at a later date.
The default language is American English, which is always present unless another language is
programmed into the BIOS using the flash memory update utility. See Section 3.1 for information
about the BIOS update utility.
In the Setup program, the user can choose to boot from a diskette drive, hard disk drive, CD-ROM,
or the network. The default setting is for the diskette drive to be the primary boot device and the
hard disk drive to be the secondary boot device. By default the third and fourth devices are
disabled.
Booting from CD-ROM is supported in compliance to the El Torito bootable CD-ROM format
specification. See Section 6.2 for information about the El Torito specification. Under the Boot
menu in the Setup program, CD-ROM is listed as a boot device. Boot devices are defined in
priority order. If the CD-ROM is selected as the boot device, it must be the first device.
The network can be selected as a boot device. This selection allows booting from a network add-in
card with a remote boot ROM installed.
3.12 OEM Logo or Scan Area
A 4 KB flash-memory user area at memory location FFFF8000h-FFFF8FFFh is for displaying a
custom OEM logo during POST. A utility is available from the Intel web site (see Section 6.1) to
assist with installing a logo into the flash memory. Contact Intel customer support for further
information. See Section 6.1 for information on contacting Intel customer support.
3.13 USB Legacy Support
USB legacy support enables USB keyboards and mice to be used although no operating system
drivers are in place. By default, USB legacy support is disabled. USB Legacy support is for use in
accessing BIOS Setup and the installation of a USB aware operating system only.
This sequence describes how USB legacy support operates in the default (disabled) mode.
1. When you power up the computer, USB legacy support is disabled.
2. POST begins.
3. USB legacy support is temporarily enabled by the BIOS. This allows you to use a USB
keyboard to enter the Setup program or the maintenance mode.
4. POST completes and disables USB legacy support (unless it was set to Enabled while in
Setup).
5. The operating system loads. While the operating system is loading, USB keyboards and mice
are not recognized. After the operating system loads the USB drivers, the USB devices are
recognized.
To install a USB aware operating system, enable USB Legacy support in BIOS Setup and follow
the operating system’s installation instructions. Once the operating system is installed and the
USB drivers configured, USB Legacy Support is no longer used. USB Legacy Support can be left
enabled in BIOS Setup if needed.
58
Overview of BIOS Features
Notes on using USB legacy support:
x
If USB legacy support is enabled, don't mix USB and PS/2 keyboards and mice. For example,
don't use a PS/2 keyboard with a USB mouse, or a USB keyboard and a PS/2 mouse.
x
It is not recommended to use USB devices with an operating system that does not support
USB. USB legacy does not support the use of USB devices in a non USB operating system.
x
USB legacy support is for keyboards and mice only. Hubs and other USB devices are not
supported in this special mode.
3.14 BIOS Setup Access
Access to the Setup program can be restricted using passwords. User and supervisor passwords
can be set using the Security menu in Setup. The default is no passwords enabled. See Section 4.4
for information about setting user and supervisor passwords.
3.15 Recovering BIOS Data
Some types of failure can destroy the BIOS. For example, the data can be lost if a power outage
occurs while the BIOS is being updated in flash memory. The BIOS can be recovered from a
diskette using the BIOS recovery mode (see Section 1.15.3).
To create a BIOS recovery diskette, a bootable diskette must be created and the recovery files
copied to it. The recovery files are available from Intel, contact Intel customer support for further
information. See Section 6.1 for information on contacting Intel customer support.
The Setup program is for viewing and changing the BIOS settings for a computer. Setup is
accessed by pressing the <F2> key after the Power-On Self Test (POST) memory test begins and
before the operating system boot begins.
Table 35 shows the menus available from the menu bar at the top of the Setup screen.
Table 35.Setup Menu Bar
Setup Menu ScreenDescription
MaintenanceSpecifies the processor speed and clears the Setup passwords. This
menu is only available in configure mode. Refer to Section 1.15 for
information about configure mode.
MainAllocates resources for hardware components.
AdvancedSpecifies advanced features available through the chipset.
SecuritySpecifies passwords and security features.
PowerSpecifies power management features.
BootSpecifies boot options and power supply controls.
ExitSaves or discards changes to the Setup program options.
Table 36 shows the function keys available for menu screens.
Table 36.Setup Function Keys
Setup KeyDescription
<F1> or <Alt-H>Brings up a help screen for the current item.
<Esc>Exits the menu.
<m> or <o>Selects a different menu screen.
<n> or <p>Moves cursor up or down.
<Home> or <End>Moves cursor to top or bottom of the window.
<PgUp> or <PgDn>Moves cursor to top or bottom of the window.
<F5> or <->Selects the previous value for a field.
<F6> or <+> or <Space>Selects the next value for a field.
<F9>Load the default configuration values for the current menu.
<F10>Save the current values and exit Setup.
<Enter>Executes command or selects the submenu.
This menu is for setting the processor speed and clearing the Setup passwords. Setup only displays
this menu in configure mode. See Section 1.15 for information about setting configure mode.
Table 37.Maintenance Menu
FeatureOptionsDescription
Processor Speed
(66 MHz Host Bus)
Processor Speed
(100 MHz Host Bus)
Clear All PasswordsNo optionsClears the user and administrative passwords
233
266
300
333
300
350
Specifies the processor speed in megahertz
With a host bus operating at 66 MHz, the board supports processors
at the following speeds: 233, 266, 300, and 333 MHz
With a host bus operating at 100 MHz, the board supports processors
at the following speeds: 300 and 333 MHz
4.2 Main Menu
This menu reports processor and memory information and is for configuring the system date,
system time, floppy options, and IDE devices.
Table 38.Main Menu
FeatureOptionsDescription
BIOS VersionNo optionsDisplays the version of the BIOS.
Processor TypeNo optionsDisplays processor type.
Processor SpeedNo optionsDisplays processor speed.
Cache RAMNo optionsDisplays size of second-level cache.
System MemoryNo optionsDisplays the total amount of RAM on the motherboard.
Memory Bank 0
Memory Bank 1
Memory Bank 2
Language
ECC Configuration
L2 Cache ECC
Support
System TimeHour, minute, and
System DateMonth, day, and yearSpecifies the current date.
No optionsDisplays size and type of DIMM installed in each memory
bank.
x
English (US)
(default)
x
Francais
x
Italiano
x
Deutch
x
Espanol
x
Non-ECC (default)
x
ECC
x
Enabled
x
Disabled (default)
second
Selects the default language used by the BIOS.
Specifies ECC memory operation.
If Enabled, allows error checking to occur on data
accessed from L2 Cache.
Specifies the current time.
62
4.3 Advanced Menu
This menu is for setting advanced features that are available through the chipset.
Table 39.Advanced Menu
FeatureOptionsDescription
Plug & Play O/SNo (default)
Yes
Reset Configuration DataNo (default)
Yes
NumlockAuto (default)
On
Off
Peripheral ConfigurationNo optionsConfigures peripheral ports and devices. When selected,
IDE ConfigurationNo optionsSpecifies type of connected IDE device.
Floppy ConfigurationNo optionsWhen selected, displays the Floppy Options submenu.
DMI Event LoggingNo optionsConfigures DMI Events Logging. When selected, displays
Video ConfigurationNo optionsConfigures video features. When selected, displays the
Resource ConfigurationNo optionsConfigures memory blocks and IRQs for legacy ISA devices.
Specifies if a Plug and Play operating system is being used.
No
lets the BIOS configure all devices.
Yes
lets the operating system configure Plug and Play
devices. Not required with a Plug and Play operating
system.
Clears the BIOS configuration data on the next boot.
Specifies the power on state of the Num Lock feature on the
numeric keypad of the keyboard.
displays the Peripheral Configuration submenu.
the DMI Events Logging submenu.
Video Configuration submenu.
When selected, displays the Resource Configuration
submenu.
Disables or enables the integrated floppy disk
controller.
Specifies the capacity and physical size of
diskette drive A.
Disables or enables write protect for the
diskette drive.
This submenu is for configuring the DMI event logging features.
Table 45.DMI Event Logging Submenu
FeatureOptionsDescription
Event log capacityNo optionsIndicates if there is space available in the event log.
Event log validityNo optionsIndicates if the contents of the event log are valid.
View DMI event log[Enter]Displays the DMI event log.
Clear all DMI event logs
Event Logging
ECC Event Logging
Mark DMI events as
read
x
No (default)
x
Yes
x
Disabled
x
Enabled (default)
x
Disabled
x
Enabled (default)
[Enter]Marks all DMI events as read.
Clears the DMI event log after rebooting.
Enables logging of DMI events.
Enables logging of ECC events.
4.3.6 Video Configuration Submenu
This submenu is for configuring video features.
Table 46.Video Configuration Submenu
FeatureOptionsDescription
Palette Snooping
AGP Aperture Size
xxDisabled (default)
x
Enabled
xx64 MB (default)
x
256 MB
Controls the ability of a primary PCI graphics
controller to share a common palette with an ISA
add-in video card.
Specifies the aperture size for the A.G.P. video
controller.
This submenu is for configuring the memory and interrupts.
Table 47.Resource Configuration Submenu
FeatureOptionsDescription
Memory Reservation
IRQ Reservation
x
C800 - CBFFAvailable (default) | Reserved
x
CC00- CFFFAvailable (default) | Reserved
x
D000 - D3FFAvailable (default) | Reserved
x
D400 - D7FFAvailable (default) | Reserved
x
D800 - DBFFAvailable (default) | Reserved
x
DC00 - DFFFAvailable (default) | Reserved
x
IRQ3Available (default) | Reserved
x
IRQ4 Available (default) | Reserved
x
IRQ5 Available (default) | Reserved
x
IRQ7Available (default) | Reserved
x
IRQ10 Available (default) | Reserved
x
IRQ11 Available (default) | Reserved
Reserves specific upper
memory blocks for use by
legacy ISA devices.
Reserves specific IRQs for
use by legacy ISA devices.
An * (asterisk) displayed
next to an IRQ indicates an
IRQ conflict.
4.4 Security Menu
This menu is for setting passwords and security features.
Table 48.Security Menu
FeatureOptionsDescription
User Password IsNo optionsReports if there is a user password set.
Administrative Password IsNo optionsReports if there is a administrative
Set User PasswordPassword can be up to seven
alphanumeric characters.
Set Administrative PasswordPassword can be up to seven
alphanumeric characters.
Clear UserNo OptionsClears the user password.
User Setup Access
Unattended Start
x
None
x
View Only (default)
x
Limited Access
x
Full
x
Disabled (default)
x
Enabled
password set.
Specifies the user password.
Specifies the administrative password.
Establishes the user access level.
Enables the unattended start feature.
When enabled, the computer boots, but the
keyboard is locked. The user must enter a
password to unlock the computer or boot
from a floppy diskette.
68
4.5 Power Menu
This menu is for setting power management features.
Table 49.Power Menu
FeatureOptionsDescription
Power Management
Inactivity Timer
Hard Drive
VESA Video Power
Down
x
Disabled
x
Enabled (default)
x
Off (default)
x
1 Minute
x
5 Minutes
x
10 Minutes
x
20 Minutes
x
30 Minutes
x
60 Minutes
x
120 Minutes
x
Disabled
x
Enabled (default)
Disabled
x
xxxStandby (default)
x
Suspend
x
Sleep
BIOS Setup Program
Enables or disables the BIOS power management
feature.
Specifies the amount of time before the computer
enters standby mode.
Enables power management for hard disks during
standby and suspend modes.
Specifies power management for video during standby
and suspend modes.
4.6 Boot Menu
This menu is for setting the boot features and the boot sequence.
Table 50.Boot Menu
FeatureOptionsDescription
Quick Boot Mode
Scan User Flash Area
After Power Failure
On Modem Ring
On LAN
x
Disabled
x
Enabled (default)
x
Disabled (default)
x
Enabled
x
Stay Off
x
Last State (default)
x
Power On
x
Stay Off
x
Power On (default)
x
Stay Off
x
Power On (default)
Enables the computer to boot without running certain
POST tests.
Enables the BIOS to scan the flash memory for user
binary files that are executed at boot time.
Specifies the mode of operation if an AC/Power loss
occurs.
Power On
Stay Off
pressed.
Last State
power loss occurred.
Specifies how the computer responds to an incoming
call on an installed modem when the power is off.
Specifies how the computer responds to a LAN
First Boot Device
Second Boot Device
Third Boot Device
Fourth Boot Device
Fifth Boot Device
Hard DriveNo optionsLists available hard disk drives. When selected,
Removable DevicesNo optionsLists available removable devices. When selected,
(continued)
xxStay Off (default)
Power On
x
x
x
Disabled (default)
x
3 Seconds
x
6 Seconds
x
9 Seconds
x
12 Seconds
x
15 Seconds
x
21 Seconds
x
30 Seconds
x
Removable devices
x
Hard Drive
x
ATAPI CD-ROM Drive
x
Network Boot
x
LANDesk Service
Agent
Specifies how the computer responds to a PME
wakeup event when the power is off.
Sets the hard disk drive pre-delay. When enabled, this
option causes the BIOS to wait the specified time
before it accesses the first hard drive. If the computer
contains a hard drive and the drive type is not
displayed during boot-up, but the drive type is
displayed following a warm boot (<Ctrl><Alt><Del>),
the hard drive may need more time before it is able to
communicate with the controller. Setting a pre-delay
provides additional time for the hard drive to initialize.
Specifies the boot sequence from the available devices.
To specify boot sequence:
1. Select the boot device with <n> or <p>.
2. Press <+> to move the device up the list or <-> to
move the device down the list.
The operating system assigns a drive letter to each
boot device in the order listed. Changing the order of
the devices changes the drive lettering.
displays the Hard Drive submenu.
displays the Removable Devices submenu.
4.6.1 Hard Drive Submenu
This submenu is for configuring the boot sequence for hard disk drives.
Table 51.Hard Drive Submenu
OptionsDescription
Bootable Add in CardSpecifies the boot sequence for the hard disk drives attached to the computer. To
specify boot sequence:
1. Select the boot device with <n> or <p>.
2. Press <+> to move the device up the list or <-> to move the device down the
list.
The operating system assigns a drive letter to each device in the order listed.
Changing the order of the devices changes the drive lettering.
70
4.6.2 Removable Devices Submenu
This submenu is for configuring the boot sequence for removable devices.
Table 52.Removable Devices Submenu
OptionsDescription
Legacy Floppy DrivesSpecifies the boot sequence for the removable devices attached to the computer.
To specify boot sequence:
1. Select the boot device with <n> or <p>.
2. Press <+> to move the device up the list or <-> to move the device down the
list.
The operating system assigns a drive letter to each device in the order listed.
Changing the order of the devices changes the drive lettering.
4.7 Exit Menu
This menu is for exiting the Setup program, saving changes, and loading and saving defaults.
BIOS Setup Program
Table 53.Exit Menu
FeatureDescription
Exit Saving ChangesExits and saves the changes in CMOS SRAM.
Exit Discarding Changes Exits without saving any changes made in Setup.
Load Setup DefaultsLoads the factory default values for all the Setup options.
Load Custom DefaultsLoads the custom defaults for Setup options.
Save Custom DefaultsSaves the current values as custom defaults. Normally, the BIOS reads the
Setup values from flash memory. If this memory is corrupted, the BIOS reads
the custom defaults. If no custom defaults are set, the BIOS reads the factory
defaults.
Discard ChangesDiscards changes without exiting Setup. The option values present when the
Diskette drive A errorDrive A: is present but fails the POST diskette tests. Ensure that the drive
controller is enabled, the drive is correctly installed, and the drive type is
properly defined in Setup.
Extended RAM Failed at
nnnn
offset:
Failing Bits:
Fixed Disk 0 Failure or
Fixed Disk 1 Failure or
Fixed Disk Controller Failure
Incorrect Drive A type - run
SETUP
Invalid NVRAM media typeProblem with NVRAM (CMOS) access.
Keyboard controller errorThe keyboard controller failed test. Try replacing the keyboard.
Keyboard errorKeyboard not working.
Keyboard error nnBIOS discovered a stuck key and displays the scan code nn for the stuck key.
Keyboard locked - Unlock
key switch
Monitor type does not match
CMOS - Run SETUP
Operating system not foundOperating system cannot be located on either drive A or drive C. Enter Setup
Parity Check 1Parity error found in the system bus. BIOS attempts to locate the address
Parity Check 2Parity error found in the I/O bus. BIOS attempts to locate the address and
Press <F1> to resume, <F2>
to Setup
nnnn
Extended memory not working or not configured properly at offset
The hexadecimal number
(System, Extended, or Shadow memory) that failed the memory test. Each 1
in the map indicates a failed bit.
Fixed disk is not working or not configured properly. Check to see if fixed
disk is installed properly. Run Setup be sure the fixed-disk type is correctly
identified and enabled.
Type of floppy drive for drive A: not correctly identified in Setup.
Unlock the system to proceed.
Monitor type not correctly identified in Setup.
and see if fixed disk and drive A are properly identified.
and display it on the screen. If it cannot locate the address, it displays ????.
display it on the screen. If it cannot locate the address, it displays ????.
Displayed after any recoverable error message. Press <F1> to start the boot
process or <F2> to enter Setup and change any settings.
nnnn
is a map of the bits at the RAM address
nnnn
.
Real time clock errorReal-time clock fails BIOS test. May require motherboard repair.
System timer errorThe timer test failed. Requires repair of system motherboard.
(continued)
Shadow RAM failed at offset
was detected.
The CMOS clock battery indicator shows the battery is dead. Replace the
battery and run Setup to reconfigure the system.
RAM cache failed the BIOS test. BIOS disabled the cache.
System CMOS RAM has been corrupted or modified incorrectly, perhaps
by an application program that changes data stored in CMOS. Run Setup
and reconfigure the system either by getting the default values and/or
making your own selections.
System RAM failed at offset
detected.
nnnn
of the 64 KB block at which the error
nnnn
of the 64 KB block at which the error was
5.2 Port 80h POST Codes
During the POST, the BIOS generates diagnostic progress codes (POST codes) to I/O port 80h. If
the POST fails, execution stops and the last POST code generated is left at port 80h. This code is
useful for determining the point where an error occurred.
Displaying the POST codes requires an add-in card (often called a POST card). The POST card
can decode the port and display the contents on a medium such as a seven-segment display. These
cards can be purchased from JDR Microdevices or other sources.
The following table provides the POST codes that can be generated by the BIOS. Some codes are
repeated in the table because that code applies to more than one operation.
Table 55.Port 80h Codes
CodeDescription of POST Operation
02hVerify real mode
03hDisable non-maskable interrupt (NMI)
04hGet processor type
06hInitialize system hardware
08hInitialize chipset with initial POST values
09hSet IN POST flag
0AhInitialize processor registers
0BhEnable processor cache
0ChInitialize caches to initial POST values
0EhInitialize I/O component
0FhInitialize the local bus IDE
continued
74
Error Messages and Beep Codes
Table 55.Port 80h Codes
CodeDescription of POST Operation Currently In Progress
10hInitialize power management
11hLoad alternate registers with initial POST valuesnew
12hRestore processor control word during warm boot
13hInitialize PCI bus mastering devices
14hInitialize keyboard controller
16hBIOS ROM checksum
17hInitialize cache before memory autosize
18h8254 timer initialization
1Ah8237 DMA controller initialization
1ChReset programmable interrupt controller
20hTest DRAM refresh
22hTest keyboard controller
24hSet ES segment register to 4 GB
26hEnable A20 line
28hAutosize DRAM
29hInitialize POST memory manager
2AhClear 512 KB base RAM
2ChRAM failure on address line
2EhRAM failure on data bits
2FhEnable cache before system BIOS shadow
30hRAM failure on data bits
32hTest processor bus-clock frequency
33hInitialize POST dispatch manager
34hTest CMOS RAM
35hInitialize alternate chipset registers
36hWarm start shut down
37hReinitialize the chipset (MB only)
38hShadow system BIOS ROM
39hReinitialize the cache (MB only)
3AhAutosize cache
3ChConfigure advanced chipset registers
3DhLoad alternate registers with CMOS valuesnew
40hSet Initial processor speed new
42hInitialize interrupt vectors
44hInitialize BIOS interrupts
45hPOST device initialization
46hCheck ROM copyright notice
CodeDescription of POST Operation Currently In Progress
47hInitialize manager for PCI option ROMs
48hCheck video configuration against CMOS RAM data
49hInitialize PCI bus and devices
4AhInitialize all video adapters in system
4BhDisplay QuietBoot screen
4ChShadow video BIOS ROM
4EhDisplay BIOS copyright notice
50hDisplay processor type and speed
51hInitialize EISA motherboard
52hTest keyboard
54hSet key click if enabled
56hEnable keyboard
58hTest for unexpected interrupts
59hInitialize POST display service
5AhDisplay prompt "Press F2 to enter SETUP"
5BhDisable processor cache
5ChTest RAM between 512 and 640 KB
60hTest extended memory
62hTest extended memory address lines
64hJump to UserPatch1
66hConfigure advanced cache registers
67hInitialize multiprocessor APIC
68hEnable external and processor caches
69hSetup System Management Mode (SMM) area
6AhDisplay external L2 cache size
6ChDisplay shadow-area message
6EhDisplay possible high address for UMB recovery
70hDisplay error messages
72hCheck for configuration errors
74hTest real-time clock
76hCheck for keyboard errors
7AhTest for key lock on
7ChSet up hardware interrupt vectors
7EhInitialize coprocessor if present
80hDisable onboard Super I/O ports and IRQs
81hLate POST device initialization
82hDetect and install external RS232 ports
83hConfigure non-MCD IDE controllers
(continued)
continued
76
Error Messages and Beep Codes
Table 55.Port 80h Codes
CodeDescription of POST Operation Currently In Progress
84hDetect and install external parallel ports
85hInitialize PC-compatible PnP ISA devices
86hRe-initialize onboard I/O ports
87hConfigure motherboard configurable devices
88hInitialize BIOS Data Area
89hEnable Non-Maskable Interrupts (NMIs)
8AhInitialize extended BIOS data area
8BhTest and initialize PS/2 mouse
8ChInitialize diskette controller
8FhDetermine number of ATA drives
90hInitialize hard-disk controllers
91hInitialize local-bus hard-disk controllers
92hJump to UserPatch2
93hBuild MPTABLE for multiprocessor boards
94hDisable A20 address line (Rel. 5.1 and earlier)
95hInstall CD ROM for boot
96hClear huge ES segment register
97hFix up multiprocessor table
98hSearch for option ROMs
99hCheck for SMART Drive
9AhShadow option ROMs
9ChSet up power management
9EhEnable hardware interrupts
9FhDetermine number of ATA and SCSI drives
A0hSet time of day
A2hCheck key lock
A4hInitialize typematic rate
A8hErase F2 prompt
AahScan for F2 key stroke
AchEnter SETUP
AehClear IN POST flag
B0hCheck for errors
B2hPOST done - prepare to boot operating system
B4hOne short beep before boot
B5hTerminate QuietBoot
B6hCheck password (optional)
B8hClear global descriptor table
B9hClean up all graphics
CodeDescription of POST Operation Currently In Progress
BahInitialize DMI parameters
BBhInitialize PnP Option ROMs
BChClear parity checkers
BDhDisplay MultiBoot menu
BehClear screen (optional)
BFhCheck virus and backup reminders
C0hTry to boot with INT 19h
C1hInitialize POST Error Manager (PEM)
C2hInitialize error logging
C3hInitialize error display function
C4hInitialize system error handler
E0hInitialize the chipset
E1hInitialize the bridge
E2hInitialize the processor
E3hInitialize system timer
E4hInitialize system I/O
E5hCheck force recovery boot
E6hChecksum BIOS ROM
E7hGo to BIOS
E8hSet huge segment
E9hInitialize multiprocessor
EahInitialize OEM special code
EbhInitialize PIC and DMA
EchInitialize memory type
EdhInitialize memory size
EehShadow boot block
EfhSystem memory test
F0hInitialize interrupt vectors
F1hInitialize runtime clock
F2hInitialize video
F3hInitialize beeper
F4hInitialize boot
F5hClear huge segment
F6hBoot to mini-DOS
F7hBoot to full DOS
(continued)
78
Error Messages and Beep Codes
NOTE
✏
If the BIOS detects error 2C, 2E, or 30 (base 512 K RAM error), it displays an additional wordbitmap (xxxx) indicating the address line or bits that failed. For example, "2C 0002" means
address line 1 (bit one set) has failed. "2E 1020" means data bits 12 and 5 (bits 12 and 5 set) have
failed in the lower 16 bits. The BIOS also sends the bitmap to the port-80 LED display. It first
displays the check point code, followed by a delay, the high-order byte, another delay, and then the
low-order byte of the error. It repeats this sequence continuously.
5.3 BIOS Beep Codes
Whenever a recoverable error occurs during power-on self test (POST), the BIOS displays an error
message describing the problem. The BIOS also issues a beep code (one long tone followed by
two short tones) during POST if the video configuration fails (a faulty video card or no card
installed) or if an external ROM module does not properly checksum to zero.
An external ROM module (for example, a video BIOS) can also issue audible errors, usually
consisting of one long tone followed by a series of short tones. For more information on the beep
codes issued, check the documentation for that external device.
There are several POST routines that issue a POST terminal error and shut down the system if they
fail. Before shutting down the system, the terminal-error handler issues a beep code signifying the
test point error, writes the error to I/O port 80h, attempts to initialize the video and writes the error
in the upper left corner of the screen (using both monochrome and color adapters).
If POST completes normally, the BIOS issues one short beep before passing control to the
operating system.
Table 56.Beep Codes
Beeps80h CodeDescription
1B4hOne short beep before boot
1-298hSearch for option ROMs
1-2-2-316hBIOS ROM checksum
1-3-1-120hTest DRAM refresh
1-3-1-322hTest 8742 keyboard controller
1-3-4-12ChRAM failure on address line
1-3-4-32EhRAM failure on data bits
1-4-1-130hRAM failure on data bits
2-1-2-346hCheck ROM copyright notice
2-2-3-158hTest for unexpected interrupts
Version 2.1, June 16, 1997
American Megatrends Inc., Award Software International
Inc., Dell Computer Corporation, Intel Corporation,
Phoenix Technologies Ltd., SystemSoft Corporation
http://www.ptltd.com/techs/specs.html
Version 1.0, January 25, 1995
Phoenix Technologies Ltd., IBM Corporation. The El
Torito specification is available on the Phoenix Web site
http://www.ptltd.com/techs/specs.html
Version 1.1, October 17, 1995
Infrared Data Association.
Phone: (510) 943-6546
Fax: (510) 943-5600
Design Guide Revision 1.1, March 1996
Intel Corporation. The specification is available at:
http://www.usb.org
USBUniversal serial bus
specification
Revision 1.0, January 15, 1996
Compaq Computer Corporation, Digital Equipment
Corporation, IBM PC Company, Intel Corporation,
Microsoft Corporation, NEC, Northern Telecom
http://www.intel.com/
82
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