Intel® IXF1104 4-Port Gigabit Ethernet
Media Access Controller
Datasheet
The Intel® IXF1104 is a four-port Gigabit MAC that supports IEEE 802.3 10/100/1000 Mbps
applications. The IXF1104 suppor ts a System Packet Interface Phase 3 (SPI3) syste m interface
to a network processor or ASIC, and co ncurrently supports copper and fiber physi cal layer
devices (PHYs).
The copper PHY interface implements t he Gigabit Media Independent Interface (GMII) and the
Reduced Gigabit Media Indep ende nt Interface (RGMII) as defined in Version 1.2a of the
Hewlett-Packard* specification. RGMII has the benefit of reducing th e PHY interface pin count
for high-port-count applications.
The fiber PHY interface implements an internal Serializer/Deserializer (SerDes) on each port to
allow direct connection to optical modules. The integration of the SerDes functionalit y reduce s
PCB area requirement s a nd system cost.
Product Features
4 Independent Ethernet MAC Ports which
support 3 interfaces for Copp er or Fiber
Physical layer connectivity.
—IEEE 8 0 2.3 compliant
— R MON Statistics
—Independent Enable/Disable of any port
Copper Mode:
—RGMII for 10/100/1000 Mbps
connections
—GMII for 1000 Mbps full-duplex
connectivity
—IEEE 802.3 MDIO interface
Fiber Mode:
—Integrated SerDes interfac e for direct
connection to opt ical modules for
1000BASE-X connectivity
—Supports IEEE 802.3 fiber auto-
negotiation including forced mode
—Small Form Factor Pluggable (SFP)
Transceiver MSA compatible
System P acket Interface Level 3 (SPI3)
—Capable of data transfers at 4 Gbps in
both SPI3 modes:
32-bit Multi-PHY mode (133 Mhz )
4 x 8bit Single-PHY mode (125 Mhz)
Operating Temperature Ranges:
MIN MAX
Copper Mode:-40°C +85°C
Fiber Mode:0°C +70°C
Flexible 32/16/8-bit CPU interface
Programmable Packet handling
—Filter packets with errors
—Filter broadcas t, multicast, unicast and
VLAN packets
—Automaticall y pad transmitted packets
less than the minimum frame size
—Remove CRC from packets received
Performance Monitoring and Diagnostics
—CRC calculation and error detection
—Detection of length error, runt or overly
large pack e ts
—Counters for dropped and errored
packets
—Loopback modes
—JTAG- and boundary-scan-capable
IEEE 802.3 Complaint Flow Control
—Loss-less flow control for up to 9.6 KB
packets and 5 km of fiber
—Jumbo frame support for 9. 6 KB packets
Internal 32 KB receive FIFO and 10 KB
transmit FIFOs per chan n el
552-ball Ceramic Ball Grid Array (CBGA)
—1.8 V core, 2.5 V RGMII, GMII, OMI,
and 3.3 V SPI3 and CPU
—.18 µ CMOS process technology
Product Ordering Number:
HFIXF1104CE.B0 853714
Document Number: 278757
Revision Number: 007
Applications
Load Balancing Sy stems
MultiService Switch
Web Caching Appliances
Intelli gent Backplane Interfaces
Edge Router
Base Station Controller
Redundant Line Cards
Base Tran sceiver Station
Serving GRPS Support Node (SGSN)
General Packet Radio Services (GGSN)
Packet Data Serving Note (PDSN)
Digital S ubscri be r L ine Ac ces s Mul tip lex er
(DSLAM)
Cable Modem Termination System
(CMTS)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
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RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety sy ste m s, o r
in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
®
The Intel
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
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AllGlobally replaced GBIC with Optical Module Interface.
AllGlobally edited signal names.
Globally changed SerDes and PLL analog power ball names as follows:
TXAVTT and RXAVTT changed to AVDD1P8_2
TXAV25 and RXAV25 changed to AVDD2P5_2
All
PLL1_V DD A and PLL2_V DD A changed to AVDD1P8_1
PLL3_VDDA changed t o AVDD2P5_1
PLL1_GNDA, PLL2_GNDA, and PLL3_GNDA changed to GND
Reworded and rearranged the Product Features section on page one
1
Changed Jumbo frame support from “10 kbytes” to “9.6 KB”.
20Changed heading to S ection 2.0, “General Desc ription” [w as Section 2.0 , “Block Diagram”].
22/36
Revers ed sections as follows:
Section 3.0, “Ball Assignments and B all List Tables”
Section 4.0, “Ball Assignments and Signal Descriptions”
Modified Table 1 “Ball List in Alphanume ric Order by Signal Name”:
Changed A10 from VCC to VDD
Changed C12 from VCC to VDD
Changed D11 from VCC to VDD
Changed J20 from GND to VDD
23
Revision Number: 007
Revision Date: March 25, 2004
(Sheet 1 of 5)
Changed Ball A1 from NC to No Pad.
Changed Balls A2, A3, A22, A23, A24, B1, B2, B23, B24, C1, C24, AB1, AB24, AC1, AC2, AC23,
AC24, AD1, AD2, AD3, AD22, AD23, AD24 from NC to No Ball.
Modified Table 2 “Ball List in Alphanumeric Order by Ba ll Location”
Changed A10 from VCC to VDD
Changed C12 form VCC to VDD
Changed D11 from VCC to VDD
Changed J20 from GND to VDD
29
Changed Ball A1 from NC to No Pad.
Changed Balls A2, A3, A22, A23, A24, B1, B2, B23, B24, C1, C24, AB1, AB24, AC1, AC2, AC23,
AC24, AD1, AD2, AD3, AD22, AD23, AD24 from NC to No Ball.
Updated Figure 4 “Interface Signals” [modified SPI3 interface signals and added MPHY and SP HY
37
categories; modif ied signal names].
Broke old T able 1, “IXF1104 Signal Descriptions” into the following:
38
Table 3 “SPI3 Interface Signal Descriptions” on page 38 through Table 14 “Power Supply Signal
Descriptions” on page 55
Modified Table 3 “SPI3 Interface Signal Descriptions” on page 38 [edited description for DTPA;
38
added text to TFCLK description; added text to RFCLK description].
Modified T able 6 “RGMII Interface Signal Descriptions” [Added Ball Designators; added notes
49
under descriptions].
50Modified Table 7 “CPU Interface Signal Descriptions” [UPX_DATA[16]: deleted J10, added M10].
52Modified Table 9 “Optical Module Interf ace Signal Descriptions” [added Ball Designators].
53Modified Table 10 “MDIO Interface Signal Descriptions” [moved note from MDC to MDIO].
Modified Table 14 “Power Supply Signal Descripti ons” [added Ball Designators A4, A 21, and AD21
55
to GND; added AVDD1P8_1, AVDD1P8_2, AVDD2P5_1, and AVDD2P5_2].
Conven tions; adde d ne w head in gs Section 4.1.1, “Signal Name Conventions” and Section 4.1.2,
“Register Address Conventions”; and added/enhanced material under headin gs.
Added ne w Section 4.5, “Multiplexed Ball Connections” with Table 16 “Line Side Interface
57
Multip le xe d Balls” and Table 17 “SPI3 MPHY/SPHY Interface”.
Modified Sectio n 4 .7 , “ Pow er S u pply Se qu en cing ” [c ha nged la ng ua ge unde r thi s se ct io n and a dde d
62
Section 4.7.1, “Power-Up Sequence” and Sec ti on 4.7.2, “Power -D o w n Seq ue nce”].
Modified Table 5 “Power Supply Sequencing” [deleted 3.3 V S upplies Stable; changed Apply 1.8 V
62
to VDD, AVDD1P8_1, and AVDD1P8_2; changed Apply 2.5 V to AVDD2P5_1 and AVDD2P5_2].
Modified T able 18 “Definition of Output and Bi-dir ectional Balls During Hardware Reset” [changed
60
comments for Optical Modules].
Modified Table 20 “Pull-Up/Pull-Down and Unused Ball Guidelines” [cha ng ed TR ST _L to p ul l- d own ;
63
added MDIO, UPX_RDY_L, I
Added ne w Section 4.9, “Analog Power Filtering” [including Figure 6 “Analog Power Supply Filter
63
Network” on page 64 and Table 21 “Analog Power Balls” on page 64].
Modified/edited text under Section 5.1, “Media Access Controller (MAC)” [rearranged and created
65
new bullets].
66Modified first paragraph under Section 5.1.1.1, “Padding of Under s ized Frames on Transmit”.
66Modified entire Section 5.1.1.3, “Filtering of Receive Packets”.
67Added new Section 5.1.1.3.6, “Filter CRC Error Packets”.
68Added note under Table 22 “CRC Errored Packets Drop Enable Behavior”.
Added ne w Section 5.1.2, “Flow Control” including Figure 7 “Packet Buffer in g FIFO”, Figure 8
68
“Ethernet Frame Format”, and Figure 9 “PAUSE Frame Format”.
Replaced Section 5.1.2.1.5, “Transmit Pause Control Interface” [added Tabl e23 “ Valid Decode s f or
72
TXPAUSEADD[2:0]” and mo di fied Table 10 “Transmit Pause Control Interface”.
73Modified Figure 10 “Transmit Pause Control Interface”
74Added note under Section 5.1.3.1 , “Configuration of the IXF1104 ”.
75Added table not e to Table 24 “Operational Mode Configuration Registers”.
76Added note under Section 5.1.4.3, “Fiber Forced Mode”.
78Modified Section 5.1.6.2, “TX Statistics” [added text to third senten ce in first parag ra ph ].
Modified Section 5.1.6.3, “Loss-less Flow Cont rol” [changed “two kilometers” to “five kilometers” in
78
last sentence.
79Modified Section 5.1.7.1.2, “RX FIFO” [changed 10 KB to 9.6 KB; added text to last paragraph].
82Rewrote/replaced Section 5.2, “SPI3 Interface”.
85Edited signal names in Figure 13 “MPHY 32-Bit Interface”.
89Edited signal names in Figure 16 “SPHY Connection for Two IXF1104 Ports (8-Bit Interface)”.
Added ne w Section 5.2.2.9, “SPI3 Flow Control”.
90
[Removed old “Packet-Level and Byte-Level Transfers” section.}
93Modified Figure 17 “MAC GMII Interconnect” [edited signal names].
Removed old Section 5.3.3 Electrical Requirements and Table 27 “Electrical Requirements” –
NA
changed Input high current Max from 40 to 15 and Input low curren t Min from -600 to -15.
95Added a note under Section 5.4, “Red uced Gigabit M edia Independent Interface (RGMII)”.
95Modified Figure 18 “RGMII Interface” [edited signal names].
97Modified Figure 19 “TX_CTL Behavior” [changed signal names].
Modified/replaced text and deleted old “Figure 19. Typical GBIC Module Functional Diagram” under
Section 5.7, “Optical Module Interface”].
107Modified second sentence under S ec tio n 5. 7. 2 .2 .1, “MOD_DE F _0 :3 ”.
108Modified second sentence under S ec tio n 5. 7. 2 .2 .3, “RX_LOS_ 0 : 3”.
108Removed third paragraph under Section 5.7.2.2.7, “RX_LO S_INT”.
109Modifie d f ir st an d se co nd paragra ph s un de r Section 5.7.3, “I²C Module Configuration Interface”.
110Modified Section 5.7.3.3, “I2C Write Operation” [edited portions of text].
115
118
Modified T able 31 “LED Interface Signal Descriptions” [changed 0.5 MHz to 720 Hz f or LED_CLK
under Signal Description].
Modified Table 35 “LED Behavior (Fiber Mode)” [changed links under Description to “Link LED
Enable ($0x502)”].
NARemoved old Figure 30 “CPU – External and Internal Connections”.
122Modified Table 37 “Byte Sw apper Behavior” [edit ed /ad ded new value s] .
122Modif ied second paragraph under Section 5.10, “TAP Interface (JTAG)”
125Modified Figure 33 “SPI3 Interface Loopback Path ”.
125Added note under Section 5.11.2, “Line Side Interfa ce Loopback”.
126Modified Figure 34 “Line Side Interface Loopback Path”.
126Changed Section 5.12, “Clocks” [from GBIC output clock to I
128Changed Section 5.12.6, “I2C Clock” [from GBIC Clock to I
2
C Clock].
2
C Clock].
129Added new Section 6.0, “Applications”.
Modified Table 39 “Absolute Maximum Ratings” [changed SerDes analog power to AVDD1P8_2
131
and AVDD2P5_2; changed “PLL1_VDDA and PLL2_VDDA to AVDD1P8_1; changed PLL3_VDDA
to AVDD2P5_1.
Modified Table 40 “Recommended Operating Conditions” [changed SerDes analog power to
132
AVDD1P8_2 and AVDD2P5_2; changed “ PLL1_VDDA and PLL2_VDDA to AVDD1P8_ 1; changed
Regist ers ($ Port Index + Offset)”, Table 62 “PHY Autoscan Registers ($ Port Index + Offset)”,
Table 63 “Glo bal Status and Configuration Registers ($ 0x500 - 0X50C)”, Ta bl e 64 “RX FIFO
Registers ($ 0x580 - 0x 5BF)”, Table 65 “TX FIFO Registers ($ 0x600 - 0x63E)”, Table 66 “MDIO
Registers ($ 0x680 - 0x683)”, Table 67 “SPI3 Registers ($ 0x700 - 0x716)”, Table 68 “SerD es
Registers ($ 0x780 - 0x798)”, and Table 69 “Optical Module Registers ($ 0x799 - 0x79F)”.
Modified T able 71 “Desired Duplex ($ Port_Index + 0x02)” [changed 100 Mbps to 1000 Mbps in
register description.
Modified Table 82 “MAC IF Mode and RGMII Speed ($ Port _Index + 0x10)” [Added text to register
description.]
Modified Table 88 “RX Config Word ($ Port_Index + 0x16)” [edited Register Desc ription text;
change d description and type for bits 13:12].
Modified Table 89 “TX Config Word ($ Port_Index + 0x17)” [edited description and type fo r bits 14,
13:12.
Modified Table 90 “Diverse Config Write ($ Port_Index + 0x18)” [edited description and type for bits
18:8; cha n ge d bit s 3:1 to R es erv e d; ad de d tabl e note 2].
Renamed/modified Table 91 “RX P ac k et Fil t e r Co ntrol ($ Port_In de x + 0x19 ) ” [old register name added RX to heading; added table note 2].
Modified T able 94 “MAC TX Statistics ($ Port_Index +0x40 – +0x58)” [changed “15 26 -ma x” to “ 1 523
- max fra me size” for Txpkts1519toMaxOctets descript ion].
Modified T able 113 “RX FIFO High Watermark Port 0 ($0x580)”, Tabl e114 “RX F IFO High
Watermark Port 1 ($0x581)”, Table 115 “RX FIFO High Watermark Port 2 ($0x582)”, and Table 116
“RX FIFO High Watermark Port 3 ($0x583)” [changed bits 11:0 description].
Renamed and modi fie d Table 121 “RX FIFO Overflow Frame D rop Counter Ports 0 - 3 ($0x594 –
0x597)”
[old register name: RX FIFO Number of Frames Removed Ports 0 to 3; renamed bit names to
match register names; removed “This register gets updated after one cycle of sw reset is applied”
under D escription] .
Modified T able 123 “RX FIFO Errored Frame Drop Enable ($0x59F)” [renamed bit names to match
register name].
Renamed/modified T able 125 “RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2 - 0x5A5)”
on page 197 [older register name: RX FIFO Dropped Packet Counter for Ports 0 to 3; renamed bit
names to match register name].
Modified T able 126 “RX FIF O SPI 3 Loopback Enable for Ports 0 - 3 ($0x5B2)” [renamed heading
and bit name; changed description and type for bits 7:0].
Renamed Table 128 “RX FIFO Transfer Threshold Port 0 ($0x5B8)” on page 200 [from “RX FIFO
Jumbo Packet Size; changed bit names an d edited/adde d text under description].
NARemoved/Reserved Table 190 “TX and RX AC/DC Coupling Selection ($7x780)”.
Deleted old Figure 19, “Typical GBIC Module Functional Diagram” under Section 5.7, “Optical
NA
Module Interface”.
NARemoved old Section 5.1.1.5, “Pause Command Frames. ”
180(old)
Removed ol d Table 1 3. TX FI FO Mini F r ame S ize for MAC and Padd in g Ena bl e Por t 0 t o 3 R egi st er
(Addr: 0x63E) and replaced with Reserved.
Revision Number: 006
Revision Date: August 21, 2003
(Sheet 1 of 2)
Page #Description
19Modified Table 1 “Intel
®
IXF1104 Signal Descriptions”
53Modified Section 5.1.1.1, “Padding of Undersized Frames on Transmit”.
60Modified text for etherStatsCollision in Table 9 “RMON Additional St atistics”.
®
87M o dif ie d Table 17 “Intel
IXF1104-to-Optical Module Interface Connections”
65Modified first paragraph under Section 5.3.1.2, “Clock Rates”.
87Modified Section 5.8.2.1, “High-Speed Seri al Interfac e”.
100Modified Figure 27 “Microprocessor — External and Internal Connections”.
110Changed PECL to LVDS under Section 6.1, “DC Specifications”.
113Modified table note 4 in Table 32 “SPI3 Receive Interface Signal Parameters”.
119Modifie d Table 3 7 “ SerDes Timing Pa ram eters”.
125Modif ie d Table 4 0 “ Mi c roprocess or Interface Wr ite Cy cl e AC Signal Parameters”.
16Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
Contents
Revision Number: 006
Revision Date: August 21, 2003
Page #Description
140
Modif ied Table 53 “IPG Receive and Transmit Time Register (Addr: Port_Index + 0x0A – +
0x0C)”.
143Modified Table 60 “S hort Runts Threshold Register (Addr: Port_Index + 0x14)”.
143Modified Table 61 “D iscard Unknown Control Frame Register (A ddr: Port_In dex + 0x15)”.
143Modified Table 62 “RX Config Word Register Bi t Definition (Addr: Port_Index + 0x16)”.
145Modified Table 64 “DiverseConfigWrite Register (Add r: Port_Index + 0x18)”.
148Modified Table 67 “RX Statistics Regis ters (Addr: Port_Index + 0x20 – + 0x39)”.
163Modified Table 82 “Microprocessor Interfa c e Register (Addr: 0x508)”.
164Modified Table 84 “LED Flash Rate Register (Add r: 0x50A)”.
169Modified Table 93 “RX FIFO Errored Frame Drop Enable Register (Addr: 0x59F)”.
170Modified Table 96 “RX FIFO Loopback Enable for Ports 0 - 3 Registe r (Addr: 0x5B2)”.
171Added Table 98 “RX FIFO Jumbo Packet Size 0-3 Register (Addr: 0x5B8 – 0x5BB”.
172Added Table 99 “RX FIFO Jumbo Packet Size Port 0 Register B it Definitions (Addr: 0x5B8)”.
172Added T able 100 “RX FIFO Jumbo Packet Size Port 1 Register Bit Definitions (Addr: 0x5B9)”.
172Added T able 101 “RX FIFO Jumbo Packet Size Port 2 Register Bit Definitions (Addr: 0x5BA)”.
172Added T able 102 “RX FIFO Jumbo Packet Size Port 3 Register Bit Definitions (Addr: 0x5BB)”.
178
Modified Table 110 “TX FIFO Number of Dropped Packets Register Ports 0-3 (Addr: 0x625 –
0x629)”.
177Modified Table 108 “TX FIFO Port Reset Register (Addr: 0x620)”.
177Modified Table 108 “TX FIFO Port Reset Register (Addr: 0x620)”.
177Modified Table107 “Loop RX Data to TX FIFO Register Ports 0 - 3 (Addr: 0x61F)”.
IXF1104 4-Port Gi gab it Ethernet Media Access Controller
1
2.0General Description
The IXF1104 provides up to a 4.0 Gbps interface to four individual 10/100/1000 Mbps full-duplex
or 10/100 Mbps half-duplex-capable Ethernet Media Access Controllers (MACs). The network
proce ssor is supported through a System Packet Interface Phase 3 (SPI3) media interface. The
following PHY interfaces are selected on a per-port basis:
• Serializer /Deserializer (SerDes) with Optical Module Interface support
• Gigabit Media Indepe ndent Interface (GMII)
• Reduced Gigabit Media Independent Interface (RGMII).
Figure 1 illustrates the IXF1104 block diagram.
Figure 1. Block Diag ram
CPU
uP IF
PHY 1 Devic e
PHY 2 Devic e
®
Intel
IXF1104 M AC
SPI3
Se rD e s /RGMI I/GMI I In t e r fa ce
PHY 3 Devic e
PHY 4 Devic e
Forw ardi n g Engi ne/N etwork Processor
MDIO
B3175-0
20Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
Figure 2 illustrates the IXF1104 internal architecture.
1
Figure 2. Internal Architecture
IXF1104 4-Port Gigabit Ethernet Media Access Controller
IXF1104 4-Port Gi gab it Ethernet Media Access Controller
35Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
IXF1104 4-Port Gi gab it Ethernet Media Access Controller
4.0Ball Assignments and Signal Descriptions
4.1N amin g C on ve nt io ns
4.1.1Signal Name Conventions
Signal names beg in with a Signal Mnem onic, and can also contain one or more of the followi ng
designations: a differential pair designation, a serial designation, a port designation (RGMII
interface), and an active low designation. Signal naming conve ntions are as follows:
Differential Pair + Port Design at ion. The positive and negative compo nents of differential pairs
tied to a specific port are designated by the Signal Mnemonic, immediately followed by an
underscore and either P (positive component) or N (negative component), and an underscore
followed by the port designation. For example, SerDes interface signals for port 0 are ident ified as
TX_P_0 and TX_N_0.
Serial Design ation . A set of signals that are not tied to any specific port are designated by the
Signal Mnemoni c, follo wed by a bracketed serial designation. For example, the set of 11 CPU
Address Bus signals is identified as UPX_ADD[10:0].
Port Designation. Individual signals that apply to a particular port are designated by the Signal
Mnemonic, immediately followed by an underscore and the Port Designation. For example,
RGMII Transmit Control signals are identified as TX_CTL_0, TX_CTL_1, TX_CTL_2, and so on.
Port Bus Designatio n. A set of bus signals that apply to a particular port are designated by the
Signal Mnemonic, immediately followed by a bracketed bus designation, followed by an
underscore and the port desi gnation. For example, RGMII transmit da ta bus signals are identified
as TD[3:0]_0, TD[3:0]_1, TD[3:0]_2, and so on.
Active Low Designation. A control input or indicator output that is active Low is designated by a
final suf fi x cons isti ng of an unde rscore fol lowe d by an upper ca se “L” . For e xample , the CPU cycl e
complete id entifier is shown as UPX_RDY_L.
4.1.2Register Address Conventions
Registers located in on-chip memory are accessed using a reg ister address, which is provided in
Hex notation. A Register Address is indicated by the dollar si gn ($), followed by the memory
location in Hex.
36Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
IXF1104 4-Port Gigabit Ethernet Media Access Controller
4.2Inter face Signal Groups
This section describes the IXF1104 signals in groups according to the associated interface or
function. Figure 4 shows the various interfaces available on the IXF1104.
Figure 4. Interface Signals
SPI3
Interface
JTA G
Interface
MDIO
Interface
Pause
Control
Interface
CPU
Interface
LED
Interface
TDAT[7:0]_0:3
TFCLK
TENB_0: 3
TERR_0:3
TPR TY _0:3
TSOP_0:3
TEOP_0:3
TADR[1:0]
DTPA_0: 3
PTPA
RDAT[7:0]_0:3
RFCLK
RENB_0:3
RVAL_0:3
RERR_0:3
RPRTY_0:3
RSOP_0: 3
REOP_0: 3
MPHYSPHY
TDA T[ 31: 0]
TFCLK
TENB_0
TERR_0
TPRTY_0
TMOD[1:0]
TSX
TSOP_0
TEOP_0
TADR [1:0]
DTPA_0:3
STPA
PTPA
RD AT[31: 0]
RFCLK
RENB_0
RVAL_0
RERR_0
RPRTY_0
RMOD[1:0]
RSX
RSOP_0
REOP_0
TMS
TDO
TCLK
TRST_L
MDIO
MDC
TXPAUSEADD [2:0]
TXPAUSEF R
UPX_WIDTH[1:0]
UPX_D ATA[31:0]
UPX_ADD [10:0]
UPX_BADD [1: 0]
UPX_WR_L
UPX_RD_L
UPX_CS_L
UPX_RD Y_L
LED_CLK
LED_DATA
LED _LATC H
TDI
Intel® IXF1104
Media A ccess
Controller
GMIIRGMII
TXC_0:3
TXD[7: 0] _0
TXD[7: 0] _1T D [3:0] _1
TXD[7: 0] _2T D [3:0] _2
TXD[7: 0] _3
TX_EN_0:3
TX_ER_0:3
RXC _0:3R XC _0: 3
RXD[7:0]_3
RXD[7:0]_2
RXD[7:0]_0
RX_D V_0:3
RX_ER_0:3
CRS_0:3
COL_0:3
* D at a and cloc k bal ls are s ha red f or
GMII and RGMII Interf aces
RX_P/N_0:3
TX_P/N_0:3
TX_D ISABLE_0: 3
MOD _DEF_0:3
TX_FAU LT_0:3
RX_LOS_0: 3
TX_FAU LT_IN T
RX_LOS_I N T
MOD _DEF_INT
2
I
C_CLK
2
I
C_DATA_0:3
** T h ese opt ica l m odule signals
ar e m ult iplex ed on t he G M I I balls .
SYS_RES_L
CLK125
TXC _0:3
TD[3:0]_0
TD[3:0]_3
TX_C TL_0:3
RD[3:0]_0
RD[3:0]_1
RD[3:0]_2RXD[7:0]_1
RD[3:0]_3
RX_C T L_0:3
TFCLK is the clock associated with all
transmit signals. Dat a and control lines are
samp le d on the r is in g edge of TFCLK
(freque ncy operation range 90 - 133 MHz).
Bits
[31:24]
[7:0] for port 3
Bits
[23:16]
[7:0] for port 2
Bits
[15:8]
[7:0] for port 1
Bits
7:0]
[7:0] for port 0
38Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Tabl e 3. SPI3 Interface Signal Description s (Sheet 2 of 8)
Signal Name
MPHYSPHY
TPRTY_0 TPRTY_0
TPRTY_1
TPRTY_2
TPRTY_3
TENB_0TENB_0
TENB_1
TENB_2
TENB_3
TERR_0TERR_0
TERR_1
TERR_2
TERR_3
TSOP_0TSOP_0
TSOP_1
TSOP_2
TSOP_3
TEOP_0TEOP_0
TEOP_1
TEOP_2
TEOP_3
Ball
Designator
D5
G3
B9
J6
B7
E2
C9
J4
A8
K1
E11
J8
C7
E3
C10
J5
A7
F3
E4
H5
TypeStandardDescription
T ransmit Parity.
TPRTY indicate s odd parit y for the TDAT
bus. TPRTY is valid on ly when a channe l
asserts either TENB or TSX. Odd parity is
the default configuration; however, even
parity can be selected (see Table 146 “SPI3
Transmit and Global Configuration
($0x70 0)” on page 212).
32-bit Multi- PHY mode: TPRTY_0 is the
parity bit covering all 32 bits.
4 x 8 Single-PHY mode: TPRTY_0:3 bits
correspond to the respective TDAT[3:0]_n
channels.
T ransmit Write Enable.
TENB_0:3 asserted causes an attach ed
PHY to process TDAT[n], TMOD, TSOP,
TEOP an d TER R si gn als.
32-bit Multi- PHY mode: TENB_0 is the
enable bit for al l 32 bits .
4 x 8 Single-PHY mode: TENB_0:3 bits
correspond to the respective TDAT[3:0]_n
channels and their associated c ontrol and
status signals.
T ransmit Erro r.
TERR indicates that there is an error in the
current packet. TERR is valid when
simultaneously as serted with TEOP and
TENB.
32-bit Multi- PHY mode: TERR_0 is the bit
asserted for all 32 bits.
4 x 8 Single-PHY mode: Each bit of
TERR_0:3 corresponds to the respective
TDAT[3:0]_n channel.
T ransmit Start-of-Packet.
TSOP indicates the start of a packe t an d is
valid when asserted simultaneously with
TENB.
32-bit Multi- PHY mode: TSOP_0 is the bit
asserted for all 32 bits.
4 x 8 Single-PHY mode:
TSOP_0:3 corresponds to the respective
TDAT[3:0]_n channel.
T ransmit End-of-Packet.
TEOP indicates the end of a packet and is
valid when asserted simultaneously with
TENB.
32-bit Multi- PHY mode: TEOP_0 is the bit
asserted for all 32 bits.
4 x 8 Single-PHY mode: Each bit of
TEOP_0:3 corresponds to the respective
TDAT[3:0]_n channel.
IXF1104 4-Port Gi gab it Ethernet Media Access Controller
Table 3. SPI3 Interface Signal Descript ions (Sheet 3 of 8)
Signal Name
MPHYSPHY
TMOD1
TMOD0
TSXNAE1Input
TADR1
TADR0
NA
TADR1
TADR0
Ball
Designator
D9
A6
A12
A11
TypeStandardDescription
Input
Input
3.3 V
LVTTL
3.3 V
LVTTL
3.3 V
LVTTL
TMOD[1:0] Transmit Word Modulo.
32-bit Multi-PHY mode: TMOD[1:0]
indicate s the val id da ta byte s of TDA T [31:0 ].
During transmission, TMOD[1:0] should
always be “00” until the last double word is
transferred on TDAT[31:0]. TMOD[1:0]
specifies the valid bytes of TDAT when
TEOP is asserted:
TMOD[1:0] – Valid Bytes of TDAT
00 =4 bytes [31:0]
01 =3 bytes [31:8]
10 =2 bytes [31:16]
11 = 1 byte [31:24]
TENB must be asserted simultaneously for
TMOD[1: 0] to be valid .
4 x 8 Singl e-PHY mode: MOD[1:0] is not
required.
Transmit St art of Transfer.
32-bit Multi-PHY mode: TSX asserted with
TENB = 1 indicates that the PHY address is
present on TDA T[7:0]. The valid values on
TDAT[7:0] ar e 3, 2, 1, an d 0. Wh en
TENB = 0, TSX is not used by the PHY
device.
NOTE: Only TDAT[1:0] are relevant; all
other bits are “Don’t Care”.
4 x 8 Singl e-PHY mode: TSX is not used.
TADR[1:0] Transmit PHY Address.
The value on TADR[1:0] selects one of the
PHY ports that drives the PTPA signal after
the rising edge of TFCLK.
40Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Tabl e 3. SPI3 Interface Signal Description s (Sheet 4 of 8)
Signal Name
MPHYSPHY
DTPA_0
DTPA_1
DTPA_2
DTPA_3
STPANAC11Output
DTPA_0
DTPA_1
DTPA_2
DTPA_3
Ball
Designator
D3
L1
A9
J7
TypeStandardDescription
Output
3.3 V
LVTTL
3.3 V
LVTTL
DTPA_0:3 Dir ect Transmit Packet
Available.
A direct status indication for transmit FIFOs
of ports 0:3.
When Hig h, DTP A in dica tes that the amo unt
of data in the TX FIFO is below the TX FIFO
High watermark. When the High watermark
is crossed, DTPA transitions Low to indicate
that the TX FIFO is almost full. It stays Low
until the amount of data in the TX FIFO
goes back below the TX FIFO Low
watermark. At this point, DTPA transitions
High to indicate that the programmed
number of bytes are now available for data
transfers.
NOTE: For more information, see
Table 132 “TX FIFO High
Watermark Ports 0 - 3 ($0x600 –
0x603)” on page 202 and T able 133
“TX FIFO Low Watermark Register
Ports 0 - 3 ($0x60A – 0x60D)” on
page 203.
DTPA is updated on the rising edge of
TFCLK.
Select ed -P H Y Trans mit Packet Available.
STPA is only meaningful in a 32-bi t multiPHY mode.
STPA is a direct status indication for
transmit FIFOs of ports 0:3.
When Hi gh , S TPA indi cate s t h at t he am ount
of data in the TX FIFO, specified by the
lates t in-band address, is below the
TX FIFO High watermark. When the High
watermar k i s cros sed , S T PA transi tion s Lo w
to indicate the TX FIFO is almost full. It
stays Low until the amo unt of data in t he
TX FIFO goes back below the TX FIFO Low
watermark. At this point, STPA transitions
High to indicate that the programmed
number of bytes are now available for data
transfers.
NOTE: For more information, see
STPA provides the status indication for the
select ed port to avoid FIFO overflows while
polling is performed. The port reported by
STPA is updated on the following ri s ing
edge of TFCLK after TSX is sampled as
asserted. STPA is updated on the rising
edge of TFCLK.
Table 132 “TX FIFO High
Watermark Ports 0 - 3 ($0x600 –
0x603)” on page 202 and T able 133
“TX FIFO Low Watermark Register
Ports 0 - 3 ($0x60A – 0x60D)” on
page 203.
PTPA allows th e polling of t he port selected
by the TADR address bus.
When High, PTPA indicates that the amount
of data i n t he TX F IFO i s be low th e TX FIF O
High watermark. When the High watermark
is crossed, PTPA transitions Low to indicate
that the TX FIFO is almost full. It stays Low
until the amount data in the TX FIFO goes
back belo w the TX FIFO Low wat erm ar k. At
this poin t, PTPA transitions Hig h to indic at e
that the programmed number of bytes are
now ava ilable for data t ran sfers.
NOTE: For more information, see
The port r eported by PTPA is updated on
the following rising edge of TFCLK after the
port address on TADR is sampled by the
PHY device.
PTPA is updated on the rising edge of
TFCLK.
Receive Data Bus.
RDAT carries payload data and in-band
addres ses from the IX F1104.
Mode
32-bit Multi-PHY
4 x 8 Single- PHY
Receive Data Bus.
RDAT carries payload data and in-band
addres ses from the IX F1104.
Mode
32-bit Multi-PHY
4 x 8 Single- PHY
Receive Data Bus.
RDAT carries payload data and in-band
addres ses from the IX F1104.
Mode
32-bit Multi-PHY
4 x 8 Single- PHY
T able 132 “TX FIFO High
Watermark Ports 0 - 3 ($0x600 –
0x603)” on page 202 and Table 133
“TX FIFO Low Watermark Register
Ports 0 - 3 ($0x60A – 0x60D)” on
page 203.
Bits
[31:24]
[7:0] for port 3
Bits
[23:16]
[7:0] for port 2
Bits
[15:8]
[7:0] for port 1
42Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Tabl e 3. SPI3 Interface Signal Description s (Sheet 6 of 8)
RDAT carries payload data and in-band
addresses from the IXF1104.
Mode
32-bit Multi-PHY
4 x 8 Single- PH Y
Receive Clock.
RFCLK is the clock associated with al l
receiv e si gn als . D ata and controls are
driven on the rising edge of RFCLK
(freq uency operation range 90 - 133 M Hz).
Receive Parity.
RPRTY indicates odd parity for the RDAT
bus. RPRTY is valid only when a channel
asserts RENB or RSX. Odd parity is the
default configuration; however, even parity
can be selected (see Table 147 on
page 214).
32-bit Multi- PHY mode: RPRTY_0 is the
parity bit for all 32 bits.
4 x 8 Single-PHY mode: Each bit of
RPRTY_0:3 corresponds to the respective
RDAT[3:0]_n channel.
Receive Read Enable.
The RENB signal controls the flow of data
from the receive FIFOs. During data
transfer, RVAL must be monitored as it
indicates if the RDAT[31:0 ], RPRT Y,
RMOD[1:0], RSOP , REOP, RERR, and RSX
are valid. The system m ay de-assert REN B
at any time if it is unable to accept data from
the IXF1104. When RENB is sampled Low,
a read is performed from the receive F IFO
and the RDAT[31:0], RPRTY, RMOD[1:0],
RSOP, REOP, RERR, RSX and RVAL
signa ls are updated o n the following rising
edge of RFCLK.
When RENB is sampled High by the PHY
device, a read is not performed, and the
RDAT[31:0], RPRTY, RMOD[1:0], RSOP,
REOP, RERR, RSX, and RVAL signals
remain unchanged on the following rising
edge of RFCLK.
32-b it Mu lti- PH Y Mo de: RENB_0 covers all
receive bits.
4 x 8 Single-PHY Mode: The RENB_0:3
bits correspond to the per-port data and
control signals.
IXF1104 4-Port Gi gab it Ethernet Media Access Controller
Table 3. SPI3 Interface Signal Descript ions (Sheet 7 of 8)
Signal Name
MPHYSPHY
RERR_0RERR_0
RERR_1
RERR_2
RERR_3
RVAL_0RVAL_0
RVAL_1
RVAL_2
RVAL_3
RSOP_0RSOP_0
RSOP_1
RSOP_2
RSOP_3
Ball
Designator
A16
G17
D20
H20
C15
B18
E19
F22
B16
C18
E23
J18
TypeStandardDescription
Receive Error.
RERR indicates that the current packet is in
error. RERR is only asserted when REOP is
asserted. Conditions that can cause RERR
to be set include FIFO overflow, CRC error,
code error, and runt or giant packets.
NOTE: RERR can only be set fo r these
Output
Output
Output
3.3 V
LVTTL
3.3 V
LVTTL
3.3 V
LVTTL
RERR is considered valid only when RV AL
is asserted.
32-bit Multi-PHY mode: RERR_0 covers
all 32 bits.
4 x 8 Singl e-PHY mode: T he RERR_0:3
bits correspond to the RDAT[7:0]_n
channels.
(n = 0, 1, 2, or 3)
Receive D ata Valid.
RVAL indicates the validity of the receive
data signals. RVAL is Low between
transfers and assertion of RSX. It is also
Low when the IXF1104 pauses a transfer
due to an empty receive FIFO. When a
transfer is paused by holding RENB High,
RVAL holds its value unchan ge d, although
no new data is present on RDAT[31:0] unti l
the transfer resumes. When RVAL is High,
the RDAT[31:0], RMOD[1:0], RSOP, REOP,
and RERR signals are valid. When RVAL is
Low, the RDAT[31:0], RMOD[1:0], RSOP,
REOP, and RERR signals are invalid and
must be disregarded.
The RSX signal is valid only when RVAL is
Low.
32-bit Multi-PHY mode: RVAL_0 covers all
receive bits.
4 x 8 Singl e-PHY mode: The RVAL_0:3
bits co rrespond to the per-port data and
contr o l si gn al s.
Receive Start of Packet.
RSOP indicates the start of a packet when
asserted with RVAL.
32-bit Multi-PHY mode: RSOP_0 covers
all 32 bits.
4 x 8 Singl e-PHY mode: The RSOP_0:3
bits correspond to the RDAT[7:0]_n
channels.
conditions if bit 0 in the “SPI3
Receive Configuration ($0x701)” is
set to 1.
44Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Tabl e 3. SPI3 Interface Signal Description s (Sheet 8 of 8)
Signal Name
MPHYSPHY
REOP_0REOP_0
RMOD1
RMOD0
RSXNAE13Output
REOP_1
REOP_2
REOP_3
NA
Ball
Designator
C16
D18
C23
J19
G13
G14
TypeStandardDescription
Output
Output
3.3 V
LVTTL
3.3 V
LVTTL
3.3 V
LVTTL
Receive End of Packet.
REOP in dicates the end of a packet when
asserted with RVAL.
32-bit Multi- PHY mode: REOP_0 covers
all 32 bits.
4 x 8 Single-PHY mode: The REOP_0:3
bits correspond to the RDAT[7:0]_n
channels.
Receive Word Modulo :
32-bit Multi- PHY mode: RMOD[1:0]
indicates the valid bytes of data in
RDAT[ 31:0] . During transmission, RMOD is
always “00”, except when the last doubleword is transferred on RDAT[31:0].
RMOD[1:0] specifies the valid packet data
bytes on RDAT[31:0] when REOP is
asserted.
RMOD[1:0]Valid Byte s of RDAT
00 =4 bytes [31:0]
01 =3 bytes [31:8]
10 =2 bytes [31:16]
11 = 1 byte [31:24]
4 x 8 Single-PHY mode: RMOD[1:0] is not
required.
RMOD is considered valid only when RVAL
is simultaneously asserted.
RENB must be asserted for RMOD[1:0] to
be valid.
Receive Start of Transfer.
32-bit Multi- PHY mode: RSX indicates
when th e in -ban d po rt a dd ress i s p re se nt o n
the RDAT bus. When RSX is High and
RVAL = 0, the value of RDAT[7:0] is the
address of the receive FIFO to be selected.
Subsequent data transfers on RDAT are
from the FIFO specified by this in- band
addres s. Values of 0, 1, 2, and 3 selec t the
corresponding port. RSX is ignored when
RVAL is de-asserted.
NOTE: Refer to the RGMII interface for shared dat a and clock signals.
Y4
AB4
AC3
AB3
AA3
Y3
Y2
Y1
AC9
AD8
AB8
AA7
AD9
AB9
AB7
AC7
AA18
AA20
AB19
AD16
AB23
AB22
AB21
AB20
W14
AA16
Y15
AA14
V17
V16
V15
V14
AB2
Y8
AC22
V12
W1
AD6
AD17
AB13
AA1
AD7
AC20
AB14
Output
Output
Output
Output
2.5 V
CMOS
2.5 V
CMOS
2.5 V
CMOS
2.5 V
CMOS
T ransmit Data.
Each bus carries eight data bits [7:0] of
the transmitted data stream to the PHY
device.
RGMII Mode: When a port is
configured in copper mode and the
RGMII interface is selected, only bits
TXD[3:0]_n are used. The data is
transmitted on both edges of TXC_0:3.
Fiber Mode: The fol lowing signals
have multiplexed functions when a port
is configured in fiber mode:
TXD4_n: TX_D ISA BLE _0 :3
T ransmit Enable.
TX_EN indicates that va lid data is
being dri ve n on the corres p on di ng
Transmit Data: TXD_0, TXD_1, TXD_2,
and TXD_3.
Transmit Error:
TX_ER indicates a transmit error in the
corresponding Transmit Data: TXD_0,
TXD_1, TXD_2, and TXD_3.
Source Synchronous Transmit
Clock.
This clock is supplied synchronous t o
the transmit data bus in either RGMII or
GMII mode.
UPX_CS_LR3Inp ut3.3 V LVTTL Chip Select. Active Low.
UPX_WR_LT4Input3.3 V LVTTL Write Strobe. Active Low.
UPX_RD_LV 6Input3 .3 V LVTTL Read Strobe. Ac tive Low.
IXF1104 4-Port Gi gab it Ethernet Media Access Controller
Table 11. LED Interface Signal Descriptions
Signal Name
LED_CLKK24Output
LED_DATAM22Output
LED_LATCHL22Output
Ball
Designator
Typ eStandard Description
Table 12. JTAG Interface Signal Descriptions
Signal Name
TCLKJ22Input
TMSH22Input
TDIJ24Input
TDOH24Output
TRST_LJ23Input
Ball
Designator
Typ eStandard Description
2.5 V
CMOS
2.5 V
CMOS
2.5 V
CMOS
2.5 V
CMOS
2.5 V
CMOS
2.5 V
CMOS
2.5 V
CMOS
2.5 V
CMOS
LED_CLK is the clock output for the LED block.
LED_DATA is the data output for the LED block.
LED_LATCH is the latch enable for the LED block.
JTAG Test Clock
Test Mode Select
Test Data Input
Test Data Output
Test Rese t; res e t input for JTAG test
Table 13. System Interface Signal Descriptions
Signal Name
CLK125AD19Input
SYS_RES_LAD12Input
Ball
Designator
Typ eStandard Description
2.5 V
CMOS
2.5 V
CMOS
CLK125 is the input clock to PLL; 125 MHz +/50 ppm
SYS_RES_L is the system hard reset (active Low).
54Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 14. Power Supply Signal Descriptions
Signal NameBall DesignatorTypeStandard Description
F6
M8
R6
W2
B8
M2
N6
U2
B6
D4
D17
F10
H4
H17
K2
K14
L5
L15
M11
N4
N17
P13
R7
R16
T15
U13
W6
W23
AA13
AC6
AC19
D6
D19
H15
K4
L9
P9
R4
T11
W4
AA15
B12
H2
M6
B21
H19
M16
N19
U23
AC13
N9
U6
AC4
A21
A4
F2
K9
B4
F8
B19
D13
F23
H13
J15
K11
K23
L13
M21
N14
P12
R14
T10
U12
W19
AA12
AB12
AC15
C12
D15
H10
J20
K21
L16
P16
R21
U15
AA10
F12
B17
F17
M13
N16
U19
AA23
AA2
B15
D12
F19
H12
J10
K19
L12
M4
GND
AVDD1P8_1A5A20Input1.8 VAnalog 1.8 V supply
AVDD1P8_2AB16T23Input1.8 VAnalog 1.8 V supply
AVDD2P5_1AD20Input2.5 VAnalog 2.5 V supply
AVDD2P5_2U14R18Input2.5 VAnalog 2.5 V supply
Fiber mode is the default. Copper interfaces are
disabled.
Fiber mode is the default.
Bit 4 is dri v en by the optical module as MOD_DEF_0.
Fiber mode is the default.
Bit 4 is dri v en by the optical module as MOD_DEF_1.
Fiber mode is the default.
Bit 4 is dri v en by the optical module as MOD_DEF_2.
Fiber mode is the default.
Bit 4 is dri v en by the optical module as MOD_DEF_3.
Fiber mode is the default.
Copper in ter f ac es ar e di sa bl ed.
Fiber mode is the default.
Copper in ter f ac es ar e di sa bl ed.
Fiber mode is the default.
Copper in ter f ac es ar e di sa bl ed.
TX_P_0:30x0–
TX_N_0:30x0–
TX_FAULT_INTHigh ZOpen-drain output, requires external pull-up.
RX_LOS_INTHigh ZOpen-drain output, requires exter nal pull-up.
MOD_DEF_INTHigh ZOpen-drain output, requires exter nal pull-up.
IXF1104 4-Port Gi gab it Ethernet Media Access Controller
4.7Power Supply Sequencing
Follow the power-up and power-down sequences described in this section to ensure correct
IXF1104 operation. The sequence described in Section 4.7 covers all IXF1104 digital and analog
supplies.
Caution:Failure to follow the seque nce described in this section might damage the IXF1104.
4.7.1Power-Up Sequence
Ensure that the 1.8 V analog and digital supplies are applied and stable prior to application of the
2.5 V analog and digital supplies.
4.7.2Power-Down Sequence
Remove the 2. 5 V suppli es prior t o removi ng the 1 .8 V power supp lie s (the reverse of the po wer -up
sequence).
Caution:Damage can occur to the ESD structur es within the analog I/Os if the 2.5 V digital and analog
supplies exceed the 1.8 V digital and analog supplies by more than 2.0 V during power-up or
power-down.
Figure 5 and Table 19 provide the IXF1104 power supply sequencing.
Figure 5. Power Sup pl y Se quencing
1.8 V Supplies Stable
t=0
Apply VDD, AVDD1P8_1, and
AVDD1P8_2
NOTE: The 3.3 V suppl y (VDD2 and VDD3) can be applied at any point during this sequence.
2.5 V Supplies Stable
Time
Sys_Res
Apply VDD4, VDD5,
AVDD2P5_1 and AVDD2P5_2
62Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
Table 19. Power Supply Sequencing
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Power SupplyPowe r-U p Ord er
VDD, AVDD1P8_1,
AVDD1P8_2
VDD4, VDD5,
AVDD2P5_1,
AVDD2P5_2
1. The value of 10 µs given is a nominal value only. The exact time difference between the application of the 2.5 V analog
supply is determined by a number of factors, depending on the power management method used. To avoid damage to the
IXF1104, the TXAV25 supply must not exceed the VDD supply by more than 2 V at any time during the power-u p or
power-down sequence.
NOTE: The 3.3 V supply (VDD2 and VDD3) can be applied at any point during this sequence.
First01.8 V supplies
Second10 µs2.5 V supplies
Time Delta to
Next Supply
1
4.8Pull-Up/Pull-Down Ball Guidelines
The signals shown in Table 20 require the add ition of a pull-up or pull-down resistor to the board
design for normal oper ation. Any balls marked as unused (NC) should be unconnected.
Table 20. Pull-Up/Pull-Down and Unused Ball Guidelines
Pin Name Pull-Up/Pull-DownCom m en ts
TX_FAULT_INTPull-up4.7 k Ω to 2.5 V. Optical module signal with open-drain I/O.
RX_LOS_INTPull-up4.7 k Ω to 2.5 V. Optical module signal with open-drain I/O.
MOD_D EF_INTP ull - up4.7 k Ω to 2.5 V. Optical module signal with open-drain I/O.
TDIPull-up10 k Ω to 3.3 V. JTAG test pin.
TDOPull-up10 k Ω to 3.3 V. JTAG test pin.
TMSPull-up10 k Ω to 3.3 V. JTAG test pin.
TCLKPull-up10 k Ω to 3.3 V. JTAG test pin.
TRST_LPull-down10 k Ω to 3.3 V. JTAG test pin.
MDIOPull-up4.7 k Ω to 2.5 V
UPX_RDY_LPull-up4.7 k Ω to 3.3 V
2
C_DATA_0:3P ull-up4.7 k Ω to 2.5 V
I
TX_DISABLE_0:3Pull-up4.7 k Ω to 2.5 V
Notes
4.9Analog Po wer Filtering
Figure 21 illustrates an analo g power supply filter network and Table 21 lists the an al o g po w er
Need to provide a filter (see Figure 6).R: A VDD1P8_1 and AVDD2P5_1 = 5.6 Ω resistor.
Need to provide a filter (see Figure 6).
R: A VDD1P8_2 and AVDD2P5_2 = 1.0 Ω resistor.
64Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
5.0Functional Descriptions
5.1Media Access Controller (MAC)
The IXF1104 main functional block consists of four independent 10/100/1000 Mbps Ethernet
MACs, which support interfaces for fiber and copper connectivity.
• Copper Mode:
— RGMII for 10/100/1000 Mbps full-duplex opera tion and 10/100 Mbps half-duplex
operation
— GMII for 1000 Mbps full-duplex operation
• Fiber Mode:
— Integrated SerDes/OMI interface for direct connection to optical module s
— 1000 Mbps full-duplex operation in fi ber mode
The following features support copper and fiber modes:
• Programmable Options:
— Automatic padding of transmitted packets that are less th an the minimum frame size
— Broadca s t, mu lt icast, and unicast addr es s fi lt er i ng o n fra m e s re ce iv ed
— Filter and drop packets with errors
— Pre-padded RX frames with two bytes (aligns the Ethernet payload on SPI3 and in
network proces sor memories)
— Remove CRC from RX f rames
— Append CRC to transmit ted frames
• Performance Monitoring and Diagnostics:
— Loopback modes
— Detection of runt and overly large packets
— Cyclic Redundancy Check (CRC) calculation and error detection
— RMON statistics for dropped packets, pack ets with errors, etc.
• Compliant with IEEE Spec 802.3x standard for flo w control
— Receive and execute PAUSE Command Frames
• Support for non-standard packet sizes up to 10 KB including loss-les s fl ow control
Note: The IXF1104 does not support 10/ 100 Mbps operation when configured in GMII mode
The MAC is fully integrated, designed for use with Ethernet 802.3 frame types, and compliant to
all of the IEEE 802 .3 MAC r equirements.
The MAC adds preamble and Start-of-Frame Delimiter (SFD) to all frames sent to it (transmit
path) and removes preamble and SFD on all frames rec eived by it (receive path). A CRC check is
also applied to all transmit and receive packets . CRC is optionally appended to transmit packets.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
CRC is removed optionally from receive packets after validation, and is not forwarded to SPI3.
Packets wit h a bad CRC are marked, counted in the statistics block, and may be optionally
dropped. A bad packet m ay be signaled with RERR on the SPI3 interface if it is not dropped.
The MAC operates only in full-duplex mode at 1000 Mbps rates on both SerDes and GMII
interface connections. The MAC is capable of operation at 1000 Mbps, full-duplex in RGMII
mode, and at full-du plex and half-duplex operation for 10/100Mbps links .
5.1.1Features for Fiber and Copper Mode
Section 5.1.1.1 through Section 5. 1.1.4 cover MAC functions that are independe nt of the line-side
interface.
5.1.1.1Padding of Undersized Frames on Transmit
The padding feature allows Ethernet frames smaller than 64 bytes to be transf erred from the SPI3
interface to the TX MAC and padded up to 64 bytes automatically by the MAC. This featur e is
enabled by setting bit 7 of the “Diverse Config Write ($ Port_Index + 0x18)".
Note: When the user selects the padding function, the MAC core adds an automatically calculated CRC
to the end of the tran smitted packet.
5.1.1.2Automatic CRC Generation
Automatic CRC Gene ration is used in con juncti on with the pa dding fea ture to ge nerate and appen d
a correct CRC to a ny tran smit f rame . Thi s feat ure is enab led by setti ng bit 6 of th e “Di ver se Conf i g
Write ($ Port_Index + 0x18)".
5.1.1.3Filte r ing o f R eceive Packets
This feature allows the MAC to filt er receive packets under various conditions and drop the
packets through an interaction with the Receive FIFO control.
5.1.1.3.1Filte r on U nicast Pack et Match
This feature is enabled when bit 0 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 1 .
Any frame received in t his mode tha t does not matc h the S ta tion Addre ss ( MAC address ) i s marked
by the MAC to be dropped. The fra me is dro pped if the appropriate bit in the “RX FIFO Errored
Frame Drop Enable ($0x59F)" = 1. Otherwise, the frame is sent out the SPI3 interface and may
optionally be signaled with an RERR (see bit 0 in “SPI3 Receive Configuration ($0x701)” on
page 214).
When bit 0 of the “RX Packet Filter Control ($ P ort_I ndex + 0x19)" = 0, all unic ast f rame s are s ent
out the SPI3 inter face.
Note: The VLAN filter overrides t he unicast filter. Therefore, a VLAN frame cannot be filtered based on
the unicast address.
66Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
5.1. 1.3.2Filter on Mult i cast Packet Ma tch
This feat u r e is en ab l ed w he n bi t 1 o f the “RX Packet Filter Control ($ Port_Index + 0x19)" = 1.
Any frame received in this mode that does not match the Port Multicast Addr ess (reserved
multicast a ddress recogni zed by MAC) i s marked by the MAC to be droppe d. The frame i s dr opped
if the appropriate bit in the “RX FIFO Errored Frame Drop Enable ($0x59F)" = 1. Otherwise, the
frame is sent out the SPI3 interface and may optionally be signaled with an RERR (see bit 0 in
“SPI3 Receive Configuration ($0x701)” on page 214).
When bit 1 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 0, all multic ast frames are
sent out the SPI3 interface.
5.1.1.3.3Filter Broadcast Packets
This feat u r e is en ab l ed w he n bi t 2 o f the “RX Packet Filter Control ($ Port_Index + 0x19)" = 1.
Any broadcast frame received in this mode is marked by the MAC to be dropped. The fr ame is
dropped if the appropri ate bit in the “RX FIFO Errored Frame Drop Enable ($0x59F)" = 1.
Otherwise, the fra me is sent out the SPI3 interface and may optionally be signaled with an RERR
(see bit 0 in “SPI3 Receive Configuration ($0x701)” on page 214).
When bit 2 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 0, all broadcast frames are
sent out the SPI3 interface.
5.1.1.3.4Filter VLAN Packets
This feat u r e is en ab l ed w he n bi t 3 o f the “RX Packet Filter Control ($ Port_Index + 0x19)" = 1.
VLAN frames received in this mode are marked by the MAC to be dropped. The frame is dropped
if the appropriate bit in the “RX FIFO Errored Frame Drop Enable ($0x59F)" = 1. Otherwise, the
VLAN frame is sent out t he SPI3 in terfac e and may opt ionall y be si gnaled wi th a n RERR (see bit 0
in “SPI3 Receive Configuration ($0x701)” on page 214).
When bit 3 of the “RX Packet Filter Control ($ Port_Ind ex + 0x19)" = 0, all VLAN frames are sent
out the SPI3 interface.
5.1.1.3.5Filter Pause Packets
This feat u r e is en ab l ed w he n bi t 4 o f the “RX Packet Filter Control ($ Port_Index + 0x19)" = 0.
Pause frames receive d in this mode are marke d by the MAC to be dro pped. The fra me is droppe d if
the appropriate bit in the “RX FIFO Errored Frame Drop Enable ($0x59F)" = 1. Otherwise, the
pause frame is sent out the SPI3 interface and may optiona lly be signaled with an RERR (see bit 0
in “SPI3 Receive Configuration ($0x701)” on page 214).
When bit 4 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 1, all pause frames are sent
out the SPI3 interface.
Note: Pause packets are not filtered if flow control is disabled in the “FC Enable ($ Port_Index + 0x12)”.
5.1.1.3.6Filter CRC Error Packets
This feat u r e is en ab l ed w he n bi t 5 o f the “RX Packet Filter Control ($ Port_Index + 0x19)” = 0.
Frames receiv ed with an errored CRC are marked as bad f ram es and may optionally be dropped in
the RX FIFO. Otherwise, the frames are sent to the SPI3 interface and may be optionally signaled
with an RERR (see Table 22 “CRC Errored Packets Drop Ena ble Behavior” on page 68).
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
When the CRC Error Pass Filter bit = 0 (“RX Packet Filter Control ($ Port_Index + 0x19)”), it
takes precedence over the other filter bits. Any packet ( Pause, Unicast, Multicast or Broadcast
packet) with a CRC error will be mar k ed as a bad frame when th e CRC Error Pass Filter bit = 0.
Table 22. CRC Errored Packets Drop Enable Behavior
CRC Error
Pass
1xx
001
000
01x
1. See Table 91 “RX Packet Filter Control ($ Port_Index + 0x19)” on page 171.
2. See Table 123 “RX FIFO Errored Frame Drop Enable ($0x59F)” on page 195.
3. See Table 147 “SPI3 Receive Configuration ($0x701)” on page 214.
NOTE: x = “DON’T CARE”
RX FIFO Errored-
1
Frame Drop
Enable
2
RERR
Enable
Actions
3
When CRC Errored PASS = 1, CRC errored packets
are not filtered and are passed to the SPI3 interface.
They are not marked as bad, cannot be dropped, and
cannot be signaled with RERR.
Packets are marked as bad but not dropped in the
RX FIFO. These packets are sent to the SPI3
interface, and are s ignaled with an RERR to the
switch o r Network Processor.
Packets are marked as bad but not dropped in the
RX FIFO. These packets are sent to the SPI3
interface, and are not signaled w ith an RERR.
CRC errored packets are marked as bad, dropped in
the RX FIFO, and never appear at the SPI3 interface.
NOTE: Packet sizes above the RX FIFO Transfer
Threshold (see Table 128 through Ta bl e 13 1)
cannot be dropped in th e RX FIFO and are
passed to the SPI3 interface. These packets
can optionally be signaled with RER R on the
SPI3 interface if the RERR Enable bit = 1.
5.1.1.4CRC Error Detection
Frames re ceived by th e MAC are check ed for a correc t C RC. When an in co r rect CRC is det ected
on a received fr ame, the RX FCSError RMON statistic counter is incremented for each CRC
errored frame. Received frames with CRC errors may optionally be dropped in the RX FIFO (refer
to Section 5.1.1.3.6, “Filter CRC Error Packets” on pa ge 67). Otherwise, the frames are sent to the
SPI3 interfac e an d may be dropped by the switch or system controller.
Frames tr ansmitt ed by th e M A C are also checked f or co r r ec t CR C. When an in co r r ec t C RC is
detected on a tra nsmitt ed frame, the TX CRCError RMON stat isti c counter is in cremente d for e ach
incorrect frame.
5.1.2Flow Control
Flow Control is an IEEE 802.3x-defined mechanism for one network node to request that its link
partner take a temporary “Pause” in packet transmission. This allows the requesting network node
to prevent FIFO over runs and dropped pa ckets, by managing incoming traffic to fit its available
memory. The temporary pause allows the device to process packets already received or in trans it,
thus freeing up the FIFO space allocated to those packets.
68Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
The IXF1104 MAC im plements the IEEE 802 .3x standa rd RX FIFO thr eshol d-based F low Control
in copper and fiber modes. When appropriately programmed, the MAC can both generate and
respond to IEEE standard pa use frames in full-duplex operation. The IXF1104 also supports
externally triggered flow control through the Transmit Pause Control interface.
In half-duplex operation, the MAC generates collisions instead of sending pause frames to manage
the incoming tr affic from the link partner
5.1.2.1802.3x Flow Control (Full-Duplex Operation)
The IEEE 802.3x standard ide ntifies four options related to system flow control:
• No Pause
• Symmetric Pause (both direc tions)
• Asymmetric Pause (Rec eive direction only)
• Asymmetric Pause (T ransmit direction only)
The IXF1104 s upport s all fo ur opt ion s on a per-p ort b asis. Bit s 2:0 of t he “ FC Enab le ($ P ort_Inde x
+ 0x12)” on page 167 provide programmable control for enabl ing or disa bling flow cont rol in each
direction inde pendently.
The IEEE 802.3x f low control mechanism is accomplished within the MAC sublaye r, and is based
on RX FIFO thresholds called wate rmarks. The RX FIFO level rises and falls as packets are
received and processed. When the RX FIFO reaches a watermark (either exceeding a High or
dropping below a Low after exc eeding a High), the IXF1104 control sublayer signals an internal
state machine to tran smit a PAUSE frame. The FIFOs automatically generate PAUSE frames ( also
calle d co n trol fram e s ) to in itiate th e fo ll o w ing:
• Halt the link partner whe n the High watermark is rea ched.
• Restart the link partner when the data stored in the FIFO falls below the Low wat ermark.
Figure 7 illustrates the IEEE 802.3 FIFO flow control functions.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
M
Figure 7. Packet Buffering FIFO
SPI3 Interface
High Watermark
AC Transfer Threshold
TX FIFO
Data Flow
TX Side
MAC
MDI
Low Watermark
High Watermark
Low Watermark
RX FIFO
Data Flow
RX Side
MAC
RX FIFO High
TXPAUSEFR (External
Strobe)
802.3 Flow
Control
802.3x Pause Frame Generation
B3231-01
5.1.2.1.1Pause Frame For mat
PAUSE frames are MAC control frames that are padded to the minimum size (64 bytes). Figure 8
and Figur e 9 illustrate th e fr ame forma t and co n tents.
Figure 8. Ethernet Frame Fo rmat
Number of bytes
Note: 64 Byte Minimum / 1518 bytes Maximum
61466246-1500
Preamble
S
DASADataFCS
F
D
Type/
Length
Ethernet Frame
B2277-01
70Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
Figure 9. PAUSE Frame Format
46
Number of bytes
Note: In the Intel
The RX interface of the MAC will process this as the pause multicast or the MAC address.
614662
DA* or
S
01-80-
Preamble
®
IXF1104 architecture, the TX block of the MAC sets this as the pause multicast address.
F
C2-00-
D
00-01
SA88-08FCS
22
Pause
Opcode
(00-01)
64 Bytes
Pause
Length
42
Pad
(with 0s)
B3218-01
An IEEE 802.3 MAC PAUSE frame is identified by detecting all of the following:
• OpCode of 00-01
• Length/Type field of 88-08
• DA matching the unique multicast address (01-80-C2-00-00-01)
XOFF. A PAUSE frame inf orms the link partner to ha lt trans miss ion for a specified le ngth of time.
The PauseLength octets specify the duration of the no-transmit period. If this time is greater than
zero, the link partner must stop sending any further packets until this time has elapsed. This is
referred to as XOFF.
XON. The MAC continues to transmit PAUSE frames with the specified Pause Length as long as
the FIFO level exceeds the threshold. If the FIFO level falls below the threshold before the Pause
Length time expir es , the MAC sends another PAUSE frame with the Pause Length time specif ied
as zero. This is referred to as XON and informs the link partner to resume normal transmiss ion of
packets.
5.1.2.1.2Pause Settings
The MAC must send PAUSE frames repeatedly to maintai n the link partner in a Pause state. The
following two inter-related variables control this process:
• Pause Length is the amount of time, measured in multiple s of 512 bi t times, that the MAC
requests the link part ner to halt tra ns mi ssion for.
• Pause Threshold is the amount of time, measured in multiples of 512 bit times, prior to the
expiration of the Pause Length that the MAC transmits another Pause frame to maintain the
link partner in the pause state.
The transmitt ed Pause Length in the IXF1104 is set by the “FC TX Timer Value ($ Port_Index +
0x07)” on page 163.
The IXF1104 PAUSE frame transmissi on interval is set by the “Pause Threshold ($ Port_Index +
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
5.1.2.1.3Response to Rece i ved PAUSE Comm a nd Frames
When Flow Control is ena bled in the receive direction (bit 0 in the “FC Enable ($ P ort_Index +
0x12)"), the IXF1104 responds to PAUSE Command frames received from the link partner as
follows:
1. The IXF1104 checks the entire frame to verify that it is a valid PAUSE control frame
addressed to the Multicast Address 01-80-C2- 00-00-01 (as specified in IEEE 802.3, Annex
31B) or ha s a Destinations Address matching the address programmed in the “St ation Addre ss
($ Port_Index +0x00 – +0x01)" .
2. If the P AUSE fr ame is valid, the transmit side of the IXF1104 pauses for the required number
of PAUSE Quanta, as specified in IEEE 802.3, Clause 31.
3. PAUSE does not begin until completion of the frame currently being transmitted.
The IXF1104 response to valid received PAUSE frames is independent of the PAUSE frame filter
settings. Refer to Section 5.1.1.3.5, “Filter Pause Packets” on page 67 for additional details.
Note: Pause packets are not filtered if flow control is disabled in bit 0 of the “FC Enabl e ($ Port_Index +
0x12)”.
5.1.2.1.4Half-D u plex Oper ati o n
Trans mit flow control is implemented only in half-duplex operation. Upon entering the flow
control state, the MAC generates a collision for all subs equent receive packets until exiting the
flow contr ol state. Any receive packet in progress when the MAC en ters the flow control state will
not be collided with but could be lost due if there is insufficient FIFO depth to comp lete packet
reception. Bit 2 of the “FC Enable ($ Port_Index + 0x12)" enables the transmit flow control
function.
5.1.2.1.5Transmit Pau se Control In terface
The Transmit Pause Control interface allows an external device to trigger the generation of pause
frames. The Transmit Pause Control interfa ce is completely asynchronous. It consists of three
address signals (TXPAUSEADD[2:0]) and a strobe si gnal (TXPAUSEFR). The required address
for this interf ace operation is placed on the TXPAUSEADD[2:0] signals and the TXPAUSEFR is
pulsed High and returned Low. Refer to Figure 10 “Transmit Pause Con trol Interface” on page 73
and Table 55 “Transmit Pause Control Interface Timing Parameters” on page 150. Table 23 shows
the valid decodes for the TXPAUSEADD[2:0] si gnals. Figure 10 illustrates the transmit pause
control interface.
Note: Flow control must be enabled in the “FC E nable ($ Port_Index + 0x12)” for Transmit Pause
Control int erface operation.
Note: There are two additional decodes provided tha t allow the user to generate ei ther an XOFF frame or
XON frame from all ports simultaneou sl y.
The default pau se quanta for each port is he ld by the “FC TX T imer Value ($ Port _Index + 0x0 7)").
The default value of this register is 0x05E after reset is applied.
72Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
Table 23. Valid Decodes for TXPAUSEADD[2:0]
TXPAUSEADD_2:0Operation of TX Pause Control Interface
0x0
0x1
0x2
0x3
0x4
0x5 to 0x6
0x7
Transmits a PAUSE frame on every port with a pause_time = ZERO (XON)
(Cancels all previous pause commands).
Transmits a PAUSE frame on port 0 with pause_time equal to the value programmed
in the port 0
Transmits a PAUSE frame on port 1 with pause_time equal to the value programmed
in the port 1
Transmits a PAUSE frame on port 2 with pause_time equal to the value programmed
in the port 2
Transmits a PAUSE frame on port 3 with pause_time equal to the value programmed
in the port 3
Reserved. Do not use these addresses. The TX Pause Control inter face will not
operate under thes e conditions.
Transmits a PAUSE frame on every port with pause_time equal to the value
programmed in the
(XOFF).
“FC TX Timer Value ($ Port_Index + 0x07)" (XOFF).
“FC TX Timer Value ($ Port_Index + 0x07)" (XOFF).
“FC TX Timer Value ($ Port_Index + 0x07)" (XOFF).
“FC TX Timer Value ($ Port_Index + 0x07)" (XOFF).
Figure 10. Transmit Pause Control Interface
TXPAUSEFR
TXPAUSEADD0
“FC TX Timer Value ($ Port_Index + 0x07)" f or each port
TXPAUSEADD1
TXPAUSEADD2
This example shows the following conditions:
Strobe 1:
Port 0: Transmit Pause Packet (XOFF)
Strobe 2:
All Ports: Transmit Pause Packet with pause_time = 0 (XON)
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
5.1.3Mixed-Mode Operation
The Intel® IXF1104 giv es the user the op tio n of config uring each po rt for 10 /100 Mbps hal f-dupl ex
copper, 10/100/1000 Mbps full-duplex copper, or 1000 Mbps full-dupl ex fiber operation. This
gives the I n tel
opera ting at the same time within a single device. (Refer to Figure 16 “Line Side Interface
Multiplexed Balls” on page 57.)
®
IXF1104 the ability to support both copper and fiber operation line-side interfac es
The Intel
®
IXF1104 provides complete flexibility in line-side connectivity by offering RGMII,
integr at ed S er Des, and GMI I .
5.1.3.1Configuration of the IXF1104
The memory maps (Table 59 “MAC Control Registers ($ Port Index + Offset)” on page 155
through Table 69 “Optical Module Registe rs ($ 0x799 - 0x79F)” on page 161) are lo gically split
into the following two distinct regions:
• Per-Port Registers
• Global Registers
To achieve a desired configuration for a giv en port, the relevant per-port regi st ers mu st be
configured corr ectly by the user. The Table 59 through Table 69 also co n tain register s that affect
the operation of all ports, such as the SPI3 interface configuration.
See Section 8.0, “Regis ter Set” on page 154 for a complete de scription of IXF1104 configuration
and status registers. The Register Maps (Table 59 through Table 69) present a summary of
important configuration registers.
Note: The initialization sequence provided in Secti on 6.1, “Change Port Mode Initialization Sequence”
on pag e 1 29 must be followed for proper configuration of the IXF1104.
5.1.3.2Key Configuration Registers
The following ke y registers select the operational mode of a given port:
74Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
“MAC IF Mode
and RGMII
Speed ($
Port_ Index +
0x10)"
“Port Enable
($0x500)"
“Interf ac e Mode
($0x501)"
“Clock and
Interf ac e Mo de
Change Enable
Ports 0 - 3
($0x794)"
The initialization sequence provided in Section 6.1, “Change Port Mode Initialization
NOTE:
Register
Address
0x002 – Port 0
0x082 – Por t 1
0x102 – Port 2
0x182 – Port 3
0x010 – Port 0
0x090 – Por t 1
0x1 10 – Port 2
0x190 – Port 3
0x500
Bit 0 – Port 0
Bit 1 – Port 1
Bit 2 – Port 2
Bit 3 – Port 3
0x501
Bit 0 – Port 0
Bit 1 – Port 1
Bit 2 – Port 2
Bit 3 – Port 3
0x794
Bit 0 – Port 0
Bit 1 – Port 1
Bit 2 – Port 2
Bit 3 – Port 3
The “Desired Duplex ($ Port_Index + 0x02)” on page 162 de fines
whether a port is to be co nfigured for full-duplex or half-duplex
operation.
NOTE: Half-duplex op erat i on is o nl y v al id for 10/ 1 00 sp eeds w h ere t he
RGMII lin e interface ha s been selec te d.
The “MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)” on
page 166 determines the MAC operational freq uency and mode for a
given p ort.
NOTE: Set the “Clock and Interface Mod e Change Enable Ports 0 - 3
($0x794)” on page 220 to 0x0 prior to any change in the
register value. This e nsures that a change in the MAC clo ck
frequency is controlled correctly. If the “Clo c k an d Inte r fa c e
Mode Change Enable Ports 0 - 3 ($0x794)" is not us ed
correctly, the IXF1104 may not be configured to the proper
mode.
Each “Port Enab le ( $0x 500) " bit relates to a port. Set the appropriate bit
to 0x1 to enable a port. This should be the last step in the configuration
process for a port.
The “Interface Mode ($0x501)" selects whether a port operates with a
copper (RGMII or GMII) line-side interface an i ntegrated SerDes fiber
line-side interface.
For copper operation for a gi ven port, set the relevant bit to 0x1.
For fiber operation for a given port, set the relevant bit to 0x0.
NOTE: All ports are configured for fiber operation in the IXF1104
default mode of operation.
The “Clock and Interface Mode Change Enable Ports 0 - 3 ($0x794)"
indicates to an internal clock generator when to sample the new value
of the “MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)" and the
“Inter face Mode ($0x501)" (copper/fiber).
When any of these two configur ation values are changed for a port, the
corresponding bits must be kept in this register under reset by writing
0x0 to the relevant bit.
Description
Sequence” on page 129 must be followed for proper configuration of the IXF1104.
5.1.4Fiber Mode
When the IXF1104 is configured for fiber mode, the TX Data path from the MAC is an internal
10-bit interfa ce as descri bed in the IEEE 802.3z specific at ion. It is co nnecte d direct ly t o an intern al
SerDes block for serialization/deserialization and transmission/reception on the fiber medium to
and from the link partner.
The MAC contains all of t he PCS (8B /10B enc oding an d 10B/ 8B decod ing) require d to enco de and
decode the data. The MAC also supports auto-negotiation per the I EE E 802. 3z specification via
access to the “TX Config Word ($ Port _Ind ex + 0x17)", “RX Config Word ($ Port_Inde x + 0x16 )" ,
and “Diverse Config Write ($ Port_Index + 0x18)".
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
When configured for fiber mode, the full set of Optical Module interface c ontrol and status signals
is presented through re-use of GMII signals on a per-port basis (see Table 4.5 “Multiplexed Ball
Connections” on page 57). Fiber mode supports only full-dupl ex Gigabit operation.
5.1.4.1Fiber Auto-Negotiation
Auto-negotiatio n is pe rformed by using t he “ TX Config Word ($ Port_Index + 0 x17)", “RX Co nfig
Word ($ Port_Index + 0x16)", and “Diverse Config Write ($ Port_Index + 0x18)". When
autoneg_enable (“Diverse Config Wr ite ($ Port_Index + 0x18)") is set, the IXF1104 performs
hardw a re-defin ed auto-ne go t iation with the “TX Config Word ($ Port_Index + 0x17)" used as an
“Auto-Negotiation Advertisement ($ Port Index + 0x64)" and the “RX Config Word ($ Port_Index
+ 0x16)" used as an “Auto-Negotiation Link Partner Base Page Ability ($ Port Index + 0x65)".
Note: While the MAC supports auto-negotiat ion functions , the IXF1104 doe s not automatical ly configur e
the MAC or other devic e blocks to be consistent with the auto-negotiation results. This
configurati on is done by the user and system soft ware .
5.1.4.2Determining If Link Is Established in Auto-Negotiation Mode
A valid link is established when the AN_complete bit is set and the RX_Sync bit reports that
synchroniz ation has occ urred. Bot h register bit s are loc ated in the “RX Config Word ($ Port_Index
+ 0x16)".
If the link goes down a fter auto-negotiation is compl eted, RX_Sync indicates that a loss of
synchroniz ation oc curr ed. The IXF1 10 4 resta rts au to-negot ia tion and attempts to reest abl ish a li nk.
Once a link is reestablished, the AN_complete bit is set and the RX_Sync bit shows that
synchroniz ation has occurred.
To manually restart auto-ne gotiation, bit 5 of the “Diverse Config Write ($ Port_Index + 0x18)”
(AN_enable) must be de-asserted, then re-asserted.
5.1.4.3Fiber Forced Mode
The MAC fiber operation c an be forc ed to opera te at 100 0 Mbps full- duple x without comple tion of
the auto-negotiation function. In this mode, the MAC RX path must achieve s ynchronization with
the link partne r. Once achieved, the MAC TX path is enabled to allow data transmission. This
forced mode is limited to operation with a link partner that operates with a full-duplex link at
1000 Mbps.
5.1.4.4Determination of Link Establishment in Forced Mode
When the IXF1104 is in forced mode operation, the “RX Config Word ($ Port_Index + 0x16)” bit
20 RX Sync indicates when synchronization occurs and a valid link establishes.
Note: The RX Sync bit indicates a loss of synchronization when the link is down.
5.1.5Copper Mode
In copper mode, the IXF1 104 transmits data on the egress path of the RGMII or GMII inte rface,
depending on the port configuration defined by the user. The copper MAC receives data on the
ingress path of the RGMII or GMII interface, depending on the port configuration defined by the
76Datasheet
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user. The RGMII interface supports operation at 10/100/1000 Mbps when a full-duplex link is
established, and supports 10/100 Mbps when a half-duplex link is established. The GMII interface
only supports a 1000 Mbps full-duplex link.
5.1.5.1Speed
The copper MAC supports 10 Mbp s, 100 Mbps, and 1000 Mbps. All required speed adjustments,
clocks, etc., are supplied by the MAC. The operating speed of the MAC is programmable through
the “MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)" (MAC_IF_Mode). The IXF1104
speed sett ing must be programmed by the sys tem software to match the speed of the attached PHY
for proper IXF1 104 operation.
Note: When the IXF1104 is configured to use the GMII interfa ce, the only mode of operation that is
supported is 1000 Mbps full-d uplex.
If 10/100 Mbps operation is required in either full-dupl ex or ha lf-duplex, the IXF1104 must be
confi gu red to use the R G M I I interface.
5.1.5.2Duplex
The MAC supports full-duplex or half-duplex depending on the line-side interface that is
configured by the “MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)" (MAC_IF_Mode).
The duplex of the MAC is set in the “Desired Duplex ($ Port_Index + 0x02)” on page 162. The
IXF1104 duplex setting must be programmed by the system software to match the attached PHY
duplex for proper IXF1104 operation.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
5.1.5.3Copper Auto-Negotiation
In the copper MAC, auto-negotiation and all other controls of the PHY devices are achieved
through the MDIO interface, an d are independent of the MAC controller. See Section 5.5, “MDIO
Control and Interface ” on page 98 for further operation details .
Note: In copper mode, auto-negotiat ion is accompli shed by the att ached PHY, not the IXF110 4. Thus , the
IXF1104 doe s not automatically configure the MAC or other blocks in the device to be con sistent
with a tt a ch ed P H Y auto- n eg o ti at i on r esu l ts. This must be ac co mplish ed by th e us er an d sys t em
software.
5.1.6Jumbo Packet Support
The IXF1104 supports jumbo frames. The jum bo frame length is dependent on the application and
the IXF1104 design is optimized for a 9.6 KB jumbo frame length. Larger lengths can be
programmed, but limited system performance may lead to data loss during certain flow-control
conditions
The value programmed into the“Max Frame Size (Addr: Port_Index + 0x0F)" determi n es the
maximum length f rame size th e MAC can re ceive or tra nsmi t withou t a ctiva ting a ny error c oun ters,
and without truncation.
The“Max Frame Size (Addr: Port_Index + 0x0F)" bits 13:0 set the frame length. The default value
programmed into thi s regist er is 0x05EE (1518). The value is int ernall y adjus ted by +4 if the frame
has a VLAN tag. The overall programmable maximum is 0x3FFF or 16383 bytes.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
The register should be programmed to 0x2667 for the 9.6 KB length jumbo frame, optim ized for
the IXF1 104. The RMON counters are also implemented for jumbo frame support as follows:
The IXF1104 checks the CRC for all legal-length jumbo frames (frames between 1519 and the
Max Frame Size). On transmission, the MAC can be program me d to append the CRC to the frame
or check the CRC and increment the appropriate counter. On reception, the MAC transmits these
frames across the SPI3 i nterface (jumb o f rames above the s etting in the “RX FIFO Transfer
Threshold Port 0 ($0x5B8)” with a bad CRC cannot be dropp ed and are sent across the SPI3
interface). If the receive frame has a bad CRC, the appr opriate counter is in cr emented and the
RxERR flag is assert ed on th e S PI 3 re ceive inter f a ce.
Jumbo frames also impact flow control. The maxim um frame size needs to be taken into account
when determining the FIFO watermarks. The current transmission must be completed before a
Pause frame is transmitted (needed when the receiver FIFO High watermark is exceeded). If the
current trans m ission is a jumbo frame, the delay may be significant and increase data loss due to
insufficient available FIFO space.
5.1.6.3Loss-less Flow Control
The IXF1104 s upports loss-less flow control when the size of a Jumbo packet is restricted to
9.6 k bytes. If this conditi on is met, th e IXF1 104 has suff icien t memory resourc es al locat ed to each
MAC port to ensure that, if both the IXF1104 and link partner are required to send Pause packets
simultaneo us ly during jumbo packet transfers across a medium of five kilometers of fiber, no
packet data should be lost due to FIFO overflows.
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Document Number: 278757
Revision Number: 007
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IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
5.1.7Packet Buffer Dimensions
5.1.7.1TX and RX FIFO Operation
5.1.7.1.1TX FIFO
The IXF1104 TX FIFOs are imple me nted with 10 KB for each channel. This provides enough
space for at least one maximum size (10 KB) packet per-port storage and ensures that no under-run
conditions occur, assuming that the sending devi ce can supply data at the required data rate.
A transfer to MAC Threshold para meter, which is user -programmable, determines when the FIFO
signals to the MAC that it has data to s end. This is configured for specific block size s , and the user
must ensure that an under-run does not occur. Also, the threshold can be set above th e maxim um
size of a normal Ethernet packet. This causes the FIFO to send only data to the MAC when this
threshold is exceeded or when the End-of-Packet marker is received. This second condition
elimin ates the possib ility of under - run, except when the controlling switch device fails. It ca n ,
however, cause idle times on the media.
5.1. 7.1.2RX FI F O
The IXF1104 RX FIFOs are provisioned so that each port has its own 32 KB of memory space .
This is enough memory to ens ure that there is never an over -run on any channel while transferring
normal Ethernet frame size data.
The FIFOs automatic ally generate Pause control frames to halt the link partner when the High
watermark is re ache d an d to r esta rt th e lin k par tne r whe n the da ta store d in t he FI FO fall s below th e
low-watermark. The RX and TX FIFOs have been sized to support lossless flow control with
9.6 KB packets. The RX FIFO has a programmable tr ansfer threshold that sets the thresh old at
which packets becom e “c ut through” and starts transiti oning to the SPI3 interface before the EOP
is rece iv ed. Packets si zes below this threshold are treated as “store an d forward.” Once a pa ck et
size exceeds th e RX FIFO trans fer thres hold, i t can no lon ger be dropped by the RX FIFO even if it
is marked to be dropped by the MAC.
5.1.8RMON Statistics Support
The IXF1104 supplies RMON statistics through the CPU interface. T hese statistics a re available in
the form of counter v alues that can be accesse d at specific addresses in the register maps (Table 59
through Table 69). Once read, these counters automatically reset and begin counting from zero. A
separate set of RMON statistics is available for each MAC device in the IXF1104.
Implementation of the RMON Statistics block is simil ar to the functionality provided by existing
Intel switch and router products. This implementation allows th e IXF1104 to provide all of the
RMON Statistics group as defined by RFC2819. The IXF1104 supports the RMON RFC2819
Group 1 statistics counters. Table 25 notes the differences and a dditional statistics registers
supported by the IXF1104 that are outside the scope of the RMON RFC2819 docum ent.
etherStatsBroadcastPktsCounter32 RxBCPkts/TxBCPktsCounter 32
etherStatsMulticastPktsCounter32 RxMCPkts/TxMCPktsCounter 32 See table note 2
etherStatsCRCAlignErrorsCounter32
etherStatsUndersizedPktsCounter32
etherStatsOversizePktsCounter32
NOTE: The RMON specification requires that this is, “The total number of events where packets were dropped
by the probe due to a lack of resources. This number is not necessarily the number of packets dropped;
it is the number of times this condition is detected." The “RX FIFO Overflow Frame Drop Counter Ports 0
- 3 ($0x594 – 0x597)" and “TX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x621 – 0x624)" in the
IXF1104 support this and incr ement when ei ther an RX FIFO or TX FIFO overflows. If any IXF1104
programmable packet filtering is enabled, the “RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2
- 0x5A5) " an d “TX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x625 – 0x629)" increment w i th eve r y
frame removed in addition to the existing frames counted due to FIFO overflow.
The IXF1104 has two
counters for receive
and tra nsm it that us e
different naming
conventions for the
total Octets and
Octets Bad. These
counters must be
combined to meet
the RMON definition
for this statistic.
The IXF1104 has
three counters for the
etherStatsPkts that
must be combined to
give the total packets
as defined by the
RMON specification.
Same as RMON
specification
The IXF1104 has two
counters for the
alignment and CRC
errors for the RX side
only.
The IXF1104 has a
CRC Error counter
for the TX side.
The IXF1104 has two
counters, one for
Runt errors and one
for ShortErrors.
Same as RMON
specification
80Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
Table 25. RM ON Add itional Statistics (Sheet 2 of 2)
etherStatsStatus
NOTE: The RMON specification requires that this is, “The total number of events where packets were dropped
by the probe due to a lack of resources. This number is not necessarily the number of packets dropped;
it is the number of times this condition is detected." The “RX FIFO O verf l ow Fr ame Dr op C ou nter Por ts 0
- 3 ($0x594 – 0x597)" and “TX FIFO Ov erflow Frame Drop Counter Ports 0 - 3 ($0x621 – 0x624)" in the
IXF1104 support this and incr ement when either an RX FIFO or TX FIFO overf lows. If any IXF1104
program mab le p ac ket fi lt eri ng is en ab le d, t he “RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2
- 0x5A5)" and “TX FIFO Erro r ed Fr ame Dro p Co un ter Por t s 0 - 3 ( $0x 625 – 0x6 29 )" increment with every
frame removed in addition to the existing frames counted due to FIFO overflow.
The TxTotalColli s ion
count value is
equiva lent to the
RMON specification
minus the
TxLateCollision
Same as RMON
specification
Same a RMON
specification
Same a RMON
specification
Same a RMON
specification
Same a RMON
specification
Same as RMON
specification
5.1.8.1Conventions
The following conventions are used throughout the RMON Management Informati on Base (MIB)
and its companion documents.
• Good Packets: E rror-free packets that have a valid frame length. For example, on Etherne t,
good packets are error-free packets that are between 64 and 1518 octets long. They follow the
form defined in IEEE 802.3, Section 3.2.
• Bad Packet s: Ba d packe ts a re pack ets that hav e proper fr aming a nd reco gnized as packe ts, b ut
contain errors within the packet or have an invalid length. For example, on Ethernet, bad
packets have a valid preamble and SFD, but have a bad CRC, or are either shorter than 64
octets or longer than 1518 octets.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
5.1.8.2IXF1104 Advantages
The following lists additional IXF1104 registers that support features not documented in RMON:
• MAC (flow) control frames
• VLAN Tagged
• Sequence Errors
• Symbol Errors
• CRC Error
These additi onal counters allow for differentiation beyond standard RMON probes.
Note: In fiber mode, a packet transfer with an invalid 10-bit symbol does not always update the s tatistics
registers correctly.
• Behavior: T he IXF1104 8B10B decoder substitutes a valid code word octet in its place. The
packet transfer is aborted and marked as bad. The new internal length of th e packet is equal to
the byte position where the invalid symbol was. No packet fragme nts are seen at the next
packet transfer.
• Issue: If the invalid 10-bit code is inserted in a byte position of 64 or greater, expected RX
statistics are reported. However , if the invalid code is inserted in a byte position of less than
64, expe ct ed RX st at is t i cs ar e n o t sto r ed.
5.2SPI3 Interface
The IXF1104 SP I 3 Interface is implemented to the System Packet Inte rface Level 3 (SPI3)
Physical Layer Interface standard. The interface function allows the IXF1104 MAC blocks to
interface to higher-layer network processors or switch fabric.
The transmit interface allows data flows from a network processor or switch fabric device to the
IXF1104. The receive interface allows data to flow from the IXF1104 to the network processor or
switc h f ab r ic device .
This interf ac e rec eives and transmits data between the MAC and the Net work P r oce ssor with
compliant S P I3 interfaces. The SPI3 interface operation is defined in the OIF-SPI3-01.0 (ava ilable
from the Optical Internet Working Fo rum [www.oiforum.com]). The OIF specification defines
operation for the transfer of data at data rates of up to 3.2 Gbps when operating at a frequency of
104 MHz. The IXF1 104 defines operation for the transfer of dat a at data rates of up to 4.256 Gbps
when operating at a maximum fr eque ncy of 133 MHz in MPHY mode and 125 MHz in SPHY
Mode.
There is no guarant ee of the number of bytes available since the size of packets is variable. An
IXF1104 port-transmit packet available status is provided on signals DTPA, STPA or PTPA,
indicating the TX FIFO is nearly full.
In the receive direction, RVAL indicates if valid data is available on the receiv e dat a bus and is
defined so that dat a transfers can be aligned with packet boundaries.
The SPI3 interfac e supports the following two modes of operation:
• MPHY or 32 bit mode (one 32-bit data bus)
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IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
• SPHY or 4 x 8 mode (four individual 8-bit data buses)
5.2.1MPHY Operation
The MPHY operati on mode is se lect ed wh en bit 21 of the“SP I3 T r ansmit and Global Confi gurati on
($0x700)” is set to 0 and bi t 7 of the “SPI3 Receive Configuration ($0x701)" is set to 1.
Data Path
The IXF1104 SPI3 interface has a single 32-bit data path in the MPHY configuration mode (see
Figure 13). The bus interface is point-to-point (one output driving only one input load), so a 32-bit
data bus would support only one IXF1104.
To support variable-length pac kets, the RMOD[1:0]/TMOD[1:0] signals are defined to specify
valid bytes in the 32-bit data bus structure. Each double-w ord must contain four valid bytes of
packet data until the last double-word of the packet t r ans f er, which is marked with the end of
packet REOP/TEOP si gnal. This last double-word of the trans f er contains up to four valid bytes
specified by the RMOD[1:0]/TMOD[1:0] signals.
The IXF1104 port selection is performed using in-band addressing. In the transmit directi on, the
network processor device selects an IXF1104 port by sending the address on the TDAT[1:0] bus
marked with the TSX signal a ctive and TENB signal inactive. All subse quent TDAT[1:0] bus
operations marked wit h th e TSX signal inactive and the TENB active are packet data for the
specified port.
In the receive direction, the IXF1104 specifies the selected port by sending the address on the
RDAT[1:0] bus marked with th e RSX sig nal active and RVAL signal inactiv e. All subseque nt
RDAT[1:0] bus operations marked with RSX inactive and RVAL active are packet dat a from the
specified port.
Note: See Table 17 “SPI3 MPHY/SPHY Interface” on page 58 for a complete list of the MPHY mode
signals. The cont rol s ignals with the port designator for Port 0 are the only ones used in MPHY
mode and they apply to all 4 ports. Table 3 “SPI3 Interface Signal Descriptions” on page 38
provides a comprehensive list of SPI3 signal descriptions.
5.2.1.1SPI3 RX Round Robin Data Transmission
The IXF1104 us es a round-robin protocol to service each of the 4 ports dependent upon the enable
status of the po rt and if th ere is data a vaila ble to be taken from the RX FI FO. The round robin ord er
goes from port 0, port 1, port 2, port 3, and back to port 0. A port is skipped and the next port is
serviced if it has no available tran smit data. The data transfer bursts are user-configurable burs t
lengths of 64, 128, or 256 bytes. The IXF1104 also has a configurable pause interva l between data
transfer bursts on the receive side of the interface. The RX SPI3 burst lengths and the pause
interval can be set in the “SPI3 Receive Configuration ($0x701)").
5.2.2MPHY Logical Timing
The SPI3 interface AC timing for MPHY can be found in Section 7.2, “SPI3 AC Timing
Specifications” on page 136. Logical timing in the following diagrams illustrates all signals
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
5.2.2.1Transmit Timing
In MPHY mode a packet transmi ssion starts with the TSX signal indica ting port address
information is on the data bus. The next clock cycle TENB and TSOP indicate present data on the
bus is the fi rst word i n th e pack et and a ll s ubsequ ent cl ocks will con tain va lid da ta as long as TENB
is active or until TEOP is asserted. Data transmission can be temporally halted when TENB goes
high then resume d when TENB is low. The valid bytes in the final word, during an active TEOP,
are indi ca te d by stat e o f TM O D [1 :0 ] .
Figure 11. MPHY Transmit Lo gi c al Tim in g
TFCLK
TENB
TSOP
TEOP
TMOD[1:0]
TERR
TSX
TDAT[31:0]
TPRTY
1
TPA
1. Applies to all transmit pack et available signals (STPA, PTPA, DTPA_0:3).
5.2.2.2Receive Timing
A packet is received when RSX indicates port address information on the data bus followed by
RSOP to indicate the data bus contains the fi rst word of a packet. All subseque nt data is valid only
while RVAL is High and until REOP is asserted. Receive data can be temporarily halted when
RENB is de-assert ed a nd starts again on the second rising edge of RFCLK following the assertion
of RENB. RMOD indicates the number of valid bytes in the last transfer when REOP is asserted.
0000 B1-B4B5-B8B41-B44 B45-B48 B49-B52B53-B56 B57
B0001
B3216-01
84Datasheet
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Revision Number: 007
Revision Date: March 25, 2004
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
5.2.2.3Cloc k R ates
In MPHY mode, the TFCLK and RFCLK can be independent of each other. TFCLK and RFCLK
should be common to the IXF1104 and the Network Processor. The IXF1104 requires a single
clock source for the transmit path and a single clock source for the receive path.
To allow all four IXF1104 ports to operate at 1 Gbps, the IXF1104 is designed to allow this
interface to b e ov ercloc ked. This all ows ope ration f or data trans fer at d ata ra tes of up to 4. 256 Gbp s
when operating at an overcl ocked frequency of 133 MHz.
Note: MPHY mode operates at a maximum clock frequency of 133 MHz (TFCLK and RFCLK).
5.2.2.4Parity
The IXF1104 ca n be odd or even (the IXF1104 is odd by default) when calculating parity on the
data bus. This can be cha nged to accommodate even parity if desire d, and can be set for transmit
and receive independently. The RX Parity is set in bit 12 of the “SPI3 Receive Configuration
($0x701)” and the TX Parity is set in bit 4 of the “SPI3 Transmit and Global Configuration
($0x700)”.
5.2.2.5SPH Y M o d e
The SPHY operation mode is selected when bit 21 of the Table 146 “SPI3 Transmit and G lobal
Configuration ($0x700)” on page 212 is set to 1. The SPHY mode is the default operation for the
IXF1104 SPI3 interface.
5.2.2.5.1Data Path
The IXF1104 SPI3 interface has fou r 8-bit data paths that ca n support four independent 8-bit pointto-point connections in SPHY mode (see Figure 16). Since each MAC port has it s own de dicated
8-bit SPI 3 data bus, each port has it own status signal (unlike MPHY). See the For a detaile d list of
all the signal s re fer to the SPI3 pin multiplexing table.. ..
Furthermore s ince each port has it own dedicated bus the in band port addressing is not needed.
The 8 bit data bus elim inates the need to have separate control signals determine the number of
valid bytes on an EOP.Therefore TSX, RSX, TMOD[1:0] RMOD[1:0] are not used in SPHY m ode.
Note: See Table 17 “SPI3 MPHY/SPHY Interface” on page 58 for a complete list of the SPHY mode
signals. Unlike MPHY mode, each port has a dedicated control signal associated with each of the
per-po rt 8-bit data buses. Table 3 “SPI3 Interface Signal Descriptions” on page 38 provides signal
descriptions for all SPI3 signals.
5.2.2.5.2Receive Data Transmission
Packets are transmitted on each port as they become available from the RX FIFO. The burst length
is determine d by the s etting of per port burst size and the B2B pause settings in the “SPI3 Receive
Configuration ($0x701)". If the B2B pause setting is zero pause cycles inserted, then the entire
packet will be burs t without any pauses unless the Network Process or de-asserts RENB. If the
B2B_Pa use s et tin g call s fo r the in ser tio n of two pa us e cy cl es on a por t , th ese a re i ns ert ed a fte r ea ch
data burst for that port. The data bursts are user configurable for each port in the “SP I3 R ec ei v e
Configuration ($0x701)".
86Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
5.2.2.6SPHY Logical Timing
SPI3 interfa ce AC timing for SPHY c an be found in Sec tion 7.2 , “SPI3 AC T im ing Specif ic ations ”
on page 136. Logical timi ng in the following diagrams illustrates all signals as sociated with SPHY
mode. SPHY mode is similar to MP HY mode exce pt the following signals are not used:
• TMOD[1:0]
• RMOD[1:0]
• TSX
• RSX
• Address Data appearing on the data bus
5.2.2.7Transmit Timing (SPHY)
Packet tra nsmission starts when TE NB and TSOP indicate prese nt data on the bus is the first word
in the packet. All s ubsequent clocks will contain valid data as long as TENB is active or until
TEOP is asserted. Dat a trans miss ion can be tempor all y halte d when TENB goes hig h the n resumed
when TE NB is low.
Figure 14. SPHY Transmit Logical Timing
TFCLK
TENB
TSOP
TEOP
TERR
TDAT[7:0]_n
TPRTY
DTPA_n
B1B2B3B60B61B62B63B64
5.2.2.8Receive Timing (SPHY)
A packet is received when RSOP is asserted to in d i cate the data bus co n tains the first word of the
packet. A ll subsequent data is valid only while RVAL is high and until REOP is asserted. Receive
data can be temporarily halted when RENB is de-asserted and sta rts again on the second rising
edge of RFCLK following the assertion of RENB. When REOP is asserted RMOD indicates the
number of valid bytes in the last transfer.
The TFCLK and RFCLK can be independent of eac h other in SPHY mode operation. TFCLK and
RFCLK should be common to all the Net work P r oce ssor devices. The IXF1104 requires an
individual single clock source for the device trans mit path and a single clock source for the device
receive path.
The IXF1104 allows this interface to be overclocked so that all four IXF1104 ports can operate at
1 Gbps. This allows data transfer at data rat es of up to 4.0 Gbps when operating at an overclocked
frequency of 125 MHz.
Note: SPHY operates at a maximum frequency of 125Mhz.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
5.2.2.8.2Parity
The IXF1104 can be odd or eve n (the IXF1104 defaults to odd) when c alculating parity on the data
bus. This can be changed to accommodate even parity if desired, and can be set for transm it and
receive port s independently. The RX and T X parity sense bits have a direct relationship to the port
parity in SPHY mode.
The per po r t RX parity is s e t in th e “SPI3 Receive Configuration ($0x7 01)" an d the per port TX
Parity is set in the “SPI3 Transmit and Globa l Configuration ($0x700)".
5.2.2.9SPI3 Flow Control
The SPI3 packet interfa ce support s transm it and re ceive data t ransfers at cloc k rate s independe nt of
the line bit rate. As a result, the IXF1104 supports packet rate decoupling using internal FIFOs.
These FIFOs are 10 KB per port in the transmit direction (egress from the IXF1104 to the line
interfaces) and 32 KB per port in the receive direction (ingress to the IXF1 104 from the line
interfaces).
Control signals are provided to the network processor and the IXF1104 to allow eith er one to
exercise flo w control. Sinc e the bus i nte rface is point- to-poin t, the rec eive i nterfac e of the IXF1 104
pushes data to the link-laye r device. For the transm it interface, the packet available status
gran ul arity is byte- based.
5.2.2.9.1RX SPI3 Flow Control
In the receive d irect ion, when the IXF1 10 4 has s tored a n end-of-pa cket (a complet e smal l packet or
the end of a larg er pac ket) or some predefined number of bytes in its rece ive FIFO, it sends the inband address foll owed by FIFO data to the link-layer device (in MPHY mode). The dat a on the
interface bus is marked with the valid signal (RVAL) asserted. The network processor device can
pause the data fl ow by de-asserting the Receive Read Enable (RENB) signal.
RENB_0:3
RENB_0:3 control s the flow of data from the IXF1104 RX FIFOs. In SPHY mode, there is a
dedicated RENB for each port. In MPHY mode, RENB_0 is used as the global signal covering all
ports. When RENB is sampled Low, the network processor can ac ce pt data. A read is performed
from the RX FIFO and the RDAT, RPRTY, RMOD[1:0], RSOP, REOP, RERR, RSX, and RVAL
signals are updated on the following rising edge of RFCLK.
RENB can be asserted Hi gh by th e Network Proc essor at any time if it is una ble to a ccept any more
data. When the RENB is sampled High by the IXF1104, a read of the RX FIFO is not performed,
and the RDAT, RPRTY, RMOD[1:0], RSOP, REOP, RERR, RSX and RVAL signals remain
unchanged on the following rising edge of RFCLK.
5.2.2.9.2TX SPI3 Flow Con tr ol
In the transmit direction, when the IXF1104 has space for some predefined number of bytes in its
transmit FIFO, it informs the Network Processor device by asserting one of the Transm it Packet
Available (TPA ) signals. The Network Processor device writes the in-band address followed by
packet data to t he IXF1 104 us ing an e nable signa l (TE NB). The ne twork proces sor devic e moni tor s
the TPA signals for a High-to-Low transition, which in dicates that the transmit FIFO is almost f u ll
(the number of bytes left in the FIFO is user-selectable by setting the “TX FIFO High Watermark
Ports 0 - 3 ($0x600 – 0x603)", and suspends data transfer to avoid an overflow. The Networ k
Processor device can pause the data flow by de-asserting the enable signal (TENB).
90Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
The IXF1104 provides the following three types of TPA signals:
• Dedicated per port Direct Transmit Packet Available (DTPA)
• Selected-PHY Transmit Packet Available (STPA), which is based on the current in-band port
address in MPHY mode.
• Polle d- PH Y Transmit pa cket Available (PTPA), which prov i d es F I F O in f or mation on th e p ort
select ed by th e TADR[ 1 :0 ] sig n al s .
The following three TPA signals (DTPA_0:3, STP A, and PTPA) provide flow contro l bas ed on the
programmable TX FIFO High and Low watermarks. Refer to Table 132 “TX FIFO High
Watermark Ports 0 - 3 ($0x600 – 0x603)” on page 202 and Ta ble 133 “TX FIFO Low W atermark
Register Ports 0 - 3 ($0x60A – 0x60D)” on page 203 for more information.
DTPA_0:3:
A direct status indication for the TX FIFOs of ports [0:3]. When DTPA is High, it indicates the
amount of data in the TX FIFO is below the TX FIFO High watermark. When the High watermark
is crossed, DTPA transitions Low to indi cate the TX FIFO is almost full. It stays low until the
amount data in the TX FIFO goes bac k below the TX FIFO Low watermark. At this point, DTPA
transitions High to indicate the programmed number of bytes are now availa ble for data transfers.
DTPA_0:3 is updated on the risi ng edge of the TFCLK.
STPA:
STPA provides TX FIFO status for the curren tly selected port in MPHY mode. When High, STPA
indicates that the amount of data in the TX FIFO for the port sele cted, specified by the latest inband address, is below the TX FIFO High watermark. When the High watermark is crossed, STPA
transitions Low to indicate the TX FIFO is a lm ost full. It stays Low until the amount of data in the
TX FIFO goes back below the TX FIFO Low watermar k. At this point, STPA transitions High to
indicate the pr ogrammed number of bytes are now available for data tr ansfers.
The port reported by STPA is updated on the rising edge of TFCLK after TSX is sampled a s
asserted. STPA is updated on the rising edge of TFCLK.
Note: STPA is only used when the IXF1104 is configured for MPHY mode of operation.
PTPA:
PTPA provides status of the TX FIFO based on the port selected by the TADR[1:0] address bus.
When High, PTPA indicates that the amount of data in the TX FIFO for the port selected is below
the TX FIFO High watermark. When the High watermark is crossed, PTPA transitions Low to
indicat e the TX FIFO is almost full. It stays Low until the amount of data in the TX FIFO goes
back below the TX FIF O Low watermark. PTPA then transitions High to indicate the programmed
number of bytes are now avail able for data transfers.
The port reported by PTPA is updated on the rising edge of TFCLK after the TADR{1:0] port
address is sampled.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
5.2.3Pre-Pending Func tion
The IXF1104 im plements a pre-pending feature to allow 1518-byte Ethernet packets to be prepadded with two additional bytes of data so that the packet becomes low-word aligned. The 2-byte
pre-pend value is all zeros and is inserted before the destination address of the packet being prepended. This va lue is fixed and cannot be changed.
This function is enabled by writing the appropriate data to the “RX FIFO Padding and CRC Strip
Enable ($0x5B3)" for each port.
A standard 1518-byte Ethernet packet occupies 379 long words (four bytes) with two additional
bytes left over (1518/4 = 379.5). To eliminate the memory-management problems for a network
processor or swit ch fabric, the two remaining bytes are dealt with by the addition of two bytes to
the start of a packet. This results in a standard 1518- byte Ethernet packet received by the IXF1104
being forwarded to the hig her-layer device as a 380-long-word packet. The upper-layer device is
responsible for stripping the additional two bytes.
This feature was add ed to the IXF110 4 t o assi st in t he des ign of high er -l ayer memory mana gement.
The additio n of the two ext ra bytes is not the default opera tion of the IXF110 4 a nd must be enable d
by the user . The defa ult opera tion of the IXF1 104 SPI3 receive int erface forward s da ta exactl y as it
is received by the IXF1104 line interface.
5.3Gigabit Media Independent Interface (GMII)
The IXF1104 s upports a subset of the GMII interface standard as defined in IEEE 802.3 2000
Edition for 1 Gbps operation only. This subset is limited to operation at 1000 Mbps full-duplex.
The GMII Interface operates as a source synchronous interface only and does not accept a TXC
clock provide d by a PHY device when ope rating at 10/100 Mbps speeds.
Note: The RGMII interface must be used for applications that require 10/100/1000 Mbps operation.
The IXF1104 does NOT support 10/100 Mbps copper PHY devices that are implemented using the
MII Interface.
Note: MII operation is not supported by the IXF1104.
The user can select GMII, RGMII, or Optica l Module/SerDes functionality on a per-port basis.
This mode of operation is c ontrolled through a configuration re gister.
While IEEE 802 .3 specifies 3.3 V operation of GMII devices, most P HYs use 2.5 V signaling. The
IXF1104 provides a 2.5 V drive and is 3.3 V-tolerant on inputs.
92Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
Table 26 “GMII Interface Signal Definitions” on page 94 provides the GMII interface signal
definitions . For information on 1000BASE-T GMII transmit and receive timing diagrams and
tables, please refer to Table 49 “GMII 1000BASE-T Transmit Sign al Parameters” on page 141,
Figure 38 “1000BASE-T Transmit Interface Ti mi ng” on page 141, Figure 39 “100 0BAS E-T
Receive Interface Timing” on page 142, and Table 50 “GMII 1000BASE-T Recei ve Signal
Parameters” on page 142
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
Table 26. GMII Interface Signal Definitions
IXF1104
Signal
TXC_0
TXC_1
TXC_2
TXC_3
TXD[7:0]_0
TXD[7:0]_1
TXD[7:0]_2
TXD[7:0]_3
TX_EN_0
TX_EN_1
TX_EN_2
TX_EN_3
TX_ER_0
TX_ER_1
TX_ER_2
TX_ER_3
RXC_0
RXC_1
RXC_2
RXC_3
RXD[7:0]_0
RXD[7:0]_1
RXD[7:0]_2
RXD[7:0]_3
RX_DV_0
RX_DV_1
RX_DV_2
RX_DV_3
RX_ER_0
RX_ER_1
RX_ER_2
RX_ER_3
CRS_0
CRS_1
CRS_2
CRS_3
COL_0
COL_1
COL_2
COL_3
GMII Standard
Signal
GTX_CLKIXF1104
TXD[7:0]IXF1104
TX_ENIXF1104
TX_ERIXF1104
RX_CLKPHY
RXD<3:0>PHY
RX_DVPHY
RX_ERPHY
CRSPHY
COLPHY
SourceDescription
Transmit Reference Clock:
125 MHz for G igabit oper ation.
MII operation for 10/100 Mbps operation is not
supported.
Transmit Data Bus:
Width of this synchronous output bus varies with the
speed/mode of operation. In 1000 Mbps mode, all 8
bits are used.
Transmit Enable:
Synchronous input that indicates Valid data is being
driven on the TXD[7:0] data bus.
Transmit Error:
Synchronous input to PHY causes the transmission of
error sy mbols in 1000 Mbps links.
Receive Clock:
Continuous reference clock is 125 MHz +/– 100 ppm.
Receive Data Bus:
Width of the bus varies with the speed and mode of
operation. In 1000 Mbps mode, all 8 bits are driven by
the PHY device.
Note: MII operati on at 10/100 Mbps is not supported.
Receive Data Valid:
This si gnal is asserted when valid data is present on
the corresponding RXD bus.
Receive Error:
In 1000 Mbps mode, asserted when error symbols or
carrier extension symbols are received.
Always sy nchronous to RX _CLK.
Carrier Sense:
Asserted when valid activity is detected at the lineside in terface.
Collision:
Asserted when a collision is de te cte d an d rem ains
asserted for the duration of the collision event. In fullduplex mode, the PHY should force this signal Low.
94Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
1
5.4Reduced Gigabit Media Independent Interface (RGM II)
The IXF1104 su pports the RGMII interface standard as defined in the RGMII Vers ion 1.2
speci fi cation. T h e R G M II in t er f ace is an alternativ e to the IEE E 8 02 .3u MII in t er f ac e .
The RGMII interface is intended as an alter n ative to the IEEE 802.3u MII and the IE EE 802.3z
GMII. The principle objec tive of the RGMII is to reduce the number of balls (from a maximum of
28 balls to 12 balls) requi red to interconnect the MAC and the PHY. This reduction is both co steffective and technology-independ ent. To accomplish this objective, the data paths and all
associated control signals are reduced, control signals are multiplexed together, and both edges of
the clock are used.
• 1000 Mbps operation – clocks operate at 125 MHz
• 100 Mbps operation – clocks operate at 25 MHz
• 10 Mbps operation – clock s operate at 2.5 MHz.
Note: The IXF1104 RGMII interface is mul tiplexed with signals from the GMII interface. See Table 16
“Line Side In terface Multiplexed Balls” on page 57 for detailed information.
Multiplexing of data and control information is achi eved by utilizing both edges of the refer enc e
clocks and sendin g the lower four bi ts on th e risi ng ed ge and the uppe r four b its on t he fall ing edge .
Control signals are multiplexed into a single clock cycle using the same technique. For further
information on ti mi ng parameters, see Figure 37 “RGMII Interface Timing” on page 140 and
Table 48 “RGMII Interface Timing Parameters” on page 140.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
5.4.2Timi ng Sp ecifi cs
The IXF1104 RGMII complies with RGMII Rev1.2a requirements. Table 27 provides the timing
specifics.
5.4.3TX_ER and RX_ER Coding
To reduce interface power, the transmit error condition (TX_ER) and the receive error c ondition
(RX_ER) are encoded on the RGMII interface to minimize transitions duri ng norm al network
operation (refer to Table 28 on page 96 for the encoding method). Ta ble 27 provides signal
definitions for RGMII.
Table 27. RGM II Signal Definitions
IXF1104
Signal
TXC_0:3TXCMAC
TD[3:0]_nTD<3:0>MAC
TX_ENTX_CTLMAC
RXC_0:3RXCPHY
RD[3:0]_nRD<3:0>PHY
RX_DVRX_CTLPHY
RGMII
Standard
Signal
SourceDescription
Depending on speed, the transmit reference clock is 125 MHz, 25 MHz,
or 2.5 MHz +/– 50ppm.
Contains register bits 3:0 on the rising ed ge of TXC and re gister bit s 7:4
on the falling edge of TXC.
TXEN is on the le ading edge of TXC .
TX_EN xor TX_ER is on the falling edge of TXC.
Continuous reference clock is 125 MHz, 25 MHz, or 2.5 MHz +/– 50
ppm.
Contains register bits 3:0 on the leading edge of RXC and register bits
7:4 on the trailing edge of RXC.
RX_DV is on the leading edge of RXC.
RX_DV or RX ER R is the fall in g edge of RXC.
The value of RGMII_TX_ER and RGMII_TX _EN ar e val id at the rising edge of the clock while
TX_ER is pr es ented on the fallin g edge of the clock. RX_ER coding behaves in the same way (see
Table 28, F igure 19, and Figure 20).
Table 28. TX_ER and RX_ER Coding Description
ConditionDescription
Receiving valid frame,
no errors
Receiving valid frame,
with errors
Receiving invalid frame
(or no frame)
Transmitting valid frame,
no errors
Transmit t in g va li d f ram e
with errors
Transmit ting invalid
frame (or no fram e)
NOTE: Refer to Figure 19 for TX_CTL behavior, and Figure 20 for RX_CTL behavior.
RX_DV = tr ue
Logic High on rising ed ge of RXC
RX_DV = tr ue
Logic High on rising ed ge of RXC
RX_DV = false
Logic Lo w on rising edge of RX C
TX_EN = true
Logic High on rising edge of TXC
TX_EN = true
Logic High on rising edge of TXC
TX_EN = false
Logic Lo w on rising edge of TXC
RX_ER = false
Logic High on the falling edge of RXC
RX_ER = true
Logic Low on the falling edge of RXC
RX_ER = false
Logic Low on the falling edge of RXC
TX_ER =fals e
Logic High on the falling edge of TXC
TX_ER = true
Logic Low on the falling edge of TXC
TX_ER = false
Logic l ow on the falling edge of TXC
96Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
5.4.3.1In-Band Status
Carrier Sense (CRS) is generated by the PHY when a packet is received from the network
interface. CRS is indicate d when:
• RXDV = true.
• RXDV = false, RXERR = true, and a value of FF exists on the RXD[7:0] bits simulta neously.
• Carrier Extend, Carrier Extend Error, or False Carrier occurs (please reference the Hewlett-
Packard* Version 1.2a RGMII Specification for details.).
Carrier Extend and Carrier Extend Error are applicable to Gigabit speeds only. Collision is
determined at the MAC by the as sertion of TXEN being true while either CRS or RXDV are true.
The PHY w ill not assert CRS as a result of TXEN being true.
5.4.410/100 Mbps Functionality
The RGMII i nterface implements the 10/100 Mbps Ethernet Media Independent Interfa ce (MII) by
reducing the clock ra te to 25 MHz for 100 Mbps operation and 2.5 MHz for 10 Mbps. The TXC is
generated by the MAC and the RXC is generated by th e PH Y. During packet reception, the RXC is
stretched on ei ther the positive or negative pulse to a cc ommodate transition from the free-running
clock to a data-s ynchronous clock domain. When the speed of the PHY changes , a similar
stretching of t he po siti ve or nega tive pu lses is allo wed. No glitc hing of the cl ocks is a llowed d uring
speed transitions.
This interface operates at 10 Mbps and 100 Mbps speeds in the same manner as 1000 Mbps spee d,
although the data may be duplicated on the falling edge of the appropriate clock. The MAC holds
TX_CTL Low until it is operating at the same speed as the PHY.
Note: The IXF1104 does not support 10/100 Mbps operation when configured in GMII mode
5.5MDIO Control and Interface
The IXF1104 supports the IEEE 802.3 MII Management Interface, also known as the Management
Data Input/Output (MDIO) Interface. This interface allows the IXF1104 to monitor and control
each of the PHY devices that are connect ed to the four ports of IXF1104 when those ports are in
copper mode.
The MDIO Master Interfa ce bl ock is impl emente d once in t he IXF1 1 04. The MDIO I nterfa ce blo ck
contains the logic through which the user accesses the registers in PHY devices connected to the
MDIO/MDC interface, which is controlled by each port.
The MDIO Master Interface block supports the management frame format, specified by IEEE
802.3, clause 22.2.4.5. This block also supports single MDI access through the CPU interface and
an autoscan mode. Autos can allows the MDIO mast er to read all 32 regist ers of the per - port coppe r
PHYs and stor e the contents in the IXF1104. This provide s external-CPU-ready acces s to the PHY
register c ontents through a single CPU read without the latency of waiting on the low-speed serial
MDIO data bus for each regi ster access.
Scan of a single register with low-frequency operation takes approximately 25.6µs. Scan of a 32register block takes approximately 820 µs, or 3.3 ms for all four ports. Autoscan data is not valid
until approximately 19.2 µs after enabling scan. These numbers scale by 7/50 for high-frequency
operation.
98Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
5.5.1MDIO Address
The 5-bit PHY address for the MDIO transactions can be set in the “MDIO Single Command
($0x680)". Bit s 5:2 of the PHY address are fixed to a value of 0. Bits 1 and 0 are programmable in
bits 9 and 8 of “MDIO Single Command ($0x680)".
5.5.2MDIO Register Descriptions
For complete information on the MDI registers, refer to the Table 142 “MDIO Single Command
($0x680)” on page 210, Table 143 “MDIO Single Read and Write Data ($0x681)” on page 210,
Table 144 “Autoscan PHY Address Enable ($0x682)” on page 211, and Table 145 “MDIO Control
($0x683)” on page 211.
5.5.3Clear When Done
The MDI Command register bit , in the “MDIO Single Command ($0x 680)", clears upon command
completion and is set by the user to start the requested single MDIO Read or Write operatio n. T h is
bit is cleared automatically upon operation completion.
5.5.4MDC Generation
The MDC clock is used for the MDIO/MDC in terface. The frequency of the MDC clock is
selectable by setting bit 0, MDC Speed, in an IXF1104 configuration register (see Table 145
“MDIO Control ($0x683)” on page 211).
5.5.4.1MDC High-Frequency Operation
The high-frequency MDC is 18 MHz, derived from the 125-MHz sys tem clock by dividi ng the
frequency by 7.
The duty cycle is as follows:
• MDC High duration: 3 x (1/125 MHz) = 3 x 8 ns = 24 ns
• MDC Low duration: 4 x (1/125 MHz) = 4 x 8 ns = 32 ns
• MDC runs continuously after reset
Refer to Figure 41 “MDC High-Speed Operation Timing” on page 144 for the high-frequency
MDC timing diagram.
5.5.4.2MDC Low-Frequency Operation
The low-frequency MDC is 2.5 MHz, which is derived from the 125-MHz system clock by
dividing the fr equency by 50.
The duty cycle is as follows:
• MDC High duration: 25 x (1/125 MHz) = 25 x 8 ns = 200 ns
• MDC Low duration: 25 x (1/125 MHz) = 25 x 8 ns = 200 ns
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
Refer to Figure 42 “MDC Low-Speed Operation Timing” on page 144 for the low frequency MDC
timing diagram.
5.5.5Management Frames
The Mana ge m e n t Int er f a ce serialize s the ex t er n al re gi st er ac cess inform at io n in to th e f o rm at
specified by IEEE 802.3, Section 22.2.4.5 (see Figure 21).
The Management Data Interface is accessed through the “MDIO Single Command ($0x680)" and
the “MDIO Single Read and Write Data ($0x681)". A single management frame is sent by setting
Register 0, bit 20 to logic 1, an d is automatically cleared when the frame is complet ed.
The Write data is first set up in Register 1, bits 15:0 for Write operation. Register 0 is initialized
with the appropria te cont rol inf ormation (s tart, op code, etc. ) and Regis ter 0, bit 20 is set to logic 1.
Register 0, bit 20 is reset to logic 0 when the frame is complete.
The steps are identical for Read operation except that in Register 1, bits 15:0, the data is ignored.
The data received from the MDIO is read by the CPU interface from Register 1, bits 31:16.
5.5.7MDI State Machine
The MDI State Machine seq u ences the information sent to it by the M D IO control regis ters and
keeps track of the current sequence bit count, enabling or disabling the MDIO driver output (see
Figure 22.
REG Addr
5 Bits
Turnaround
2 Bits
Data
16 Bits
100Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
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