Intel IXF1104 User Manual 2

Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller

Datasheet

The Intel® IXF1104 is a four-port Gigabit MAC that supports IEEE 802.3 10/100/1000 Mbps applications. The IXF1104 suppor ts a System Packet Interface Phase 3 (SPI3) syste m interface to a network processor or ASIC, and co ncurrently supports copper and fiber physi cal layer devices (PHYs).

The copper PHY interface implements t he Gigabit Media Independent Interface (GMII) and the Reduced Gigabit Media Indep ende nt Interface (RGMII) as defined in Version 1.2a of the Hewlett-Packard* specification. RGMII has the benefit of reducing th e PHY interface pin count for high-port-count applications.

The fiber PHY interface implements an internal Serializer/Deserializer (SerDes) on each port to allow direct connection to optical modules. The integration of the SerDes functionalit y reduce s PCB area requirement s a nd system cost.

Product Features



4 Independent Ethernet MAC Ports which support 3 interfaces for Copp er or Fiber Physical layer connectivity.

—IEEE 8 0 2.3 compliant — R MON Statistics —Independent Enable/Disable of any port



Copper Mode:

—RGMII for 10/100/1000 Mbps

connections

—GMII for 1000 Mbps full-duplex

connectivity

—IEEE 802.3 MDIO interface



Fiber Mode:

—Integrated SerDes interfac e for direct

connection to opt ical modules for 1000BASE-X connectivity

—Supports IEEE 802.3 fiber auto-

negotiation including forced mode

—Small Form Factor Pluggable (SFP)

Transceiver MSA compatible



System P acket Interface Level 3 (SPI3)

—Capable of data transfers at 4 Gbps in

both SPI3 modes: 32-bit Multi-PHY mode (133 Mhz ) 4 x 8bit Single-PHY mode (125 Mhz)



Operating Temperature Ranges:

MIN MAX

Copper Mode: -40°C +85°C

Fiber Mode: 0°C +70°C



Flexible 32/16/8-bit CPU interface



Programmable Packet handling

—Filter packets with errors —Filter broadcas t, multicast, unicast and

VLAN packets

—Automaticall y pad transmitted packets

less than the minimum frame size

—Remove CRC from packets received



Performance Monitoring and Diagnostics

—CRC calculation and error detection —Detection of length error, runt or overly

large pack e ts

—Counters for dropped and errored

packets —Loopback modes —JTAG- and boundary-scan-capable



IEEE 802.3 Complaint Flow Control

—Loss-less flow control for up to 9.6 KB

packets and 5 km of fiber —Jumbo frame support for 9. 6 KB packets



Internal 32 KB receive FIFO and 10 KB transmit FIFOs per chan n el



552-ball Ceramic Ball Grid Array (CBGA)

—1.8 V core, 2.5 V RGMII, GMII, OMI,

and 3.3 V SPI3 and CPU —.18 µ CMOS process technology



Product Ordering Number: HFIXF1104CE.B0 853714

Document Number: 278757

Revision Number: 007

Applications



Load Balancing Sy stems



MultiService Switch



Web Caching Appliances



Intelli gent Backplane Interfaces



Edge Router



Base Station Controller



Redundant Line Cards



Base Tran sceiver Station



Serving GRPS Support Node (SGSN)



General Packet Radio Services (GGSN)



Packet Data Serving Note (PDSN)



Digital S ubscri be r L ine Ac ces s Mul tip lex er (DSLAM)



Cable Modem Termination System (CMTS)

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHA TSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety sy ste m s, o r in nuclear facility applications.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling

1-800-548-4725 or by visiting Intel's website at http://www.intel.com. AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, i386, i486,

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IXF1104 Media Access Controller may contain design defects or errors known as errata which may cause the product to deviate from

2 Datasheet

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004

Contents

1.0 Introduction..................................................................................................................................19

1.1 What You Will Find in This Document ................................................................................19

1.2 Related Documents............................................................................................................19

2.0 General Description ....................................................................................................................20

3.0 Ball Assign ments and Ball List Tables......................................................................................22

3.1 Ball Assignments................................................................................................................22

3.2 Ball List Tables...................................................................................................................23

3.2.1 Balls Listed in Alphabetic Order by Signal Name ..................................................23

3.2.2 Balls Listed in Alphabetic Order by Ball Location ..................................................29

4.0 Bal l Assignm ents and Sign al Descrip tions ..............................................................................36

4.1 Naming Conventions ..........................................................................................................36

4.1.1 Signal Name Conventions .....................................................................................36

4.1.2 Regi ste r Ad d ress Conventions ..............................................................................36

4.2 Interface Signal Groups.............................................................. .............. ....... ............ .......37

4.3 Signal Description Tables.................................................................. ............ .............. .......38

4.4 Ball Usage Summary..........................................................................................................56

4.5 Multiplexed Ball Connections.............................................................................................. 57

4.5.1 GMII/RGMII/SerDes/OMI Multiplexed Ball Connections................................. .......57

4.5.2 SPI3 MPHY/SPHY Ball Connections.....................................................................58

4.6 Ball State During Reset ......................................................................................................60

4.7 Powe r Su p ply Se q uen cing.... ..............................................................................................62

4.7.1 Power-Up Sequence........................................................... .. ....... ....... ..... ....... .......62

4.7.2 Power-Down Sequence.........................................................................................62

4.8 Pul l-Up/Pull-Down Ball Guide li n e s................................................................. .....................63

4.9 Analog Power Filtering........................................................................................................63

5.0 Function al Descriptions.............................................................................................................. 65

5.1 Me dia Access Controller (MAC) .........................................................................................65

5.1.1 Features for Fiber and Copper Mode ............................................................. .......66

5.1.1.1 Padding of Undersized Frames on Transmit .........................................66

5.1.1.2 Automatic CRC Generation ...................................................................66

5.1.1.3 Filtering of Receive Packets ..................................................................66

5.1.1.4 CRC Error Detection..............................................................................68

5.1.2 Flow Cont ro l..................................................... ......................................................68

5.1.2.1 802.3x Flow Control (Full-Duplex Operation)......................................... 69

5.1.3 Mixed- Mode Operation ..........................................................................................74

5.1.3.1 Configuration of the IXF1104.............................................. ...................74

5.1.3.2 Key Configuratio n Registers ............ ......................................................74

5.1.4 Fiber Mo d e..... ........................................................................................................75

5.1.4.1 Fiber Auto-Negotiation...........................................................................76

5.1.4.2 Determining If Link Is Established in Auto-Negotiation Mode................76

5.1.4.3 Fiber Forced Mode .................................................................................76

5.1.4.4 Determination of Link Establishment in Forced Mode ...........................76

5.1.5 Copper Mode................................................................... ......................................76

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Contents

5.1.5.1 Speed.....................................................................................................77

5.1.5.2 Duplex....................................................................................................77

5.1.5.3 Copper Auto-Negotiation .......................................................................77

5.1.6 Jumbo Packet Support ..........................................................................................77

5.1.6.1 Rx Statistics...........................................................................................78

5.1.6.2 TX Statistics...........................................................................................78

5.1.6.3 Loss-less Flow Contro l............... ............................................................78

5.1.7 Packet Buffer Dimensions ........ .............................................................................79

5.1.7.1 TX and RX FIFO Operation ...................................................................79

5.1.8 RMON Statis tics Support..... ..................................................................................79

5.1.8.1 Conventions...........................................................................................81

5.1.8.2 IXF1104 Advantages .............................................................................82

5.2 SPI3 In te rface..................................................................................................................... 82

5.2.1 MPHY Operatio n ....................................................................................................83

5.2.1.1 SPI3 RX Round Robin Data Transmission ............................................ 83

5.2.2 MPHY Logical Timing ............................................................................................83

5.2.2.1 Transmit Timin g.....................................................................................84

5.2.2.2 Receive Timing ......................................................................................84

5.2.2.3 Clock Rates... .........................................................................................86

5.2.2.4 Parity...................................................................................................... 86

5.2.2.5 SPHY Mode...........................................................................................86

5.2.2.6 SPHY Logical Timing.............................................................................87

5.2.2.7 Transmit Timin g (S PHY)........................................................................87

5.2.2.8 Receive Timing (SPHY).........................................................................87

5.2.2.9 SPI3 Flow Control..................................................................................90

5.2.3 Pre-Pending Function....................................................... ....... ....... ....... ............ ....92

5.3 Gigabit Media Independent Interface (GMII) ......................................................................92

5.3.1 GMII Signal Multiplexing............................................ ............................................93

5.3.2 GMII Interface Signal Definition......................................................................... ....93

5.4 Reduced Gigabit Media Independent Interface (RGMII) ....................................................95

5.4.1 Multiplexing of Data and Control.......................................................................... ..95

5.4.2 Timing Specifics.....................................................................................................96

5.4.3 TX_ER and RX_ER Coding...... .............................................................................96

5.4.3.1 In-Band Statu s.......................................................................................98

5.4.4 10/100 Mbp s Func tionality.......... ...........................................................................98

5.5 MDIO Control and Interface........................................................ ........................................98

5.5.1 MDIO Address.......................................................................................................99

5.5.2 MDIO Register Descriptions..................................................................................99

5.5.3 Clear When Done................................................... ...............................................99

5.5.4 MDC Generation ....................................................................................................99

5.5.4.1 MDC High-Frequency Operation ...........................................................99

5.5.4.2 MDC Low-Frequency Operation..................................... ............ ...........99

5.5.5 Management Frames...........................................................................................100

5.5.6 Single MDI Command Operation.........................................................................100

5.5.7 MDI State Machi n e....... .......................................................................................100

5.5.8 Autoscan Operation.............................................................................................102

5.6 SerDes Interface...............................................................................................................102

5.6.1 Features...............................................................................................................102

5.6.2 Functional Description.........................................................................................102

5.6.2.1 Transmitter Operational Overview.......................................................103

5.6.2.2 Transmitter Programmable Driver-Power Levels.................................103

4 Datasheet

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004

Contents

5.6.2.3 Receiver Operational Overview ...........................................................104

5.6.2.4 Selective Power-Down.........................................................................104

5.6.2.5 Receiver Jitter Tolerance.....................................................................104

5.6.2.6 Transmit Jitter ......................................................................................105

5.6.2.7 Receive Jitte r.......................................................................................105

5.7 Optical Module Interface...................................................................................................106

5.7.1 IXF1104-Supported Optical Module Interface Signals.........................................1 06

5.7.2 Func tional Descriptions ......... ..............................................................................107

5.7.2.1 High-Speed Serial Interface.................................................................107

5.7.2.2 Low-Speed Status Signaling Interface................................................. 107

5.7.3 I²C Module Configuration Interface................................................................... ...109

5.7.3.1 I

5.7.3.2 I

5.7.3.3 I

C Control and Data Registers............................................................109

C Read Operation..............................................................................109

C Write Operation ..............................................................................110

5.7.3.4 I²C Protocol Spec ifics...........................................................................111

5.7.3.5 Port Protocol Operation .......................................................................111

5.7.3.6 Clock and Data Transitions..................................................................111

5.8 LED In te rface....................................................................................................................114

5.8.1 Modes o f Oper a tion .............................................................................................114

5.8.2 LED Interface Signal Description.......................................... ..... ....... .. .......... .. .....114

5.8.3 Mode 0: Detailed Operation.................................................................................1 15

5.8.4 Mode 1: Detailed Operation.................................................................................1 16

5.8.5 Power-On, Reset, Initialization ............................................................................117

5.8.6 LED DATA Decodes............................................................................................117

5.8.6.1 LED Signaling Behavior.......................................................................118

5.9 CPU Inte r face ...................................................................................................................119

5.9.1 Func tional Description.... .....................................................................................120

5.9.1.1 Read Access........ ................................................................................120

5.9.1.2 Write Access........................................................................................1 20

5.9.1.3 CPU Timing Parameters......................................................................121

5.9.2 Endian..................................................................................................................121

5.10 TAP Interfa c e (JTAG ).......................................................................................................122

5.10.1 TAP State Machin e........... ...................................................................................122

5.10.2 Instruction Register and Supported Instructions..................................................123

5.10.3 ID Register........................................................................................................... 1 24

5.10.4 Boundary Scan Register........................ ..............................................................124

5.10.5 Bypass Register...................................................................................................124

5.11 Loopbac k Modes ..............................................................................................................124

5.11.1 SPI3 Interfac e Loopback .....................................................................................124

5.11.2 Line Side Interface Loopback..............................................................................1 25

5.12 Clocks...............................................................................................................................126

5.12.1 System Interface Reference Clocks.....................................................................126

5.12.1.1 CLK125................................................................................................127

5.12.2 SPI3 Rec eive and Transm it Clocks ........................................................... ..........127

5.12.3 RGMII Clocks.......................................................................................................127

5.12.4 MDC Clock...........................................................................................................127

5.12.5 JTAG Clock..........................................................................................................128

5.12.6 I

C Clock..................................... .........................................................................128

5.12.7 LED Clock..................................................................................................... .......128

Datasheet 5

Document Number: 278757 Revision Number: 007 Revision Date: March 25, 2004

Contents

6.0 Applications...............................................................................................................................129

6.1 Change Port Mode Initialization Sequence.......................................................................129

7.0 Electrical Specifications ...........................................................................................................131

7.1 DC Speci fi c a ti o n s.............................................................................................................132

7.1.1 Undershoot / Overshoot Specifications ................................................. ............ ..134

7.1.2 RGMII Elec tr i c a l Chara c te ristics........ ..................................................................134

7.2 SPI3 AC Ti mi ng Spe c i fications.........................................................................................136

7.2.1 Receive In te rface Timing.......... ...........................................................................136

7.2.2 Transmit Interface Timing....................................................................................138

7.3 RGMII AC Ti mi ng Spe c i fication........................................................................................140

7.4 GMII AC Timi n g Spe cification......... ..................................................................................141

7.4.1 1000 Base-T Operation .......................................................................................141

7.4.1.1 1000 BASE-T Transmit Interface.........................................................141

7.4.1.2 1000BASE-T Receiv e In te rface...........................................................142

7.5 SerDes AC Timing Specification.......................................................................................143

7.6 MDIO AC Timing Specification.........................................................................................144

7.6.1 MDC High-Speed Operation Timing....................................................................144

7.6.2 MDC Low-Speed Operation Timing.....................................................................144

7.6.3 MDIO AC Timing..................................................................................................145

7.7 Optical Module and I

7.7.1 I

C Interface Timing.............................................................................................146

C AC Timing Specifi ca tion .............................................................146

7.8 CPU AC Timing Specification........................................................................................... 148

7.8.1 CPU Interface Read Cycle AC Timing.................................................................148

7.8.2 CPU Interface Write Cycle AC Timing.................................................................148

7.9 Transmit Pause Control AC Timing Specification.............................................................150

7.10 JTAG AC Timing Specifi ca tion .........................................................................................151

7.11 System AC Timing Specification.......................................................................................152

7.12 LED AC Timing Specification............................................................................................153

8.0 Register Set................................................................................................................................154

8.1 Docu ment Structure..........................................................................................................154

8.2 Graphical Representation................................................................................... .......... .. ..154

8.3 Per Port Registers............................................................................................................155

8.4 Register Map ....................................................................................................................155

8.4.1 MAC Control Registers........................................................................................162

8.4.2 MAC RX Statistics Register Overview.................................................................173

8.4.3 MAC TX Statistics Register Overview .................................................................177

8.4.4 PHY Autoscan Registers.....................................................................................180

8.4.5 Global Status and Configuration Register Overview ...........................................187

8.4.6 RX FIFO Register Overview................................................................................192

8.4.7 TX FIFO Register Overview........ .........................................................................202

8.4.8 MDIO Register Overview.....................................................................................210

8.4.9 SPI3 Register Overview............................................. ..........................................212

8.4.10 SerDes Register Overview..................................................................................219

8.4.11 Optical Module Register Overview ......................................................................221

9.0 M ech anical Speci fications........................................................................................................223

9.1 Overview ...........................................................................................................................223

9.1.1 Features...............................................................................................................223

6 Datasheet

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004

Contents

9.2 Package Specifics for the IXF1104...................................................................................223

9.3 Package Information.........................................................................................................224

9.3.1 Example Package Marking......................... ....... ....... .......... ....... ....... .. ............ .....226

10.0 Product Ordering Information ..................................................................................................227

Figures

1 Block Diagram ............................................................................................................................20

2 Internal Architecture....................................................................................................................21

3Intel

4 Interface Signals . .......................................................................................................................37

5 Power Supply Sequencing.... ......................................................................................................62

6 Analog Power Supply Filter Network .................................................... ......................................64

7 Packet Buffering FIFO................................................................................................................70

8 Ethernet Fram e Forma t..............................................................................................................70

9 PAUSE Frame Format................................................................................................................71

10 Transmit Pause Control Inter fa ce...............................................................................................73

11 MPHY Transmit Logical Timing............................. .....................................................................84

12 MPHY Receive Logical Timing...................................................................................................85

13 MPHY 32-Bit Interface................................................................................................................85

14 SPHY Transmit Logical Timing...................................................... ................... ................... .......87

15 SPHY Re ce ive Logical Timing....................................................................................................88

16 SPHY Connection for Two IXF1104 Ports (8-Bit Interface)........................................................89

17 MAC GMII Interconnect..............................................................................................................93

18 RGMII Interface.......................................................................................................................... 95

19 TX_CTL Behavior............................................................................ ...........................................97

20 RX_ C TL Be h av ior...... .................................................................................................................97

21 Management Frame Structure (Single-Frame Format) ............................................................1 00

22 MDI State..................................................................................................................................1 01

23 Se r De s Receiver Jitter Tolerance........ ......................................................................... ............105

24 I

25 Data Validity Timing..................................................................................................................1 12

26 Start and Stop Definition Timing...............................................................................................112

27 Ackn o w l e d ge Ti mi n g.. ...............................................................................................................113

28 Random Read...........................................................................................................................114

29 Mode 0 Timing..........................................................................................................................115

30 Mode 1 Timing..........................................................................................................................117

31 Read Timing Diagram - Asynchronous Interface....................................................... ...............120

32 W rite Timing Diagram - Asynchronous Interface......................................................................121

33 SPI3 Interface Loopback Path........................................................................................ ..........125

34 Line Side Interface Loopback Path.................................. ............ ............ ....... ......... ............ .....126

35 SPI3 Receive Interface Timing.................................................................................................136

36 SPI3 Transmit Interface Timing................................................................................................138

37 RGMII Interface Timing.............................................................................................................140

38 1000BASE-T Transmit Interface Timing ...................................................................................141

39 1000BASE-T Receive Interface Timing....................................................................................142

40 SerDes Timing Diagram...........................................................................................................143

41 MDC High-Speed Operation Timing.........................................................................................144

42 MDC Low-Speed Operation Timing..........................................................................................1 44

IXF1104 552-Ball CBGA Assignments (Top View).......... .................................................22

C Random Read Transaction .................................................................................. ...............1 10

Datasheet 7

Document Number: 278757 Revision Number: 007 Revision Date: March 25, 2004

Contents

43 MDIO Write Timing Diagram ....................................................................................................145

44 MDIO Rea d Timin g Diag r a m....................................................................................................145

45 Bus Tim in g Diag ra m.......... ....................................................................................................... 146

46 Write Cycle Diagram.................................................................................................................146

47 CPU Interface Read Cycle AC Timing......................................................................................148

48 CPU Interface Write Cycle AC Timing ......................................................................................148

49 Pause Control Interface Timing....... .........................................................................................150

50 JTAG AC Timing.......................................................................................................................151

51 System Reset AC Timing.........................................................................................................152

52 LED AC Inter fa ce Ti mi n g............ ..............................................................................................153

53 Memory Overview Diagram ...................................................................................................... 154

54 Regi ste r Overview Diagram.......... ............................................................................................155

55 CBGA Package Diagram.......................... ....... ..... ....... ....... ..... ....... .. .......... ....... .. ....... .......... .. ..224

56 CBGA Package Side View Diagram.........................................................................................225

57 Intel

IXF1104 Example Package Marking ..............................................................................226

58 Orde r ing Information – Sample ......... .......................................................................................227

Tables

1 Ball List in Alphanumeric Order by Signal Name.......................................... ....... ....... ............ ....23

2 Ball List in Alphanume ric Order by Ball Location........................................................................29

3 SPI3 Interface Signal Descriptions.............................................................................................38

4 SerDes Interface Signal Descriptions......................................................................... .......... .. ....46

5 GMII Interface Signal Descriptions.............................................................................................47

6 RGMII Interface Signal Descriptions ..........................................................................................49

7 CPU Interface Signal Descriptions ........................................................................... .. ............ ....50

9 Optical Module Interface Signal Descript ions. ............................................................................52

8 Transmit Pause Control Interface Signal Descriptions...............................................................52

10 MDIO Interface Signal Descriptions ...........................................................................................53

11 LED Interface Signal Descriptions........................ .. .......... ....... .. ....... ..... ....... ..... ....... .. .......... .. ....54

12 JTAG Interface Signal Descriptions............................................................................................54

13 System Interface Signal Descriptions.................................................................. ....... .......... ......54

14 Power Su p ply Signal Descriptions..............................................................................................55

15 Ball Usage Summary..................................................................................................................56

16 Line Side Interface Multiplexed Balls ..........................................................................................57

17 SPI3 MPHY/SPHY Interface.......................................................................................................58

18 Definition of Output and Bi-directional Balls During Hardware Reset.........................................60

19 Power Supply Sequencing .................................................................... ....... ....... ..... ....... ....... ....63

20 Pull-Up/Pull-Down and Unused Ball Guid e li n e s........................................... ..............................63

21 Analog Power Balls ....................................................................................................................64

22 CRC Errored Packets Drop Enable Behavior.............................................................................68

23 Valid Decodes for TXPAUSEADD[2:0].......................................................................................73

24 Operational Mode Configuration Registers................................................................................75

25 RMON Additional Statistics ............................................................................ ............................ 80

26 GMII Interface Signal Definitions................................................................................................94

27 RGMII Signal Definitions ...................................................... ......................................................96

28 TX_ER and RX_ER Coding Description.....................................................................................96

29 SerDes Driver TX Power Levels...............................................................................................103

30 IXF1104-to-SFP Optical Module Interface Connections........................ ..... ....... .. ....... .......... .. ..106

31 LED Interface Signal Descriptions........................ .. .......... ....... .. ....... ..... ....... ..... ....... .. .......... .. ..115

32 Mode 0 Clock Cycle to Data Bit Relationship...........................................................................116

8 Datasheet

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Revision Date: March 25, 2004

Contents

33 Mode 1 Clock Cycle to Data Bit Relationship ...........................................................................1 17

34 LED_DATA# Decodes..............................................................................................................118

35 LED Behavior (Fiber Mode)......................................................................................................1 18

36 LED Behavior (Copper Mode) ..................................................................................................119

37 Byte Swapper Behavior......................................... ...................................................................1 22

38 Instruction Register Description................................................................................................123

39 Absolute Maximum Ratings......................................................................................................131

40 Recommended Operating Conditions.......................................................................................132

41 Intel® IXF1104 MAC DC Specifications ......................................................... .. ..... ....... ..... .......133

42 SerDes Transmit Characteristics..............................................................................................133

43 Intel® IXF1104 MAC SerDes Receive Characteristics................................................. ..... .. .....134

44 Undershoot / Overshoot Limits.................................................................................................134

45 RGMII Power............................................................................................................................135

46 SPI3 Receive Interface Signal Parameters ..............................................................................137

47 SPI3 Transmit Interface Signal Parameters .............................................................................139

48 RGMII Interface Timing Parameters.........................................................................................1 40

49 GMII 1000BASE-T Trans mit Signal Parameters............................................................... .......141

50 GMII 1000BASE-T Receive Signal Parameters .............................. .........................................1 42

51 SerDes Timing Parameters ......................................................................................................143

52 MDIO Timing Parameters.........................................................................................................145

53 I

C AC Timing Characteristics..................................................................................................146

54 CPU Interface Write Cycle AC Signal Parameters...................................................................149

55 Transmit Pause Control Inter fa ce Ti mi n g Para me ter s..............................................................150

56 JTAG AC Timing Parameters ...................................................................................................151

57 System Reset AC Timing Parameters......................................................................................152

58 LED Interface AC Timing Parameters......................................................................................153

59 MAC Control Registers ($ Port Index + Offset) ........................... ....... ..... .. ..... .. ....... ..... ..... .. .....155

60 MAC RX Statistics Registers ($ Port Index + Offset)................................................................ 1 56

61 MAC TX Statistics Registers ($ Port Index + Offset) ................................................................157

62 PHY Autoscan Registers ($ Port Index + Offset)......................................................................158

63 Global Status and Configuration Registers ($ 0x500 - 0X50C)................................................158

64 RX FIFO Registers ($ 0x580 - 0x5 BF)......................................................................................1 58

65 TX FIF O Registers ($ 0x600 - 0x63E)......................................................................................159

66 MDIO Registers ($ 0x680 - 0x683)............................................................ ....... ....... ..... ....... .....160

67 SPI3 Registers ($ 0x700 - 0 x716).............................................................................................160

68 SerDes Registers ($ 0x780 - 0x798) .................................................................. ......................161

69 Optical Module Registers ($ 0x799 - 0x79F) ....................................................................... .....161

70 Station Address ($ Port_Index +0x00 – +0x01)........ ................................................................162

71 Desired Duplex ($ Port_Index + 0x02).....................................................................................162

72 FD FC Type ($ Port_Index + 0x03) ....... ...................................................................................162

73 Collision Distance ($ Port_Index + 0x05) .................................................................................1 63

74 Co ll ision Threshold ($ Port_Index + 0x06) ...............................................................................163

75 FC TX Timer Value ($ Port_Index + 0x07) ...............................................................................163

76 FD FC Add r e ss ( $ Port_ Index + 0x08 – + 0x09) .... ..................................................................163

77 IPG Receive Time 1 ($ Port_Index + 0x0A) .............................................................................164

78 IPG Receive Time 2 ($ Port_Index + 0x0B) .............................................................................164

79 IPG Transmit Time ($ Port_Index + 0x0C) ............................................................................... 1 64

80 Pause Threshold ($ Port_Index + 0x0E) ..................................................................................1 65

81 Max Frame Size (Addr: Port_Index + 0x0F)............................................................................. 165

82 MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)..........................................................166

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Contents

83 Flush TX ($ Port_Index + 0x11)............................................................................. ...................166

84 FC Enable ($ Port_Index + 0x12).............................................................................................167

85 FC Back Pressure Length ($ Port_Index + 0x13)..................................................................... 167

86 Short Runts Threshold ($ Port_Index + 0x14).......................................................................... 168

87 Discard Unknown Control Frame ($ Port_Index + 0x15)..........................................................168

88 RX Config Word ($ Port_Index + 0x16).................. ..... ....... ....... ....... .......... .. ....... ....... .......... ....168

89 TX Config Word ($ Port_Index + 0x17)....................................................................................169

90 Diverse Config Write ($ Port_Index + 0x18)....................... ....... ....... ............ ....... ....... .......... ....170

91 RX Packet Filter Control ($ Port_Index + 0x19) ........................................... ....... ....... .......... .. ..171

92 Port Multicast Address ($ Port_Index +0x1A – +0x1B) ............................................................172

93 MAC RX Statistics ($ Port_Index + 0x20 – + 0x39)..................................................................173

94 MAC TX Statistics ($ Port_Index +0x40 – +0x58)....................... .............................................177

95 PHY Control ($ Port Index + 0x60)................................................................. ..........................180

96 PHY Status ($ Port Index + 0x61) ............................................................................................181

97 PHY Identification 1 ($ Port Index + 0x62) ...............................................................................182

98 PHY Identification 2 ($ Port Index + 0x63) ...............................................................................182

99 Auto-Negotiation Advertisement ($ Port Index + 0x64) ............................................................183

100 Auto-Negotiation Link Partner Base Page Ability ($ Port Index + 0x65)...................................184

101 Auto-Negotiation Expansion ($ Port Index + 0x66) ..................................................................185

102 Auto-Negotiation Next Page Transmit ($ Po rt Index + 0x67) ...................................................186

103 Port Enable ($0x500)................................................................................................................187

104 Inte r fa ce Mod e ($0 x5 0 1)..........................................................................................................187

105 Link LED Enable ($0x502) ..................................................................................... ...................188

106 MAC Soft Reset ($0x505).........................................................................................................188

107 MDIO Soft Reset ($ 0 x5 0 6)........... ............................................................................................189

108 CPU Interface ($0x508)................................. ....... ....... ....... ....... ....... .......... ....... ....... ....... .........189

109 LED Contro l ($ 0 x5 0 9)................................................ ...............................................................189

110 LED Flash Rate ( $ 0 x5 0A ).........................................................................................................190

111 LED Fault Disable ($0x50B).....................................................................................................190

112 JTAG ID ($0x50C).................................................................................................................... 191

113 RX FIFO High Watermark Port 0 ($0x580)............................................................ ...................192

114 RX FIFO High Watermark Port 1 ($0x581)............................................................ ...................192

115 RX FIFO High Watermark Port 2 ($0x582)............................................................ ...................192

116 RX FIFO High Watermark Port 3 ($0x583)............................................................ ...................193

117 RX FIFO Low Watermark Port 0 ($0x58A)............................................................................... 193

118 RX FIFO Low Watermark Port 1 ($0x58B)............................................................................... 193

119 RX FIFO Low Watermark Port 2 ($0x58C) ...............................................................................194

120 RX FIFO Low Watermark Port 3 ($0x58D) ...............................................................................194

121 RX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x594 – 0x597)....................................194

122 RX FIFO Port Reset ($0x59E)..................................................................................................195

123 RX FIFO Errored Frame Drop Enable ($0x59F) .......................................................................195

124 RX FIFO Overflow Event ($0x5A0) ..........................................................................................196

125 RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2 - 0x5A5)......................................197

126 RX FIFO SPI3 Loopback Enable for Ports 0 - 3 ($0x5B2) .......................................................198

127 RX FIFO Padding and CRC Strip Enable ($0x5B3) ..................................................... ............199

128 RX FIFO Transfer Threshold Port 0 ($0x5B8)..........................................................................200

129 RX FIFO Transfer Threshold Port 1 ($0x5B9)..........................................................................200

130 RX FIFO Transfer Threshold Port 2 ($0x5BA) .........................................................................201

131 RX FIFO Transfer Threshold Port 3 ($0x5BB) .........................................................................201

132 TX FIFO High Watermark Ports 0 - 3 ($0x600 – 0x603) ..........................................................202

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133 TX FIF O Low Water mar k Register Ports 0 - 3 ($0x60A – 0x60D)......................... ...................203

134 TX FIFO MAC Threshold Register Ports 0 - 3 ($0x614 – 0x617).............................................204

135 TX FIF O Overflow/Underflow/Out of Sequence Event ($0x61E)..............................................205

136 Loop RX Data to TX FIFO (Line-Side Loopback) Ports 0 - 3 ($0x6 1F) ...................................206

137 TX FIFO Port Reset ($0x620)..................... .. ..... ....... ..... .. ....... ..... ....... ..... .. ....... ..... .. .......... .. .....206

138 TX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x621 – 0x624)............................... .....207

139 TX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x625 – 0x629) ......................................208

140 TX FIFO Occupancy Counte r for Ports 0 - 3 ($0x62D – 0x630)...............................................2 09

141 TX FIFO Port Drop Enable ($0x63D)....................................................... .. ....... ..... .. ..... ....... .....209

142 MDI O Si ngl e Comma nd ($ 0x 680). ............................................................................................210

143 MDIO Single Read and Write Data ($0x681)............................................................................210

144 Autoscan PHY Address Enable ($0x682)................................................................................. 2 11

145 MDI O Cont r o l ($0 x 6 83).............................................................................................................211

146 SPI3 Transmit and Global Configuration ($0x700)............................................. ......................2 12

147 SPI3 Receive Configuration ($0x701)......................................................................................214

148 Add re ss Pa r ity Error Packet Drop Counter ($0x7 0 A)................................... ............................218

149 TX Driver Power Level Ports 0 - 3 ($0x784).............................................................................219

150 TX and RX Power-Down ($0x787) ...........................................................................................219

151 RX Signal Detect Level Ports 0 - 3 ($ 0x793) ............................................................................219

152 Clock and Interface Mode Change Enable Ports 0 - 3 ($0x794)..............................................2 20

153 Optical Module Status Ports 0-3 ($0x799) . ...............................................................................221

154 Optical Module Control Ports 0 - 3 ($0x79A)........................................... .. ....... ....... ..... ....... .....221

155 I

C Control Ports 0 - 3 ($0x79B)............ .......................................................................... .........222

156 I

C Data Ports 0 - 3 ($0x79F)................................................................................................... 222

157 Product Information ....................................................... ....... ....... ............ ....... ....... ....... ............2 27

Datasheet 11

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Contents

Revision History

Page # Description

All Globally replaced GBIC with Optical Module Interface. All Globally edited signal names.

Globally changed SerDes and PLL analog power ball names as follows: TXAVTT and RXAVTT changed to AVDD1P8_2 TXAV25 and RXAV25 changed to AVDD2P5_2

All

PLL1_V DD A and PLL2_V DD A changed to AVDD1P8_1 PLL3_VDDA changed t o AVDD2P5_1 PLL1_GNDA, PLL2_GNDA, and PLL3_GNDA changed to GND

Reworded and rearranged the Product Features section on page one

Changed Jumbo frame support from “10 kbytes” to “9.6 KB”.

20 Changed heading to S ection 2.0, “General Desc ription” [w as Section 2.0 , “Block Diagram”].

22/36

Revers ed sections as follows:

Section 3.0, “Ball Assignments and B all List Tables” Section 4.0, “Ball Assignments and Signal Descriptions”

Modified Table 1 “Ball List in Alphanume ric Order by Signal Name”: Changed A10 from VCC to VDD Changed C12 from VCC to VDD Changed D11 from VCC to VDD Changed J20 from GND to VDD

Revision Number: 007

Revision Date: March 25, 2004

(Sheet 1 of 5)

Changed Ball A1 from NC to No Pad. Changed Balls A2, A3, A22, A23, A24, B1, B2, B23, B24, C1, C24, AB1, AB24, AC1, AC2, AC23, AC24, AD1, AD2, AD3, AD22, AD23, AD24 from NC to No Ball.

Modified Table 2 “Ball List in Alphanumeric Order by Ba ll Location” Changed A10 from VCC to VDD Changed C12 form VCC to VDD Changed D11 from VCC to VDD Changed J20 from GND to VDD

Changed Ball A1 from NC to No Pad. Changed Balls A2, A3, A22, A23, A24, B1, B2, B23, B24, C1, C24, AB1, AB24, AC1, AC2, AC23, AC24, AD1, AD2, AD3, AD22, AD23, AD24 from NC to No Ball.

Updated Figure 4 “Interface Signals” [modified SPI3 interface signals and added MPHY and SP HY

categories; modif ied signal names]. Broke old T able 1, “IXF1104 Signal Descriptions” into the following:

Table 3 “SPI3 Interface Signal Descriptions” on page 38 through Table 14 “Power Supply Signal Descriptions” on page 55

Modified Table 3 “SPI3 Interface Signal Descriptions” on page 38 [edited description for DTPA;

added text to TFCLK description; added text to RFCLK description]. Modified T able 6 “RGMII Interface Signal Descriptions” [Added Ball Designators; added notes

under descriptions].

50 Modified Table 7 “CPU Interface Signal Descriptions” [UPX_DATA[16]: deleted J10, added M10]. 52 Modified Table 9 “Optical Module Interf ace Signal Descriptions” [added Ball Designators]. 53 Modified Table 10 “MDIO Interface Signal Descriptions” [moved note from MDC to MDIO].

Modified Table 14 “Power Supply Signal Descripti ons” [added Ball Designators A4, A 21, and AD21

to GND; added AVDD1P8_1, AVDD1P8_2, AVDD2P5_1, and AVDD2P5_2].

12 Datasheet

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Contents

Revision Number: 007

Revision Date: March 25, 2004

Page # Description

Modified Section 4.3, “Signal Description Tables” [changed heading from “Signal Naming

Conven tions; adde d ne w head in gs Section 4.1.1, “Signal Name Conventions” and Section 4.1.2,

“Register Address Conventions”; and added/enhanced material under headin gs.

Added ne w Section 4.5, “Multiplexed Ball Connections” with Table 16 “Line Side Interface

Multip le xe d Balls” and Table 17 “SPI3 MPHY/SPHY Interface”.

Modified Sectio n 4 .7 , “ Pow er S u pply Se qu en cing ” [c ha nged la ng ua ge unde r thi s se ct io n and a dde d

Section 4.7.1, “Power-Up Sequence” and Sec ti on 4.7.2, “Power -D o w n Seq ue nce”].

Modified Table 5 “Power Supply Sequencing” [deleted 3.3 V S upplies Stable; changed Apply 1.8 V

to VDD, AVDD1P8_1, and AVDD1P8_2; changed Apply 2.5 V to AVDD2P5_1 and AVDD2P5_2]. Modified T able 18 “Definition of Output and Bi-dir ectional Balls During Hardware Reset” [changed

comments for Optical Modules]. Modified Table 20 “Pull-Up/Pull-Down and Unused Ball Guidelines” [cha ng ed TR ST _L to p ul l- d own ;

added MDIO, UPX_RDY_L, I Added ne w Section 4.9, “Analog Power Filtering” [including Figure 6 “Analog Power Supply Filter

Network” on page 64 and Table 21 “Analog Power Balls” on page 64].

Modified/edited text under Section 5.1, “Media Access Controller (MAC)” [rearranged and created

new bullets].

66 Modified first paragraph under Section 5.1.1.1, “Padding of Under s ized Frames on Transmit”. 66 Modified entire Section 5.1.1.3, “Filtering of Receive Packets”. 67 Added new Section 5.1.1.3.6, “Filter CRC Error Packets”. 68 Added note under Table 22 “CRC Errored Packets Drop Enable Behavior”.

Added ne w Section 5.1.2, “Flow Control” including Figure 7 “Packet Buffer in g FIFO”, Figure 8

“Ethernet Frame Format”, and Figure 9 “PAUSE Frame Format”.

Replaced Section 5.1.2.1.5, “Transmit Pause Control Interface” [added Tabl e23 “ Valid Decode s f or

TXPAUSEADD[2:0]” and mo di fied Table 10 “Transmit Pause Control Interface”. 73 Modified Figure 10 “Transmit Pause Control Interface” 74 Added note under Section 5.1.3.1 , “Configuration of the IXF1104 ”. 75 Added table not e to Table 24 “Operational Mode Configuration Registers”. 76 Added note under Section 5.1.4.3, “Fiber Forced Mode”. 78 Modified Section 5.1.6.2, “TX Statistics” [added text to third senten ce in first parag ra ph ].

Modified Section 5.1.6.3, “Loss-less Flow Cont rol” [changed “two kilometers” to “five kilometers” in

last sentence.

79 Modified Section 5.1.7.1.2, “RX FIFO” [changed 10 KB to 9.6 KB; added text to last paragraph]. 82 Rewrote/replaced Section 5.2, “SPI3 Interface”. 85 Edited signal names in Figure 13 “MPHY 32-Bit Interface”. 89 Edited signal names in Figure 16 “SPHY Connection for Two IXF1104 Ports (8-Bit Interface)”.

Added ne w Section 5.2.2.9, “SPI3 Flow Control”.

[Removed old “Packet-Level and Byte-Level Transfers” section.}

93 Modified Figure 17 “MAC GMII Interconnect” [edited signal names].

Removed old Section 5.3.3 Electrical Requirements and Table 27 “Electrical Requirements” –

changed Input high current Max from 40 to 15 and Input low curren t Min from -600 to -15.

95 Added a note under Section 5.4, “Red uced Gigabit M edia Independent Interface (RGMII)”. 95 Modified Figure 18 “RGMII Interface” [edited signal names]. 97 Modified Figure 19 “TX_CTL Behavior” [changed signal names].

(Sheet 2 of 5)

C_DATA_ 3:0, and TX_DISABLE_3:0].

Datasheet 13

Document Number: 278757 Revision Number: 007 Revision Date: March 25, 2004

Contents

Revision Number: 007

Revision Date: March 25, 2004

(Sheet 3 of 5)

Page # Description

97 Modified Figure 20 “RX_CTL Behavior” [changed signal names].

Modified Section 5.5, “MDIO Control and Interface” [changed 3.3 us to 3.3 ms in fourth paragraph,

third se nt en ce].

102

Modif ied/replaced all text under Section 5.6, “SerDes Interface” on page 102 [added Table29

“SerDes Driver TX Power Levels”].

NA Removed old Section 5.6.2.4 AC/DC Coupling. NA Removed old Section 5.6.2.9 System Ji tter.

106 Modified Table 30 “IXF1104-to -SFP Optical Module Interface Connections” [edited signal names]. 106

Modified/replaced text and deleted old “Figure 19. Typical GBIC Module Functional Diagram” under

Section 5.7, “Optical Module Interface”].

107 Modified second sentence under S ec tio n 5. 7. 2 .2 .1, “MOD_DE F _0 :3 ”. 108 Modified second sentence under S ec tio n 5. 7. 2 .2 .3, “RX_LOS_ 0 : 3”. 108 Removed third paragraph under Section 5.7.2.2.7, “RX_LO S_INT”. 109 Modifie d f ir st an d se co nd paragra ph s un de r Section 5.7.3, “I²C Module Configuration Interface”. 110 Modified Section 5.7.3.3, “I2C Write Operation” [edited portions of text].

115

118

Modified T able 31 “LED Interface Signal Descriptions” [changed 0.5 MHz to 720 Hz f or LED_CLK

under Signal Description].

Modified Table 35 “LED Behavior (Fiber Mode)” [changed links under Description to “Link LED

Enable ($0x502)”].

NA Removed old Figure 30 “CPU – External and Internal Connections”.

122 Modified Table 37 “Byte Sw apper Behavior” [edit ed /ad ded new value s] . 122 Modif ied second paragraph under Section 5.10, “TAP Interface (JTAG)” 125 Modified Figure 33 “SPI3 Interface Loopback Path ”. 125 Added note under Section 5.11.2, “Line Side Interfa ce Loopback”. 126 Modified Figure 34 “Line Side Interface Loopback Path”. 126 Changed Section 5.12, “Clocks” [from GBIC output clock to I 128 Changed Section 5.12.6, “I2C Clock” [from GBIC Clock to I

C Clock].

129 Added new Section 6.0, “Applications”.

Modified Table 39 “Absolute Maximum Ratings” [changed SerDes analog power to AVDD1P8_2

131

and AVDD2P5_2; changed “PLL1_VDDA and PLL2_VDDA to AVDD1P8_1; changed PLL3_VDDA

to AVDD2P5_1.

Modified Table 40 “Recommended Operating Conditions” [changed SerDes analog power to

132

AVDD1P8_2 and AVDD2P5_2; changed “ PLL1_VDDA and PLL2_VDDA to AVDD1P8_ 1; changed

PLL3_VDDA to AVDD2P5_1.

133

141

142

145

Modified Table 42 “SerDes Transmit Characteristics” [included SerDes power driver level

information].

Modified Table 49 “GMII 1000BASE-T Transmit Signal Parameters” (changed Min values f or t1 and

t2.

Modified Table 50 “GMII 1000BASE-T Receive Signal Parameters” (changed Min values for t1 and

t2.

Replaced old MDIO Timing diagram and table with Figure 43 “M DIO Write Timing Diagram”, Figure

44 “MDIO Read Timing Diagram”, an d Table 52 “MDIO Timing Parameters”.

14 Datasheet

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Revision Number: 007

Revision Date: March 25, 2004

Revision Number: 007

Revision Date: March 25, 2004

Page # Description

Broke up the old Register Map into Table 59 “MAC Control Registers ($ Port Index + Offset)”,

Table 60 “MAC RX Statistics Registers ($ Port Index + Offset)”, Table 61 “MAC TX Statistics

155

158 Edited Table 63 “Global Status and Configuration Registers ($ 0x500 - 0X50C)” [no offset]. 158 Edited Table 64 “RX FIFO Registers ($ 0x580 - 0x5BF)” [no offset]. 159 Edited Table 65 “TX FIFO Registers ($ 0x600 - 0x63E)” [no offset]. 160 Edited Table 66 “MDIO Registers ($ 0x680 - 0x683)” [no offset]. 160 Edited Table 67 “SPI3 Registers ($ 0x700 - 0x716)” [no offset]. 161 Edited Table 68 “SerDes Registers ($ 0x780 - 0x798)” [no offset]. 161 Edited Table 69 “Optical Module Registers ($ 0x799 - 0x79F)” [no offset].

162

166 167 Modified Table 84 “FC Enable ($ Port_Index + 0x12) ” [changed description for bits 1:0]. 168

169

170

171

173

177

192

194

195

197

198

200

Regist ers ($ Port Index + Offset)”, Table 62 “PHY Autoscan Registers ($ Port Index + Offset)”, Table 63 “Glo bal Status and Configuration Registers ($ 0x500 - 0X50C)”, Ta bl e 64 “RX FIFO Registers ($ 0x580 - 0x 5BF)”, Table 65 “TX FIFO Registers ($ 0x600 - 0x63E)”, Table 66 “MDIO Registers ($ 0x680 - 0x683)”, Table 67 “SPI3 Registers ($ 0x700 - 0x716)”, Table 68 “SerD es Registers ($ 0x780 - 0x798)”, and Table 69 “Optical Module Registers ($ 0x799 - 0x79F)”.

Modified T able 71 “Desired Duplex ($ Port_Index + 0x02)” [changed 100 Mbps to 1000 Mbps in register description.

Modified Table 82 “MAC IF Mode and RGMII Speed ($ Port _Index + 0x10)” [Added text to register description.]

Modified Table 88 “RX Config Word ($ Port_Index + 0x16)” [edited Register Desc ription text; change d description and type for bits 13:12].

Modified Table 89 “TX Config Word ($ Port_Index + 0x17)” [edited description and type fo r bits 14, 13:12.

Modified Table 90 “Diverse Config Write ($ Port_Index + 0x18)” [edited description and type for bits 18:8; cha n ge d bit s 3:1 to R es erv e d; ad de d tabl e note 2].

Renamed/modified Table 91 “RX P ac k et Fil t e r Co ntrol ($ Port_In de x + 0x19 ) ” [old register name added RX to heading; added table note 2].

Modified Table 93 “MAC RX Statistics ($ Port_Index + 0x20 – + 0x39)” [added note to RxPauseMacControlReceivedCounter description; edited note 3 and added note 4].

Modified T able 94 “MAC TX Statistics ($ Port_Index +0x40 – +0x58)” [changed “15 26 -ma x” to “ 1 523

- max fra me size” for Txpkts1519toMaxOctets descript ion]. Modified T able 113 “RX FIFO High Watermark Port 0 ($0x580)”, Tabl e114 “RX F IFO High

Watermark Port 1 ($0x581)”, Table 115 “RX FIFO High Watermark Port 2 ($0x582)”, and Table 116 “RX FIFO High Watermark Port 3 ($0x583)” [changed bits 11:0 description].

Renamed and modi fie d Table 121 “RX FIFO Overflow Frame D rop Counter Ports 0 - 3 ($0x594 –

0x597)”

[old register name: RX FIFO Number of Frames Removed Ports 0 to 3; renamed bit names to match register names; removed “This register gets updated after one cycle of sw reset is applied” under D escription] .

Modified T able 123 “RX FIFO Errored Frame Drop Enable ($0x59F)” [renamed bit names to match register name].

Renamed/modified T able 125 “RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2 - 0x5A5)”

on page 197 [older register name: RX FIFO Dropped Packet Counter for Ports 0 to 3; renamed bit

names to match register name]. Modified T able 126 “RX FIF O SPI 3 Loopback Enable for Ports 0 - 3 ($0x5B2)” [renamed heading

and bit name; changed description and type for bits 7:0]. Renamed Table 128 “RX FIFO Transfer Threshold Port 0 ($0x5B8)” on page 200 [from “RX FIFO

Jumbo Packet Size; changed bit names an d edited/adde d text under description].

(Sheet 4 of 5)

Contents

Datasheet 15

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Contents

Revision Number: 007

Revision Date: March 25, 2004

(Sheet 5 of 5)

Page # Description

206

207

208

Modified Table 136 “Loop RX Data to TX FIFO (Line-Side Loopback) Ports 0 - 3 ($0x61F )”

[renamed heading and bit name].

Modified Table 138 “TX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x621 – 0x624)”

[renamed from TX FIFO Number of Frames Removed Ports 3 - 0].

Modified Table 139 “TX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x625 – 0x629)” [renamed

from TX FIFO Number of Dr opped Packets Ports 0-3 and text under the description].

209 Modified Table 141 “TX FIFO Port Drop Enable ($0x63D)” [changed description for bits 3:0]. 210

Modified Table 142 “MDIO Single Command ($0x680)” [changed default; changed description and

default for bits 9:8; changed default for bits 4:0].

211 Modified Table 144 “Autoscan PHY Address Enable ($0x682)” [added note to register description]. 212

214

Modified Table 146 “SPI3 Transmit and Global Configuration ($0x700)” [broke out bits 19:16, 7:4,

and 3:0 and changed description te xt].

Modified Table 147 “SPI3 Receive Configuration ($0x701)” [broke out bits and modified all text

adding SPHY and MPHY modes].

Modified Table 152 “Cloc k and Interface Mode Change Enable Ports 0 - 3 ( $0x794)” [deleted

220

second paragraph of the Register Description; renamed bits to match caption; changed text under

Description].

221 Added note under Section 8.4.11, “Optical Module Register Overview”. 221 Modified Table 153 “Optical Module Status Ports 0-3 ($0x799)” [edited register description]. 221 Modified Table 154 “Optical Module Control Ports 0 - 3 ($0x79A)” [changed register description].

NA Removed/Reserved Table 190 “TX and RX AC/DC Coupling Selection ($7x780)”.

Deleted old Figure 19, “Typical GBIC Module Functional Diagram” under Section 5.7, “Optical

Module Interface”.

NA Removed old Section 5.1.1.5, “Pause Command Frames. ”

180(old)

Removed ol d Table 1 3. TX FI FO Mini F r ame S ize for MAC and Padd in g Ena bl e Por t 0 t o 3 R egi st er

(Addr: 0x63E) and replaced with Reserved.

Revision Number: 006

Revision Date: August 21, 2003

(Sheet 1 of 2)

Page # Description

19 Modified Table 1 “Intel

IXF1104 Signal Descriptions” 53 Modified Section 5.1.1.1, “Padding of Undersized Frames on Transmit”. 60 Modified text for etherStatsCollision in Table 9 “RMON Additional St atistics”.

87 M o dif ie d Table 17 “Intel

IXF1104-to-Optical Module Interface Connections” 65 Modified first paragraph under Section 5.3.1.2, “Clock Rates”. 87 Modified Section 5.8.2.1, “High-Speed Seri al Interfac e”.

100 Modified Figure 27 “Microprocessor — External and Internal Connections”. 110 Changed PECL to LVDS under Section 6.1, “DC Specifications”. 113 Modified table note 4 in Table 32 “SPI3 Receive Interface Signal Parameters”. 119 Modifie d Table 3 7 “ SerDes Timing Pa ram eters”. 125 Modif ie d Table 4 0 “ Mi c roprocess or Interface Wr ite Cy cl e AC Signal Parameters”.

16 Datasheet

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Contents

Revision Number: 006

Revision Date: August 21, 2003

Page # Description

140

Modif ied Table 53 “IPG Receive and Transmit Time Register (Addr: Port_Index + 0x0A – +

0x0C)”. 143 Modified Table 60 “S hort Runts Threshold Register (Addr: Port_Index + 0x14)”. 143 Modified Table 61 “D iscard Unknown Control Frame Register (A ddr: Port_In dex + 0x15)”. 143 Modified Table 62 “RX Config Word Register Bi t Definition (Addr: Port_Index + 0x16)”. 145 Modified Table 64 “DiverseConfigWrite Register (Add r: Port_Index + 0x18)”. 148 Modified Table 67 “RX Statistics Regis ters (Addr: Port_Index + 0x20 – + 0x39)”. 163 Modified Table 82 “Microprocessor Interfa c e Register (Addr: 0x508)”. 164 Modified Table 84 “LED Flash Rate Register (Add r: 0x50A)”. 169 Modified Table 93 “RX FIFO Errored Frame Drop Enable Register (Addr: 0x59F)”. 170 Modified Table 96 “RX FIFO Loopback Enable for Ports 0 - 3 Registe r (Addr: 0x5B2)”. 171 Added Table 98 “RX FIFO Jumbo Packet Size 0-3 Register (Addr: 0x5B8 – 0x5BB”. 172 Added Table 99 “RX FIFO Jumbo Packet Size Port 0 Register B it Definitions (Addr: 0x5B8)”. 172 Added T able 100 “RX FIFO Jumbo Packet Size Port 1 Register Bit Definitions (Addr: 0x5B9)”. 172 Added T able 101 “RX FIFO Jumbo Packet Size Port 2 Register Bit Definitions (Addr: 0x5BA)”. 172 Added T able 102 “RX FIFO Jumbo Packet Size Port 3 Register Bit Definitions (Addr: 0x5BB)”.

178

Modified Table 110 “TX FIFO Number of Dropped Packets Register Ports 0-3 (Addr: 0x625 –

0x629)”. 177 Modified Table 108 “TX FIFO Port Reset Register (Addr: 0x620)”. 177 Modified Table 108 “TX FIFO Port Reset Register (Addr: 0x620)”. 177 Modified Table107 “Loop RX Data to TX FIFO Register Ports 0 - 3 (Addr: 0x61F)”.

179

Added Table 111 “TX FIFO Occupancy Counter for Ports 0 - 3 Registers (Addr: 0x62D –

0x630)”. 180 Added Table 112 “TX FIFO Port Drop Enable Register (Addr: 0x63D)”. 181 Modified Table 114 “MDI Single Command Register (Addr: 0x680)”. 186 Added Table 122 “Tx an d Rx Power-Down Register (Addr: 0x787)”. 194 Replaced Figure 53 “Intel

(Sheet 2 of 2)

IXF1104 Example Package Marking”.

Revision Date: April 30, 2003

Revision 005

Page # Description

Initial ex te rna l release.

Revisions 001 through 004

Revision Date: April 2001 – December 2002

Page # Description

Internal releases.

Datasheet 17

Document Number: 278757 Revision Number: 007 Revision Date: March 25, 2004

Contents

18 Datasheet

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004

IXF1104 4-Port Gigabit Ethernet Media Access Controller

1.0 Introduction

This document contains information on the Intel® IXF1104 4-Port 10/100/1000 Mbps Ethernet Media Access Controller (MAC).

1.1 What You W ill Find in This Document

This document co ntains the following sections :

• Section 2.0, “General Description” on page 20 provides the block diagram system

architecture.

• Section 3.0, “Ball Assignments and Ball List Tables” on page 22 shows the signal naming

methodology and signal descriptions.

• Section 4.0, “Ball Assignments and Signal Descriptions” on pa ge 36 illustrates and lists the

IXF1104 bal l grid diagram with two ball list tables ( by si gnal name and ball location)

• Section 5.0, “Fun ctional Descriptions” on page 65 gives detailed information about the

operation of the IXF1104 including general features, and interface types and descriptions.

• Sect io n 7.0, “E l e c trical S p e c if ications” on page 131 provides information on the product-

operating parameters, electrical specifications, and timing parameters.

• Section 8.0, “Register Set” on page 154 illustrates and lists the memory map, detailed

descriptions , default values for the register set, and detailed information on each register.

• Section 9.0, “Mechanical Specifications” on pag e 223 illustrates the packaging information.

• Section 10.0, “Pro duct Ordering Information” on page 227 provides ordering information.

1.2 Related Documents

Document

Intel

IXF1104 Media Access Controller Design and La yout Guide 278696

IXF1104 Media Access Controller Thermal Design Considerations 278751

Intel

IXF1104 Media Access Controller Development Kit Manual 278785

IXF1104 Media Ac cess Controller Specification Update 278756

Intel

Document

Number

Datasheet 19

Document Number: 278757 Revision Number: 007 Revision Date: March 25, 2004

IXF1104 4-Port Gi gab it Ethernet Media Access Controller

2.0 General Description

The IXF1104 provides up to a 4.0 Gbps interface to four individual 10/100/1000 Mbps full-duplex or 10/100 Mbps half-duplex-capable Ethernet Media Access Controllers (MACs). The network proce ssor is supported through a System Packet Interface Phase 3 (SPI3) media interface. The following PHY interfaces are selected on a per-port basis:

• Serializer /Deserializer (SerDes) with Optical Module Interface support

• Gigabit Media Indepe ndent Interface (GMII)

• Reduced Gigabit Media Independent Interface (RGMII).

Figure 1 illustrates the IXF1104 block diagram.

Figure 1. Block Diag ram

CPU

uP IF

PHY 1 Devic e

PHY 2 Devic e

Intel

IXF1104 M AC

SPI3

Se rD e s /RGMI I/GMI I In t e r fa ce

PHY 3 Devic e

PHY 4 Devic e

Forw ardi n g Engi ne/N etwork Processor

MDIO

B3175-0

20 Datasheet

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004

Figure 2 illustrates the IXF1104 internal architecture.

Figure 2. Internal Architecture

IXF1104 4-Port Gigabit Ethernet Media Access Controller

SPI3 Interface

CPU Interface RMON Statistics

PLLs

Packet

Buffer

Packet

Buffer

Packet

Buffer

Packet

Buffer

MDIO OMI

Clock Control Block Clock Register Block

10/100/1000 MAC

RGMII/GMII Inte rface

PMA Layer SerDes

RGMII/GMII Inte rface

PMA Layer SerDes

RGMII/GMII Inte rface

PMA Layer SerDes

RGMII/GMII Inte rface

PMA Layer SerDes

B3176-0

Datasheet 21

Document Number: 278757 Revision Number: 007 Revision Date: March 25, 2004

IXF1104 4-Port Gi gab it Ethernet Media Access Controller

3.0 Ball Assignments and Ball List T abl es

3.1 Ball Assignments

See Figure 3, Table 1 “Ball List in Alphanumeric Order by Signal Name” on page 23, and Table 2

“Ball List in Alphanumeric Order by Ball Location” on page 29 for the IXF1104 ball assignments.

Figure 3. Intel

IXF1104 552-Ball CBGA Assignments (Top View)

AD AC AB AA Y W V U T R P N M L K J H G F E D C B A

AD1

AC2

AC3AD3

3 4 5 6 7 8

AD8

9 10 11 12 13 14 15 16

17 18 19 20 21

22 23 24

W7Y7AA7AB7AC7AD7

V7 U7 T7 R7 P7 N7 M7 L7 K7 J7 H7 G7 F7 E7 D7 G7 B7 A7

W8Y8AA8AB8AC8

W9Y9AA9AB9AC9AD9

T10

U10

V10

W10Y10AA10AB10AC10AD10

T11

U11

V11

W11Y11AA11AB11AC11AD11

T12

U12

V12

W12Y12AA12AB12AC12AD12

T13

U13

V13

W13Y13AA13AB13AC13AD13

T14

U14

V14

W14Y14AA14AB14AC14AD14

T15

U15

V15

W15Y15AA15AB15AC15AD15

T16

U16

V16

W16Y16AA16AB16AC16AD16

T17

U17

W17Y17AA17AB17AC17AD17

T18

U18

V18

W18Y18AA18AB18AC18AD18

T19

U19

V19

W19Y19AA19AB19AC19AD19

T20

U20

V20

W20Y20AA20AB20AC20AD20

T21

U21

V21

W21Y21AA21AB21AC21AD21

T22

U22

V22

W22

AA22AB22AC22AD22

Y22

T23

U23

V23

W23Y23AA23AB23AC23AD23

T24

U24

V24

W24Y24AA24AB24AC24AD24

R10 R11

R12

R13 R14

R15 R16 R17

R18

R19

R20 R21 R22

R23

R24

N10

P10

N11

P11

N12

P12

N13

P13

N14

P14

N15

P15

N16

P16

N17

P17

N18

P18

N19

P19

N20

P20

N121

P21

N22

P22

N23

P23

N24

P24

M10 M11

M12

M13 M14

M15 M16 M17

M18

M19

M20 M21 M22

M23

M24

L10 L11

L12

L13 L14

L15 L16 L17

L18

L19

L20 L21 L22

L23

L24

K10 K11

K12

K13 K14

K15 K16 K17

K18

K19

K20 K21 K22

K23

K24

J10 J11

J12

J13 J14

J15 J16 J17

J18

J19

J20 J21 J22

J23

J24

J8 J9

G10

H10

G11

H11

G12

H12

G13

H13

G14

H14

G15

H15

G16

H16

G17

H17

G18

H18

G19

H19

G20

H20

G21

H21

G22

H22

G23

H23

G24

H24

AD AC AB AA Y W V U T R P N M L K J H G F E D C B A

= No Pad (A1) = No Ball (A2, A3, A22, A23, A24, B1, B2, B23, B24, C1, C24, AB1, AB24, AC1, AC2, AC23, AC24, AD1, AD2, AD3,

AD22, AD23, AD24)

F10 F11

F12

F13 F14

F15 F16 F17

F18

F19

F20 F21 F22

F23

F24

B1C1D1E1F1G1H1J1K1L1M1N1P1R1T1U1V1W1Y1AA1AB1AC1

A2B2C2D2E2F2G2H2J2K2L2M2N2P2R2T2U2V2W2Y2AA2AB2AD2

A3B3C3D3E3F3G3H3J3K3L3M3N3P13R3T3U3V3W3Y3AA3AB3

A4B4C4D4E4F4G4H4J4K4L4M4N4P4R4T4U4V4W4Y4AA4AB4AC4AD4

A5B5C5D5E5F5G5H5J5K5L5M5N5P5R5T5U5V5W5Y5AA4AB5AC5AD5

A6B6C6D6F6F6G6H6J6K6L6M6N6P6R6T6U6V6W6Y6AA6AB6AC6AD6

6 7

F8 F9

E10 E11

E12

E13 E14

E15 E16 E17

E18

E19

E20 E21 E22

E23

E24

C10

D10

C11

D11

C12

D12

C13

D13

C14

D14

C15

D15

C16

D16

C17

D17

C18

D18

C19

D19

C20

D20

C21

D21

C22

D22

C23

D23

C24

D24

B28

B9 B10 B11

B12

B13 B14

B15 B16 B17

B18

B19

B20 B21 B22

B23

B24

A9 A10 A11

A12

A13 A14

A15 A16 A17

A18

A19

A20 A21 A22

A23

A24

B1458-01

8 9 10 11 12

13 14 15 16

17 18 19 20 21

22 23 24

22 Datasheet

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004

IXF1104 4-Port Gi gab it Ethernet Media Access Controller

3.2 Ball List Tables

3.2.1 Balls Listed in Alphabetic Order by Signal Name

Table 1 shows the ball locations and signa l names arranged in alphanumeric order by signa l name.

The following table notes relate to Table 1 and Table 2:

1. GMII Ball Connection:

See T able 16 for connection in RGMII or fiber mode.

2. SPI3 Ball Connection:

See T able 17 for proper SPHY and MPHY connection.

3. Fiber Mode Ball Connection:

See T able 16 for use in RGMII and GMII (copper mode).

Tab le 1. Ba ll Li st in Alp hanumeric Orde r by Signal Name

Signal Name

AVDD1P8_1 A5 AVDD1P8_1 A20 AVDD1P8_2 T23 AVDD1P8_2 AB16 AVDD2P5_1 AD20 AVDD2P5_2 R18 AVDD2P5_2 U14

CLK125 AD19

COL_0

COL_1

COL_2

COL_3

CRS_0

CRS_1

CRS_2

CRS_3 DTPA_0 DTPA_1 DTPA_2 DTPA_3

GND B6 GND B10 GND B15 GND B19

Ball

Location

AB6 AB10 AD15 AB17

AA5

AA9 AB15 AC16

Signal Name

GND D4 GND D8 GND D12 GND D13 GND D17 GND D21 GND F2 GND F6 GND F10 GND F15 GND F19 GND F23 GND H4 GND H8 GND H12 GND H13 GND H17 GND H21 GND J10 GND J15 GND K2 GND K6 GND K9 GND K11

Ball

Location

Signal Name

GND K14 GND K16 GND K19 GND K23 GND L10 GND L12 GND L13 GND L15 GND M4 GND M8 GND M11 GND M14 GND M17 GND M21 GND N4 GND N8 GND N11 GND N14 GND N17 GND N21 GND P10 GND P12 GND P13 GND P15

Ball

Location

23 Datasheet

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004

IXF1104 4-Port Gigabit Ethernet Media Access Controller

Signal Name

GND R2 GND R6 GND R9 GND R11 GND R14 GND R16 GND R19 GND R23 GND T10 GND T15 GND U4 GND U8 GND U12 GND U13 GND U17 GND U21 GND W2 GND W6 GND W10 GND W15 GND W19 GND W23 GND AA4 GND AA8 GND AA12 GND AA13 GND AA17 GND AA21 GND AC6 GND AC10 GND AC15 GND AC19 GND AC14 GND L20 GND L5 GND R7 GND AB12 GND A4

Ball

Location

Signal Name

Ball

Location

GND A21 GND AD21

C_CLK L23

C_DATA_0

C_DATA_1

C_DATA_2

C_DATA_3

L24 M24 N24

P24

LED_CLK K24

LED_DATA M22

LED_LATCH L22

MDC

MDIO

W24

V21

MOD_DEF_INT N22

NC D24 NC E12 NC F11 NC G15 NC H7 NC H18 NC J21 NC K7 NC K18 NC K20 NC K22 NC L18 NC L19 NC L21 NC M7 NC M18 NC M20 NC N3 NC N18 NC P2 NC P4 NC P6 NC P7 NC P8 NC P17

Signal Name

NC P18 NC R5 NC R10 NC R12 NC R13 NC R15 NC R20 NC T6 NC T7 NC T8 NC T9 NC T21 NC T22 NC U5 NC U7 NC U9 NC U11 NC U18 NC V9 NC V10 NC V11 NC V13 NC AB18 NC AD4

NC AD5 No Ball A2 No Ball A3 No Ball A22 No Ball A23 No Ball A24 No Ball B1 No Ball B2 No Ball B23 No Ball B24 No Ball C1 No Ball C24 No Ball AB1 No Ball AB24

Ball

Location

Datasheet 24

Document Number: 278757 Revision Number: 007 Revision Date: March 25, 2004

IXF1104 4-Port Gi gab it Ethernet Media Access Controller

Signal Name

No Ball AC1 No Ball AC2 No Ball AC23 No Ball AC24 No Ball AD1 No Ball AD2 No Ball AD3 No Ball AD22 No Ball AD23 No Ball AD24 No Pad A1

PTPA RDAT_0 RDAT_1 RDAT_2 RDAT_3 RDAT_4 RDAT_5 RDAT_6 RDAT_7 RDAT_8 RDAT_9

RDAT_10 RDAT_11 RDAT_12 RDAT_13 RDAT_14 RDAT_15 RDAT_16 RDAT_17 RDAT_18 RDAT_19 RDAT_20 RDAT_21 RDAT_22 RDAT_23 RDAT_24 RDAT_25

Ball

Location

B11 A15 A14 B14 C14 C13 D14 E14 F14 A17 C17 D16 E16 F16 E17 E18 F18 B20 B22 C20 C21 C22 D22 E22 E21 G18 G19

Signal Name

RSX

RDAT_26 RDAT_27 RDAT_28 RDAT_29 RDAT_30 RDAT_31

RENB_0 RENB_1 RENB_2 RENB_3 REOP_0 REOP_1 REOP_2 REOP_3 RERR_0 RERR_1 RERR_2 RERR_3

RFCLK RMOD0 RMOD1

RPRTY_0 RPRTY_1 RPRTY_2 RPRTY_3

RSOP_0 RSOP_1 RSOP_2 RSOP_3

RVAL_0 RVAL_1 RVAL_2 RVAL_3

RX_DV_0 RX_DV_1 RX_DV_2 RX_DV_3

Ball

Location

G20 G21 G22 G23 G24

F24 A13 A18 C19 E24 C16 D18 C23

J19 A16 G17 D20 H20 A19 G14 G13 E15 G16 E20

F20 B16 C18 E23

J18 E13 C15 B18 E19

F22

AB11

Y24 V18

Signal Name

RX_ER_0 RX_ER_1 RX_ER_2 RX_ER_3

RX_LOS_INT

RXC_0 RXC_1 RXC_2 RXC_3

RX_N_0 RX_N_1 RX_N_2 RX_N_3 RX_P_0 RX_P_1 RX_P_2 RX_P_3

RXD0_0 RXD0_1 RXD0_2 RXD0_3 RXD1_0 RXD1_1 RXD1_2 RXD1_3 RXD2_0 RXD2_1 RXD2_2 RXD2_3 RXD3_0 RXD3_1 RXD3_2 RXD3_3 RXD4_0 RXD4_1 RXD4_2 RXD4_3 RXD5_0

Ball

Location

Y12

AA22

U20 P19 R22 U22 R24 V24 P22 V22 T24 U24

V4 AD11 AA24

V23

Y20 Y17

Y11 Y21 Y18

W11

Y22 Y19

Y23

W18

Y6 AD10

W22

T16

25 Datasheet

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004

IXF1104 4-Port Gigabit Ethernet Media Access Controller

Signal Name

RXD5_1

RXD6_1

RXD7_1

STPA

RXD5_2 RXD5_3 RXD6_0

RXD6_2 RXD6_3 RXD7_0

RXD7_2 RXD7_3

Ball

Location

AC11

V20 T17 AB5

AA11

V19 T18 AC5 Y10

W20

T19 C11

SYS_RST_L AD12

TADR0 TADR1

A11

A12

TCLK J22 TDAT0 TDAT1 TDAT2 TDAT3 TDAT4 TDAT5 TDAT6 TDAT7 TDAT8 TDAT9

TDAT10 TDAT11 TDAT12 TDAT13 TDAT14 TDAT15 TDAT16 TDAT17 TDAT18 TDAT19 TDAT20 TDAT21

B3 C2 C3 D1 C4 C5 B5 C6 F1 G1 G2 H1 J1 J2 J3 H3 E5 E6 E7 E8 E9

E10

Signal Name

TDAT22

TDAT23

TDAT24

TDAT25

TDAT26

TDAT27

TDAT28

TDAT29

TDAT30

TDAT31

TDI J24

TDO H24

TFCLK TMOD0 TMOD1

TENB_0 TENB_1 TENB_2 TENB_3 TEOP_0 TEOP_1 TEOP_2 TEOP_3 TERR_0 TERR_1 TERR_2 TERR_3

TMS H22 TPRTY_0 TPRTY_1 TPRTY_2 TPRTY_3

TRST_L J23 TSOP_0 TSOP_1 TSOP_2 TSOP_3

TSX E1

Ball

Location

F9 C8 G4 G5 G6 G7 G8 G9 F5 F7

B7 E2 C9

J4 A7 F3 E4 H5 A8 K1

E11

J8 D7 A6 D9

D5 G3 B9

C7 E3

C10

Signal Name

TX_EN_0 TX_EN_1 TX_EN_2 TX_EN_3 TX_ER_0 TX_ER_1 TX_ER_2 TX_ER_3

TX_FAULT_INT

TX_N_0

TX_N_1

TX_N_2

TX_N_3

TX_P_0

TX_P_1

TX_P_2

TX_P_3

TXC_0

TXC_1

TXC_2

TXC_3

TXD0_0

TXD0_1

TXD0_2

TXD0_3

TXD1_0

TXD1_1

TXD1_2

TXD1_3

TXD2_0

TXD2_1

TXD2_2

TXD2_3

TXD3_0

TXD3_1

TXD3_2

TXD3_3

TXD4_0

Ball

Location

AB2

AC22

V12

AD6

AD17

AB13

P23 Y14

AD14

Y16

AD18

Y13

AD13

W16

AC18

AA1

AD7

AC20

AB14

AC7

AB20

V14

AB7

AB21

V15

AB9

AB22

V16 AA3

AD9

AB23

V17 AB3

Datasheet 26

Document Number: 278757 Revision Number: 007 Revision Date: March 25, 2004

IXF1104 4-Port Gi gab it Ethernet Media Access Controller

Signal Name

TXD4_1

TXD4_2

TXD4_3

TXD5_0

TXD5_1

TXD5_2

TXD5_3

TXD6_0

TXD6_1

TXD6_2

TXD6_3

TXD7_0

TXD7_1

TXD7_2

TXD7_3

Ball

Location

AA7 AD16 AA14

AC3

AB8 AB19

Y15

AB4

AD8 AA20 AA16

AC9 AA18

W14 TXPAUSE_ADD0 N20 TXPAUSE_ADD1 P20 TXPAUSE_ADD2 P21

TXPAUSEFR T20

UPX_ADD0 P3 UPX_ADD1 N1 UPX_ADD2 P1 UPX_ADD3 R1 UPX_ADD4 T1 UPX_ADD5 U1 UPX_ADD6 V1 UPX_ADD7 V2 UPX_ADD8 V3

UPX_ADD9 U3 UPX_ADD10 T3 UPX_BADD0 T2 UPX_BADD1 W3

UPX_CS_L R3 UPX_DATA0 L2 UPX_DATA1 K3 UPX_DATA2 L3 UPX_DATA3 M3 UPX_DATA4 L4

Signal Name

Ball

Location

UPX_DATA5 N5 UPX_DATA6 M5 UPX_DATA7 K5 UPX_DATA8 P5 UPX_DATA9 L6

UPX_DATA10 L7

UPX_DATA11 N7 UPX_DATA12 L8 UPX_DATA13 H9 UPX_DATA14 J9 UPX_DATA15 N10 UPX_DATA16 M10 UPX_DATA17 K10 UPX_DATA18 G10 UPX_DATA19 H11 UPX_DATA20 G11 UPX_DATA21 K12 UPX_DATA22 G12 UPX_DATA23 K13 UPX_DATA24 H14 UPX_DATA25 K15 UPX_DATA26 N15 UPX_DATA27 M15 UPX_DATA28 J16 UPX_DATA29 H16 UPX_DATA30 J17 UPX_DATA31 L17

UPX_RD_L V6

UPX_RDY_L M1 UPX_WIDTH0 U16 UPX_WIDTH1 T5

UPX_WR_L T4

VDD D6 VDD D10 VDD D15 VDD D19 VDD F4 VDD F21

Signal Name

VDD H10 VDD H15 VDD J11 VDD J14 VDD K4 VDD K8 VDD K17 VDD K21 VDD L9 VDD L11 VDD L14 VDD L16 VDD P9 VDD P11 VDD P14 VDD P16 VDD R4 VDD R8 VDD R17 VDD R21 VDD T11 VDD T14 VDD U10 VDD U15 VDD W4 VDD W21 VDD AA6 VDD AA10 VDD AA15 VDD AA19 VDD C12 VDD D11 VDD J20

VDD A10 VDD2 B4 VDD2 B8 VDD2 B12 VDD2 D2

Ball

Location

27 Datasheet

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004

IXF1104 4-Port Gigabit Ethernet Media Access Controller

Signal Name

VDD2 F8 VDD2 F12 VDD2 H2 VDD2 H6 VDD2 J12 VDD2 M2 VDD2 M6 VDD2 M9 VDD2 M12 VDD3 B13 VDD3 B17 VDD3 B21 VDD3 D23 VDD3 F13 VDD3 F17 VDD3 H19 VDD3 H23 VDD3 J13 VDD3 M13 VDD3 M16 VDD3 M19 VDD3 M23 VDD4 N13 VDD4 N16 VDD4 N19 VDD4 N23 VDD4 T13 VDD4 U19 VDD4 U23 VDD4 W13 VDD4 W17 VDD4 AA23 VDD4 AC13 VDD4 AC17 VDD4 AC21 VDD5 N2 VDD5 N6 VDD5 N9

Ball

Location

Signal Name

VDD5 N12 VDD5 T12 VDD5 U2 VDD5 U6 VDD5 W8 VDD5 W12 VDD5 AA2 VDD5 AC4 VDD5 AC8 VDD5 AC12

Ball

Location

Datasheet 28

Document Number: 278757 Revision Number: 007 Revision Date: March 25, 2004

IXF1104 4-Port Gi gab it Ethernet Media Access Controller

3.2.2 Balls Listed in Alphabetic Order by Ball Location

Table 2 shows the ball locations and signa l names arranged in order by ball location.

Table 2. Ball List in Alphanumeric Order by Ball Location

Ball

Location

Signal Name

A1 No Pad A2 No Ball A3 No Ball A4 GND A5 AVDD1P8_1 A6 TMOD0 A7 TEOP_0 A8 TERR_0

A9 DTPA_2 A10 VDD A11 TADR0 A12 TADR1 A13 RENB_0 A14 RDAT_1 A15 RDAT_0 A16 RERR_0 A17 RDAT_8 A18 RENB_1 A19 RFCLK A20 AVDD1P8_1 A21 GND A22 No Ball A23 No Ball A24 No Ball

B1 No Ball

B2 No Ball

B3 TDAT0

B4 VDD2

B5 TDAT6

B6 GND

B7 TENB_0

B8 VDD2

B9 TPRTY_2

Ball

Location

Signal Nam e

B10 GND B11 PTPA

B12 VDD2 B13 VDD3 B14 RDAT_2

B15 GND B16 RSOP_0 B17 VDD3 B18 RVAL_1

B19 GND

B20 RDAT_16 B21 VDD3 B22 RDAT_17 B23 No Ball B24 No Ball

C1 No Ball C2 TDAT1 C3 TDAT2 C4 TDAT4 C5 TDAT5 C6 TDAT7 C7 TSOP_0 C8 TDAT23

C9 TENB_2 C10 TSOP_2 C11 STPA

C12 VDD C13 RDAT_4

C14 RDAT_3 C15 RVAL_0

C16 REOP_0 C17 RDAT_9

C18 RSOP_1 C19 RENB_2

Ball

Location

Signal Name

C20 RDAT_18 C21 RDAT_19 C22 RDAT_20 C23 REOP_2 C24 No Ball

D1 TDAT3 D2 VDD2 D3 DTPA_0 D4 GND D5 TPRTY_0 D6 VDD D7 TFCLK D8 GND

D9 TMOD1 D10 VDD D11 VDD D12 GND D13 GND D14 RDAT_5 D15 VDD D16 RDAT_10 D17 GND D18 REOP_1 D19 VDD D20 RERR_2 D21 GND D22 RDAT_21 D23 VDD3 D24 NC

E1 TSX

E2 TENB_1

E3 TSOP_1

E4 TEOP_2

E5 TDAT16

29 Datasheet

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004

IXF1104 4-Port Gigabit Ethernet Media Access Controller

Ball

Location

Signal Name

E6 TDAT17 E7 TDAT18 E8 TDAT19

E9 TDAT20 E10 TDA T21 E11 TERR_2 E12 NC E13 RSX E14 RDAT_6 E15 RPRTY_0 E16 RDAT_11 E17 RDAT_13 E18 RDAT_14 E19 RVAL_2 E20 RPRTY_2 E21 RDAT_23 E22 RDAT_22 E23 RSOP_2 E24 RENB_3

F1 TDAT8 F2 GND F3 TEOP_1 F4 VDD F5 TDAT30 F6 GND F7 TDAT31 F8 VDD2

F9 TDAT22 F10 GND F11 NC F12 VDD2 F13 VDD3 F14 RDAT_7 F15 GND F16 RDAT_12 F17 VDD3 F18 RDAT_15 F19 GND

Ball

Location

F20 RPRTY_3 F21 VDD F22 RVAL_3 F23 GND F24 RDAT_31

G1 TDAT9 G2 T DAT10

G3 TPRTY_1 G4 T DAT24 G5 T DAT25 G6 T DAT26 G7 T DAT27 G8 T DAT28

G9 T DAT29 G10 UPX_DATA18 G11 UPX_DATA20 G12 UPX_DATA22 G13 RMOD1 G14 RMOD0 G15 NC G16 RPRTY_1

G17 RERR_1 G18 RDAT_24

G19 RDAT_25 G20 RDAT_26

G21 RDAT_27 G22 RDAT_28

G23 RDAT_29 G24 RDAT_30

H1 TDAT11

Signal Name

H2 VDD2

H3 TDAT15

H4 GND

H5 TEOP_3

H6 VDD2

H7 NC

H8 GND

H9 UPX_DATA13

Ball

Location

Signal Name

H10 VDD

H11 UPX_DATA19 H12 GND H13 GND H14 UPX_DATA24 H15 VDD H16 UPX_DATA29 H17 GND H18 NC H19 VDD3 H20 RERR_3 H21 GND H22 TMS H23 VDD3 H24 TDO

J1 TDAT12 J2 TDAT13 J3 TDAT14 J4 TENB_3 J5 TSOP_3 J6 TPRTY_3 J7 DTPA_3 J8 TERR_3

J9 UPX_DATA14 J10 GND J11 VDD J12 VDD2 J13 VDD3 J14 VDD J15 GND J16 UPX_DATA28 J17 UPX_DATA30 J18 RSOP_3 J19 REOP_3 J20 VDD J21 NC J22 TCLK J23 TRST_L

Datasheet 30

Document Number: 278757 Revision Number: 007 Revision Date: March 25, 2004

+ 197 hidden pages

Intel IXF1104 User Manual 2

Specifications and Main Features

Frequently Asked Questions

User Manual

1.0 Introduction

1.1 What You W ill Find in This Document

1.2 Related Documents

2.0 General Description

Figure 1. Block Diag ram

Figure 2. Internal Architecture

3.0 Ball Assignments and Ball List T abl es

3.1 Ball Assignments

3.2 Ball List Tables

3.2.1 Balls Listed in Alphabetic Order by Signal Name

Tab le 1. Ba ll Li st in Alp hanumeric Orde r by Signal Name

3.2.2 Balls Listed in Alphabetic Order by Ball Location

Table 2. Ball List in Alphanumeric Order by Ball Location