Intel IXD1110 User Manual
Intel® IXD1110 Demo Board
Development Kit Manual
June 2003
Document Number: 250807
Revision Number: 003
Revision Date: June 27, 2003
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future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
®
The Intel
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*Other names and brands may be claimed as the property of others.
Copyright © 2003, Intel Corporation
IXF1110 may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
2 Development Kit Manual
Document Number: 250807
Revision Number: 003
Revision Date: June 27, 2003
Contents
Contents
1.0 Introduction......................................................................................................................... 7
1.1 About This Kit.....................................................................................................................7
1.2 Additional Equipment Required..........................................................................................7
1.3 About This Demo Board .....................................................................................................8
1.3.1 Features .................................................................................................................8
1.3.2 Component Location and Description ..................................................................9
2.0 Quick Start........................................................................................................................11
2.1 Setup..................................................................................................................................11
3.0 Typical Test Setup............................................................................................................12
4.0 CPU Daughter Card ......................................................................................................... 13
4.1 CPU FPGA ........................................................................................................................14
4.2 IXF1110 Register Modifications on Startup .....................................................................14
5.0 IXF1110 Software.............................................................................................................15
5.1 PC Requirements...............................................................................................................15
5.2 Installing the IXF1110 Software .......................................................................................16
5.3 Changing the IP Address of the CPU Daughter Card (Optional)......................................16
6.0 Optional Configurations.................................................................................................... 18
6.1 Reset Jumper JP2...............................................................................................................18
6.1.1 Standard Operation .............................................................................................18
6.2 JTAG Test Signals.............................................................................................................18
7.0 LEDs................................................................................................................................. 19
8.0 Test Points ....................................................................................................................... 20
8.1 Reset Test Points ...............................................................................................................20
8.2 IXF1110 Input Clock Test Points......................................................................................20
8.3 GBIC Test Points...............................................................................................................20
8.4 Mictor Connectors.............................................................................................................21
8.5 Power and Ground Test Points..........................................................................................22
8.6 Unused Test Points............................................................................................................24
9.0 Board Schematics ............................................................................................................ 25
10.0 Bill of Materials ................................................................................................................. 38
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Contents
Figures
Tables
1Intel
2 Typical Test Setup ............................................................................................. 12
3Intel
4Intel
5Intel
6Intel
7Intel
8Intel
9Intel
10 Intel
11 Intel
12 Intel
13 Intel
14 Intel
15 Intel
16 Intel
1Intel
®
IXD1110 Demo Board (Top View)............................................................... 9
®
IXF1110 CPU Daughter Card.................................................................... 13
®
IXD1110 Demo Board Power (Revision A1) ............................................. 25
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IXD1110 Digital Power .............................................................................. 26
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IXD1110 Analog Power ............................................................................. 27
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IXD1110 Control........................................................................................ 28
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IXD1110 SerDes GBIC Ports 0-2 .............................................................. 29
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IXD1110 SerDes GBIC Ports 3-5 .............................................................. 30
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IXD1110 SerDes GBIC Ports 6-8 .............................................................. 31
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IXD1110 SerDes GBIC Port 9 ................................................................... 32
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IXD1110 SPI4-2 ........................................................................................ 33
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IXD1110 LEDs........................................................................................... 34
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IXD1110 CPU Interface Control ................................................................ 35
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IXD1110 CPU Connectors ........................................................................ 36
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IXD1110 CPU Logic Probe Connectors .................................................... 37
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IXD1110 Demo Board Principal Components ............................................. 9
2 Pinout for DB-9–to–RJ-45 Connector ................................................................. 14
3 JTAG Test Signals (JP1)..................................................................................... 18
4 IXF1110 LED Behavior ....................................................................................... 19
5Intel
6Intel
®
IXF1110 Reset Test Points ....................................................................... 20
®
IXF1110 Differential Input Clock Test Points............................................. 20
7 GBIC Test Points ................................................................................................ 20
8 Mictor Connector Test Points .............................................................................. 21
9 Power Test Points ............................................................................................... 22
10 Ground Test Points ............................................................................................. 23
11 Unused Test Points............................................................................................. 24
12 Intel
®
IXD1110 Demo Board Bill of Materials (Rev. A1)...................................... 38
4 Development Kit Manual
Document Number: 250807
Revision Number: 003
Revision Date: June 27, 2003
Revision History
Page # Description
11 Added second bullet under Section 2.0, “Quick Start”.
13 Modified Figure 3, “Intel
16 Added Section 5.3, “Changing the IP Address of the CPU Daughter Card (Optional)”.
18 Added note under Section 6.2, “JTAG Test Signals”.
18 Modified pin 8 description in Table 3, “JTAG Test Signals (JP1)”.
19 Modified Table 4, “IXF1110 LED Behavior”.
Page Number Description
14 Modified bulleted list under Section 4.2, “IXF1110 Register Modifications on Startup”.
Revision 003
Rev. Date: June 27, 2003
®
IXF1110 CPU Daughter Card”.
Revision Number: 002
Revision Date: July 31, 2002
Contents
Page Number Description
Initial release.
Revision Number: 001
Revision Date: May 31, 2002
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Document Number: 250807
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Contents
6 Development Kit Manual
Document Number: 250807
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Revision Date: June 27, 2003
1.0 Introduction
This document describes all the necessary requirements, settings, and procedures for evaluating the
®
Intel
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller (MAC) using the
®
Intel
IXD1110 demo board. For immediate operation, refer to Section 2.0, “Quick Start” on
page 11. For optional configurations, see Section 6.0, “Optional Configurations” on page 18.
IXD1110 Demo Board
The IXD1110 demo board kit includes a CPU daughter card that attaches to the underside of the
board. Through the CPU daughter card, the Intel
MAC Demonstration Software (included on the CD) provides access to all IXF1110 registers and
RMON statistics.
Additional sections include information about LEDs, test points, board schematics, and a bill of
materials.
Note: For comprehensive information in evaluating the IXF1110 using the IXD1110 demo board, use the
IXF1110 Demonstration Software Help File and the IXF1110 Datasheet (document number
250210) in conjunction with this document.
®
IXF1010/IXF1110 10-Port 100/1000 Ethernet
1.1 About This Kit
The IXD1110 demo board kit includes the following:
• IXD1110 demo board with CPU daughter card
• IXF1110 Demonstration Software CD (includes a software help file)
• SPI4-2 loopback connector
• IXD1110 Demo Board Development Kit Manual
1.2 Additional Equipment Required
The following additional equipment is required for board setup:
• Packet Generator with 1000BASE-SX capabilities
• 3.3 V DC power supply with 6A current capability
• 2.5 V DC power supply with 6A current capability
• 1.8 V DC power supply with 6A current capability
• One to ten fiber cables (for data transmission)
• Two CAT5-UTP cables (for IXF1110 software)
• DB-9–to–RJ-45 converter [optional] (for IXF1110 software)
• PC (for IXF1110 software) (see Section 5.1, “PC Requirements” on page 15)
• GBIC SFP modules [up to 10] (Agilent* HFBR-5710L)
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Document Number: 250807
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Revision Date: June 27, 2003
IXD1110 Demo Board
1.3 About The IXD1110 Demo Board
The IXD1110 demo board provides a working platform for the evaluation of the IXF1110 in
1000 Mbps fiber optic applications. All ten network ports provide a 1000BASE-SX connection
through the GBIC Small Form Factor Pluggable (SFP) modules (not included).
The IXD1110 demo board contains one IXF1110 device, one SPI4-2 interface connector, ten GBIC
SFP connectors, and one plug-in CPU daughter card. The SPI4-2 interface connector allows for
loopback connection.
Note: In loopback mode, the board cannot be tested or used with other devices or equipment.
Connection can be made to an alternate SPI4-2 device or to another IXD1010 or IXD1110 demo
board utilizing a SPI4-2 connector board. In these modes, the SPI4-2 interface can be tested for
lengths greater than that in loopback mode.
The attached CPU daughter card uses the IXF1110 CPU interface to access all registers and RMON
statistics through the supplied IXF1110 software.
1.3.1 Features
The following is a list of IXD1110 demo board features and evaluation capabilities:
• Ten IEEE 802.3 compliant 1000BASE-SX MAC ports
• SPI4-2 interface
— Capable of data transfers up to 12.8 Gbps
— Supports SPI4-2 loopback mode (default)
— Can be connected to another SPI4-2 device (optional)
For example, a SPI4-2 enabled daughter card (FPGAs, bridges, etc.)
• SerDes interface with GBIC SFP modules not included
• Motorola* MCP860 32-bit CPU
— Mounted on the daughter card, which is attached to the bottom side of the demo board
(see Figure 2)
• Access to all supported registers for full evaluation
• Access to all RMON statistics registers
• Broadcast, multicast, and unicast address filtering capability
• Independent port enable/disable
• Programmable option to filter packets with errors
• Compliance with IEEE 802.3x flow control standard
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1.3.2 Component Location and Description
Figure 1 illustrates the top view of the IXD1110 demo board.
Figure 1. Intel
®
IXD1110 Demo Board (Top View)
IXD1110 Demo Board
GBIC SFP
Connectors
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
GND 1.8 V IXF 2.5 V IXF 3.3 V 2.5 V
JP1
J
T
A
G
ResetS1JP2
GND
Mictor Connector
Probe D
®
Intel
IXF1110
EPROM
FPGA
Mictor Connector
Probe C
Mictor Connector
Probe A
Intel® IXF1110
LEDs
SMB Connectors
SPI4-2
Connector
Table 1 provides a list of the various principal components found on the IXD1110 demo board.
Table 1. Intel® IXD1110 Demo Board Principal Components
Component Description
IX F1110
10-port Gigabit MAC that supports IEEE 802.3 1000 Mbps applications. Refer to the
IXF1110 Datasheet for additional information.
The IXF1110 uses a serial interface consisting of three signals to provide LED data to
IXF1110 LEDs
an external driver. This interface provides the data for 30 separate direct drive LEDs
and allows three LEDs per MAC port. Refer to Section 7.0, “LEDs” on page 19.
JP1
JP2
This jumper provides access to the JTAG test signals. Refer to Section 6.2, “JTAG
Test Signals” on page 18.
This reset jumper is required for proper board operation. Refer to Section 6.1, “Reset
Jumper JP2” on page 18 for more information.
1. For evaluation of the signals provided by the Mictor connector, use the corresponding logic analyzer probe.
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Document Number: 250807
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Revision Date: June 27, 2003
IXD1110 Demo Board
Table 1. Intel® IXD1110 Demo Board Principal Components (Continued)
Component Description
S1 Reset Switch: This switch resets the entire board when pressed.
SPI4-2 Interface
Connector
Mictor Connectors A,
C, and D
GBIC Connectors These connectors allow for SFP modules (Agilent* HFBR-5710L).
FPGA
EPROM EPROM is used to program the FPGA.
1
1. For evaluation of the signals provided by the Mictor connector, use the corresponding logic analyzer probe.
Allows a loopback connection when the loopback module is installed. This connector
can also interface with alternate SPI4-2 connections.
Provide access to selected IXF1110 signals. Refer to Section 8.4, “Mictor Connectors”
on page 21 for more information.
Converts the IXF11110 asynchronous CPU signals into a synchronous format. Refer
to Section 4.1, “CPU FPGA” on page 14 for more information.
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Revision Date: June 27, 2003
2.0 Quick Start
The quick-start procedure allows for IXF1110 1000 Mbps SerDes data transfer evaluation in the
following interfaces:
• IXF1110 SPI4-2 loopback data transfer
2
• I
C signals
• CPU interface
2.1 Setup
The following quick-start procedure uses the IXIA* 1600T packet generator to evaluate the
IXD1110 demo board. All ports on the IXF1110 are set to a default setting of 1000 Mbps
full-duplex (see Figure 2, “Typical Test Setup” on page 12).
1. Set reset jumper JP2 to the HRESET position.
2. Jumper pins 6 and 8 of JP1.
3. Install optic modules on all ten ports.
4. Connect the IXF1110 optic modules to the external ports on the IXIA* 1600T LM1000SX
cards.
5. Verify that the CPU daughter card is installed on the bottom of the board.
6. Verify that the SPI4-2 loopback module is connected to the SPI4-2 connector.
IXD1110 Demo Board
7. Connect the 1.8 V DC power supply to BN1 (“1.8 V IXF”).
8. Connect the 2.5 V DC power supply to BN4 (“2.5 V IXF”) and BN5 (“2.5 V”).
9. Connect the 3.3 V DC power supply to BN6 (“3.3 V”).
10. Connect all power supply return lines to ground BN3 (“GND”).
11. With the board properly configured, proceed in the following order:
a. Apply +1.8 V DC power
b. Apply +2.5 V DC power
c. Apply+3.3 V, DC power
d. Press reset switch S1
12. Once the CPU Daughter Card has completed autoboot, the board is ready for evaluation of
standard packets (64 - 1518 bytes) at 1000 Mbps full-duplex on all ports.
13. To access registers and RMON statistics, install the IXF1110 software. Instructions are
provided in Section 5.2, “Installing the IXF1110 Software” on page 16. This allows the user to
change the default settings of the IXF1110 and configure the device for other modes of
operation.
14. Proceed with evaluation as desired.
Note: The IXF1110 software modifies some of the IXF1110 registers on power-up. For a complete list of
registers modified, please refer to Section 4.2, “IXF1110 Register Modifications on Startup” on
page 14.
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Revision Date: June 27, 2003
IXD1110 Demo Board
3.0 Typical Test Setup
Figure 2 shows a typical test setup for standard operation of the IXF1110 (see Section 2.0, “Quick
Start” on page 11 for step-by-step details). The IXD1110 demo board can be connected to an
IXIA* 1600T packet generator with LM1000SX cards for evaluation of the board. Each port can be
connected to the IXIA* box with fiber cables. For IXF1110 software use, connect CAT5-UTP
cables to the ports shown on the CPU daughter card. One of the cables connects to the COM port
on the IXIA* box by using a DB-9–to–RJ-45 connector. The other cable connects to the network
port on the IXIA* box. Refer to Figure 2 and Section 5.2, “Installing the IXF1110 Software” on
page 16 for proper installation.
Note: The IXF1110 evaluation software can be run from the IXIA or an added PC connected to the CPU
daughter card.
Figure 2. Typical Test Setup
Connect to
COM port
DB-9-to-RJ- 45
Connector
Connect To
Network Port
Advanced Multi-port Performance Tester
Fiber Connectors
IXIA* 1600T
Demo Software
Power
Supplies
Monitor
for IXIA
LM1000SX
Cards
Cables
Fiber
GBIC SFP
Modules
IXF1110
Intel® IXD1110
TCP/IP connection
UTP to Serial Connection
®
Intel
SPI4-2
Connector
Demo Board
CAT5 UTP
SPI4-2
Loop-back
CPU Daughter
Card
B1895
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Document Number: 250807
Revision Number: 003
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