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This document describes all the necessary requirements, settings, and procedures for evaluating the
®
Intel
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller (MAC) using the
®
Intel
IXD1110 demo board. For immediate operation, refer to Section 2.0, “Quick Start” on
page 11. For optional configurations, see Section 6.0, “Optional Configurations” on page 18.
IXD1110 Demo Board
The IXD1110 demo board kit includes a CPU daughter card that attaches to the underside of the
board. Through the CPU daughter card, the Intel
MAC Demonstration Software (included on the CD) provides access to all IXF1110 registers and
RMON statistics.
Additional sections include information about LEDs, test points, board schematics, and a bill of
materials.
Note:For comprehensive information in evaluating the IXF1110 using the IXD1110 demo board, use the
IXF1110 Demonstration Software Help File and the IXF1110 Datasheet (document number
250210) in conjunction with this document.
®
IXF1010/IXF1110 10-Port 100/1000 Ethernet
1.1About This Kit
The IXD1110 demo board kit includes the following:
• IXD1110 demo board with CPU daughter card
• IXF1110 Demonstration Software CD (includes a software help file)
• SPI4-2 loopback connector
• IXD1110 Demo Board Development Kit Manual
1.2Additional Equipment Required
The following additional equipment is required for board setup:
• Packet Generator with 1000BASE-SX capabilities
• 3.3 V DC power supply with 6A current capability
• 2.5 V DC power supply with 6A current capability
• 1.8 V DC power supply with 6A current capability
The IXD1110 demo board provides a working platform for the evaluation of the IXF1110 in
1000 Mbps fiber optic applications. All ten network ports provide a 1000BASE-SX connection
through the GBIC Small Form Factor Pluggable (SFP) modules (not included).
The IXD1110 demo board contains one IXF1110 device, one SPI4-2 interface connector, ten GBIC
SFP connectors, and one plug-in CPU daughter card. The SPI4-2 interface connector allows for
loopback connection.
Note:In loopback mode, the board cannot be tested or used with other devices or equipment.
Connection can be made to an alternate SPI4-2 device or to another IXD1010 or IXD1110 demo
board utilizing a SPI4-2 connector board. In these modes, the SPI4-2 interface can be tested for
lengths greater than that in loopback mode.
The attached CPU daughter card uses the IXF1110 CPU interface to access all registers and RMON
statistics through the supplied IXF1110 software.
1.3.1Features
The following is a list of IXD1110 demo board features and evaluation capabilities:
• Ten IEEE 802.3 compliant 1000BASE-SX MAC ports
• SPI4-2 interface
— Capable of data transfers up to 12.8 Gbps
— Supports SPI4-2 loopback mode (default)
— Can be connected to another SPI4-2 device (optional)
For example, a SPI4-2 enabled daughter card (FPGAs, bridges, etc.)
• SerDes interface with GBIC SFP modules not included
• Motorola* MCP860 32-bit CPU
— Mounted on the daughter card, which is attached to the bottom side of the demo board
(see Figure 2)
• Access to all supported registers for full evaluation
• Access to all RMON statistics registers
• Broadcast, multicast, and unicast address filtering capability
• Independent port enable/disable
• Programmable option to filter packets with errors
• Compliance with IEEE 802.3x flow control standard
8Development Kit Manual
Document Number: 250807
Revision Number: 003
Revision Date: June 27, 2003
1.3.2Component Location and Description
Figure 1 illustrates the top view of the IXD1110 demo board.
Figure 1. Intel
®
IXD1110 Demo Board (Top View)
IXD1110 Demo Board
GBIC SFP
Connectors
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
GND1.8 V IXF2.5 V IXF3.3 V2.5 V
JP1
J
T
A
G
ResetS1JP2
GND
Mictor Connector
Probe D
®
Intel
IXF1110
EPROM
FPGA
Mictor Connector
Probe C
Mictor Connector
Probe A
Intel® IXF1110
LEDs
SMB Connectors
SPI4-2
Connector
Table 1 provides a list of the various principal components found on the IXD1110 demo board.
Table 1. Intel® IXD1110 Demo Board Principal Components
ComponentDescription
IX F1110
10-port Gigabit MAC that supports IEEE 802.3 1000 Mbps applications. Refer to the
IXF1110 Datasheet for additional information.
The IXF1110 uses a serial interface consisting of three signals to provide LED data to
IXF1110 LEDs
an external driver. This interface provides the data for 30 separate direct drive LEDs
and allows three LEDs per MAC port. Refer to Section 7.0, “LEDs” on page 19.
JP1
JP2
This jumper provides access to the JTAG test signals. Refer to Section 6.2, “JTAG
Test Signals” on page 18.
This reset jumper is required for proper board operation. Refer to Section 6.1, “Reset
Jumper JP2” on page 18 for more information.
1. For evaluation of the signals provided by the Mictor connector, use the corresponding logic analyzer probe.
Table 1. Intel® IXD1110 Demo Board Principal Components (Continued)
ComponentDescription
S1Reset Switch: This switch resets the entire board when pressed.
SPI4-2 Interface
Connector
Mictor Connectors A,
C, and D
GBIC ConnectorsThese connectors allow for SFP modules (Agilent* HFBR-5710L).
FPGA
EPROMEPROM is used to program the FPGA.
1
1. For evaluation of the signals provided by the Mictor connector, use the corresponding logic analyzer probe.
Allows a loopback connection when the loopback module is installed. This connector
can also interface with alternate SPI4-2 connections.
Provide access to selected IXF1110 signals. Refer to Section 8.4, “Mictor Connectors”
on page 21 for more information.
Converts the IXF11110 asynchronous CPU signals into a synchronous format. Refer
toSection 4.1, “CPU FPGA” on page 14 for more information.
10Development Kit Manual
Document Number: 250807
Revision Number: 003
Revision Date: June 27, 2003
2.0Quick Start
The quick-start procedure allows for IXF1110 1000 Mbps SerDes data transfer evaluation in the
following interfaces:
• IXF1110 SPI4-2 loopback data transfer
2
• I
C signals
• CPU interface
2.1Setup
The following quick-start procedure uses the IXIA* 1600T packet generator to evaluate the
IXD1110 demo board. All ports on the IXF1110 are set to a default setting of 1000 Mbps
full-duplex (see Figure 2, “Typical Test Setup” on page 12).
1. Set reset jumper JP2 to the HRESET position.
2. Jumper pins 6 and 8 of JP1.
3. Install optic modules on all ten ports.
4. Connect the IXF1110 optic modules to the external ports on the IXIA* 1600T LM1000SX
cards.
5. Verify that the CPU daughter card is installed on the bottom of the board.
6. Verify that the SPI4-2 loopback module is connected to the SPI4-2 connector.
IXD1110 Demo Board
7. Connect the 1.8 V DC power supply to BN1 (“1.8 V IXF”).
8. Connect the 2.5 V DC power supply to BN4 (“2.5 V IXF”) and BN5 (“2.5 V”).
9. Connect the 3.3 V DC power supply to BN6 (“3.3 V”).
10. Connect all power supply return lines to ground BN3 (“GND”).
11. With the board properly configured, proceed in the following order:
a. Apply +1.8 V DC power
b. Apply +2.5 V DC power
c. Apply+3.3 V, DC power
d. Press reset switch S1
12. Once the CPU Daughter Card has completed autoboot, the board is ready for evaluation of
standard packets (64 - 1518 bytes) at 1000 Mbps full-duplex on all ports.
13. To access registers and RMON statistics, install the IXF1110 software. Instructions are
provided in Section 5.2, “Installing the IXF1110 Software” on page 16. This allows the user to
change the default settings of the IXF1110 and configure the device for other modes of
operation.
14. Proceed with evaluation as desired.
Note:The IXF1110 software modifies some of the IXF1110 registers on power-up. For a complete list of
registers modified, please refer to Section 4.2, “IXF1110 Register Modifications on Startup” on
Figure 2 shows a typical test setup for standard operation of the IXF1110 (see Section 2.0, “Quick
Start” on page 11 for step-by-step details). The IXD1110 demo board can be connected to an
IXIA* 1600T packet generator with LM1000SX cards for evaluation of the board. Each port can be
connected to the IXIA* box with fiber cables. For IXF1110 software use, connect CAT5-UTP
cables to the ports shown on the CPU daughter card. One of the cables connects to the COM port
on the IXIA* box by using a DB-9–to–RJ-45 connector. The other cable connects to the network
port on the IXIA* box. Refer to Figure 2 and Section 5.2, “Installing the IXF1110 Software” on
page 16 for proper installation.
Note:The IXF1110 evaluation software can be run from the IXIA or an added PC connected to the CPU
daughter card.
Figure 2. Typical Test Setup
Connect to
COM port
DB-9-to-RJ- 45
Connector
Connect To
Network Port
Advanced Multi-port Performance Tester
Fiber Connectors
IXIA* 1600T
Demo Software
Power
Supplies
Monitor
for IXIA
LM1000SX
Cards
Cables
Fiber
GBIC SFP
Modules
IXF1110
Intel® IXD1110
TCP/IP connection
UTP to Serial Connection
®
Intel
SPI4-2
Connector
Demo Board
CAT5 UTP
SPI4-2
Loop-back
CPU Daughter
Card
B1895
12Development Kit Manual
Document Number: 250807
Revision Number: 003
Revision Date: June 27, 2003
4.0CPU Daughter Card
The IXD1110 demo board uses the Embedded Planet* RPX Classic LF (CLLF_BW31), a singleboard computer that uses the Motorola* MPC860 CPU. This card attaches to the underside of the
board and is used to interface with the IXF1110 CPU interface. Figure 3provides a top-level view
of the CPU daughter card.
Figure 3. Intel
®
IXF1110 CPU Daughter Card
IXD1110 Demo Board
CPU Daughter
Card
IP Address located on
the side of the connector
RJ-45 #1 10Mbps
Ethernet Connection
RJ-45 #2 Serial
Connection
Not Used
The IXF1110 software requires the proper connections to the daughter card as follows:
Note:For full operation of the IXF1110 software, RJ-45 #1 and #2 (see Figure 3) must be connected to a
PC.
• RJ-45 #1 (10 Mbps Ethernet): Requires the following connection (this connection gives access
to the GUI):
— CAT5-UTP cable (connected to the CPU daughter card)
— Network port on a PC (connected to the CAT5-UTP cable), installed with IXF1110
software
• RJ-45 #2 (Serial): Requires a connection that gives access to the HyperTerminal interface of
the IXF1010 software (refer to Section 5.2, “Installing the IXF1110 Software” on page 16 for
complete setup information).
• Table 2 provides the DB-9–to–RJ-45 connector pinout for connection to a PC COM port.
Only three pins are used for the DB-9–to–RJ-45 connector.
For more information on the HyperTerminal and GUI interfaces, please refer to the IXF1110
Software Help File.
4.1CPU FPGA
The IXD1110 demo board has a Field Programmable Gate Array (FPGA) that allows the
Motorola* CPU, which requires a synchronous interface, to interoperate with the asynchronous
IXF1110 CPU interface.
For additional information regarding the IXF1110 CPU interface, refer to the IXF1110 Datasheet.
4.2IXF1110 Register Modifications on Startup
The Motorola* CPU automatically modifies some of the IXF1110 registers on startup to put the
board in a 1000 Mbps evaluation mode. The following registers are modified from default settings
on startup:
• TX FIFO Highwater Mark Ports 0-9 are set to 0x00000BB8
• RX FIFO Errored Frame Drop Enable is set to 0x000003FF
• MAC Transfer Threshold Ports 0-9 are set to 0x000003E8
• Diverse Config Ports 0-9 are set to 0x0000112D
• LED Control is set to 0x00000003
For additional information on these registers, please refer to the IXF1110 Datasheet.
14Development Kit Manual
Document Number: 250807
Revision Number: 003
Revision Date: June 27, 2003
5.0IXF1110 Software
The IXF1110 software allows access to the following register blocks through the Graphical User
Interface (GUI) or the Serial Monitor (HyperTerminal) interface:
• MAC Control
• MAC RX Statistics
• MAC TX Statistics
• Global Status and Configuration
• RX Block
• TX Block
• SPI4-2 Block
• SerDes Block
• GBIC Block
For additional information on all of the registers, please refer to the IXF1110 Datasheet or On-Line
Help.
IXD1110 Demo Board
Note:For help on using IXF1110 software, refer to the On-Line Help included in the software provided
with the IXD1110 demo board.
5.1PC Requirements
The following is a list of the minimum PC requirements for installation of the IXF1110 software:
®
• Intel
• 128 MB RAM
• 16 MB Video Card
• Serial port
• Microsoft* Windows 98, 2000 operating system
Note:Microsoft* Windows 95, ME, NT, and XP have not been tested.
For proper installation of the IXF1110 software, follow these steps:
1. Verify that the CAT5-UTP cable is connected between the PC and the IXF1110 CPU daughter
card. This allows access to the GUI interface. Refer to Section 4.0, “CPU Daughter Card” on
page 13 for detailed installation instructions.
2. (Optional) The following connection is required to access the HyperTerminal interface:
— CAT5-UTP cable (connected to a CPU daughter card)
— DB-9–to–RJ-45 connector (connected to a CAT5-UTP cable)
— DB-9–to–RJ-45 connector (connected to a COM port on a PC installed with IXF1110
software)
For more information, refer to Section 4.0, “CPU Daughter Card” on page 13 for detailed
instructions.
3. Insert the CD into the PC.
4. If your system supports Autorun, follow the on-screen instructions.
5. If your system does not support Autorun, select Run... from the Start menu. The Run dialog
opens.
6. Select setup.exe from the CD in the Open: window (click Browse... to find setup.exe if not
already in the window).
7. Click OK.
8. Follow the on-screen instructions.
9. Locate the IXD1110 demo board IP address that is located on the CPU daughter card. The IP
address is required each time the GUI is opened.
10. Start the IXF1110 software GUI by double clicking the desktop icon.
Note:The IXF1110 software includes online documentation that describes how to run the GUI and
HyperTerminal interfaces. Refer to the quick-start section of the IXF1110 Demonstration Software
Help File for additional instructions on use of these interfaces.
5.3Changing the IP Address of the CPU Daughter Card
(Optional)
The CPU daughter card comes with a default IP address, which is listed on a sticker attached to the
daughter card. The GUI uses this IP address to locate the IXD1110 demo board. The IP address
may need to be changed depending on the PC or network to which the board is attached. Use the
following procedure to permanently change the IP Address of the CPU daughter card:
1. Ensure the IXD1110 demo board has been set up correctly (see Section 2.0, “Quick Start” on
page 11).
2. Open the HyperTerminal on the PC to which the CPU daughter card serial port is attached, and
configure the relevant COM port with the following settings:
• Speed: 9600 Baud
• Databits: 8
16Development Kit Manual
Document Number: 250807
Revision Number: 003
Revision Date: June 27, 2003
IXD1110 Demo Board
• Parity: None
• Stops bits: 1
• Flow Control: None
3. Press the reset button switch SW1. The following message appears on the HyperTerminal:
MPC8xx PlanetCore Boot Loader v2.00
Copyright 2001 Embedded Planet. All rights reserved.
DRAM available size = 16 MB
wvCV
DRAM OK
Autoboot in 2 seconds.
ESC to abort, SPACE or ENTER to go.
4. Press the ESC key to stop the Autoboot. The following message appears on the
HyperTerminal:
Autoboot aborted.
>
5. Type the following at the > prompt:
> set ip 10.254.21.34 (Changes the IP address to the value entered)
> store (Permanently changes the IP address)
> reset (Restarts the IXD1110 demo board)
Once the Autoboot is complete, the GUI can access the IXD1110 demo board using the newly
programmed IP address.
The Reset Jumper JP2 is required for standard operation of the IXD1110 demo board. Use the
HRESET position for standard operation.
The POR position is not recommended for standard operation of the IXD1110 demo board. This
configuration only affects the CPU operation, and does not affect IXF1110 operation. The only
difference between HRESET and POR is that POR also resets the CPU PLLs and state machines.
This difference is seen when reset is asserted by pressing switch S1. For more information on the
POR position of JP2, refer to Table 12 (MPC860 Reset Responses) of the Motorola* MPC860 CPU
Datasheet.
6.2JTAG Test Signa ls
The boundary scan test port for the IXF1110 is accessed using JP1 for board-level testing. Table 3
describes JTAG test signals.
Note:For normal IXD1110 demo board operation, connect TRST_N pin 8 on JP1 to ground by
jumpering pins 6 and 8 of JP1.
Table 3. JTAG Test Signals (JP1)
Jumper
JP1
Pin
Number
2,4,6GND–Connect to system ground
Symbol
1TDIAC18Test Data Input
3TDOY24Test Data Output
5TMST16Test Mode Select
7TCLKAA29Test Clock
8TRSTN18Test Reset (jumper pins 6 and 8)
IXF1110 Ball
Designator
Description
18Development Kit Manual
Document Number: 250807
Revision Number: 003
Revision Date: June 27, 2003
7.0LEDs
Table 4 describes the behavior of the Link LED - Amber, Link LED - Green, and Activity LED for
the IXF1110.
Table 4. IXF1110 LED Behavior
TypeStatusDescription
IXD1110 Demo Board
Off
Amber On
RxLED
TxLED
NOTES:
1. The LED behavior table assumes the port is enabled in the Port Enable Register (Addr: 0x500) and the
LEDs are enabled in the LED Control Register (Addr: 0x509). If a port is not enabled, all the LEDs for that
port will be off. If the LEDs are not enabled, all of the LEDs will be off.
2. For a detailed description of the LED interface and register information, refer to the IXF1110 Datasheet.
Amber Blinking
Green On
Green Blinking
Off
Green Blinking
Synchronization has occurred but no packets are being
received and the Link LED Enable Register (Addr:
0x502) is not set.
RX Synchronization has not occurred or no optical
signal exists.
Port has remote fault and the LED Fault Disable
Register (Addr: 0x50B) is not set. Based on remote
fault bit setting received in Rx_Config word.
RX Synchronization has occurred and the Link LED
Enable Register (Addr: 0x502) bit is set.
RX Synchronization has occurred and port is receiving
data.
Port is not transmitting data or the Link LED Enable
Register (Addr: 0x502)” is not set.
Port is transmitting data and the Link LED Enable
Register (Addr: 0x502)” bit is set.
Two test points allow evaluation of the IXF1110 reset signals. TP21 allows IXF1110 Sys_Res
signal monitoring. DTP3 allows board reset signal monitoring. The board Sys_Res
monitored on both test points if it is asserted by Switch S1 or the CPU. The resetis seen at TP21 if
an IXF1110 reset is issued by the software interface.
can be
Table 5. Intel
®
IXF1110 Reset Test Points
Test PointSymbol
TP21Sys_Res
DTP3Sys_Res
NOTE: DTP = Differential Test Point, TP = Test Point
IXF1110 Ball
Designator
Y4System reset for IXF1110
–Board reset
8.2IXF1110 Input Clock Test Points
The IXF1110 requires input clocks of 50 and 125 MHz. There are two test points that allow the
user to monitor those signals (see Tab le 6).
Table 6. Intel® IXF1110 Differential Input Clock Test Points
Test PointSymbol
DTP1CLK125AA5125 MHz input clock for IXF1110
DTP2CLK50C2150 MHz input clock for IXF1110
NOTE: DTP = Differential Test Point
IXF1110 Ball
Designator
8.3GBIC Test Points
Description
Description
Table 7 lists GBIC test points that allow evaluation of the I2C clock, which is connected to all of
the GBIC modules, and the I
2
C Data pins for each of the ten ports. For more information on the I2C
interface, refer to the IXF1110 Datasheet.
Table 7. GBIC Test Points (Sheet 1 of 2)
Test PointSymbol
DTP6I
DTP7I
DTP8I
DTP9I
DTP10I
NOTE: DTP = Differential Test Point
2
C_CLKL19I2C_CLK for IXF1110
2
C_DATA_0G22I2C_DATA_0 for IXF1110
2
C_DATA_1G23I2C_DATA_1 for IXF1110
2
C_DATA_2J24I2C_DATA_2 for IXF1110
2
C_DATA_3F22I2C_DATA_3 for IXF1110
IXF1110 Ball
Designator
Description
20Development Kit Manual
Document Number: 250807
Revision Number: 003
Revision Date: June 27, 2003
Table 7. GBIC Test Points (Sheet 2 of 2)
IXD1110 Demo Board
Test PointSymbol
DTP11I2C_DATA_4E23I2C_DATA_4 for IXF1110
2
DTP12I
DTP13I
DTP14I
DTP15I
DTP16I
NOTE: DTP = Differential Test Point
C_DATA_5H24I2C_DATA_5 for IXF1110
2
C_DATA_6G20I2C_DATA_6 for IXF1110
2
C_DATA_7E22I2C_DATA_7 for IXF1110
2
C_DATA_8G24I2C_DATA_8 for IXF1110
2
C_DATA_9F24I2C_DATA_9 for IXF1110
IXF1110 Ball
Designator
8.4Mictor Connectors
Table 8 provides a detailed list of the Mictor Connector test points that are available using Mictor
Connectors and that are designed for easy use with the Tektronix* P6434 Mass Termination Probe.
Using these connectors with a Tektronix* logic analyzer allows the probing of the signals in
Table 8.
Table 8. Mictor Connector Test Points (Sheet 1 of 2)
Probe ACPU Data
Bus
A0(0)uPx_Data0B3C0(0)TA–D0(0)–
A0(1)uPx_Data1A4C0(1)Start_XFER–D0(1)–
A0(2)uPx_Data2B9C0(2)RD/~WR–D0(2)–
A0(3)uPx_Data3A7C0(3)Gen_PCsN–D0(3)–
A0(4)uPx_Data4C12C0(4)–D0(4)–
A0(5)uPx_Data5E11C0(5)CsN–D0(5)–
A06)uPx_Data6C13C0(6)Bus_request–D0(6)–
A0(7)uPx_Data7A8C0(7)Bus_Busy–D0(7)–
A1(0)uPx_Data8A10C1(0)Bus_Grant–D1(0)–
A1(1)uPx_Data9A9C1(1)–D1(1)–
A1(2)uPx_Data10E12C1(2)uPx_RdyNC22D1(2)–
A1(3)uPx_Data11A11C1(3)–D1(3)–
A1(4)uPx_Data12G12C1(4)uPx_CsNF20D1(4)–
A1(5)uPx_Data13E10C1(5)uPx_WrNA18D1(5)–
A1(6)uPx_Data14F11C1(6)uPx_RdNH14D1(6)POR–
A1(7)uPx_Data15D7C1(7)–D1(7)HRESET–
A2(0)uPx_Data16D14C2(0)uPx_Add0J1D2(0)–
A2(1)uPx_Data17C14C2(1)uPx_Add1G4D2(1)–
A2(2)uPx_Data18F14C2(2)uPx_Add2F3D2(2)–
1. For evaluation of the signals provided by the Mictor connector, use the corresponding logic analyzer probe.
The unused test points are for internal testing only and are not designed for evaluation of the
IXF1110 device. Table 11 provides a list of the unused test points.
Table 11. Unused Test Points
Test PointsDescription
J29
J30
J31
J32
J33
J34
TP1
J29, J30, 31, J32, J33, J34, and TP1 are not
designated for IXF1110 evaluation
24Development Kit Manual
Document Number: 250807
Revision Number: 003
Revision Date: June 27, 2003
9.0Board Schematics
D
C
B
A
Figure 4. Intel® IXD1110 Demo Board Power (Revision A1)