Intel Itanium 9050, Itanium 9020, Itanium 9015, Itanium 9010, Itanium 9152 User Manual
...
Dual-Core Intel® Itanium® Processor
9000 and 9100 Series
Dual-Core Intel® Itanium® Processor 1.6 GHz with 24 MB L3 Cache 9050
Dual-Core Intel® Itanium® Processor 1.6 GHz with 18 MB L3 Cache 9040
Dual-Core Intel® Itanium® Processor 1.6 GHz with 8 MB L3 Cache 9030
Dual-Core Intel® Itanium® Processor 1.42 GHz with 12 MB L3 Cache 9020
Dual-Core Intel® Itanium® Processor 1.4 GHz with 12 MB L3 Cache 9015
Intel® Itanium® Processor 1.6 GHz with 6 MB L3 Cache 9010
Dual-Core Intel® Itanium® Processor 1.66/1.6 GHz with 24 MB L3 Cache 9152
Dual-Core Intel® Itanium® Processor 1.66 GHz with 24 MB L3 Cache 9150M
Dual-Core Intel® Itanium® Processor 1.6 GHz with 24 MB L3 Cache 9150N
Dual-Core Intel® Itanium® Processor 1.66 GHz with 18 MB L3 Cache 9140M
Dual-Core Intel® Itanium® Processor 1.6 GHz with 18 MB L3 Cache 9140N
Dual-Core Intel® Itanium® Processor 1.42 GHz with 12 MB L3 Cache 9120N
Dual-Core Intel® Itanium® Processor 1.66 GHz with 8 MB L3 Cache 9130M
Intel® Itanium® Processor 1.6 GHz with 12 MB L3 Cache 9110N
Datasheet
October 2007
Document Number: 314054-002
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Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them
The Dual-Core Intel® Itanium® 9000 and 9100 series processor may contain design defects or errors known as errata which may
cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained
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Intel, Itanium, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United
States and other countries.
Copyright © 2002-2007, Intel Corporation
*Other names and brands may be claimed as the property of others.
I2C is a two-wire communication bus /protocol developed by Phillips. SMBus is a subset of the I2C bus/protocol developed by Intel.
Implementation of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Phillips
Electronics, N.V. and North American Phillips Corporation.
2 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet
Contents
1 Introduction............................................................................................................... 11
1.1 Overview ......................................................................................................... 11
1.2 Processor Abstraction Layer................................................................................ 11
1.3 Mixing Processors of Different Frequencies and Cache Sizes .................................... 12
1.4 Terminology ..................................................................................................... 12
1.5 State of Data.................................................................................................... 12
1.6 Reference Documents ........................................................................................ 13
2 Electrical Specifications ............................................................................................... 15
2.1 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series System Bus.................. 15
2.1.1 System Bus Power Pins ........................................................................ 15
2.1.2 System Bus No Connect ....................................................................... 15
2.2 System Bus Signals ........................................................................................... 15
2.2.1 Signal Groups ..................................................................................... 15
2.2.2 Signal Descriptions .............................................................................. 17
2.3 Package Specifications ....................................................................................... 18
2.4 Signal Specifications.......................................................................................... 18
2.4.1 Maximum Ratings................................................................................ 22
2.5 System Bus Signal Quality Specifications and Measurement Guidelines ..................... 23
2.5.1 Overshoot/Undershoot Magnitude.......................................................... 23
2.5.2 Overshoot/Undershoot Pulse Duration .................................................... 24
2.5.3 Activity Factor..................................................................................... 24
2.5.4 Reading Overshoot/Undershoot Specification Tables................................. 24
2.5.5 Determining if a System Meets the Overshoot/Undershoot
Specifications...................................................................................... 25
2.5.6 Wired-OR Signals ................................................................................ 25
2.6 Voltage Regulator Connector Signals.................................................................... 27
2.7 System Bus Clock and Processor Clocking............................................................. 31
2.8 Recommended Connections for Unused Pins.......................................................... 33
3 Pinout Specifications................................................................................................... 35
4 Mechanical Specifications............................................................................................. 65
4.1 Processor Package Dimensions............................................................................ 65
4.1.1 Voltage Regulator (MVR) to Processor Package Interface........................... 71
4.2 Package Marking ............................................................................................... 72
4.2.1 Processor Top-Side Marking ..................................................................72
4.2.2 Processor Bottom-Side Marking ............................................................. 73
5 Thermal Specifications ................................................................................................ 75
5.1 Thermal Features ..............................................................................................75
5.1.1 Thermal Alert...................................................................................... 75
5.1.2 Enhanced Thermal Management ............................................................ 76
5.1.3 Power Trip.......................................................................................... 76
5.1.4 Thermal Trip....................................................................................... 76
5.2 Case Temperature ............................................................................................. 76
6 System Management Feature Specifications ................................................................... 79
6.1 System Management Bus ................................................................................... 79
6.1.1 System Management Bus Interface........................................................ 79
6.1.2 System Management Interface Signals ................................................... 79
6.1.3 SMBus Device Addressing ..................................................................... 81
6.2 Processor Information ROM ................................................................................ 82
6.3 Scratch EEPROM ............................................................................................... 85
Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet 3
6.4 Processor Information ROM and Scratch EEPROM Supported SMBus
Transactions .....................................................................................................85
6.5 Thermal Sensing Device .....................................................................................86
6.6 Thermal Sensing Device Supported SMBus Transactions..........................................87
6.7 Thermal Sensing Device Registers........................................................................88
6.7.1 Thermal Reference Registers .................................................................88
6.7.2 Thermal Limit Registers ........................................................................89
6.7.3 Status Register....................................................................................89
6.7.4 Configuration Register ..........................................................................89
6.7.5 Conversion Rate Register ......................................................................90
A Signals Reference .......................................................................................................91
A.1 Alphabetical Signals Reference ............................................................................91
A.1.1 A[49:3]# (I/O).......................................................................................91
A.1.2 A20M# (I) .............................................................................................91
A.1.3 ADS# (I/O)............................................................................................91
A.1.4 AP[1:0]# (I/O).......................................................................................91
A.1.5 ASZ[1:0]# (I/O).....................................................................................91
A.1.6 ATTR[3:0]# (I/O) ...................................................................................92
A.1.7 BCLKp/BCLKn (I) ....................................................................................92
A.1.8 BE[7:0]# (I/O).......................................................................................92
A.1.9 BERR# (I/O) ..........................................................................................93
A.1.10 BINIT# (I/O)..........................................................................................94
A.1.11 BNR# (I/O)............................................................................................94
A.1.12 BPM[5:0]# (I/O) ....................................................................................94
A.1.13 BPRI# (I) ..............................................................................................94
A.1.14 BR[0]# (I/O) and BR[3:1]# (I).................................................................94
A.1.15 BREQ[3:0]# (I/O)...................................................................................95
A.1.16 CCL# (I/O) ............................................................................................96
A.1.17 CPUPRES# (O) .......................................................................................96
A.1.18 D[127:0]# (I/O).....................................................................................96
A.1.19 D/C# (I/O) ............................................................................................96
A.1.20 DBSY# (I/O)..........................................................................................96
A.1.21 DBSY_C1# (O).......................................................................................96
A.1.22 DBSY_C2# (O).......................................................................................96
A.1.23 DEFER# (I)............................................................................................96
A.1.24 DEN# (I/O)............................................................................................97
A.1.25 DEP[15:0]# (I/O) ...................................................................................97
A.1.26 DHIT# (I)..............................................................................................97
A.1.27 DPS# (I/O)............................................................................................98
A.1.28 DRDY# (I/O)..........................................................................................98
A.1.29 DRDY_C1# (O).......................................................................................98
A.1.30 DRDY_C2# (O).......................................................................................98
A.1.31 DSZ[1:0]# (I/O) ....................................................................................98
A.1.32 EXF[4:0]# (I/O) .....................................................................................98
A.1.33 FCL# (I/O) ............................................................................................99
A.1.34 FERR# (O).............................................................................................99
A.1.35 GSEQ# (I).............................................................................................99
A.1.36 HIT# (I/O) and HITM# (I/O)....................................................................99
A.1.37 ID[9:0]# (I) ..........................................................................................99
A.1.38 IDS# (I)................................................................................................99
A.1.39 IGNNE# (I)............................................................................................99
A.1.40 INIT# (I)...............................................................................................99
A.1.41 INT (I) ................................................................................................100
A.1.42 IP[1:0]# (I).........................................................................................100
A.1.43 LEN[2:0]# (I/O) ...................................................................................100
A.1.44 LINT[1:0] (I) .......................................................................................100
4 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet
A.1.45 LOCK# (I/O)........................................................................................ 100
A.1.46 NMI (I) ............................................................................................... 101
A.1.47 OWN# (I/O) ........................................................................................ 101
A.1.48 PMI# (I) ............................................................................................. 101
A.1.49 PWRGOOD (I)...................................................................................... 101
A.1.50 REQ[5:0]# (I/O) .................................................................................. 101
A.1.51 RESET# (I) ......................................................................................... 102
A.1.52 RP# (I/O) ........................................................................................... 102
A.1.53 RS[2:0]# (I) ....................................................................................... 103
A.1.54 RSP# (I) ............................................................................................. 103
A.1.55 SBSY# (I/O)........................................................................................ 103
A.1.56 SBSY_C1# (O)..................................................................................... 103
A.1.57 SBSY_C2# (O)..................................................................................... 103
A.1.58 SPLCK# (I/O) ...................................................................................... 103
A.1.59 STBn[7:0]# and STBp[7:0]# (I/O)......................................................... 103
A.1.60 TCK (I) ............................................................................................... 104
A.1.61 TDI (I)................................................................................................ 104
A.1.62 TDO (O).............................................................................................. 104
A.1.63 THRMTRIP# (O) ................................................................................... 104
A.1.64 THRMALERT# (O)................................................................................. 104
A.1.65 TMS (I)............................................................................................... 104
A.1.66 TND# (I/O) ......................................................................................... 104
A.1.67 TRDY# (I) ........................................................................................... 105
A.1.68 TRST# (I) ........................................................................................... 105
A.1.69 WSNP# (I/O)....................................................................................... 105
A.2 Signal Summaries ........................................................................................... 105
Figures
2-1 Generic Clock Waveform .................................................................................... 21
2-2 SMSC Clock Waveform....................................................................................... 22
2-3 System Bus Signal Waveform Exhibiting Overshoot/Undershoot............................... 23
2-4 Processors Power Tab Physical Layout .................................................................. 28
2-5 System Bus Reset and Configuration Timings for Cold Reset.................................... 31
2-6 System Bus Reset and Configuration Timings for Warm Reset ................................. 32
3-1 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Pinout.......................... 35
4-1 Processor Package............................................................................................. 66
4-2 Package Height and Pin Dimensions..................................................................... 67
4-3 Processor Package Mechanical Interface Dimensions .............................................. 69
4-4 Processor Package Top-Side Components Height Dimensions .................................. 70
4-5 Processor Package Bottom-Side Components Height Dimensions ............................. 70
4-6 Processor to MVR Interface Loads........................................................................ 71
4-7 Processor Top-Side Marking on IHS ..................................................................... 73
4-8 Processor Bottom-Side Marking Placement on Interposer........................................ 74
5-1 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Thermal
Features .......................................................................................................... 75
5-2 Itanium® Processor Package Thermocouple Location.............................................. 77
6-1 Logical Schematic of SMBus Circuitry ................................................................... 80
Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet 5
Tables
2-1 Itanium® Processor System Bus Signal Groups ......................................................16
2-2 Nominal Resistance Values for Tuner1, Tuner2, and Tuner3.....................................17
2-3 Processor Package Specifications .........................................................................18
2-4 AGTL+ Signals DC Specifications..........................................................................19
2-5 Power Good Signal DC Specifications....................................................................19
2-6 System Bus Clock Differential HSTL DC Specifications.............................................19
2-7 TAP Connection DC Specifications ........................................................................19
2-8 SMBus DC Specifications.....................................................................................20
2-9 LVTTL Signal DC Specifications ............................................................................20
2-10 System Bus Clock Differential HSTL AC Specifications .............................................20
2-11 SMBus AC Specifications.....................................................................................21
2-12 Dual-Core Intel® Itanium® Processor Absolute Maximum Ratings.............................22
2-13 Source Synchronous AGTL+ Signal Group and Wired-OR Signal Group
Absolute Overshoot/Undershoot Tolerance ............................................................25
2-14 Source Synchronous AGTL+ Signal Group Time-Dependent Overshoot/
Undershoot Tolerance for 400-MHz System Bus .....................................................26
2-15 Wired-OR Signal Group (BINIT#, HIT#, HITM#, BNR#, TND#, BERR#)
Overshoot/Undershoot Tolerance for 400-MHz System Bus......................................26
2-16 Source Synchronous AGTL+ Signal Group Time-Dependent Overshoot/
Undershoot Tolerance for 533-MHz System Bus .....................................................26
2-17 Wired-OR Signal Group (BINIT#, HIT#, HITM#, BNR#, TND#, BERR#)
Overshoot/Undershoot Tolerance for 533-MHz System Bus......................................27
2-18 VR Connector Signals .........................................................................................27
2-19 Power Connector Pinouts ....................................................................................28
2-20 Processors Core Voltage Identification Code (VCORE and VCACHE)...........................30
2-21 Connection for Unused Pins.................................................................................33
2-22 TUNER1/TUNER3 Translation Table.......................................................................34
3-1 Pin/Signal Information Sorted by Pin Name ...........................................................36
3-2 Pin/Signal Information Sorted by Pin Location........................................................50
4-1 Processor Package Dimensions ............................................................................67
4-2 Processor Package Mechanical Interface Dimensions...............................................68
4-3 Processor Package Load Limits at Power Tab .........................................................71
5-1 Case Temperature Specification...........................................................................77
6-1 System Management Interface Signal Descriptions.................................................79
6-2 Thermal Sensing Device SMBus Addressing on the Dual-Core Intel
Itanium® Processor 9000 and 9100 series.............................................................81
6-3 EEPROM SMBus Addressing on the Dual-Core Intel® Itanium® Processor
9000 and 9100 Series ........................................................................................82
6-4 Processor Information ROM Format ......................................................................82
6-5 Current Address Read SMBus Packet ....................................................................85
6-6 Random Address Read SMBus Packet ...................................................................86
6-7 Byte Write SMBus Packet....................................................................................86
6-8 Write Byte SMBus Packet....................................................................................87
6-9 Read Byte SMBus Packet ....................................................................................87
6-10 Send Byte SMBus Packet ....................................................................................87
6-11 Receive Byte SMBus Packet.................................................................................87
6-12 ARA SMBus Packet.............................................................................................87
6-13 Command Byte Bit Assignment............................................................................88
6-14 Thermal Sensing Device Status Register ...............................................................89
6-15 Thermal Sensing Device Configuration Register......................................................89
6-16 Thermal Sensing Device Conversion Rate Register..................................................90
®
6 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet
A-1 Address Space Size ........................................................................................... 92
A-2 Effective Memory Type Signal Encoding................................................................ 92
A-3 Special Transaction Encoding on Byte Enables ....................................................... 93
A-5 BR0# (I/O), BR1#, BR2#, BR3# Signals for 2P Rotating Interconnect ...................... 95
A-4 BR0# (I/O), BR1#, BR2#, BR3# Signals for 4P Rotating Interconnect ...................... 95
A-6 BR[3:0]# Signals and Agent IDs ......................................................................... 95
A-7 DID[9:0]# Encoding .......................................................................................... 97
A-8 Extended Function Signals .................................................................................. 98
A-9 Length of Data Transfers .................................................................................. 100
A-10 Transaction Types Defined by REQa#/REQb# Signals........................................... 102
A-11 STBp[7:0]# and STBn[7:0]# Associations .......................................................... 104
A-12 Output Signals ................................................................................................ 105
A-13 Input Signals .................................................................................................. 105
A-14 Input/Output Signals (Single Driver) .................................................................. 106
A-15 Input/Output Signals (Multiple Driver)................................................................ 107
Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet 7
Revision History
Document
Number
314054 -002
314054 -001 • Initial release of the document. July 2006
Revision
Number
Description Date
• Updated with 9100 series product information; updated brand name from
“Itanium 2” to “Itanium”.
October 2007
8 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet
Dual-Core Intel® Itanium® Processor 9000 and
9100 Series
Dual-Core Intel® Itanium® Processor 1.6 GHz with 24 MB L3 Cache 9050
Dual-Core Intel® Itanium® Processor 1.6 GHz with 18 MB L3 Cache 9040
Dual-Core Intel® Itanium® Processor 1.6 GHz with 8 MB L3 Cache 9030
Dual-Core Intel® Itanium® Processor 1.42 GHz with 12 MB L3 Cache 9020
Dual-Core Intel® Itanium® Processor 1.4 GHz with 12 MB L3 Cache 9015
Intel® Itanium® Processor 1.6 GHz with 6 MB L3 Cache 9010
Dual-Core Intel® Itanium® Processor 1.66 GHz with 24 MB L3 Cache 9150M
Dual-Core Intel® Itanium® Processor 1.6 GHz with 24 MB L3 Cache 9150N
Dual-Core Intel® Itanium® Processor 1.66 GHz with 18 MB L3 Cache 9140M
Dual-Core Intel® Itanium® Processor 1.6 GHz with 18 MB L3 Cache 9140N
Dual-Core Intel® Itanium® Processor 1.42 GHz with 12 MB L3 Cache 9120N
Dual-Core Intel® Itanium® Processor 1.66 GHz with 8 MB L3 Cache 9130M
Intel® Itanium® Processor 1.6 GHz with 12 MB L3 Cache 9110N
Product Features
Dual Core
— Two complete 64-bit processing cores on one
processor.
EPIC (Explicitly Parallel Instruction Computing)
Technology for current and future requirements of
high-end enterprise and technical workloads
— Provide a variety of advanced
implementations of parallelism, predication,
and speculation, resulting in superior
Instruction-Level Parallelism (ILP).
Hyper-Threading Technology
— Two times the number of OS threads per core
provided by earlier single-thread
implementations.
Wide, parallel hardware based on Intel® Itanium
architecture for high performance:
— Integrated on-die L3 cache of up to 24MB;
cache hints for L1, L2, and L3 caches for
reduced memory latency.
— 128 general and 128 floating-point registers
supporting register rotation.
— Register stack engine for effective
management of processor resources.
— Support for predication and speculation.
Extensive RAS features for business-critical
applications:
— Full SMBus compatibility.
— Enhanced machine check architecture with
extensive ECC and parity protection.
— Enhanced thermal management.
— Built-in processor information ROM (PIROM).
— Built-in programmable EEPROM.
— Socket Level Lockstep
— Core Level Lockstep
a. This feature is applicable to only the 9100 series processors
®
Intel® Virtualization Technology for virtualization for
data-intensive applications.
— Reduces virtualization complexity.
— Improves virtualization performance.
— Increases operating system compatibility.
Intel® Cache Safe Technology ensures mainframecaliber availability.
— Minimize L3 cache errors.
Outstanding Energy Efficiency.
— 20 percent less power than previous Intel
Itanium processor.
— 2.5 times higher performance per watt.
High-bandwidth system bus for multiprocessor
scalability:
— Up to 8.53GB/s bandwidth.
— 128-bit wide data bus.
— 50-bits of physical memory addressing and
64-bits of virtual addressing.
— Up to four physical processors on the same
system bus at 400-MHz or 533-MHz data bus
frequency.
— Expandable to systems with multiple system
buses.
Features to support flexible platform environments:
— IA-32 Execution Layer supports IA-32
application binaries.
— Bi-endian support.
— Processor abstraction layer eliminates
processor dependencies.
667-MHz, 1.66-GHz, 3-load bus
— This feature enables increased bandwidth for
Enterprise and HPC.
Demand Based Switching (DBS)
— Provides additional power management
capability.
a
a
Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet 9
The Dual-Core Intel® Itanium® processor 9000 and 9100 series delivers new levels of flexibility,
reliability, performance, and cost-effective scalability for your most data-intensive business and
technical applications. With double the performance of previous Intel Itanium processors, the DualCore Intel Itanium processor 9000 and 9100 series provides more reasons than ever to migrate your
business-critical applications off RISC and mainframe systems and onto cost-effective Intel
architecture servers. The Dual-Core Intel Itanium processor 9000 and 9100 series provides close to
triple the amount of L3 cache (24 megabytes), Hyper-Threading Technology for increased
performance, Intel® Virtualization Technology for improved virtualization, Intel® Cache Safe
Technology for increased availability, and 20 percent lower power consumption.
Dual-Core Itanium®-based systems are available from leading OEMs worldwide and run popular 64bit operating systems such as Microsoft* Windows Server* 2003; Linux* from SuSE, Red Hat, Red
Flag, and other distributions; HP NonStop*; OpenVMS*; and HP-UX*. More than 7,000 applications
are available for Itanium-based systems, from vendors such as Microsoft, BEA, IBM, Ansys, Gaussian,
Symantec/VERITAS, Oracle, SAP, and SAS. And with industry support growing and future Intel
Itanium processor family advances already in development, your Itanium-based server investment
will continue to deliver performance advances and savings for your most demanding applications.
§
10 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet
Introduction
1 Introduction
1.1 Overview
The Dual-Core Intel Itanium processor 9000 and 9100 series employs Explicitly Parallel
Instruction Computing (EPIC) design concepts for a tighter coupling between hardware
and software. In this design style, the interface between hardware and software is
engineered to enable the software to exploit all available compile-time information and
efficiently deliver this information to the hardware. It addresses several fundamental
performance bottlenecks in modern computers, such as memory latency, memory
address disambiguation, and control flow dependencies. The EPIC constructs provide
powerful architectural semantics and enable the software to make global optimizations
across a large scheduling scope, thereby exposing available Instruction Level
Parallelism (ILP) to the hardware. The hardware takes advantage of this enhanced ILP,
and provides abundant execution resources. Additionally, it focuses on dynamic runtime optimizations to enable the compiled code schedule to flow at high throughput.
This strategy increases the synergy between hardware and software, and leads to
greater overall performance.
The Dual-Core Intel Itanium processor 9000 and 9100 series provides a 6-wide and 8stage deep pipeline, running at up to 1.6 GHz. This provides a combination of abundant
resources to exploit ILP as well as increased frequency for minimizing the latency of
each instruction. The resources consist of six integer units, six multimedia units, two
load and two store units, three branch units, two extended-precision floating-point
units, and one additional single-precision floating-point unit per core. The hardware
employs dynamic prefetch, branch prediction, a register scoreboard, and non-blocking
caches to optimize for compile-time non-determinism. Three levels of on-die cache
minimize overall memory latency. This includes up to a 24 MB L3 cache, accessed at
core speed, providing up to 8.53 GB/sec. of data bandwidth. The system bus is
designed to support up to four physical processors (on a single system bus), and can
be used as an effective building block for very large systems. The balanced core and
memory subsystem provide high performance for a wide range of applications ranging
from commercial workloads to high-performance technical computing.
The Dual-Core Intel Itanium processor 9000 and 9100 series supports a range of
computing needs and configurations from a two-way to large SMP servers. This
document provides the electrical, mechanical and thermal specifications for the DualCore Intel Itanium processor 9000 and 9100 series for use while employing systems
with the processors.
1.2 Processor Abstraction Layer
The Dual-Core Intel Itanium processor 9000 and 9100 series requires implementationspecific Processor Abstraction Layer (PAL) firmware. PAL firmware supports processor
initialization, error recovery, and other functionality. It provides a consistent interface
to system firmware and operating systems across processor hardware
implementations. The Intel® Itanium® Architecture Software Developer’s Manual,
Volume 2: System Architecture, describes PAL. Platforms must provide access to the
firmware address space and PAL at reset to allow the processors to initialize.
Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet 11
Introduction
The System Abstraction Layer (SAL) firmware contains platform-specific firmware to
initialize the platform, boot to an operating system, and provide runtime functionality.
Further information about SAL is available in the Intel®Itanium®Processor Family
System Abstraction Layer Specification.
1.3 Mixing Processors of Different Frequencies and
Cache Sizes
All Dual-Core Intel Itanium processor 9000 and 9100 series on the same system bus
are required to have the same cache size (24 MB, 18 MB, 12 MB, 8 MB or 6 MB) and
identical core frequency. Mixing components of different core frequencies and cache
sizes is not supported and has not been validated by Intel. Operating system support
for multiprocessing with mixed components should also be considered.
While Intel has done nothing to specifically prevent processors within a multiprocessor
environment from operating at differing frequencies and differing cache sizes, there
may be uncharacterized errata that exist in such configurations. Customers would be
fully responsible for validation of system configurations with mixed components other
than the supported configurations described above.
1.4 Terminology
In this document, “the processor” refers to the “Dual-Core Intel Itanium processor
9000 and 9100 series” processor, unless otherwise indicated.
A ‘#’ symbol after a signal name refers to an active low signal. This means that a signal
is in the active state (based on the name of the signal) when driven to a low level. For
example, when RESET# is low, a processor reset has been requested. When NMI is
high, a non-maskable interrupt has occurred. In the case of lines where the name does
not imply an active state but describes part of a binary sequence (such as address or
data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’
refers to a hex ‘A’, and D [3:0] # = ‘LHLH’ also refers to a hex ‘A’ (H = High logic level,
L = Low logic level).
The term “system bus” refers to the interface between the processor, system core logic,
and other bus agents. The system bus is a multiprocessing interface to processors,
memory, and I/O.
A signal name has all capitalized letters, for example, VCTERM.
A symbol referring to a voltage level, current level, or a time value carries a plain
subscript, for example, V
1.5 State of Data
The data contained in this document is subject to change. It is the best information
that Intel is able to provide at the publication date of this document.
, or a capitalized, abbreviated subscript, for example, TCO.
core
12 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet
Introduction
1.6 Reference Documents
The reader of this specification should also be familiar with material and concepts
presented in the following documents:
Intel®Itanium®2 Processor Specification Update
Intel® Itanium® Architecture Software Developer’s Manual, Volume 1:
Application Architecture
Intel® Itanium® Architecture Software Developer’s Manual, Volume 2: System
Architecture
Intel® Itanium® Architecture Software Developer’s Manual,
Volume 3: Instruction Set Reference
®
Itanium®2 Processor Reference Manual for Software Development and
Intel
Optimization
Intel®Itanium®Processor Family System Abstraction Layer Specification
ITP700 Debug Port Design Guide
System Management Bus Specification
Note: Contact your Intel representative or check http://developer.intel.com for the latest
revision of the reference documents.
§
Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet 13
Introduction
14 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet
Electrical Specifications
2 Electrical Specifications
This chapter describes the electrical specifications of the Dual-Core Intel Itanium
Processor 9000 and 9100 series.
2.1 Dual-Core Intel® Itanium® Processor 9000 and
9100 Series System Bus
Most Dual-Core Intel Itanium processor 9000 and 9100 series signals use the Itanium
processor’s assisted gunning transceiver logic (AGTL+) signaling technology. The
termination voltage, V
reference voltage. The buffers that drive most of the system bus signals on the
processor are actively driven to V
times and reduce noise. These signals should still be considered open-drain and require
termination to V
terminated to V
termination, in which case, the termination is provided by external resistors connected
to V
CTERM
.
CTERM
CTERM
, is generated on the baseboard and is the system bus high
CTERM
during a low-to-high transition to improve rise
CTERM
which provides the high level. The processor system bus is
at each end of the bus. There is also support of off-die
AGTL+ inputs use differential receivers which require a reference signal (V
used by the receivers to determine if a signal is a logical 0 or a logical 1. The processor
generates V
source.
on-die, thereby eliminating the need for an off-chip reference voltage
REF
2.1.1 System Bus Power Pins
VCTERM (1.2 V) input pins on the processor provide power to the driver buffers and ondie termination. The GND pins, in addition to the GND input at the power tab connector,
provide ground to the processor. Power for the processor core is supplied through the
power tab connector by V
to provide power to the system management bus (SMBus). The V
pins must remain electrically separated from each other.
Core
, V
Cache, Vfixed.
2.1.2 System Bus No Connect
All pins designated as “N/C” or “No Connect” must remain unconnected.
2.2 System Bus Signals
2.2.1 Signal Groups
Table 2-1 shows processor system bus signals that have been combined into groups by
buffer type and whether they are inputs, outputs, or bidirectional, with respect to the
processor.
). V
REF
The 3.3 V pin is included on the processor
, 3.3 V, and GND
CTERM
REF
is
Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet 15
..
Table 2-1. Itanium® Processor System Bus Signal Groups
Group Name Signals
AGTL+ Input Signals BPRI#, BR[3:1]#, DEFER#, GSEQ#, ID[9:0]#, IDS#, RESET#1, RS[2:0]#,
AGTL+ I/O Signals A[49:3]#, ADS#, AP[1:0]#, BERR#, BINIT#, BNR#, BPM[5:0]#1, BR0#,
AGTL+ Output Signals FERR#, THRMTRIP#, DBSY[1:0]#, DRDY[1:0]#, SBSY[1:0]#
Special AGTL+ Asynchronous
Interrupt Input Signals
Power Good Signal
HSTL Clock Signals BCLKn, BCLKp
TAP Input Signals
TAP Output Signals
System Management Signals13.3 V, SMA[2:0], SMSC, SMSD, SMWP, THRMALERT#
Power Signals GND, VCTERM
LVTTL Power Pod Signals
Other TERMA, TERMB, TUNER1, TUNER2, TUNER3, VCCMON, VSSMON
Notes:
1. Signals will not be terminated on-die even when on-die termination (ODT) is enabled. See the Intel®Itanium
2 Processor Hardware Developer’s Manual for further details.
1
1
1
1
RSP#, TRDY#
D[127:0]#, DBSY#, DEP[15:0]#, DRDY#, HIT#, HITM#, LOCK#,
REQ[5:0]#, RP#, SBSY#, STBN[7:0]#, STBP[7:0]#, TND#
A20M#, IGNNE#, INIT#, LINT[1,0], PMI#
PWRGOOD
TCK, TDI, TMS, TRST#
TDO
CPUPRES#, OUTEN, PPODGD#
Electrical Specifications
®
All system bus outputs should be treated as open drain signals and require a high-level
source provided by the V
AGTL+ inputs have differential input buffers which use V
output signals require termination to V
CTERM
supply.
as a reference level. AGTL+
. In this document, “AGTL+ Input Signals”
CTERM
REF
refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving.
Similarly, “AGTL+ Output Signals” refers to the AGTL+ output group as well as the
AGTL+ I/O group when driving.
The Test Access Port (TAP) connection input signals use a non-differential receiver with
levels that are similar to AGTL+. No reference voltage is required for these signals. The
TAP Connection Output signals are AGTL+ output signals.
The processor system bus requires termination on both ends of the bus. The processor
system bus supports both on-die and off-die termination controlled by two pins, TERMA
and TERMB. Please see the TERMA and TERMB pin description in Section 2.2.2.
The HSTL clock signals are the differential clock inputs for the processor. The SMBus
signals and LVTTL power pod signals are driven using the 3.3 V CMOS logic levels listed
in Table 2-8 and Table 2-9, respectively.
16 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet
Electrical Specifications
2.2.2 Signal Descriptions
Appendix A, “Signals Reference”, contains functional descriptions of all system bus
signals and LVTTL power pod signals. Further descriptions of the system management
signals are contained in Chapter 6. The signals listed under the “Power” and “Other”
group are described here:
V
CTERM
GND System ground.
N/C No connection can be made to these pins.
TERMA, TERMB The processor uses two pins to control the on-die termination
TUNER1, TUNER2,
TUNER3 The TUNER1 Pin can either be left as a no-connect or left
VCCMON, VSSMON These pins allows remote measurement of on-die Vcore voltage.
System bus termination voltage.
function: TERMA and TERMB. Both of these termination pins
must be pulled to VCTERM in order to terminate the system bus
using the on-die termination resistors. Both of these termination
pins must be pulled to GND in order to use off-die termination.
connected to VCTERM via resistor for the majority of platforms
supporting the Dual-Core Intel Itanium processor 9000 and
9100 series. The TUNER2 resistor is used to control the
termination resistance for the system bus I/O buffers. A lower
resistance will cause a lower on-die termination resistance. Ondie termination mode will only be selected if the TERMA and
TERMB pins are terminated as indicated above. The TUNER3 pin
will not be required for the majority of platforms supporting the
Dual-Core Intel Itanium processor 9000 and 9100 series. The
TUNER3 pin is used only in the case where A[21:17]# are driven
to all zeros or all ones during the configuration cycles at reset.
When all zeros or all ones are observed by the processor the
presence of the TUNER3 and TUNER1 pins is used to determine
system bus frequency. See Table 2-22 for the various TUNER pin
combinations and resulting system bus frequency and slew rate
combination.
No connections that constitute a current load can be made to
these pins.
Table 2-2. Nominal Resistance Values for Tuner1, Tuner2, and Tuner3
5-Load Platform (Ohms)
Tuner1: NC
Tuner2: 150
Tuner3: NC
Notes:
1. Depending on system configuration, the processor may or may not require a resistor on the
Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet 17
400 MHz
1
1
TUNER pin. OEMs may leave the pin unconnected or connect it to VCTERM through a 150
or 100 ohm resistor. If A[21:17]:# are driven to all 0’s or all 1’s at reset, see Table 2-22
for proper use of the TUNER Pins.
3-Load Platform (Ohms)
Tuner1: NC
Tuner2: 150
Tuner3: NC
400 MHz
1
1
3-Load Platform (Ohms)
Tuner1: NC
Tuner2: 150
Tuner3: NC
533 MHz
1
1
2.3 Package Specifications
Table 2-3 through Table 2-9 list the DC voltage, current, and power specifications for
the processor. The voltage and current specifications are defined at the processor pins.
Operational specifications listed in Table 2-3 through Table 2-9 are only valid while
meeting specifications for case temperature, clock frequency, and input voltages.
Table 2-3. Processor Package Specifications
Electrical Specifications
Symbol Parameter
V
core, PSVCC
V
cache, PSVcache
V
fixed, PSVfixed
V
CTERM
R
TERM
V
TAP
I
core,PS
I
cache,PS
I
fixed,PS
I
CTERM
PS
TT
PWR
max
PWR
TPE
PWR
TDP
Notes:
1. The range for Vcore is 1.0875 V to 1.25 V.
2. Vcache typical is 1.025 V.
3. The processor system bus is terminated at each end of the system bus. The processor supports both on-die
and off-die termination which is selected by the TERMA and TERMB pins. Termination tolerance is ±15% for
on-die termination measured at VOL and ±1% for off-die termination.
4. This is measured for On-Die Termination with a 45-ohm pull up resistor.
5. Max power is peak electrical power that must be provided for brief periods by the VR.
6. Represents the TDP level that should be used for system thermal design. Sustained power for all real-world
applications will remain at or below this power level.
from the Voltage
Regulator
from the Voltage
Regulator
from the Voltage
Regulator
Termination Voltage All 1.2-1.5% 1.2 1.2+1.5% V
Recommended Termination
Resistance
Test Access Port Voltage
)
(VCC
TAP
Core Current Required from
Power Supply
Cache Current Required from
Power Supply
Fixed Current Required from
Power Supply
Termination Voltage Current All 7.2 A
Power Supply Slew Rate for
the Termination Voltage at the
Processor Pins
Max Power All 177 W
Thermal Power Envelope All 130 W
Thermal Design Power – dual
core
Thermal Design Power –
single core
Core
Frequency
All VID-17 mV VID VID+17 mV V
All VID-17 mV VID VID+17 mV V
All 1.25-20 mV 1.25 1.25+20 mV V
All 45-15% 45 45+15% Ohm
All 1.2-1.5% 1.2 1.5 V
All 2.8 89 121 A
All 2.0 17 18 A
All 0.7 9.2 11 A
All 0.05 A/ns
All 104 W
1.6 GHz 75 W
Minimum Typ Maximum Unit Notes
1
2
3
4
5
6
2.4 Signal Specifications
This section describes the DC specifications of the system bus signals. The processor
signal’s DC specifications are defined at the processor pins. Table 2-4 through Table 2-9
describe the DC specifications for the AGTL+, PWRGOOD, HSTL clock, TAP port, system
management, and LVTTL signals. Please refer to the ITP700 Debug Port Design Guide
for the TAP connection signals’ DC specifications at the debug port.
18 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet
Electrical Specifications
Table 2-4. AGTL+ Signals DC Specifications
Symbol Parameter
V
IL
V
IH
V
OL
V
OH
I
OL
I
OL
I
L
C
AGTL+
Notes:
1. The typical transition point between VIL and VIH assuming 125 mV V
V
REF_low
and V
2. Parameter measured into a 22.5 ohm resistor to 1.2 V. Minimum VOL and IOL are guaranteed by design/
characterization.
3. Calculated using off-die termination through two 45 ohm ±1% resistors in parallel.
4. Calculated using on-die termination to a 45 ±15% resistor measured at VOL.
5. At 1.2 V ±1.5%. V
6. Total of I/O buffer with ESD structure and processor parasitics if applicable. Capacitance values guaranteed
by design for all AGTL+ buffers.
Input Low Voltage All 0.625 V
Input High Voltage All 0.875 V
Output Low Voltage All 0.3 0.4 V
Output High Voltage All V
Output Low Current @ 0.3 V All 34 mA
Output Low Current @ 0.3 V All 17 mA
Leakage Current All ±100 µA
AGTL+ Pad Capacitance All 2 pF
levels are V
levels are V
REF_low
±100 mV, respectively, for a system bus agent using on-board termination. V
REF
±125 mV, respectively, for a system bus agent using on-die termination.
REF
, minimum Vpin V
CTERM
Core
Frequency
, maximum.
CTERM
Minimum Typ Maximum Unit Notes
1
1
2
,
CTERM
minimum
V
CTERM
REF
V
,
CTERM
maximum
uncertainty for ODT. V
V
REF_high
3
4
5
6
and
REF_high
Table 2-5. Power Good Signal DC Specifications
Symbol Parameter Minimum Maximum Unit Notes
V
IL
V
IH
Input Low Voltage 0.440 V
Input High Voltage 0.875 V
Table 2-6. System Bus Clock Differential HSTL DC Specifications
Symbol Parameter Minimum Maximum Unit Notes
V
IH
V
IL
V
X
C
CLK
Input High Voltage 0.78 1.3 V
Input Low Voltage –0.3 0.5 V
Input Crossover Voltage 0.55 0.85 V
Input (Pad) Capacitance 1.75 pF
Table 2-7. TAP Connection DC Specifications
Symbol Parameter Minimum Maximum Unit Notes
V
IL
V
IH
V
OL
V
OH
I
OL
I
IC
Notes:
1. There is a 100 mV hysteresis on TCK.
2. VIH, MAX = 1.5 V + 5%, VOH, MAX = 1.2 V +5%.
3. There is no internal pull-up. An external pull-up is always assumed. Max voltage tolerated at TDO is 1.5 V.
4. Per input pin.
Input Low Voltage –0.3 0.5 V
Input High Voltage 1.1 1.57 V
Output Low Voltage 0.3 V
Output High Voltage 1.2 V
Output Low Current 20 mA
Input Current 690 uA
1
1, 2
2, 3
4
Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet 19
Table 2-8. SMBus DC Specifications
Symbol Parameter Minimum Typ Maximum Unit Notes
3.3V VCC for the System Management
Components
V
V
V
I
I
I
I
I
IL
IH
OL
3.3V
OL
OL2
LI
LO
Input Low Voltage –0.3 0.3*3.3 V V
Input High Voltage 2.31 3.47 V Max =
Output Low Voltage 0.4 V
3.3V Supply Current 5.0 30.0 mA
Output Low Current 3 mA
Output Low Current 6 mA
Input Leakage Current 10 µA
Output Leakage Current 10 µA
Notes:
1. The value specified for IOLapplies to all signals except for THRMALERT#.
2. The value specified for I
applies only to THRMALERT#, which is an open drain signal.
OL2
Table 2-9. LVTTL Signal DC Specifications
Symbol Parameter Minimum Maximum Unit Notes
V
IL
V
IH
V
OL
V
OH
Input Low Voltage 0.8 V
Input High Voltage 2.0 3.63 V
Output Low Voltage 0.4 V
Output High Voltage 2.4 V
Electrical Specifications
3.14 3.3 3.47 V 3.3 V ±5
3.3 +5%
Min +
0.7*3.3V
1
2
Table 2-10 through Table 2-11 list the AC specifications for the processor’s clock and
SMBus (timing diagrams begin with Figure 2-1). The processor uses a differential HSTL
clocking scheme with a frequency of 200, 266, or 333 MHz. The SMBus is a subset of
the I2C* interface which supports operation of up to 100 kHz.
Table 2-10.System Bus Clock Differential HSTL AC Specifications (Sheet 1 of 2)
System
Symbol Parameter
T
BCLKp Period 200 5.0 ns Figure 2-1
period
T
skew
f
BCLK
T
jitter
T
high
T
low
T
period
T
skew
f
BCLK
T
jitter
T
high
T
low
System Clock Skew 200 100 ps
BCLKp Frequency 200 200 200 MHz Figure 2-1
BCLKp Input Jitter 200 100 ps Figure 2-1
BCLKp High Time 200 2.25 2.5 2.75 ns Figure 2-1
BCLKp Low Time 200 2.25 2.5 2.75 ns Figure 2-1
BCLKp Period 266 3.75 ns Figure 2-1
System Clock Skew 266 60 ps
BCLKp Frequency 266 266 266 MHz Figure 2-1
BCLKp Input Jitter 266 50 ps Figure 2-1
BCLKp High Time 266 1.69 1.88 2.06 ns Figure 2-1
BCLKp Low Time 266 1.69 1.88 2.06 ns Figure 2-1
Bus
Clock
(MHz)
Minimum Typ Maximum Unit Figure Notes
1
2
3
4
4
5
2
3
4
4
20 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet
Electrical Specifications
Table 2-10.System Bus Clock Differential HSTL AC Specifications (Sheet 2 of 2)
System
Symbol Parameter
T
rise
T
fall
V
PP
Notes:
1. The system clock skew is ±100 ps.
2. Measured on cross-point of rising edge of BCLKp and falling edge of BCLKn. Long-term jitter is defined as peak-to-peak variation
measured by accumulating a large number of clock cycles and recording peak-to-peak jitter.
3. Cycle-to-cycle jitter is defined as peak-to-peak variation measured over 10,000 cycles peak-to-peak jitter.
4. Measured on cross point of rising edge of BCLKp and falling edge of BCLKn.
5. The system clock skew is ±60 ps.
6. V
PPmin
7. The measurement is taken at 40-60% of the signal and extrapolated to 20-80%.
BCLKp Rise Time
BCLKp Fall Time
Minimum Input Swing All 600 mV Figure 2-1
is defined as the minimum input differential voltage which will cause no increase in the clock receiver timing.
7
7
Bus
Clock
(MHz)
All 333 500 667 ps Figure 2-1 20–80%
All 333 500 667 ps Figure 2-1 20–80%
Minimum Typ Maximum Unit Figure Notes
6
Table 2-11. SMBus AC Specifications
Symbol Parameter Minimum Maximum Unit Notes
f
SMSC
T
SMSC
t
high
t
low
t
rise
t
fall
t
VALID
t
SU
t
HLD
t
FREE
Notes:
1. Please refer to Figure 2-2 for the Standard Microsystems Corporation (SMSC)* clock waveform.
2. Bus Free Time is the minimum time allowed between request cycles.
SMSC Clock Frequency 100 kHz
SMSC Clock Period 10 µs
SMSC Clock High Time 4.0 µs
SMSC Clock Low Time 4.7 µs
SMSC Clock Rise Time 1.0 µs
SMSC Clock Fall Time 0.3 µs
SMBus Output Valid Delay 1.0 µs
SMBus Input Setup Time 250 ns
SMBus Input Hold Time 0 ns
Bus Free Time 4.7 µs
1
1
1
1
2
Figure 2-1. Generic Clock Waveform
T
high
T
rise
V
Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet 21
80%
pp
20%
T
Rise Time
=
rise
T
Fall Time
=
fall
T
High Time
=
high
T
Low Time
=
low
T
period
period
T
jitter
V
pp
T
low
T
fall
BCLKN
BCLKP
=T
Period
=
Long Term Peak-to-Peak Jitter
=
Peak-to-Peak Swing
=
T
jitter
000615
Figure 2-2. SMSC Clock Waveform
T
rise
75% V
T
T
rise
fall
cc
cc
Rise Time
=
Fall Time
=
SMSC
25% V
2.4.1 Maximum Ratings
Table 2-12 contains the processor stress ratings. Functional operation at the absolute
maximum and minimum is neither implied nor guaranteed. The processor should not
receive a clock while subjected to these conditions. Functional operating conditions are
given in the DC tables. Extended exposure to the maximum ratings may affect device
reliability. Furthermore, although the processor contains protective circuitry to resist
damage from static electric discharge, one should always take precautions to avoid
static voltages or electric fields.
T
T
T
high
T
fall
high
low
High Time
=
Low Time
=
90% V
Electrical Specifications
V (3.3V)
cc
T
low
cc
000618
Table 2-12. Dual-Core Intel® Itanium® Processor Absolute Maximum Ratings
Symbol Parameter Minimum Maximum Unit Notes
T
storage
T
shipping
V
core
V
cache
V
fixed
3.3V Any 3.3 V Supply Voltage with Respect to
V
in, SMBus
V
in, AGTL+
V
CTERM
V
in,TAP
Notes:
1. Storage temperature is temperature in which the processor can be stored for up to one year.
2. Shipping temperature is temperature in which the processor can be shipped for up to 24 hours.
3. Parameters are from third-party vendor specifications.
4. Maximum instantaneous voltage at receiver buffer input.
5. Specification includes V
respect to GND.
Processor Storage Temperature –10 45 °C
Processor Shipping Temperature –45 75 °C
Any V
Any V
Any V
GND
SMBus Buffer DC Input Voltage with
Respect to GND
AGTL+ Buffer DC Input Voltage with
Respect to GND
Any V
TAP Buffer DC Input Voltage with Respect
to GND.
Voltage with Respect to GND -0.3 1.55 V
core
Voltage with Respect to GND -0.3 1.55 V
cache
Voltage with Respect to GND -0.3 1.55 V
fixed
–0.3 5.5 V
–0.1 6.0 V
–0.45 1.65 V
Voltage with Respect to GND -0.45 1.65 V
CTERM
-0.45 1.65 V
in,AGTL+
and V
in,AGTL+ ASYNCHRONOUS
(AGTL+ asynchronous buffer DC input voltage with
1
2
3
3
4, 5
4
22 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet
Electrical Specifications
2.5 System Bus Signal Quality Specifications and
Measurement Guidelines
Overshoot (or undershoot) is the absolute value of the maximum voltage above the
nominal V
undershoot specifications limit transitions beyond V
edge rates. The processor can be permanently damaged by repeated overshoot or
undershoot events on any input, output, or I/O buffer if the charge is large enough
(that is, if the overshoot/undershoot is great enough). Determining the impact of an
overshoot/undershoot condition requires knowledge of the magnitude, the pulse
duration, and the activity factor (AF).
2.5.1 Overshoot/Undershoot Magnitude
Magnitude describes the maximum potential difference between a signal and its voltage
reference level. For the processor, both are referenced to GND, as shown in Figure 2-3.
It is important to note that overshoot and undershoot conditions are separate and their
impact must be determined independently. Overshoot/undershoot magnitude levels
must observe the absolute maximum specifications listed in Table 2-13 through
Table 2-17. These specifications must not be violated at any time, regardless of bus
activity or system state. Within these specifications are threshold levels that define
different allowed pulse duration. Provided that the magnitude of the overshoot/
undershoot is within the absolute maximum specifications, the pulse magnitude,
duration, and activity factors must all be used to determine if the overshoot/
undershoot pulse is within specifications.
voltage (or below GND), as shown in Table 2-3. The overshoot/
CTERM
or GND due to the fast signal
CTERM
Figure 2-3. System Bus Signal Waveform Exhibiting Overshoot/Undershoot
000588
Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet 23
Electrical Specifications
2.5.2 Overshoot/Undershoot Pulse Duration
Pulse duration describes the total time that an overshoot/undershoot event exceeds the
overshoot/undershoot reference voltage (V
encompass several oscillations above the reference voltage. Multiple overshoot/
undershoot pulses within a single overshoot/undershoot event may need to be
measured to determine the total pulse duration.
Note: Oscillations below the reference voltage cannot be subtracted from the total overshoot/
undershoot pulse duration.
/GND). The total time could
CTERM
2.5.3 Activity Factor
Activity factor (AF) describes the frequency of overshoot (or undershoot) occurrence
relative to a clock. Since the highest frequency of assertion of any common clock signal
is every other clock, an AF = 1 indicates that the specific overshoot (or undershoot)
waveform occurs every other clock cycle. Thus, an AF = 0.01 indicates that the specific
overshoot (or undershoot) waveform occurs one time in every 200 clock cycles. For
source synchronous signals (data, and associated strobes), the activity factor is in
reference to the strobe edge. The highest frequency of assertion of any source
synchronous signal is every active edge of its associated strobe. So, an AF = 1
indicates that the specific overshoot (or undershoot) waveform occurs every other
strobe cycle. The specifications provided in Table 2-14 through Table 2-17 show the
maximum pulse duration allowed for a given overshoot/undershoot magnitude at a
specific activity factor. Each table entry is independent of all others, meaning that the
pulse duration reflects the existence of overshoot/undershoot events of that magnitude
ONLY. A platform with an overshoot/undershoot that just meets the pulse duration for a
specific magnitude where the AF <1, means that there can be no other overshoot/
undershoot events, even of lesser magnitude (if AF = 1, then the event occurs at all
times and no other events can occur).
Note: AF for the common clock AGTL+ signals is referenced to BCLKn, and BCLKp frequency.
The wired-OR Signals (BINIT#, HIT#, HITM#, BNR#, TND#, BERR#) are common
clock AGTL+ signals.
Note: AF for source synchronous (2x) signals is referenced to STBP#[7:0], and STBN#[7:0].
2.5.4 Reading Overshoot/Undershoot Specification Tables
The overshoot/undershoot specification for the processor is not a simple single value.
Instead, many factors are needed in order to correctly interpret the overshoot/
undershoot specification. In addition to the magnitude of the overshoot, the following
parameters must also be known: the width of the overshoot and the AF. To determine
the allowed overshoot for a particular overshoot event, the following must be done:
1. Determine the signal group that the particular signal falls into. For AGTL+ signals
operating in the 2x source synchronous domain, use Table 2-14 through
Table 2-16. If the signal is a wired-OR AGTL+ signal operating in the common clock
domain, use Table 2-15 through Table 2-17.
2. Determine the magnitude of the overshoot, or the undershoot (relative to GND).
3. Determine the activity factor (how often does this overshoot occur?).
4. Next, from the appropriate specification table, determine the maximum pulse
duration (in nanoseconds) allowed. The pulse duration shown in the table refers to
the period where either the maximum overshoot (for high phase) and undershoot
(for low phase) occurred.
24 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet
Electrical Specifications
5. Compare the specified maximum pulse duration to the signal being measured. If
the pulse duration measured is less than the pulse duration shown in the table,
then the signal meets the specifications.
6. Undershoot events must be analyzed separately from overshoot events, as they are
mutually exclusive.
2.5.5 Determining if a System Meets the Overshoot/Undershoot
Specifications
The overshoot/undershoot specifications listed in Table 2-13 through Table 2-17 specify
the allowable overshoot/undershoot for a single overshoot/undershoot event. However,
most systems will have multiple overshoot and/or undershoot events that each has
their own set of parameters (duration, AF and magnitude). While each overshoot on its
own may meet the overshoot specification, the total impact of all overshoot events may
cause the system to fail. A guideline to ensure a system passes the overshoot and
undershoot specifications is shown below:
1. Ensure that no signal ever exceeds V
2. If only one overshoot/undershoot event magnitude occurs, ensure that it meets the
specifications listed in Table 2-13 through Table 2-17.
3. If multiple overshoots and/or multiple undershoots occur, measure the worst-case
pulse duration for each magnitude and compare the results against the AF = 1
specifications. If all of these worst-case overshoot or undershoot events meet the
specifications (measured time < specifications) in the table (where AF = 1), then
the system passes.
CTERM
or GND.
2.5.6 Wired-OR Signals
To ensure platform compatibility between the processors, system bus signals must
meet certain overshoot and undershoot requirements. The system bus wired-OR
signals (BINIT#, HIT#, HITM#, BNR#, TND#, BERR#) have the same absolute
overshoot and undershoot specification as the Source Synchronous AGTL+ Signals, but
they have different time-dependent overshoot/undershoot requirements.
Table 2-13. Source Synchronous AGTL+ Signal Group and Wired-OR Signal Group Absolute
Overshoot/Undershoot Tolerance
Parameter Description Specification Units
V
CTERM
V
MAX
V
MIN
Overshoot Time dependent overshoot amount above V
Undershoot Time dependent undershoot amount below GND.
Notes:
1. These parameters cannot be specified in absolute terms.
Notes: The following notes apply to Table 2-14 through Table 2-17:
1. Absolute Maximum Overshoot magnitude of 1.65 V must never be exceeded.
2. Absolute Maximum Overshoot is measured referenced to GND. Pulse duration of overshoot is measured
relative to V
3. Absolute Maximum Undershoot and Pulse Duration of undershoot is measured relative to GND.
4. Ringback below V
5. Lesser undershoot does not allocate overshoot with longer duration or greater magnitude.
6. All values specified by design characterization.
I/O power supply voltage (nominal). 1.20 V
Maximum absolute voltage for system bus signals at the input
of the receiver buffers.
Minimum absolute voltage for system bus signals at the input
of the receiver buffers.
CTERM .
.
CTERM
cannot be subtracted from overshoots/undershoots.
CTERM
1.65 V
–0.45 V
1
1
Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet 25
Electrical Specifications
Table 2-14. Source Synchronous AGTL+ Signal Group Time-Dependent Overshoot/
Undershoot Tolerance for 400-MHz System Bus
Absolute
Maximum (V)
Overshoot
1.65 –0.45 0.0035 0.0036 0.0037 0.0040 0.0121 0.0241 0.1207
1.55 –0.35 0.0124 0.0168 0.0255 0.0520 0.1309 0.2626 1.3107
1.45 –0.25 0.1304 0.1755 0.2671 0.5438 1.3629 2.5 2.5
1.35 –0.15 1.3163 1.7815 2.5 2.5 2.5 2.5 2.5
1.25 –0.05 2.5 2.5 2.5 2.5 2.5 2.5 2.5
Notes:
1. Activity Factor = 1 means signal toggles every 5 ns.
Under-
shoot
1.6 –0.4 0.0039 0.0040 0.0045 0.0157 0.0396 0.0799 0.3996
1.5 –0.3 0.0405 0.0546 0.0833 0.1682 0.4279 0.8546 2.5
1.4 –0.2 0.4136 0.5581 0.8524 1.7215 2.5 2.5 2.5
1.3 –0.1 2.5 2.5 2.5 2.5 2.5 2.5 2.5
AF = 1
1
AF = 0.75 AF = 0.5 AF = 0.25 AF = 0.1 AF = 0.05 AF = 0.01
Pulse Duration (ns)
Table 2-15. Wired-OR Signal Group (BINIT#, HIT#, HITM#, BNR#, TND#, BERR#)
Overshoot/Undershoot Tolerance for 400-MHz System Bus
Absolute
Maximum (V)
Overshoot
1.65 –0.45 0.0166 0.0192 0.0306 0.0614 0.1539 0.3067 1.5374
1.55 –0.35 0.1659 0.2216 0.3342 0.6676 1.6734 3.3413 5
1.45 –0.25 1.7343 2.3194 3.4995 5 5 5 5
1.35 –0.15 5 5 5 5 5 5 5
Notes:
1. Activity Factor = 1 means signal toggles every 10 ns.
Under-
shoot
1.6 –0.4 0.0506 0.0674 0.1017 0.2032 0.5090 1.0213 5
1.5 –0.3 0.5413 0.7218 1.0840 2.1814 5 5 5
1.4 –0.2 5 5 5 5 5 5 5
AF = 1
1
AF = 0.75 AF = 0.5 AF = 0.25 AF = 0.1 AF = 0.05 AF = 0.01
Pulse Duration (ns)
Table 2-16. Source Synchronous AGTL+ Signal Group Time-Dependent Overshoot/
Undershoot Tolerance for 533-MHz System Bus (Sheet 1 of 2)
Absolute
Maximum (V)
Overshoot
1.65 –0.45 0.0026 0.0027 0.0028 0.0030 0.0091 0.0181 0.0902
1.55 –0.35 0.0093 0.0126 0.0191 0.0387 0.0980 0.1963 0.9822
1.45 –0.25 0.3095 0.4191 0.6366 1.2965 1.875 1.875 1.875
26 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet
Under-
shoot
1.6 –0.4 0.0029 0.0030 0.0034 0.0118 0.0297 0.0600 0.2989
1.5 –0.3 0.0303 0.0409 0.0625 0.1268 0.3178 0.6406 1.875
AF = 11AF = 0.75 AF = 0.5 AF = 0.25 AF = 0.1 AF = 0.05 AF = 0.01
Pulse Duration (ns)
Electrical Specifications
Table 2-16. Source Synchronous AGTL+ Signal Group Time-Dependent Overshoot/
Undershoot Tolerance for 533-MHz System Bus (Sheet 2 of 2)
Absolute
Maximum (V)
1.4 –0.2 0.9925 1.3358 1.875 1.875 1.875 1.875 1.875
1.35 –0.15 1.875 1.875 1.875 1.875 1.875 1.875 1.875
1.3 –0.10 1.875 1.875 1.875 1.875 1.875 1.875 1.875
Notes:
1. Activity Factor = 1 means signal toggles every 3.75 ns.
Pulse Duration (ns)
Table 2-17. Wired-OR Signal Group (BINIT#, HIT#, HITM#, BNR#, TND#, BERR#)
Overshoot/Undershoot Tolerance for 533-MHz System Bus
Absolute
Maximum (V)
Overshoot
1.65 –0.45 0.01248 0.0144 0.0230 0.0461 0.1155 0.2301 1.1530
1.55 -0.35 0.1250 0.1668 0.2507 0.5004 1.2537 2.5059 3.75
1.45 –0.25 1.3013 1.7396 2.6246 3.75 3.75 3.75 3.75
1.35 –0.15 3.75 3.75 3.75 3.75 3.75 3.75 3.75
Notes:
1. Activity Factor = 1 means signal toggles every 7.5 ns.
Under-
shoot
1.6 –0.4 0.0380 0.0507 0.0763 0.1522 0.3814 0.7627 3.75
1.5 –0.3 0.4054 0.5424 0.8163 1.6302 3.75 3.75 3.75
1.4 -0.2 3.75 3.75 3.75 3.75 3.75 3.75 3.75
AF = 1
1
AF = 0.75 AF = 0.5 AF = 0.25 AF = 0.1 AF = 0.05 AF = 0.01
Pulse Duration (ns)
2.6 Voltage Regulator Connector Signals
The VR module consists of three DC-DC converters, V
Table 2-18 lists all of the signals which are part of the processor package VR output
connector.
Table 2-18. VR Connector Signals
Group Name Signals
Voltage Regulator
Connector
PPODGD#, CPUPRES#, GND, Vid_valid, Vid_Core[5:0],
Vid_cache [5:0], Vcache_sense, Gnd_sense, Vcore_sense,
Vfixed_sense, OUTEN.
Warning: If the VR cannot supply the voltages requested by the components in the processor
package, then it must disable itself.
Figure 2-4 shows the top view of the processor package power tab. See Table 2-19 for
power tab connector signals.
core
, V
cache
, and V
fixed
.
Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet 27
Figure 2-4. Processors Power Tab Physical Layout
Table 2-19. Power Connector Pinouts (Sheet 1 of 2)
Electrical Specifications
001356
Power Tab VR Pads Description
A1 - C1 GND
L1 - N1 GND
A2 PPODGD#
B2 CPUPRES#
D1, K1, C2, D2, E2 Vfixed
H2 - N2 Vfixed
A3 Vid_valid
B3 Vid_core [0]
C3 Vid_core [1]
D3 Vid_core [2]
E3 Vid_core [3]
F3 Vid_core [4]
G3 Vid_core [5]
H3 Vid_cache [0]
J3 Vid_cache [1]
K3 Vid_cache [2]
L3 Vid_cache [3]
M3 Vid_cache [4]
N3 Vid_cache [5]
A4 - N4 GND
A5 - N5 Vcache
A6 - N6 GND
A7 - N7 Vcore
A8 - N8 GND
A9 - N9 Vcore
28 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet
Electrical Specifications
Table 2-19. Power Connector Pinouts (Sheet 2 of 2)
Power Tab VR Pads Description
A10 - N10 GND
A11 - N11 Vcore
A12 - N12 GND
A13 - N13 Vcore
A14 - N14 GND
A15 - N15 Vcore
A16 - N16 GND
A17 - N17 Vcore
A18 - N18 GND
A19 - N19 Vcore
A20 - N20 GND
A21 - N21 Vcore
A22 - N22 GND
A23 - N23 Vcore
A24 - N24 GND
A25 - N25 Vcore
A26 - N26 GND
A27 - N27 Vcache
A28 - N28 GND
A29 Vcache_sense
B29 Gnd_sense
C29 Vcore_sense
D29 Vfixed_sense
K29 GND
L29 Reserved
M29 Reserved
N29 OUTEN
A30 - D30 GND
L30 - N30 GND
The VR shall provide a selectable output voltage controlled via multiple binary weighted
Voltage Identification (VID) inputs. The VID value (high = 1; low = 0) is defined in
Table 2-20. VID pins will be controlled by the processor.
Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet 29
Electrical Specifications
Table 2-20. Processors Core Voltage Identification Code (V
Processor Pins (0 = low, 1 = high)
400 200 100 50 25 12.5 (mV) 400 200 100 50 25 12.5 (mV)
VID5VID4VID3VID2VID1VID0Vout
1 1 1 1 1 1 OFF 0 1 1 1 1 1 0.9125
1 1 1 1 1 0 1.3 0 1 1 1 1 0 0.9
1 1 1 1 0 1 1.2875 0 1 1 1 0 1 0.8875
1 1 1 1 0 0 1.275 0 1 1 1 0 0 0.875
1 1 1 0 1 1 1.2625 0 1 1 0 1 1 0.8625
1 1 1 0 1 0 1.25 0 1 1 0 1 0 0.85
1 1 1 0 0 1 1.2375 0 1 1 0 0 1 0.8375
1 1 1 0 0 0 1.225 0 1 1 0 0 0 0.825
1 1 0 1 1 1 1.2125 0 1 0 1 1 1 0.8125
1 1 0 1 1 0 1.2 0 1 0 1 1 0 0.8
1 1 0 1 0 1 1.1875 0 1 0 1 0 1 0.7875
1 1 0 1 0 0 1.175 0 1 0 1 0 0 0.775
1 1 0 0 1 1 1.1625 0 1 0 0 1 1 0.7625
1 1 0 0 1 0 1.15 0 1 0 0 1 0 0.75
1 1 0 0 0 1 1.1375 0 1 0 0 0 1 0.7375
1 1 0 0 0 0 1.125 0 1 0 0 0 0 0.725
1 0 1 1 1 1 1.1125 0 0 1 1 1 1 0.7125
1 0 1 1 1 0 1.1 0 0 1 1 1 0 0.7
1 0 1 1 0 1 1.0875 0 0 1 1 0 1 0.6875
1 0 1 1 0 0 1.075 0 0 1 1 0 0 0.675
1 0 1 0 1 1 1.0625 0 0 1 0 1 1 0.6625
1 0 1 0 1 0 1.05 0 0 1 0 1 0 0.65
1 0 1 0 0 1 1.0375 0 0 1 0 0 1 0.6375
1 0 1 0 0 0 1.025 0 0 1 0 0 0 0.625
1 0 0 1 1 1 1.0125 0 0 0 1 1 1 0.6125
1 0 0 1 1 0 1 0 0 0 1 1 0 0.6
1 0 0 1 0 1 0.9875 0 0 0 1 0 1 0.5875
1 0 0 1 0 0 0.975 0 0 0 1 0 0 0.575
1 0 0 0 1 1 0.9625 0 0 0 0 1 1 0.5625
1 0 0 0 1 0 0.95 0 0 0 0 1 0 0.55
1 0 0 0 0 1 0.9375 0 0 0 0 0 1 0.5375
1 0 0 0 0 0 0.925 0 0 0 0 0 0 0.525
VID5VID4VID3VID2VID1VID0Vout
(V)
CORE
and V
CACHE)
(V)
30 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet
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