Intel Itanium 2 Processor User Manual
Intel® It anium® 2 Processor
Intel® Itanium® 2 Processor 1.66 GHz with 9 MB L3 Cache
®
Intel
Itanium® 2 Processor 1.66 GHz with 6 MB L3 Cache
®
Intel
Itanium® 2 Processor 1.6 GHz with 9 MB L3 Cache
®
Intel
Itanium® 2 Processor 1.6 GHz with 6 MB L3 Cache
®
Intel
Itanium® 2 Processor 1.5 GHz with 6 MB L3 Cache
®
Intel
Itanium® 2 Processor 1.5 GHz with 4 MB L3 Cache
®
Intel
Itanium® 2 Processor 1.4 GHz with 4 MB L3 Cache
®
Intel
Itanium® 2 Processor 1.3 GHz with 3 MB L3 Cache
®
Intel
Itanium® 2 Processor 1.0 GHz with 3 MB L3 Cache
®
Intel
Itanium® 2 Processor 900 MHz with 1.5 MB L3 Cache
Datasheet
February 2006
Document Number: 250945-005
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PRO PERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEV ER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING T O FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY P ATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “un defined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them
®
The Intel
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product o rder.
Copies of documents which have an order number and are referenced in this document, or other Inte l literature, may be obta ined by calling1-800-5 48-
4725, or by visiting Intel's website at http://www.intel.com.
Intel and Itanium are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
Copyright © 2002-2006, Intel Corporation
*Other names and brands may be claimed as the property of others.
I2C is a two-wire communication bus /protocol developed by Phillips. SMBus is a subset of the I2C bus/protocol developed by Intel. Implementation of
the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Phillips Electronics, N.V. and North American
Phillips Corporation.
Itanium® 2 processor may contain design defects or errors known as errata which may cause the product to deviate from published
2 Datasheet
Contents
1 Introduction.......................................................................................................................11
1.1 Overview .............................................................................................................11
1.2 Processor Abstraction Layer............................................................................ ...11
1.3 Mixing Processors of Different Frequencies and Cache Sizes ...........................12
1.4 Terminology.........................................................................................................12
1.5 State of Data .......................................................................................................12
1.6 Reference Documents.........................................................................................13
2 Electrical Specifications....................................................................................................15
2.1 Itanium
2.1.1 System Bus Power Pins.........................................................................15
2.1.2 System Bus No Connect. ... .... ... ... ... .... ... ... ... ..........................................15
2.2 System Bus Signals ............................................................................................15
2.2.1 Signal Groups.................. ... .... ... ... ... .... ... ... .............................................15
2.2.2 Signal Descriptions............. .... ... ... ... .... ... ................................................16
2.3 Package Specifications.......................................................................................17
2.4 Signal Specifications.... ... ... .... ... ..........................................................................18
2.4.1 Maximum Ratings................... ... ... ... .... ... ... ... ... .... ... ................................22
2.5 System Bus Signal Quality Specifications and Measurement Guidelines...........23
2.5.1 Overshoot/Undershoot Magnitude .........................................................23
2.5.2 Overshoot/Undershoot Pulse Duration......... ... .... ... ... ... .... ... ... ... ... ..........24
2.5.3 Activity Factor.........................................................................................24
2.5.4 Reading Overshoot/Undershoot Specification Tables............................25
2.5.5 Determining if a System Meets the Overshoot/Undershoot
2.5.6 Wired-OR Signals...................................................................................28
2.6 Power Pod Connector Signals ............................................................................30
2.7 Itanium
2.8 Recommended Connections for Unused Pins ....................................................35
®
2 Processor System Bus......................................................................15
Specifications.........................................................................................25
®
2 Processor System Bus Clock and Processor Clocking .....................32
3 Pinout Specifications........................................................................................................37
4 Mechanical Specifications................................................................................................69
4.1 Mechanical Dimensions ......................................................................................69
4.2 Package Marking.................................................................................................72
4.2.1 Processor Top-Side Marking........................... .... ... ... ... .... ... ... ... ... .... ... ...72
4.2.2 Processor Bottom-Side Marking.............................................................72
5 Thermal Specifications........ .......................................... ... ... .......................................... ...75
5.1 Thermal Features............................................. ... ... .......................................... ...75
5.1.1 Thermal Alert............................. ... ..........................................................75
5.1.2 Enhanced Thermal Management...........................................................76
5.1.3 Thermal Trip................................. ... .... ... ... ... ... .... ...................................76
5.2 Case Temperature .............................................. ... ... ..........................................76
6 System Management Feature Specifications...................................................................79
6.1 System Management Bus...................................................................................79
6.1.1 System Management Bus Interface .......................................................79
6.1.2 System Management Interface Signals..................................................79
Datasheet 3
6.1.3 SMBus Device Addressing.....................................................................81
6.2 Processor Information ROM................................................................................82
6.3 Scratch EEPROM ...............................................................................................85
6.4 Processor Information ROM and Scratch EEPROM Supported
SMBus Transactions...........................................................................................85
6.5 Thermal Sensing Device.....................................................................................86
6.6 Thermal Sensing Device Supported SMBus Transactions .................................87
6.7 Thermal Sensing Device Registers.....................................................................88
6.7.1 Thermal Reference Registers ................................................................88
6.7.2 Thermal Limit Registers .........................................................................89
6.7.3 Status Register... ... ... .... ..........................................................................89
6.7.4 Configuration Register ...........................................................................89
6.7.5 Conversion Rate Register......................................................................90
A Signals Reference........................ ... ... .... ... ... ... .... .............................................................91
A.1 Alphabetical Signals Reference ..........................................................................91
A.1.1 A[49:3]# (I/O)..........................................................................................91
A.1.2 A20M# (I) ...............................................................................................91
A.1.3 ADS# (I/O)................................. ... ... ... .... ... ...................................... .... ...91
A.1.4 AP[1:0]# (I/O) ............................................... ... ... .... ... ... ... .... ...................91
A.1.5 ASZ[1:0]# (I/O).......................................................................................91
A.1.6 ATTR[3:0]# (I/O).....................................................................................92
A.1.7 BCLKp/BCLKn (I)...................................................................................92
A.1.8 BE[7:0]# (I/O) ............................................... ... ... .... ... ... ... .... ...................92
A.1.9 BERR# (I/O)...........................................................................................93
A.1.10 BINIT# (I/O)............................................................................................94
A.1.11 BNR# (I/O) ...................... ... ... .... ... ... ....................................... ... ... ... .... ...94
A.1.12 BPM[5:0]# (I/O) ......................................................................................94
A.1.13 BPRI# (I) ................................................................................................94
A.1.14 BR[0]# (I/O) and BR[3:1]# (I)..................................................................94
A.1.15 BREQ[3:0]# (I/O)....................................................................................95
A.1.16 CCL# (I/O)..............................................................................................96
A.1.17 CPUPRES# (O)......................................................................................96
A.1.18 D[127:0]# (I/O) .......................................................................................96
A.1.19 D/C# (I/O)...............................................................................................96
A.1.20 DBSY# (I/O) ................................................. ... ... .... ... .............................96
A.1.21 DBSY_C1# (O).......................................................................................96
A.1.22 DBSY_C2# (O).......................................................................................97
A.1.23 DEFER# (I)................................... ... ... ....................................... ... ... .... ...97
A.1.24 DEN# (I/O) ...................... ... ... .... ... ....................................... ... ... ... ... .......97
A.1.25 DEP[15:0]# (I/O).....................................................................................97
A.1.26 DHIT# (I) ......................... ... ... .... ... ... ....................................... ... ... ... .... ...97
A.1.27 DPS# (I/O).................................... ... ... ....................................... ... ... .... ...98
A.1.28 DRDY# (I/O)...........................................................................................98
A.1.29 DRDY_C1# (O) ......................................................... .............................98
A.1.30 DRDY_C2# (O) ......................................................... .............................98
A.1.31 DSZ[1:0]# (I/O).......................................................................................98
A.1.32 EXF[4:0]# (I/O).......................................................................................98
A.1.33 FCL# (I/O) ..............................................................................................99
A.1.34 FERR# (O) ...................................................... ... .... ... ... ... .... ...................99
A.1.35 GSEQ# (I) ....................... ... ... .... ... ... ... .... ... ...................................... .... ...99
A.1.36 HIT# (I/O) and HITM# (I/O) ....................................................................99
4 Datasheet
A.1.37 ID[9:0]# (I) ..............................................................................................99
A.1.38 IDS# (I)...................................................................................................99
A.1.39 IGNNE# (I)............................................................................................100
A.1.40 INIT# (I)................................................................................................100
A.1.41 INT (I)...................................................................................................100
A.1.42 IP[1:0]# (I).............................................................................................100
A.1.43 LEN[2:0]# (I/O) .................................................................... ... ..............100
A.1.44 LINT[1:0] (I) ..........................................................................................101
A.1.45 LOCK# (I/O) .........................................................................................101
A.1.46 NMI (I) ..................................................................................................101
A.1.47 OWN# (I/O) ............................................ ... ... ... .... ... ... ...........................101
A.1.48 PMI# (I)...................... ... ... ... .... ... ....................................... ... ... ... ... .... ... .101
A.1.49 PWRGOOD (I)................. ... .... ... ... ... .....................................................101
A.1.50 REQ[5:0]# (I/O) ...................................... ... ... ....................................... .101
A.1.51 RESET# (I)...........................................................................................102
A.1.52 RP# (I/O)..............................................................................................102
A.1.53 RS[2:0]# (I)...........................................................................................103
A.1.54 RSP# (I)................................................................................................103
A.1.55 SBSY# (I/O)..........................................................................................103
A.1.56 SBSY_C1# (O)................... ..................................................................103
A.1.57 SBSY_C2# (O)................... ..................................................................103
A.1.58 SPLCK# (I/O) ......................................... ... ... ... .... ... ..............................103
A.1.59 STBn[7:0]# and STBp[7:0]# (I/O).........................................................104
A.1.60 TCK (I)..................................................................................................104
A.1.61 TDI (I)...................................................................................................104
A.1.62 TDO (O)..................... ...................................... .... ... ... ... .... ... ... ..............104
A.1.63 THRMTRIP# (O)...................................................................................104
A.1.64 THRMALERT# (O)...............................................................................105
A.1.65 TMS (I) ................................................... ... ... ... .... ... ... ...........................105
A.1.66 TND# (I/O)............................................................................................105
A.1.67 TRDY# (I).............................................................................................105
A.1.68 TRST# (I)..............................................................................................105
A.1.69 WSNP# (I/O) ........................................................................................105
A.2 Signal Summaries........ ... ... .... ... ... ... .... .......................................... ... ... ... ...........105
Figures
2-1 Generic Clock Waveform ....................................................................................22
2-2 SMSC Clock Waveform.......................................................................................22
2-3 System Bus Signal Waveform Exhibiting Overshoot/Undershoot.......................24
2-4 Itanium
2-5 Processor Full, Normal and Low Power Mode with Timings...............................32
2-6 System Bus Reset and Configuration Timings for Cold Reset............................34
2-7 System Bus Reset and Configuration Timings for Warm Reset..........................35
3-1 Itanium
4-1 Itanium
4-2 Itanium
4-3 Itanium
4-4 Processor Top-Side Marking on IHS...................................................................72
4-5 Processor Bottom-Side Marking Placement on Interposer .................................73
5-1 Itanium
Datasheet 5
®
2 Processor Power Tab Physical Layout..............................................30
®
2 Processor Pinout...............................................................................37
®
2 Processor Package ...........................................................................69
®
2 Processor Package ...........................................................................70
®
2 Processor Package Power Tab.........................................................71
®
2 Processor Thermal Features.............................................................75
Tables
5-2 Itanium® 2 Processor Package Thermocouple Location.....................................77
6-1 Logical Schematic of SMBus Circuitry ................................................................80
2-1 Itanium® 2 Processor System Bus Signal Groups..............................................16
2-2 Itanium
2-3 Itanium
®
2 Processor Package Specifications....................................................17
®
2 Processor Power Supply Specifications............................................18
2-4 AGTL+ Signals DC Specifications.......................................................................18
2-5 Power Good Signal DC Specifications......................... ... .... ... ... ... .... ... ... ... ... .... ...19
2-6 System Bus Clock Differential HSTL DC Specifications .....................................19
2-7 TAP Connection DC Specifications.....................................................................19
2-8 SMBus DC Specifications ...................................................................................20
2-9 LVTTL Signal DC Specific at ions .................................................................. .... ...20
2-10 System Bus Clock Differential HSTL AC Specifications .....................................20
2-11 SMBus AC Specifications ...................................................................................21
2-12 Itanium
®
2 Processor Absolute Maximum Ratings .............................................22
2-13 Source Synchronous AGTL+ Signal Group and Wired-OR Signal Group
Absolute Overshoot/Undershoot Tolerance........................................................26
2-14 Itanium
®
2 Processors (900 MHz, 1.0 GHz, 1.3 GHz, 1.4 GHz, 1.5 GHz/6 MB)
Source Synchronous AGTL+ Signal Group Time Dependent
Overshoot/Undershoot Tolerance for 400 MHz System Bus ..............................26
2-15 Itanium
®
2 Processors (1.5 GHz/4 MB, 1.6 GHz) Source
Synchronous AGTL+ Signal Group Time-Dependent
Overshoot/Undershoot Tolerance for 400 MHz System Bus ..............................27
2-16 Itanium
®
2 (9 MB) Processors Source Synchronous AGTL+
Signal Group Time-Dependent Over sho o t/Undershoot Tolerance
for 533 MHz System Bus ....................................................................................27
2-17 Itanium
®
2 Processors (1.66 GHz) Source Synchronous AGTL+
Signal Group Time-Dependent Over sho o t/Undershoot Tolerance
for 667 MHz System Bus ....................................................................................28
2-18 Itanium
®
2 Processors (900 MHz, 1.0 GHz, 1.3 GHz, 1.4 GHz,
1.5 GHz/6 MB) Wired-OR Signal Group
(BINIT#, HIT#, HITM#, BNR#, TND#, BERR#)
Overshoot/Undershoot Tolerance for 400 MHz System Bus ..............................28
2-19 Itanium
®
2 Processors (1.5 GHz/4 MB, 1.6 GHz) Wired-OR Signal
Group (BINIT#, HIT#, HITM#, BNR#, TND#, BERR#)
Overshoot/Undershoot Tolerance for 400 MHz System Bus ..............................29
2-20 Itanium
®
2 (9 MB) Processors Wired-OR Signal Group
(BINIT#, HIT#, HITM#, BNR#, TND#, BERR#) Overshoot/Undershoot
Tolerance for 533 MHz System Bus ...................................................................29
2-21 Itanium
®
2 (1.66 GHz) Processors Wired-OR Signal Group
(BINIT#, HIT#, HITM#, BNR#, TND#, BERR#) Overshoot/Undershoot
Tolerance for 667 MHz System Bus ...................................................................29
2-22 Itanium
®
2 Processor Power Pod Connector Signals.........................................30
2-23 Processor Core Voltage Identification Code .......................................................31
2-24 Processor Power States......................................................................................32
2-25 Itanium
®
2 Processor System Bus Ratios...........................................................33
2-26 Connection for Unused Pins ...............................................................................35
3-1 Pin/Signal Information Sorted by Pin Name........................................................38
3-2 Pin/Signal Information Sorted by Pin Location....................................................53
5-1 Case Temperature Specification.........................................................................76
6-1 System Management Interface Signal Descriptions ...........................................79
6 Datasheet
6-2 Thermal Sensing Device SMBus Addressing on the Itanium® 2 Processor .......81
6-3 EEPROM SMBus Addressing on the Itanium
®
2 Processor......................... ... ...82
6-4 Processor Information ROM Format ...................................................................82
6-5 Current Address Read SMBus Packet................................................................86
6-6 Random Address Read SMBus Packet ..............................................................86
6-7 Byte Write SMBus Packet ...................................................................................86
6-8 Write Byte SMBus Packet...................................................................................87
6-9 Read Byte SMBus Packet...................................................................................87
6-10 Send Byte SMBus Packet ...................................................................................87
6-11 Receive Byte SMBus Packet...............................................................................87
6-12 ARA SMBus Packet ............................................................................................87
6-13 Command Byte Bit Assignment...........................................................................88
6-14 Thermal Sensing Device Status Register............................................................89
6-15 Thermal Sensing Device Configuration Register ................................................89
6-16 Thermal Sensing Device Conversion Rate Register...........................................90
A-1 Address Space Size............................................................................................92
A-2 Effective Memory Type Signal Encoding................................................ ... .... ... ...92
A-3 Special Transaction Encoding on Byte Enables..................................................93
A-5 BR0# (I/O), BR1#, BR2#, BR3# Signals for 2P Rotating Interconnect................95
A-4 BR0# (I/O), BR1#, BR2#, BR3# Signals for 4P Rotating Interconnect................95
A-6 BR[3:0]# Signals and Agent IDs............................. .......................................... ...95
A-7 DID[9:0]# Encoding.............................................................................................97
A-8 Extended Function Signals........................................................ .... ... ... ... ... .... ... ...99
A-9 Length of Data Transfers...................................................................................100
A-10 Transaction Types Defined by REQa#/REQb# Signals ....................................102
A-11 STBp[7:0]# and STBn[7:0]# Associations .........................................................104
A-12 Output Signals...................................................................................................105
A-13 Input Signals......................................................................................................106
A-14 Input/Output Signals (Single Driver)..................................................................107
A-15 Input/Output Signals (Multiple Driver) ...............................................................107
Datasheet 7
Revision History
Revision No. Description Date
-001 Initial release of this document. July 2002
-002 Updated content to include information pertaining to Itanium
(1.5 GHz, 6 MB), Itanium
processor (1.3 GHz, 3 MB).
-003 Updated content to include information pertaining to Itanium
processor (1.5 GHz, 4 MB) and Itanium
9MB).
-004 Updated content to include information pertaining to Itanium
processor (1.66 GHz, 6 MB and 9 MB).
-005 Updated content to include information pertaining to Itanium
processor (533 MHz system bus speed).
2 processor (1.4 GHz, 4 MB) and Itanium 2
2 processor (1.6 GHz, 6 MB and
2 processor
®
2
®
2
®
2
June 2003
November 2004
July 2005
February 2006
8 Datasheet
Intel® Itanium® 2 Processor
Intel® Itanium® 2 Processor 1.66 GHz with 9 MB L3 Cache
®
Intel
Itanium® 2 Processor 1.66 GHz with 6 MB L3 Cache
®
Intel
Itanium® 2 Processor 1.6 GHz with 9 MB L3 Cache
®
Intel
Itanium® 2 Processor 1.6 GHz with 6 MB L3 Cache
®
Intel
Itanium® 2 Processor 1.5 GHz with 6 MB L3 Cache
®
Intel
Itanium® 2 Processor 1.5 GHz with 4 MB L3 Cache
®
Intel
Itanium® 2 Processor 1.4 GHz with 4 MB L3 Cache
®
Intel
Itanium® 2 Processor 1.3 GHz with 3 MB L3 Cache
®
Intel
Itanium® 2 Processor 1.0 GHz with 3 MB L3 Cache
Intel® Itanium® 2 Processor 900 MHz with 1.5 MB L3 Cache
Product Features
■ Wide, parallel hardware based on In tel
architecture for high performance:
— Integrated on-die cache of up to 9 MB; cache
hints for L1, L2, and L3 caches for reduced
memory latency.
— 128 general and 128 floating-point registers
supporting register rotation.
— Register stack engine for effective management
of processor resources.
— Support for predication and speculation.
■ Extensive RAS features for business-critical
applications:
— Full SMBus compatibility.
— Enhanced machine check architecture with
extensive ECC and parity protection.
— Enhanced thermal management.
— Built-in processor information ROM (PIROM).
— Built-in programmable EEPROM.
®
Itanium®
■ High bandwidth system bus for multiprocessor
scalability:
— Up to 10.6 GB/s bandwidth.
— 128-bit wide data bus.
— 50-bits of physical memory addressing and 64-
bits of virtual addressing.
— Up to four processors on the same system bus at
400 MHz data bus frequency.
— Up to two processors on the same system bus at
533 MHz or 667 MHz data bus frequency.
— Expandable to systems with multiple system
buses.
■ Features to support flexible platform environments:
— Support for IA-32 application binaries.
— Bi-endian support.
— Processor abstraction layer eliminates processor
dependencies.
The Intel® Itanium® 2 processor is designed to address the needs of high-performance servers and workstations.
The Itanium architecture goes beyond RISC and CISC approaches by employing Explicitly Parallel Instruction
Computing (EPIC), which pairs extensive processing resources with intelligent compilers that enable parallel
execution explicit to the processor. The processor’s large internal resources combine with predication and
speculation to enable optimization for high performance applications running on multiple operating systems,
including versions of Microsoft Windows*, HP-UX* and Linux*. The Itanium 2 processor is designed to support
very large scale systems, including those employing thousands of processors, to provide the processing power and
performance head room for the most demanding enterprise and technical computing applications. SMBus
compatibility and comprehensive reliability, availability and serviceability (RAS) features make the Itanium 2
processor ideal for applications requiring high up-time. For high performance servers and workstations, the
Itanium 2 processor offers outstanding performance and reliability for today’s applications and the scalability to
address the growing e-business needs of tomorrow.
Datasheet 9
10 Datasheet
1 Introduction
1.1 Overview
The Itanium 2 processor employs Explicitly Parallel Instruction Computing (EPIC) design
concepts for a tighter coupling between hardware and software. In this design style, the interface
between hardware and software is designed to enable the software to exploit all available compiletime information, and efficiently deliver this information to the hardware. It addresses several
fundamental performance bottlenecks in modern computers, such as memory latency, memory
address disambiguation, and control flow dependencies. The EPIC constructs provide powerful
architectural semantics, and enable the software to make global optimizations across a large
scheduling scope, thereby exposing available Instruction Level Parallelism (ILP) to the hardware.
The hardware takes advantage of this enhanced ILP, and provid e s abundant execution resources.
Additionally, it focuses on dynamic run-time optimizations to enable the compiled code schedule
to flow at high throughput. This strategy increases the synergy between hardware and software, and
leads to greater overall performance.
The Itanium 2 processor provides a 6-wide and 8-stage deep pipeline, running at up to 1.66 GHz.
This provides a combination of abundant resources to ex ploit ILP as well as increased frequency
for minimizing the latency of each instruction. The resources consist of six integer units, six
multimedia units, two load and two store units, three branch units, two extended-precision floating
point units, and one additional single-precision floating point unit. The hardware employs dynamic
prefetch, branch prediction, a register scoreboard, and non-blocking caches to optimize for
compile-time non-determinism. Three levels of on-die cache minimize overall memory latency.
This includes up to a 9 MB L3 cache, accessed at core speed, providing up to 84.8 Gb/sec of data
bandwidth. The system bus is designed to support up to four processors (on a single system bus),
and can be used as an effective building block for very large systems. The balanced core and
memory subsystem provide high performance for a wide range of applications ranging from
commercial workloads to high performance technical computing.
The Itanium 2 processor supports a range of computing needs and configurations from a 2-way to
large SMP servers. This document provides the electrical, mechanical and thermal specifications
for the Itanium 2 processor for use while using systems with Itanium 2 processors.
1.2 Processor Abstraction Layer
The Itanium 2 processor requires implementation-specific Processor Abstraction Layer (PAL)
firmware. P AL firmware supports processor initialization, error recovery , and other functionality . It
provides a consistent interface to system firmware and operating systems across processor
hardware implementations. The Intel
Volume 2: System Architecture, describes PAL. Platforms must provide access to the firmware
address space and PAL at reset to allow Itanium 2 processors to initialize.
The System Abstraction Layer (SAL) firmware contains platform-specific firmware to initialize
the platform, boot to an operating system, and provide runtime functionality. Further information
about SAL is available in the Intel
Specification.
Datasheet 11
®
Itanium® Architecture Software Developer’s Manual,
®
Itanium® Processor Family System Abstraction Layer
Introduction
1.3 Mixing Processors of Different Frequencies and Cache Sizes
All Itanium 2 processors on the same system bus are required to have the same cache size (9 MB,
6 MB, 4 MB, 3 MB or 1.5 MB) and identical core frequency. Mixing components of different core
frequencies and cache sizes is not supported and has not been validated by Intel. Operating system
support for multiprocessing with mixed components should also be considered.
While Intel has done nothing to specifically prevent processors within a multiprocessor
environment from operating at differing frequencies and differing cache sizes, there may be
uncharacterized errata that exist in such configurations. Customers would be fully responsible for
validation of system configurations with mixed components other than the supported
configurations described above.
1.4 Terminology
In this document, a ‘#’ symbol after a signal name refers to an active low signal. This means that a
signal is in the active state (based on the name of the signal) when driven to a low level. For
example, when RESET# is low, a processor reset has been requested. When NMI is high, a nonmaskable interrupt has occurred. In the case of lines where the name does not imply an active state
but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the
signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D [3:0] # = ‘LHLH’ also
refers to a hex ‘A’ (H = High logic level, L = Low lo gic level).
The term “system bus” refers to the interface between the processor, system core logic and other
bus agents. The system bus is a multiprocessing interface to processors, memory and I/O.
A signal name has all capitalized letters, for example, VCTERM.
A symbol referring to a voltage level, current level, or a time value carries a plain subscript, e.g.,
V
, or a capitalized abbreviated subscript, for example, TCO.
CC,core
1.5 State of Data
The data contained in this document is subject to change. It is the best information that Intel is able
to provide at the publication date of this document.
12 Datasheet
1.6 Reference Documents
The reader of this specification should also be familiar with material and concepts presented in the
following documents:
Title Document Number
®
Intel
Itanium® 2 Processor Specification Update 251141
®
Itanium® Architecture Software Developer’s Manual, Volume 1:
Intel
Application Architecture
®
Intel
Itanium® Architecture Software Developer’s Manual, Volume 2: System
Architecture
®
Intel
Itanium® Architecture Software Developer’s Manual,
Volume 3: Instruction Set Reference
®
Intel
Itanium® 2 Processor Reference Manual for Software Development and
Optimization
®
Intel
Itanium® Processor Family System Abstraction Layer Specification 245359
ITP700 Debug Port Design Guide 249679
System Management Bus Specification http://www.smbus.org/specs
Introduction
245317
245318
245319
251110
Note: Contact your Intel representative or check http://developer.intel.com for the latest revision of the
reference documents.
Datasheet 13
Introduction
14 Datasheet
2 Electrical Specifications
This chapter describes the electrical specifications of the Itanium 2 processor.
2.1 Itanium® 2 Processor System Bus
Most Itanium 2 processor signals use the Itanium processor’s assisted gunning transceiver logic
(AGTL+) signaling technology. The termination voltage, V
and is the system bus high reference voltage. The buffers that drive most of the system bus signals
on the Itanium 2 processor are actively driven to V
improve rise times and reduce noise. These signals should still be considered open-drain and
require termination to V
is terminated to V
which case the termination is provided by external resistors connected to V
CTERM
, which provides the high level. The Itanium 2 processor system bus
CTERM
at each end of the bus. There is also support of off-die termination in
during a low-to-high transition to
CTERM
, is generated on the baseboard
CTERM
CTERM
.
AGTL+ inputs use differential receivers which require a reference signal (V
the receivers to determine if a signal is a logical 0 or a logical 1. The Itanium 2 processor generates
V
on-die, thereby eliminating the need for an off-chip reference voltage source.
REF
2.1.1 System Bus Power Pins
VCTERM (1.2 V) input pins on the Itanium 2 processor provide power to the driver buffers and
on-die termination. The GND pins, in addition to the GND
provide ground to the processor. Power for the processor core is provided through the power tab
connector by V
management bus (SMBus). The V
from each other.
. The 3.3 V pin is included on the processor to provide power to the system
CC,PS
CTERM
2.1.2 System Bus No Connect
All pins designated as “N/C” or “No Connect” must remain unconnected.
2.2 System Bus Signals
2.2.1 Signal Groups
Table 2-1 contains Itanium 2 processor system bus signals that have been combined into groups by
buffer type and whether they are inputs, outputs or bidirectional with respect to the processor.
). V
REF
input at the power tab connector,
, 3.3 V, and GND pins must remain electrically separated
is used by
REF
Datasheet 15
Electrical Specifications
..
Table 2-1. Itanium
AGTL+ Input Signals BPRI#, BR[3:1]#, DEFER#, GSEQ#, ID[9:0]#, IDS#, RESET#
AGTL+ I/O Signals A[49:3]#, ADS#, AP[1:0]#, BERR#, BINIT#, BNR#, BPM[5:0]#1, BR0#,
AGTL+ Output Signals FERR#, THRMTRIP#, DBSY[1:0]#, DRDY[1:0]#, SBSY[1:0]#
Special AGTL+ Asynchronous
Interrupt Input Signals
Power Good Signal
HSTL Clock Signals BCLKn, BCLKp
TAP Input Signals
TAP Output Signals
System Management Signals
Power Signals GND, VCTERM
LVTTL Power Pod Signals
Other TERMA, TERMB, TUNER1, TUNER2, VCCMON, VSSMON
NOTES:
1. Signals will not be terminated on-die even when on-die termination (ODT) is enabled. See Intel® Itanium® 2 Processor
®
Group Name Signals
Hardware Developer’s Manual for further details.
2 Processor System Bus Signal Groups
RSP#, TRDY#
D[127:0]#, DBSY#, DEP[15:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[5:0]#,
RP#, SBSY#, STBN[7:0]#, STBP[7:0]#, TND#
A20M#, IGNNE#, INIT#, LINT[1,0], PMI#
1
1
1
PWRGOOD
TCK, TDI, TMS, TRST#
TDO
1
3.3V, SMA[2:0], SMSC, SMSD, SMWP, THRMALERT#
1
CPUPRES#, OUTEN, PPODGD#
1
, RS[2:0]#,
All system bus outputs should be treated as open drain signals and require a high level source
provided by the V
CTERM
supply.
AGTL+ inputs have differential input buffers which use V
signals require termination to V
AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output
Signals” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.
The Power Good (PWRGOOD) signal and Test Access Port (TAP) connection input signals use a
non-differential receiver with levels that are similar to AGTL+. No reference voltage is required for
these signals. The TAP Connection Output signals are AGTL+ output signals.
The Itanium 2 processor system bus requires termination on both ends of the bus. The Itanium 2
processor system bus supports both on-die and off-die termination controlled by two pins, TERMA
and TERMB. Please see the TERMA and TERMB pin description in Section 2.2.2.
The HSTL clock signals are the differential clock inputs for the Itanium 2 processor. The SMBus
signals and LVTTL power pod signals are driven using the 3.3 V CMOS logic levels listed in
Table 2-8 and Table 2-9, respectively.
2.2.2 Signal Descriptions
Appendix A, “Signals Reference”contains functional descriptions of all system bus signals and
L VTTL power pod signals. Further descriptions of the system management signals are contained in
Chapter 6. The signals listed under the “Power” and “Other” group are described here:
as a reference level. AGTL+ output
. In this document, “AGTL+ Input Signals” refers to the
CTERM
REF
16 Datasheet
Electrical Specifications
V
CTERM
System bus termination voltage.
GND System ground.
N/C No connection can be made to these pins.
TERMA, TERMB The Itanium 2 processor uses two pins to control the on-die termination
function, TERMA and TERMB. Both of these termination pins must be
pulled to VCTERM in order to terminate the system bus using the on-die
termination resistors. Both of these termination pins must be pulled to
GND in order to use off-die termination.
TUNER1, TUNER2 TUNER1 is used to control the slew rate of the system bus I/O buffers.
The nominal value for the TUNER1 resistor is 150 ohms. A lower
resistance will cause a faster slew rate. TUNER2 is used to control the
termination resistance for the system bus I/O buffers. The nominal value
for the TUNER2 resistor is 150 ohms. A lower resistance will cause a
lower on-die termination resistance. On-die termination mode will only
be selected if the TERMA and TERMB pins are terminated as indicated
above.
VCCMON, VSSMON These pins provide a remote sense connection from the processor to the
power pod. No connections that constitute a current load can be made to
these pins.
2.3 Package Specifications
Table 2-2 through Table 2-9 list the DC voltage, current and power specifications for the Itanium 2
processor. The voltage and current specifications are defined at the Itanium 2 processor pins.
Operational specifications listed in Table 2-2 through Table 2-9 are only valid while meeting
specifications for case temperature, clock frequency, and input voltages.
Table 2-2. Itanium
Symbol Parameter
V
CTERM
R
TERM
V
TAP
I
CTERM
PWR
MAX
PWR
TDE
PWR
TDP
®
2 Processor Package Specifications
Core
Frequency
Termination Voltage All 1.2 –1.5% 1.2 1.2 +1.5% V
Recommended Termination
Resistance
Test Access Port Voltage
(VCC
Termination Voltage Current All 7.2 A
Maximum Processor Power All 130 W
Thermal Design Envelope All 130 W
Thermal Design Power 900 MHz 90 W
TAP
)
All 45 W
All 1.2 –1.5% 1.2 1.5 V
1.0 GHz 100 W
1.3 GHz 97 W
1.4 GHz 91 W
1.5 GHz 107 W
1.6 GHz 122 W
1.66 GHz 122 W
Minimum Typ Maximum Unit Notes
1
2
3
4
5
6
6
6
6
6
6
6
Datasheet 17
Electrical Specifications
NOTES:
1. This is the tolerance requirement, across a 200 MHz bandwidth, at the processor pins. The requirement at the processor pins
accounts for voltage drops (and impedance discontinuities) at the processor pins and to the processor core. In addition to the
±1.5% DC tolerance, there is a ±3.5% AC tolerance for a total of ±5% tolerance.
2. The Itanium
die and off-die termination which is selected by the TERMA and TERMB pins. Termination tolerance is ±15% for on-die
termination measured at V
3. Maximum termination voltage current on one terminating agent.
4. For all core frequencies and cache sizes.
5. Maximum thermal design envelope is provided for the design of thermal/chassis solutions.
6. Maximum thermal design power is an estimate of the power dissipation for the Itanium 2 processor offering while executing a
worst-case application mix under nominal V
®
2 processor system bus is terminated at each end of the system bus. The Itanium 2 processor supports both on -
and ±1% for off-die termination.
OL
and worst-case temperature.
CC,PS
Table 2-3. Itanium® 2 Processor Power Supply Specificat ions
Symbol Parameter Minimum Typ Maximum Unit Notes
V
CC,PS
I
CC,PS
PS
slew_rate
PS
TT
NOTES:
1. The power pod DC set point accuracy is ±1.5%. Included for reference only, under worst case switching activit y, the power pod
tolerance is ±7%.
2. The V
3. The maximum current (I
defined to be based on worst-case V
VCC from the Power Supply VID –1.5% VID VID +1.5% V
Current Required from Power Supply 100 A
Power Supply Slew Rate at the
Processor Power Pod Connector
Power Supply Slew Rate for the
Termination Voltage at the Processor
Pins
for the processor is defined by the VID bits specified in Table 2-23.
CC,PS
) specification is intended for system power supply design. The maximum current values are
CC,PS
, temperature and application mix.
CC,PS
1, 2
3
100 A/µs
0.05 A/ns
2.4 Signal Specifications
This section describes the DC specifications of the system bus signals. The processor signal’s DC
specifications are defined at the Itanium 2 processor pins. Table 2-4 through Table 2-9 describe the
DC specifications for the AGTL+, PWRGOOD, HSTL clock, TAP port, system management, and
LVTTL signals. Please refer to the ITP700 Debug Port Design Guide for the TAP connection
signals DC specifications at the debug port.
Table 2-4. AGTL+ Signals DC Specifications (Sheet 1 of 2)
Symbol Parameter
V
IL
V
IH
V
IL
V
IH
Input Low Voltage All 0.625 V
Input High Voltage All 0.875 V
Input Low Voltage
(1.6x GHz, I.5 GHz/4 MB
®
Itanium
2 Processors)
Input High Voltage
(1.6x GHz, I.5 GHz/4 MB
Itanium 2 Processors)
V
OL
V
OH
I
OL
I
OL
Output Low Voltage All 0.3 0.4 V
Output High Voltage All V
Output Low Current @ 0.3V All 34 mA
Output Low Current @ 0.3V All 17 mA
Core
Frequency
All 0.65 V
All 0.85 V
Minimum Typ Maximum Unit Notes
1
1
1
1
2
,
CTERM
minimum
V
CTERMVCTERM
maximum
,
V
3
4
18 Datasheet
Table 2-4. AGTL+ Signals DC Specifications (Sheet 2 of 2)
Electrical Specifications
Symbol Parameter
I
L
C
AGTL+
Leakage Current All ±100 µA
AGTL+ Pad Capacitance 900 MHz 3 pF
Core
Frequency
1.0 GHz 3 pF
1.3 GHz 1.5 pF
1.4 GHz 1.5 pF
1.5 GHz 1.5 pF
1.6 GHz 1.5 pF
1.66 GHz 1.5 pF
NOTES:
1. The typical transition point between VIL and VIH assuming 125 mV V
±100 mV respectively, for a system bus agent using on-board termination. V
V
REF
mV respectively, f or a system bus agent using on-die termination.
2. Parameter measured into a 22.5 ohm resistor to 1.2V. Minimum V
3. Calculated using off-die termination through two 45 ohm ±1% resistors in parallel.
4. Calculated using on-die termination to a 45 ±15% resistor measured at V
5. At 1.2V ±1.5%. V
6. Total of I/O buffer with ESD structure and processor parasitics if applicable. Capacitance values guaran teed by design for all
AGTL+ buffers.
, minimum ≤ Vpin ≤ V
CTERM
CTERM
, maximum.
Table 2-5. Power Good Signal DC Specifications
Symbol Parameter Minimum Maximum Unit Notes
V
IL
V
IH
Input Low Voltage 0.440 V
Input High Voltage 0.875 V
Minimum Typ Maximum Unit Notes
5
6
6
6
6
6
6
6
uncertainty for ODT. V
REF
and IOL are guaranteed by design/characterization.
OL
.
OL
REF_high
and V
REF_high
REF_low
and V
REF_low
levels are V
levels are
±125
REF
Table 2-6. System Bus Clock Differential HSTL DC Specifications
Symbol Parameter Minimum Maximum Unit Notes
V
IH
V
IL
V
X
C
CLK
Input High Voltage 0.78 1.3 V
Input Low Voltage –0.3 0.5 V
Input Crossover Voltage 0.55 0.85 V
Input (Pad) Capacitance 1.75 pF
Table 2-7. TAP Connection DC Specifications
Symbol Parameter Minimum Maximum Unit Notes
V
IL
V
IH
V
OL
V
OH
I
OL
I
IC
NOTES:
1. There is a 100 mV hysteresis on TCK.
2. VIH, MAX = 1.5V + 5%, VOH, MAX = 1.2V +5%.
3. There is no internal pull-up. An external pull-up is always assumed. Max voltage tolerated at TDO is 1.5V.
4. Per input pin.
Input Low Voltage –0.3 0.5 V
Input High Voltage 1.1 1.57 V
Output Low Voltage 0.3 V
Output High Voltage 1.2 V
Output Low Current 20 mA
Input Current 690 uA
1
1, 2
2, 3
4
Datasheet 19
Electrical Specifications
Table 2-8. SMBus DC Specifications
Symbol Parameter Minimum Typ Maximum Unit Notes
3.3V V
V
IL
V
IH
V
OL
I
3.3V
I
OL
I
OL2
I
LI
I
LO
NOTES:
1. The value specified for I
2. The value specified for I
for the System Management
CC
Components
Input Low Voltage –0.3 0.3*3.3V V
Input High Voltage 2.31 3.47 V Max =
Output Low Voltage 0.4 V
3.3V Supply Current 5.0 30.0 mA
Output Low Current 3 mA
Output Low Current 6 mA
Input Leakage Current 10 µA
Output Leakage Current 10 µA
3.14 3.3 3.47 V 3.3V ±5%
applies to all signals except for THRMALERT#.
OL
applies only to THRMALERT# which is an open drain signal.
OL2
3.3 +5%
Min +
0.7*3.3V
1
2
Table 2-9. LVTTL Signal DC Specifications
Symbol Parameter Minimum Maximum Unit Notes
V
IL
V
IH
V
OL
V
OH
Input Low Voltage 0.8 V
Input High Voltage 2.0 3.63 V
Output Low Voltage 0.4 V
Output High Voltage 2.4 V
Table 2-10 through Table 2-11 list the AC specifications for the Itanium 2 processor’s clock and
SMBus (timing diagrams begin with Figure 2-1). The Itanium 2 processor uses a differential HSTL
clocking scheme with a frequency of 200, 266 or 333 MHz. The SMBus is a subset of the I2C*
interface which supports operation of up to 100 kHz.
Table 2-10. System Bus Clock Differential HSTL AC Specifications (Sheet 1 of 2)
System
Symbol Parameter
BCLKp Period 200 5.0 ns Figure 2-1
T
period
T
skew
f
BCLK
T
jitter
T
high
T
low
T
period
T
skew
f
BCLK
T
jitter
T
high
System Clock Skew 200 100 ps
BCLKp Frequency 200 200 200 MHz Figure 2-1
BCLKp Input Jitter 200 100 ps Figure 2-1
BCLKp High Time 200 2.25 2.5 2.75 ns Figure 2-1
BCLKp Low Time 200 2.25 2.5 2.75 ns Figure 2-1
BCLKp Period 266 3.75 ns Figure 2-1
System Clock Skew 266 60 ps
BCLKp Frequency 266 266 266 MHz Figure 2-1
BCLKp Input Jitter 266 50 ps Figure 2-1
BCLKp High Time 266 1.69 1.88 2.06 ns Figure 2-1
Bus
Clock
(MHz)
Minimum Typ Maximum Unit Figure Notes
1
2
3
4
4
5
2
3
4
20 Datasheet
Electrical Specifications
Table 2-10. System Bus Clock Differential HSTL AC Specifications (Sheet 2 of 2)
System
Symbol Parameter
T
low
T
period
T
skew
f
BCLK
T
jitter
T
high
T
low
T
rise
T
fall
V
PP
BCLKp Low Time 266 1.69 1.88 2.06 ns Figure 2-1
BCLKp Period 333 3.0 ns Figure 2-1
System Clock Skew 333 60 ps
BCLKp Frequency 333 333 333 MHz Figure 2-1
BCLKp Input Jitter 333 50 ps Figure 2-1
BCLKp High Time 333 1.35 1.5 1.65 ns Figure 2-1
BCLKp Low Time 333 1.35 1.5 1.65 ns Figure 2-1
BCLKp Rise Time All 333 500 667 ps Figure 2-1 20–80%
BCLKp Fall Time All 333 500 667 ps Figure 2-1 20–80%
Minimum Input Swing All 600 mV Figure 2-1
NOTES:
1. The system clock skew is ±100 ps.
2. Measured on cross point of rising edge of BCLKp and falling edge of BCLKn. Long term jitter is defined as peak-to-peak variation measured by
accumulating a large number of clock cycles and recording peak-to-peak jitter.
3. Cycle-to-cycle jitter is defined as peak-to-peak variation measured over 10000 cycles peak-to-peak jitter.
4. Measured on cross point of rising edge of BCLKp and falling edge of BCLKn.
5. The system clock skew is ±60 ps.
is defined as the minimum input differential voltage which will cause no increase in the clock receiver timing.
6. V
PPmin
Bus
Clock
(MHz)
Minimum Typ Maximum Unit Figure Notes
4
3
4
4
6
Table 2-11. SMBus AC Specifications
Symbol Parameter Minimum Maximum Unit Notes
f
SMSC
T
SMSC
t
high
t
low
t
rise
t
fall
t
VALID
t
SU
t
HLD
t
FREE
NOTES:
1. Please refer to Figure 2-2 for the Standard Microsystems Corporation (SMSC)* clock waveform.
2. Bus Free Time is the minimum time allowed between request cycles.
SMSC Clock Frequency 100 kHz
SMSC Clock Period 10 µs
SMSC Clock High Time 4.0 µs
SMSC Clock Low Time 4.7 µs
SMSC Clock Rise Time 1.0 µs
SMSC Clock Fall Time 0.3 µs
SMBus Output Valid Delay 1.0 µs
SMBus Input Setup Time 250 ns
SMBus Input Hold Time 0 ns
Bus Free Time 4.7 µs
1
1
1
1
2
Datasheet 21
Electrical Specifications
Figure 2-1. Generic Clock Waveform
T
rise
V
80%
pp
20%
T
Rise Time
=
rise
T
Fall Time
=
fall
T
High Time
=
high
T
Low Time
=
low
Figure 2-2. SMSC Clock Waveform
T
rise
75% V
SMSC
25% V
cc
cc
T
high
T
T
T
V
high
T
period
period
jitter
pp
fall
T
low
T
fall
BCLKN
BCLKP
=
=T
Period
Long Term Peak-to-Peak Jitter
=
Peak-to-Peak Swing
=
90% V
cc
T
low
T
jitter
000615
V (3.3V)
cc
T
T
rise
fall
=
Rise Time
Fall Time
=
T
T
high
low
=
High Time
Low Time
=
2.4.1 Maximum Ratings
Table 2-12 contains the Itanium 2 processor stress ratings. Functional operation at the absolute
maximum and minimum is neither implied nor guaranteed. The processor should not receive a
clock while subjected to these conditions. Functional operating conditions are given in the DC
tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore,
although the processor contains protective circuitry to resist damage from static electric discharge,
one should always take precautions to avoid static voltages or electric fields.
Table 2-12. Itanium® 2 Processor Absolute Maximum Ratings (Sheet 1 of 2)
Symbol Parameter Minimum Maximum Unit Notes
T
storage
T
shipping
V
CC,Processor
3.3V Any 3.3V Supply Voltage with Respect to
Processor Storage Temperature –10 45 °C
Processor Shipping Temperature –45 75 °C
Any V
to GND
CC,Processor
Voltage with Respect
–0.1 2.1 V
–0.3 5.5 V
GND
000618
1
2
3
4
22 Datasheet
Electrical Specifications
Table 2-12. Itanium® 2 Processor Absolute Maximum Ratings (Sheet 2 of 2)
Symbol Parameter Minimum Maximum Unit Notes
V
in, SMBus
V
in, AGTL+
V
CTERM
V
in,TAP
NOTES:
1. Storage temperature is temperature in which the processor can be stored for up to one year.
2. Shipping temperature is temperature in which the processor can be shipped for up to 24 hours.
3. See Table 2-4 through Table 2-9 inclusive for operating voltages.
4. Parameters are from third party vendor specifications.
5. Maximum instantaneous voltage at receiver buffer input.
6. Specification includes V
respect to GND.
SMBus Buffer DC Input Voltage with
Respect to GND
AGTL+ Buffer DC Input Voltage with
Respect to GND
Any V
GND
TAP Buffer DC Input Voltage with
Respect to GND.
in,AGTL+
Voltage with Respect to
CTERM
and V
in,AGTL+ ASYNCHRONOUS
–0.1 6.0 V
–0.1 1.9 V
–0.1 1.9 V
–0.1 2.1 V
(AGTL+ asynchronous buffer DC input voltage with
2.5 System Bus Signal Quality Specifications and Measurement Guidelines
4
5, 6
3
5
Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal
V
limit transitions beyond V
voltage (or below GND), as shown in Table 2-3. The overshoot/undershoot specifications
CTERM
or GND due to the fast signal edge rates. The processor can be
CTERM
permanently damaged by repeated overshoot or undershoot events on any input, output, or I/O
buffer if the charge is large enough (that is, if the overshoot/undershoot is great enough).
Determining the impact of an overshoot/undershoot condition requires knowledge of the
magnitude, the pulse duration, and the activity factor (AF).
2.5.1 Overshoot/Undershoot Magnitude
Magnitude describes the maximum potential difference between a signal and its voltage reference
level. For the Itanium 2 processor, both are referenced to GND as shown in Figure 2-3. It is
important to note that overshoot and undershoot conditions are separate and their impact must be
determined independently. Overshoot/undershoot magnitude levels must observe the absolute
maximum specifications listed in Table 2-13 through Table 2-21. These specifications must not be
violated at any time regardless of bus activity or system state. Within these specifications are
threshold levels that define different allowed pulse duration. Provided that the magnitude of the
overshoot/undershoot is within the absolute maximum specifications (1.8 V for overshoot and
–0.60 V for undershoot), the pulse magnitude, duration and activity factor must all be used to
determine if the overshoot/undershoot pulse is within specifications.
Datasheet 23
Electrical Specifications
p
Figure 2-3. System Bus Signal Waveform Exhibiting Overshoot/Undershoot
Maximum
Absolute
Overshoot
V
MAX
V
CTERM
V
REF
V
OL
GND
V
MIN
Maximum
Absolute
Undershoot
2.5.2 Overshoot/Undershoot Pulse Duration
Pulse duration describes the total time an overshoot/undershoot event exceeds the
overshoot/undershoot reference voltage (V
oscillations above the reference voltage. Multiple overshoot/undershoot pulses within a single
overshoot/undershoot event may need to be measured to determine the total pulse duration.
/GND). The total time could encompass several
CTERM
Time-dependent
Overshoot
Time-de
Undershoot
endent
000588
Note: Oscillations below the reference voltage cannot be subtracted from the total overshoot/undershoot
pulse duration.
2.5.3 Activity Factor
Activity factor (AF) describes the frequency of overshoot (or undershoot) occurrence relative to a
clock. Since the highest frequency of assertion of any common clock signal is every other clock, an
AF = 1 indicates that the specific overshoot (or undershoot) waveform occurs every other clock
cycle. Thus, an AF = 0.01 indicates that the specific overshoot (or undershoot) waveform occurs
one time in every 200 clock cycles. For source synchronous signals (data, and associated strobes),
the activity factor is in reference to the strobe edge. The highest frequency of assertion of any
source synchronous signal is every active edge of its associated strobe. So, an AF = 1 indicates that
the specific overshoot (or undershoot) waveform occurs every other strobe cycle. The
specifications provided in Table 2-14 through Table 2-21 show the maximum pulse duration
allowed for a given overshoot/undershoot magnitude at a specific activity factor. Each table entry is
independent of all others, meaning that the pulse duration reflects the existence of
overshoot/undershoot events of that magnitude ONLY. A platform with an overshoot/undershoot
that just meets the pulse duration for a specific magnitude where the AF <1, means that there can
be no other overshoot/undershoot events, even of lesser magnitude (if AF = 1, then the event
occurs at all times and no other events can occur).
24 Datasheet
Electrical Specifications
Note: AF for the common clock AGTL+ signals is referenced to BCLKn, and BCLKp frequency.
The wired-OR Signals (BINIT#, HIT#, HITM#, BNR#, TND#, BERR#) are common clock
AGTL+ signals.
Note: AF for source synchronous (2x) signals is referenced to STBP#[7:0], and STBN#[7:0].
2.5.4 Reading Overshoot/Undershoot Specification Tables
The overshoot/undershoot specification for the processor is not a simple single value. Instead,
many factors are needed in order to correctly interpret the overshoot/undershoot specification. In
addition to the magnitude of the overshoot, the following parameters must also be known: the
width of the overshoot and the AF. To determine the allowed overshoot for a particular overshoot
event, the following must be done:
1. Determine the signal group that the particular signal falls into. For AGTL+ signals operating
in the 2x source synchronous domain, use Table 2-14 through Table 2-17. If the signal is a
wired-OR AGTL+ signal operating in the common clock domain, use Table 2-18 through
Table 2-21.
2. Determine the magnitude of the overshoot, or the undershoot (relative to GND).
3. Determine the activity factor (how often does this overshoot occur?).
4. Next, from the appropriate specification table, determine the maximum pulse duration (in
nanoseconds) allowed. The pulse duration shown in the table are referring to the period where
either the maximum overshoot (for high phase) and undershoot (for low phase) occurred.
5. Compare the specified maximum pulse duration to the signal being measured. If the pulse
duration measured is less than the pulse duration shown in the table, then the signal meets the
specifications.
6. Undershoot events must be analyzed separat e ly from oversho ot events as they are
mutually exclusive.
NOTES: The following notes also apply when reading the Overshoot/Undershoot tables.
1. Absolute Maximum Overshoot magnitude must never be exceeded.
2. Absolute Maximum Overshoot magnitude is measured referenced to GND. Pulse Duration of overshoot is
measured relative to VCTERM.
3. Absolute Maximum Undershoot magnitude and Pulse Duration of undershoot is measured relative to
VCTERM.
4. Ringback below VCTERM cannot be subtracted from overshoots/undershoots.
5. Lesser undershoot does not allocate overshoot with longer duration or greater magnitude.
6. OEM’s are strongly encouraged to follow Intel layout guidelines.
7. All values specified by design characterization.
2.5.5 Determining if a System Meets the Overshoot/Undershoot Specifications
The overshoot/undershoot specifications listed in Table 2-13 through Table 2-21 specify the
allowable overshoot/undershoot for a single overshoot/undershoot event. However, most systems
will have multiple overshoot and/or undershoot events that each have their own set of parameters
(duration, AF and magnitude). While each overshoot on its own may meet the overshoot
specification, the total impact of all overshoot events may cause the system to fail. A guideline to
ensure a system passes the overshoot and undershoot specifications is shown below:
1. Ensure no signal ever exceeds V
2. If only one overshoot/undershoot event magnitude occurs, ensure it meets the specifications
listed in Table 2-13 through Table 2-21.
Datasheet 25
CTERM
or GND.
Electrical Specifications
3. If multiple overshoots and/or multiple undershoots occur, measure the worst-case pulse
duration for each magnitude and compare the results against the AF = 1 specifications. If all of
these worst-case overshoot or undershoot events meet the specifications (measured time <
specifications) in the table (where AF = 1), then the system passes.
Table 2-13. Source Synchronous AGTL+ Signal Group and Wired-OR Signal Group Absolute
Overshoot/Undershoot Tolerance
Parameter Description Specification Units
V
CTERM
V
MAX
V
MIN
Overshoot Time dependent overshoot amount above V
Undershoot Time dependent undershoot amount below GND.
NOTES:
1. These parameters cannot be specified in absolute terms.
NOTES: The following notes apply to Table 2-14 through Table 2-21:
1. Absolute Maximum Overshoot magnitude of 1.8V must never be exceeded.
2. Absolute Maximum Overshoot is measured referenced to GND. Pulse duration of overshoot is measured
relative to V
3. Absolute Maximum Undershoot and Pulse Duration of undershoot is measured relative to V
4. Ringback below V
5. Lesser undershoot does not allocate overshoot with longer duration or greater magnitude.
6. All values specified by design characterization.
I/O power supply voltage (nominal). 1.20 V
Maximum absolute voltage for system bus signals at the input
of the receiver buffers.
Minimum absolute voltage for system bus signals at the input of
the receiver buffers.
CTERM .
.
CTERM
cannot be subtracted from overshoots/undershoots.
CTERM
1.80 V
–0.60 V
1
1
CTERM
.
Table 2-14. Itanium® 2 Processors (900 MHz, 1.0 GHz, 1.3GHz, 1.4GHz, 1.5GHz/6MB) Source
Synchronous AGTL+ Signal Group Time Dependent Overshoot/Undershoot
Tolerance for 400 MHz System Bus
Absolute
Maximum (V)
Overshoot
1.75 –0.55 0.0206 0.0276 0.0413 0.0827 0.2067 0.4139 2.0680
1.65 –0.45 0.1851 0.2470 0.3702 0.7392 1.8500 2.5 2.5
1.55 –0.35 1.6100 2.1451 2.5 2.5 2.5 2.5 2.5
1.45 –0.25 2.5 2.5 2.5 2.5 2.5 2.5 2.5
NOTES:
1. Activity factor = 1 means signal toggles every 5 ns.
Under-
shoot
1.8 –0.6 0.0083 0.0089 0.0137 0.02750 0.0688 0.1376 0.6863
1.7 –0.5 0.0621 0.0828 0.1239 0.2480 0.6207 1.2420 2.5
1.6 –0.4 0.5477 0.7296 1.0972 2.1915 2.5 2.5 2.5
1.5 –0.3 2.5 2.5 2.5 2.5 2.5 2.5 2.5
AF = 1
1
AF = 0.75 AF = 0.5 AF = 0.25 AF = 0.1 AF = 0.05 AF = 0.01
Pulse Duration (ns)
26 Datasheet
Electrical Specifications
Table 2-15. Itanium® 2 Processors (1.5 GHz/4 MB, 1.6 GHz) Source Synchronous AGTL+
Signal Group Time-Dependent Overshoot/Undershoot Tolerance for 400 MHz
System Bus
Absolute
Maximum (V)
Overshoot
1.75 –0.55 0.0216 0.0287 0.0430 0.0861 0.2157 0.4313 2.1552
1.65 –0.45 0.1925 0.2572 0.3858 0.7700 1.9264 2.5 2.5
1.55 –0.35 1.1.676 2.2351 2.5 2.5 2.5 2.5 2.5
1.45 –0.25 2.5 2.5 2.5 2.5 2.5 2.5 2.5
NOTES:
1. Activity Factor = 1 means signal toggles every 5 ns.
Under-
shoot
1.8 –0.6 0.0083 0.0090 0.0143 0.0287 0.0717 0.1431 0.7169
1.7 –0.5 0.0646 0.0861 0.1291 0.2584 0.6457 1.2914 2.5
1.6 –0.4 0.5713 0.7625 1.1408 2.2831 2.5 2.5 2.5
1.5 –0.3 2.5 2.5 2.5 2.5 2.5 2.5 2.5
AF = 1
1
AF = 0.75 AF = 0.5 AF = 0.25 AF = 0.1 AF = 0.05 AF = 0.01
Pulse Duration (ns)
Table 2-16. Itanium® 2 (9 MB) Processors Source Synchronous AGTL+ Signal Group Time-
Dependent Overshoot/Undershoot Tolerance for 533 MHz System Bus
Absolute
Maximum (V)
Overshoot
1.75 –0.55 0.0161 0.0215 0.0323 0.0647 0.1619 0.3230 1.6161
1.65 –0.45 0.1444 0.1924 0.2894 0.5776 1.4465 1.875 1.875
1.55 –0.35 1.2573 1.6763 1.875 1.875 1.875 1.875 1.875
1.45 –0.25 1.875 1.875 1.875 1.875 1.875 1.875 1.875
NOTES:
1. Activity Factor = 1 means signal toggles every 3.75 ns.
Under-
shoot
1.8 –0.6 0.0032 0.0035 0.0107 0.0214 0.0538 0.1074 0.5371
1.7 –0.5 0.0494 0.0646 0.0969 0.1937 0.4853 0.9692 1.875
1.6 –0.4 0.4279 0.5705 0.8561 1.7130 1.875 1.875 1.875
1.5 –0.3 1.875 1.875 1.875 1.875 1.875 1.875 1.875
AF = 1
1
AF = 0.75 AF = 0.5 AF = 0.25 AF = 0.1 AF = 0.05 AF = 0.01
Pulse Duration (ns)
Datasheet 27
Electrical Specifications
Table 2-17. Itanium
®
2 Processors (1.66 GHz) Source Synchronous AGTL+ Signal Group
Time-Dependent Overshoot/Undershoot Tolerance for 667 MHz System Bus
Absolute
Maximum (V)
Overshoot
1.75 –0.55 0.0129 0.0172 0.0258 0.0517 0.1292 0.2585 1.2953
1.65 –0.45 0.1158 0.1544 0.2311 0.4629 1.1564 1.5 1.5
1.55 –0.35 1.0065 1.3411 1.5 1.5 1.5 1.5 1.5
1.45 –0.25 1.5 1.5 1.5 1.5 1.5 1.5 1.5
NOTES:
1. Activity Factor = 1 means signal toggles every 3 ns.
Under-
shoot
1.8 –0.6 0.0050 0.0054 0.0086 0.0172 0.0423 0.0858 0.4297
1.7 –0.5 0.0387 0.0516 0.0775 0.1553 0.3882 0.7748 1.5
1.6 –0.4 0.3429 0.4562 0.6845 1.3728 1.5 1.5 1.5
1.5 –0.3 1.5 1.5 1.5 1.5 1.5 1.5 1.5
AF = 1
1
2.5.6 Wired-OR Signals
System bus signals must meet certain overshoot and undershoot requirements. The maximum
absolute overshoot voltage is 1.8V and the minimum absolute undershoot voltage is
–0.6V. The system bus wired-OR signals (BINIT#, HIT#, HITM#, BNR#, TND#, BERR#) hav e
the same absolute overshoot and undershoot specification as the Source Synchronous AGTL+
Signals, but they have different time dependent overshoot/undershoot requirements. Please refer to
Table 2-18 through Table 2-21 for the wired-O R time dependant overshoot/undershoot limits.
Pulse Duration (ns)
AF = 0.75 AF = 0.5 AF = 0.25 AF = 0.1 AF = 0.05 AF = 0.01
Table 2-18. Itanium® 2 Processors (900 MHz, 1.0 GHz, 1.3 GHz, 1.4 GHz, 1.5 GHz/6 MB) Wired-
OR Signal Group (BINIT#, HIT#, HITM#, BNR#, TND#, BERR#)
1
Overshoot/Undershoot Tolerance for 400 MHz System Bus
Absolute
Maximum (V)
Overshoot
1.75 –0.55 0.1485 0.1977 0.2966 0.5933 1.4834 2.9659 5
1.65 –0.45 1.3290 1.7670 2.6529 5 5 5 5
1.55–0.355555555
NOTES:
1. Wired-OR signals operate at 200 MHz.
2. Activity factor = 1 means signal toggles every 10ns.
Under-
shoot
1.8 –0.6 0.0493 0.06576 0.0985 0.1968 0.4923 0.9852 4.9228
1.7 –0.5 0.4444 0.5932 0.8898 1.7798 4.4448 5 5
1.6 –0.4 3.9270 555555
1.5–0.35555555
AF = 1
2
AF = 0.75 AF = 0.5 AF = 0.25 AF = 0.1 AF = 0.05 AF = 0.01
Pulse Duration (ns)
28 Datasheet
Electrical Specifications
Table 2-19. Itanium® 2 Processors (1.5 GHz/4 MB, 1.6 GHz) Wired-OR Signal Group (BINIT#,
HIT#, HITM#, BNR#, TND#, BERR#) Overshoot/Undershoot Tolerance for 400 MHz
System Bus
Absolute
Maximum (V)
Overshoot
1.75 –0.55 0.1547 0.2059 0.3088 0.6192 1.5458 3.0902 5
1.65 –0.45 1.3836 1.8410 2.7641 5555
1.55–0.355555555
NOTES:
1. Activity Factor = 1 means signal toggles every 10 ns.
Under-
shoot
1.8 –0.6 0.0513 0.0685 0.1026 0.2054 0.5129 1.0258 5
1.7 –0.5 0.4640 0.6191 0.9265 1.8536 4.6313 5 5
1.6–0.44.0947555555
1.5–0.35555555
AF = 1
1
AF = 0.75 AF = 0.5 AF = 0.25 AF = 0.1 AF = 0.05 AF = 0.01
Pulse Duration (ns)
Table 2-20. Itanium® 2 (9 MB) Processors Wired-OR Signal Group (BINIT#, HIT#, HITM #, BNR#,
TND#, BERR#) Overshoot/Undershoot Tolerance for 533 MHz System Bus
Absolute
Maximum (V)
Overshoot
1.75 –0.55 0.1161 0.1548 0.2317 0.4641 1.1593 2.3177 3.75
1.65 –0.45 1.0365 1.3801 2.0731 3.75 3.75 3.75 3.75
1.55 -0.35 3.75 3.75 3.75 3.75 3.75 3.75 3.75
NOTES:
1. Activity Factor = 1 means signal toggles every 7.5 ns.
Under-
shoot
1.8 –0.6 0.0385 0.0513 0.0770 0.1541 0.3853 0.7690 3.75
1.7 –0.5 0.3473 0.4643 0.6945 1.3895 3.4738 3.75 3.75
1.6 –0.4 3.0710 3.75 3.75 3.75 3.75 3.75 3.75
1.5 –0.3 3.75 3.75 3.75 3.75 3.75 3.75 3.75
AF = 1
1
AF = 0.75 AF = 0.5 AF = 0.25 AF = 0.1 AF = 0.05 AF = 0.01
Pulse Duration (ns)
Table 2-21. Itanium® 2 (1.66 GHz) Processors Wired-OR Signal Group (BINIT#, HIT#, HITM#,
BNR#, TND#, BERR#) Overshoot/Undershoot Tolerance for 667 MHz System Bus
(Sheet 1 of 2)
Absolute
Maximum (V)
Overshoot
1.75 –0.55 0.0928 0.1237 0.1855 0.3706 0.9291 1.8546 3
1.65 –0.45 0.8288 1.1056 1.6585 3333
Under-
shoot
1.8 –0.6 0.0308 0.0411 0.0615 0.1231 0.3079 0.6167 3
1.7 –0.5 0.2780 0.3714 0.5568 1.1136 2.7783 3 3
AF = 1
1
AF = 0.75 AF = 0.5 AF = 0.25 AF = 0.1 AF = 0.05 AF = 0.01
Datasheet 29
Pulse Duration (ns)
Electrical Specifications
Table 2-21. Itanium® 2 (1.66 GHz) Processors Wired-OR Signal Group (BINIT#, HIT#, HITM#,
BNR#, TND#, BERR#) Overshoot/Undershoot Tolerance for 667 MHz System Bus
(Sheet 2 of 2)
Absolute
Maximum (V)
1.6 –0.4 2.4567 333333
1.55–0.353333333
1.5–0.33333333
NOTES:
1. Activity Factor = 1 means signal toggles every 6 ns.
Pulse Duration (ns)
2.6 Power Pod Connector Signals
Power delivery for the Itanium 2 processor is from a DC-DC converter called the “power pod”. The
power pod consists of a DC-DC converter and a semi-flexible connector which delivers the voltage
to the processor.
Table 2-22 lists all of the signals which are part of the It anium 2 processor power pod connector.
Table 2-22. Itanium® 2 Processor Power Pod Connector Signals
Group Name Signals
Power Pod Connector OUTEN, CPUPRES#, PPODGD#, VCC, VCCMON, GND, VSSMON, VID[4:0]
Warning: If the power supply canno t su pply the voltages requested by the components in the Itanium 2
processor, then it must disable itself.
Figure 2-4 shows the top and bottom views of the power tab connector. The processor ground,
V
SS,Processor
, connection is provided on the power tab connector as well.
Figure 2-4. Itanium® 2 Processor Power Tab Physical Layout
Reserved
OUTEN
VSSMON
VCCMON
PPODGD#
GND / VSS
CPUPRES#
Processor
Reserved
VID[4]
VID[3]
VID[2]
VID[1]
VID[0]
To Power Pod
Top View of Processor Bottom View of Processor
To Power Pod
Processor
VCC
Pins
000983a
30 Datasheet
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