Intel iSBC 86/12 Hardware Reference Manual

Page 1
rr
iSBC 86/12
SINGLE BOARD COMPUTER
HARDWARE
REFERENCE MANUAL
Manual Order Number: 9800645A
I
Intel Corporation, 3065 Bowers
Copyright © 197E:
Av.~nue,
Intel
Corporation
Santa Clara, California 95051
.
L
Page 2
The infonnation in this manual kind with regard to this manual, including, but not limited to, the implied warranties
is
subject to change without notice. Intel Corporation makes
no
warranty
of
merchantability and
of
any
fitness for a particular purpose. Intel Corporation assumes no responsibility for any errors that may appear in this manual. Intel Corporation makes no commitment to update nor to keep current the infonnation contained in this manual.
No
part
of
of
this manual may be copied or reproduced
Intel Corporation. The following are trademarks
in
any fonn
or
of
by any means without the prior written consent
Intel Corporation and may be used only
to
describe
Intel products:
ICE·
30
ICE·gO
INSITE INTEL INTEU.EC
iSBC
LIBRARY
MANAGER MCS MEGACHASSIS MICROMAP
MULTIBUS PROMPT UPI RMX
ii
Printed in
U.S,A./B66/0778(TL
7.SK
Page 3
PREFACE
This manual provides general information, installation, programming information, principles of operation, and service information for the Intel iSBC 86/12 Single Board
Computer. Additional information
is
available in the following documents:
• 8086 Assembly Language Reference
• Intel MCS-85 User's Manual, Order No. 98-366
• Intel 8255A Programmable Peripheral 1 nterface , Application Note AP-15
• Intel 8251 Universal Synchronous/Asynchronous Receiver/Transmitter, Application
AP-16
Note
• Intel MULTIBUS Interfacing, Application Note AP-28
• Intel 8259 Programmable Interrupt
Ma~ual,
Cm~troller,
Order No. 9800640
Application Note AP-31
iii
Page 4
CHAPTER 1 GENERAL INFORMATION
Introduction Description System Software Development Equipment Equipment Required Specifications
....................................
.....................................
.....................
Supplied . . . . . . . . . . . . . . . . . . . . . . . . . . . .
..............................
...................................
CHAPTER 2 PREPARATION
Introduction
Unpacking and Inspection
Installation Considerations . . . . . . . . . . . . . . . . . . . . . . .
User-Furnished Components Power Requirement Cooling Requirement Physical Dimensions
Component Installation. . . . . . . . . . . . . . . . . . . . . . . . . .
ROM/EPROM Chips Line Drivers and
Jumper/Switch Configuration
RAM Addresses (Multibus Access) Priority Interrupts
Serial I/O Port Configuration. . . . . . . . . . . . . . . . . . .
Parallel I/O Port Configuration
Multibus Configuration
Signal Characteristics Serial Priority Resolution
Parallel Priority Resolution Power Fail/Memory Protect Configuration Parallel I/O Cabling Serial I/O Cabling Board Installation
.....................................
FOR USE
.........................
.....................
............................
...........................
............................
...........................
I/O Terminators
...
. . . . . . . . . . . . . . . . . . . . . . . . .
...........................
..........................
.......................
.............................
...............................
...............................
.................
.......................
................
...................
.....................
...........
CHAPTER 3
PROGRAMMING INFORMATION
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Failsafe Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Addressing
CPU Access
Multibus Access I/O Addressing System Initialization 8251A
USART Programming
Mode Instruction Fonnat Sync CharaCters Command Instruction Fonnat
........................................
Reset
Addressing
Initialization Operation
.....................................
Data
Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Read
..............................
..................................
................................
..................................
..............................
......................
........................
...............................
....................
....................................
..................................
.................................
PAGE
,
1-1 I-I 1-3
..
1-3 1-3 1-3
2-1 2-1
..
2-1 2-1 2-1 2-1 2-1
..
2-1 2-1
2-4
2-4
2-4
..
2-6
..
2-9 2-9
2-9 2-13 2-13
2-13 2-13 2-23 2-23 2-23
..
3-1
..
3-1 3-1 3-1
3-2 3-3 3-3
3-4
3-4
3-5
3-5 .
3-5
3-5
3-6
3-7
..
3-7 3-7
CONTENTS]
8253 PIT Programming
Mode Control Word and Count Addressing Initialization
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Counter Read Clock Frequency/Divide Ratio Selection Rate Generator/Interval Interrupt Timer
8255;\
Control Word Fonnat Addressing Iniitialization
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Write
8259A
Interrupt
Nested Mode Fully Nested Mode Automatic Rotating Mode Specific Rotating Mode Special Mask Mode Poll Mode
Status Read
Initialization Command Words
Operation Command Words. . . . . . . . . . . . . . . . . . .
Addressing Initialization
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Interrupts
Non-Maskable Interrupt (NMI) Maskable Interrupt (lNTR)
Master
Slave PIC Byte Identifier
..................................
.................................
ppl
Programming . . . . . . . . . . . . . . . . . . . . . . .
..................................
.................................
Operation
Operation
PIC-Programming
Priority Modes. . . . . . . . . . . . . . . . . . . . . .
.................................
..................................
..................................
.................................
PIC Byte Identifier
CHAPTER 4 PRINCIPLES
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description
Clock Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Central
Processor Unit . . . . . . . . . . . . . . . . . . . . . . . .
Interval Timer Serial I/O Parallel I/O Interrupt Controller
ROM/EPROM Configuration
RAM Configuration
Bus Structure Multibus Interface
.....................................
.................
...........................
...................
..............................
Timer.
.............................
..........................
.............................
............................
.........................
...............................
..........................
.........................
.............................
. . . . . . . . . . . . . .
....................
......................
..................
..................
.....................
....................
....................•
OF OPERATION
............................
.................................
. . . . . . . . . . . . . . . .
.............•...............
.....................
............................
.................................
.............................
.........
PAGE
3-8
3-8 3 -12 3 -12
..
3-1"3 3-13 3-13
..
3 -14 3-14
..
3 -14
3-15 3-15 3-16
..
3 -16 3-16 3-16 3-17
..
3 -17 3-17 3-17 3 -17 3-17
3-18 3-18 3-18
3 -18
..
3 -19
3 -19
3 -19
..
3 -19 3-25
3-25
3-25
3-25
3-25
..
4-1
4-1 .. ..
..
, 4-3
4-1 4-1 4-1 4-1 4-1 4-2 4-2 4-2 4-2
iv
I,
Page 5
CONTENTS (Continued)
Circuit Analysis
Initialization Clock Circuits Central Processor Unit
Basic Timing
Bus Timing Address Bus Data Bus Bus Time Out Internal Control Signals
Dual Port Control Logic
Multibus Access Timing
CPU Access Timing
Multibus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Operation
On-Board I/O Operation System I/O
ROM/EPROM Operation . . . . . . . . . . . . . . . . . . . . . . .
.................................
.................................
.................................
..........................
................................
.................................
..................................
.....................................
...............................
.........................
...........................
........................
............................
..................................
.......................
Operation.
. . . . . . . . . . . . . . . . . . . . . . .
PAGE
"
..
4-11 4-11 4-11
..
4-12
..
4-12
4-3
4-4 4-4
4-4 4-4 4-4 4-6 4-6
4-6
4-8 4-8 4-8 4-8
RA\1 Operation
RA\1 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
RA\1 Chips On-Board Read/Write Operation Bus Read/Write Operation Byte Operation
Interrupt
Operation. NBVlnterrupt B V Interrupt
................................
..................................
.................
......................
.............................
. . . . . . . . . . . . . . . . . . . . . . . .
................................
...............................
" 4-13
.. " 4-14
"
CHAPTER 5 SERVICE INFORMATION
Introduction Replaceable Service Diagrams
Service and Repair Assistance. . . . . . . . . . . . . . . . . .
.....................................
Parts
.............................
............................
APPENDIX A TELETYPEWRITER MODIFICATIONS
PAGE
4-12
4-13 4-13 4-13
4-14
4-14
5-1 5-1 5-1 5-1
v
Page 6
I
TABLES
TABLE
1·1
2·1
2~2
2·3
2·4 2·5 2·6
2·7
2·8
2·9
2·10
2·11
2·12
2·13
2·14
2·15
2·16
2·17
3·}
3·2
3·3
3·4
3·5
TITLE
Specifications
User-Furnished- and Installed Components
Furnished Connector Details
User· Line Driver and Jumper and Switch Selectable Options Priority Interrupt Jumper Matrix Serial
I/O Connector J2 Pin Assignments
Configuration Jumpers Parallel Multibus Connector Multibus Signal Functions
iSBC 86/12 DC Characteristics iSBC 86/12 AC Characteristics
(Master Mode)
iSBC 86/12 AC Characteristics
(Slave Mode) Auxiliary Connector P2 Pin Assignments Auxiliary Signal (Connector P2)
DC Characteristics
Parallel
Pin Assignments Parallel
DC Characteristics Connector J2 Vs RS232C Pin
Correspondence On -Board Memory Addresses
(CPU Access) I/O Address Assignments Typical
Instruction Subroutine Typical USART Data, Character Read
Subroutine Typical
Subroutine
...........................
...........
I/O Terminator Locations . .
............
....... : ..........
I/O Port Configuration Jumpers
PJ.
Pin Assignments
................
............
.......................
........ : ...............
.............
I/O Connector I/O Signal (Connector 11)
USART Mode
............................
USART Data Character Write
............................
11
......................
....................
.......................
.........................
..................
or
Command
..................
.......
'
.......
Vs
.....
....
....
PAGE
....
..
1-4 2-2 2-3
2-4 2-5 2-8
2-9
2-10 2-14 2-15
2-16
2-18
2-18
2-22
2-22 2-23
2-24
2-24
3-2
3-3
3 -7
3-8
3-8
TABLE
3-6
3-7
3-8 3-9
3-10
3-11
3-12
3-13 3-14 3-15 3-16
3-17
3-18
3-19 3-20
3-21
3-22
3-23 3·24
3-25 5-1
5-2
TITLE
Typical PIT Counter Operation Typical PIT Control Word Subroutine Typical PIT Count Value Load
Typical PIT Counter Read Subroutine PIT Count Value
PIT Rate Generator Frequencies and
PIT Time Intervals
Typical PPI Initialization Subroutine. . . . . .
Typical PPI Port Read Subroutine Typical PPI Port Write Subroutine Typical PIC Initialization Subroutine
Typical Master PIC Initialization Subroutine
Typical Slave PIC Initialization Subroutine
PIC Operation Procedures Typical PIC Interrupt Request
Typical PIC In-Service Register
Typical PIC Set Mask Register Subroutine Typical PIC Mask Register Read
Typical PIC End-of-Interrupt Command
Replaceable Parts List
US
ART Status Read Subroutine
Vs
Gate Inputs
Subroutine
Each Baud Rate
Timer Intervals . . . . . . . . . . . . . .
(NBV Mode)
(BV Mode)
(BV Mode)
Register Read Subroutine
Read Subroutine
Subroutine
Subroutine
of
...........................
Vs
Rate Multiplier for
......................
Vs
Timer Counts
.........................
..........................
..........................
...........................
...........................
........................
Manufacturers' Codes
................
......................
...............
..............
......
......
......
..
. . . . .
.......
..........
.........
.....
PAGE
..
..
...
3-9 3·12 3-12
3·12 3-13
3-14
3 -15 3-15 3-16 3-16 3-16
3-21
3-21
3-22 3-22
3-24
3-24 3-24
3-24
3-25
5-1
5·3
vi
Ij'
Page 7
ILLUSTRATIONS
FIGURE
I-I
2-1
2-2
2-3 2-4
2-5
2-6 3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8 3-9 3-10
TITLE
iSBC 86/12 Single Board Computer Dual Port RAM Address Configuration
(Multibus Access)
Simplified Master/Slave
Interconnect Example Bus Exchange Timing (Master Mode) Bus Exchange Timing (Slave Mode) Serial
Priority Resolution Scheme Parallel Priority Resolution Scheme Dual Port RAM Addressing
(Multibus Access)
USART Synchronous
Word Format
USART Synchronous
...............................
Format
US
ART Asynchronous Mode Instruction
Word Format
USART
USART Word Format Typical USART Initialization and
USART Status PIT Mode Control Word Format
PIT Programming Sequence Examples
Asynchronous Mode Transmission
Format
...............................
Command Instruction
I/O Data Sequence
......................
PIC
...................
......................
Mode Instruction
..........................
Mode Transmission
..........................
............................
.....................
Read Format
.........
........
..........
........
...............
...........
......
......
PAGE
I-I
2-7
2-8 2-19 2-20 2-21 2-21
3-2
3-4
3-4
3-5
3-5
3-6
3-6
3-9 3-10 3-11
FIGURE
3-11
3-12 3-13
3-14
3-15 4-1
4-2
4-3 4-4 4-5 4-6
4-7
4-8
5-1 5-2 5-3 5-4
TITLE
PIT Counter Register Latch Control
Word Format PPI Control Word Format PPI Port C Bit Set/Reset Control
Word Format. PIC Initialization Command
Word Formats PIC Operation Control Word Formats iSBC 86/12 Input/Output and Interrupt
Simplified
86/12 ROM/EPROM and Dual Port RAM
iSBC
Simplified Logic Diagram " Internal Bus Structure CPU
Read Timing
CPU
Write Timing
CPU Interrupt Acknowledge
Cycle Timing
Dual Port Control Multibus Access
Timing With
Dual Port Control CPU Access Timing
With Multibus Lockout
iSBC
86/12 86/12 Schematic Diagram
iSBC iSBC 604 Schematic iSBC
614 Schematic Diagram
.....................
...................
...................
Logic
Diagram.
...................
...........
.......................
.........................
CPU Lockout
PaJ1s
Location Diagram
Diagram
...............
. . . . . . . . . 4-15
............
,
...........
..
. . . . . . . . . .
................
.........
............
.............
.............
...
PAGE
.
3-13
.
3-15
.
3-17
3-18
.
.
3-20
4-17
" 4-3
4-5 4-6
4-7
..
4-9
4-10
5-6
5-7 5-29 5-31
vii/viii
Page 8
Page 9
CHAPTER 1
1-1. INTRODUCTION
The iSBC 86/12 Single Board Computer, which member products, printed-circuit assembly. The
16-bit central processing unit (CPU), 32K bytes dynamic RAM, a serial communications interface, three programmable parallel priority interrupt control, Multibus control logic, and bus expansion drivers for interface with other compatible expansion boards. Also included control logic to allow the RAM device to other Multibus masters Provision is made for user installation of
of
Intel's complete line
is
a complete computer system on a single
read only memory.
of
iSBC 80/86 computer
iSBC 86/12 includes a
I/O ports, programmable timers,
is
iSBC 86/12 to act
in
the system.
of
up to 16K bytes
is
Multibus-
dual port
as
a slave
of
1-2. DESCRIPTION
The iSBC 86/12 Single Board Computer (figure 1-1) controlled by an Intel 8086 The
8086 CPU includes four 16-bit general purpose regis-
ters that may also be addressed as eight 8-bit registers. In
16-
B it Microprocessor (CPU) .
is
GENERAL
addition, the CPU contains two 16-bit pointer registers and two 16-bit index registers. Four 16-bit segment ters allow extended addressing to a full megabyte
a
memory. The CPU instruction set supports a wide range of
addressing modes and data transfer operations, signed and unsigned 8-bit and 16-bit arithmetic including hardware mUltiply and divide, and logical and string ations. The CPU architecture features dynamic code relo­cation, reentrant code, and instruction lookahead.
iSBC 86/12 has an internal bus for all on-board
The
memory and (Multibus) for all external memory and Hence, local (on-board) operations do not involve the Multibus, processing when several bus masters (e. and other single board computers) are used in a ter scheme.
Dual port control logic dynamic RAM with the Multibus so that the can function the Multibus. The CPU has priority when accessing on­board RAM. After the CPU completes its read
I/O operations and accesses the system bus
making the Multibus available for true parallel
as
a slave RAM device when not in control
INFORMATION
I/O operations.
g.,
D MA devices
is
included to interface the
regis-
of
oper-
multimas-
iSBC 86/12
of
or
write
(MULTIBUS)
645-1
f4'igure
(AUXIUARy)
1-1. iSBC 86/12 Single Board Computer
1-1
Page 10
General Information
iSBC 86/12
operation, the controlling bus master is allowed RAM and complete its operation. Where both the
and the controlling bus master have the need to write or
read several bytes
their operations ary interleaved. For CPU access, the
on-board RAM addresses are assigned from the bottom up
of
the I-megabyte address space;
The slave RAM address decode logic includes jumpers
and switchers to allow partitioning the on-based RAM into any 128K segment space.
The slave RAM can be configured to allow either 8K, 16K
or
24K, RAM can be configured to allow other bus masters to access a segment another segment strictly for on-board use. The addressing scheme accommodates both 16-bit and 20-bitaddressing.
Four IC sockets are included bytes jumpers allow read only memory to be installed in 2K, 4K,
The lines implemented by means grammable software tion The
peripheral requirements and, in order to take full advan­tage sockets are provided for interchangeable
and terminators. Hence, the flexibility
interface the appropriate combination terminators'to and drive/termination characteristics for each application.
The 24-programmable
are brought with flat, woven,
32K access by another bus master. Thus, the
of
user-installed read only memory. Configuration
or
8K increments.
iSBC 86/12 includes 24 programmable parallel I/O
is
used to configure the I/O lines in any combina-
of
unidirectional input/output and bidirectional ports.
I/O interface may be customized to meet specific
of
the large number
is
or
words to
of
of
the on-board RAM and still reserve
Peripheral Interface (PPI). The system
of
further enhanced by the capability
provide the required sink current, polarity,
I/O ,lines and signal ground lines
out to a 50-pin edge connector
or
round cable.
or
from on-board RAM,
i.e.,
the 1-megabyte system address
to
accommodate up to 16K
of
an Intel 8255A Pro-
possible I/O configurations, IC
of
of
optional line drivers and
to
access
CPU
0OOOO-07FFFH·
I/O line drivers
the parallel I/O
of
selecting
(11)
that mates
In the asynchronous mode the following are program­mable:
a.
Character length,
b.
Baud rate factor (clock divide ratios
c.
Stop bits, and Parity.
d.
In both the synchronous and asychronous modes, the
serial
I/O port features half­fered transmit and receive capability. In addition, error detection circuits can check for parity, overrun, and framing errors. The rates are supplied by a programmable baud rate/time generator. These clocks may optionally be supplied from an external source. The RS232C command lines, serial data lines, and signal ground lines are brought out to a 50-pin edge connector cable.
Three independent, fully programmable 16-bit interval timer/event counters are provided by an Intel 8253 Pro­grammable Interval Timer of
operating in either BCD
counters are available
accurate time intervals under software control. Routing
for the outputs and gate /trigger inputs counters may rammable Interrupt Controller
of
puts associated with the 8255A
the two counters may
from the 8255A
programmable baud rate generator for the serial
In utilizing the
configures, via software, each counter independently to
meet system requirements. Whenever a given time delay
is
or count
select the desired function. The contents
may
simple operations special commands are each counter·can
needed, software commands to the 8253 PIT
be
read at any time during system operation with
USART transmit and receive clock
be
independently routed to the 8259A Prog-
PPI. The third counter is used as a
iSBC 86/12, the systems designer simply
for event counting applications, and
be
read
or
full-duplex, double buf-
(12)
that mates with flat
(PIT). Each counter is capable
or
binary modes; two
to
the systems designer to generate
(PIC). The gate/trigger in-
be
routed to I/O terminators
PPI
or
included ~ that the contents
"on
the
of
1, 16,
or
64),
USART
or
round
of
these
of
two
of
these
as input connections
I/O
port.
of
each counter
fly".
of
The RS232C compatible serial I/O port is controlled arid
interfaced by an Intel 8251A
Syncronous/Asynchrortous
The
USART in most synchronous mission formats
In the synchronous mode the following are programma- . ble:
a. Character length,
Sync character (or chlU1lcters), and
b. c.
Parity.
1-2
is
individually programmable for operation
(including· iBM Bi-Sync).
ReceiverlTransmitter) chip.
or
asynchronous serial data trans-
US
ART (Universal
..
The iSBC 86/
~ruid
non-bus vectored (NBY) interrupts. An on-board
In.tel 8259A Programmable Interrupt Controller (PIC)
handles up to eight NBV interrupts. By using external PIC's slaved. to the on-board PIC (master), the interrupt structure can ityof
PIC, which can
The sensitive
signal condition as an interrupt request. After resolving the interrupt priority, the request to the programmable under software control. The program-
mable interrupt priority modes are:
12
provides vectoring for bus vectored (B V)
be
expanded to handle and resolve the prior-
upto
64 BV sources.
be
programmed to respond to edge-
or
level-sensitive inputs, treats each true input
PIC issues a single interrupt
·CPU. Interrupt priorities are independently
Page 11
iSBC
86/12
a.
Fully Nested Priority. Each interrupt request has a
0
is
fixed priority: input
b.
Auto-Rotating Priority. Each interrupt request has
highest, input 7
is
lowest.
equal priority. Each level, after receiving service, becomes the lowest priority level until the next inter­rupt occurs.
c. Specific priority. Software assigns lowest priority.
Priority
of
all other levels
is
in
numerical sequence
based on lowest priority.
CPU includes a non-maskable interrupt (NMI) and a
The
is
maskable interrupt (lNTR). The NMI interrupt to be used for catastrophic events such that require immediate action
is
interrrupt
driven by the 8259A PIC which, on demand,
provides an 8-bit identifier
C~U
multiplies the 8-bit identifier
of
of
the interrupting source. The
as
the CPU. The INTR
by
four to derive a
intended
power outages
pomter to the service routine for the interrupting device.
18
Interrupt requests may originate from the necessity
of
external hardware. Two jumper-
sources without
selectable interrupt requests can be automatically gener-
by
ated when a byte
~086
tIOn output buffer requests can be automatically generated when a character CPU character
data buffer request can be generated by two
the Programmable Peripheral Interface (PPI)
of
information
CPU (i.e., input buffer is full) or a byte
is
ready to be transferred to the
of
informa-
has been transferred to a peripheral device (i.e.,
is
empty). Two jumper-selectable interrupt
by
the
US
ART
is
ready to be transferred
(i.e., receive channel buffer
is
ready to be transmitted (i.e., transmit channel
is
empty.) A jumper-selectable interrupt
is
of
to
the 8086
full)
or
when a
the programmable counters and eight additional interrupt request lines are ava.ilable to the user for direct interfaces to user-designated penpheral devices via the Multibus.
One interrupt request
line may be jumper routed directly from a peripheral via
th~
~arallel
VO
driverlterminator section and one power
fall mterrupt may be input via auxiliary connector P2.
Th~
iSBC 86/12 includes the resources for supporting a
~anety
tIOns benefits
of
OEM system requirements. For those applica-
requiring additional processing capacity and the
of
multiprocessing (Le., several
CPU's
and/or controllers logically sharing systems tasks with com­munication over the Multibus), the
iSBC 86/12 provides
full bus arbitration control logic . This control logic allows up to three bus masters (e.g., combination DMA controller, diskette controller, etc.) Multibus
in
serial (daisy-chain) fashion
of
iSBC 86/12
to
or
up to
share the
16
bus
masters to share the Multibus using an external parallel priority resolving network.
General
lers
to
share resources on the same bus,. and transfers via
~he
bus proceed asynchronously. Thus, the transfer speed
IS
dependent on transmitting and receiving devices only.
Information
This design prevents slower master modules from being handicapped in their attempts
gain control
of
the bus,
to but does not restrict the speed at which faster modules can transfer data via the same bus. The most obvious applica-
of
tions for the master-slave capabilities
the bus are mul­tiprocessor configurations, high-speed direct memory access (DMA) operations, and high-speed peripheral
by
no
control, but are
means limited to these three.
1-3. SYSTEM SOFTWARE
DEVELOPMENT
The development cycle may be significantly reduced using an Intel Intellec Mic-
rocomputer Development and system monitor greatly simplify the design, develop-
~ent,
and
deb~g
dIskette operatmg system provides a relocating loader and linkage editor, and a library manager.
Intel's high level programming language, available
ment
program
the need PUM
as
a resident Intellec Microcomputer Develop-
System option.
in
a natural, algorithmic language and eliminates
to
manage register usage
86 programs can be written in a much shorter time
than assembly language programs for a given application.
of
iSBC 86/12 based products
System. The resident text editor
of
iSBC system software.
PUM
86 provides the capability to
or
An
optional
PUM86,
is
also
allocate memory.
1-4. EQUIPMENT SUPPLIED
The following are supplied with the iSBC 86/12 Single
Board Computer:
a.
Schematic diagram, dwg no. 2002259
b. Assembly drawing, dwg no. 1001801
1-5. EQUIPMENT REQUIRED
Because the iSBC 86/12 is designed to satisfy a variety applications, the user must purchase and install only those components required to satisfy his particular needs. A list of
components required to configure all the intended ap-
plications
of
the iSBC86/12
is
provided in table 2-1.
of
T~e
Multibus arbitration logic operates synchronously
WIth
the bus clock, which
86/12
or
can be optionally generated
master. Data, however,
is
derived either from the iSBC
is
transferred via a handshake between the controlling master and the addressed slave module. This arrangement allows different speed control-
by
some other bus
1-6. SPECIFICATIONS
Specifications are listed
of
the iSBC 86/12 Single Board Computer
in
table 1-1.
1-3
Page 12
General Information
WORD SIZE
iSBC 86/12
Table 1-1. Specifications
Instruction: Data
CYCLE TIME:
MEMORY CAPACITY On-Board ROM/EPROM:
On-Board Dynamic RAM: Off-Board Expansion:
MEMORY
On-Board ROM/EPROM:
On-Board RAM:
On-Board RAM:
SERIAL COMMUNICATIONS
Synchronous:
ADDRESSING
(CPU Access)
(Multi bus Access)
8,
16,
24,
or
8/16 bits.
800 nanosecond for fastest executable instruction (assumes instruction is
1.2 microseconds for fastest executable instruction (assumes instruction is not
queue).
Up to 16K bytes; user installed in 1 32K bytes. Integrity maintained during power failure with user-furnished batteries. Up to 1 megabyte of user-specified combination of RAM,
FFOOO-FFFFFH
FEOOO-FFFFFH
FCOOO-FFfFFH (using 2332 ROM's).
00000-07FFFH .
Jumpers and switches allow board to act as slave RAM device for access by another bus master. Addresses may 1-megabyte system address space. Access is selectable for
5-, 6-, 7-,
Intemal; 1
Automatic sync insertion.
32 bits.
(using 2758 EPROM's), (using 2316E ROM's
or
8-bit characters.
or
2 sync characters.
in
the queue).
K,
2K,
or
4K byte increments.
ROM, and EPROM.
or
2716 EPROM's), and
be
set within any 8K boundary of any 128K segment of the
8K,
16K, 24K,
or32K
in
bytes.
the
Asynchronous:
Sample Baud Rate:
5-, 6-, 7-, Break character generation. 1, 1 Y2, False start bit detection.
Notes:
or
8-bit characters.
or
2 stop bits.
Frequency'
(kHz, Software Selectable)
153.6
76.8
38.4
19.2
9.6
4.8
2.4
1.76
1.
Frequency selected by I/O writes of appropriate 16-bit freq uency factor to Baud Rate Register.
2.
Baud rates shown here are only a sample subset of possible software­programmable rates available. Any frequency from 18.75 Hz to 613.5 kHz may
be generated utilizing on-board crystal oscillator and 16-bit Program-
mable Interval T'imer (used here as frequency divider).
Baud Rate (Hz)2
Synchronous Asynchronous
+16
-
-
38400 2400 19200
9600 4800 300 2400 1760 110
9600 2400
4800 1200
1200
600 150 150
+64
600 300
-
-
75
1-4
Page 13
JSBC
86/12
General Information
Table 1-1. Specifications (Continued)
INTERVAl GENERATOR
Input Frequency (selectable):
Output Frequencies:
SYSTEM CLOCK (8086 CPU):
I/O ADDRESSING:
INTERFACE COMPATIBILITY
Serial I/O:
TIMER AND BAUD RATE
2.46 MHz
1.23 MHz
153.6 kHz
5.0 MHz ±0.1%.
All communication to Parallel I/O and Serial I/O Ports, Timer, and InterruptControlier is via read and write commands from on-board
EIA Standard RS232C signals provided and supported:
±0.1% (0.41 ±0.1% (0.82
±0.1% (6.5
Function
Real-Time Interrupt Interval
Rate Generator 2.342 (Frequency)
Clear to Send Receive Data Data Set Ready Secondary Receive Data* Data Terminal Ready Secondary Request to Send Transmit Clock* Receive Clock Transmit Data
jLsec jLsec
jLsec
Min.
1.63
period nominal), period nominal), and
period nominal).
Single Timer
Max.
jLsec
Hz
427.1 msec
613.5 kHz
*Can support only one.
(Two Timers Cascaded)
Min. Max.
3.26
0.000036 Hz
8086 CPU. Refer to table 3-2.
CTS*
Dual Timers
jLsec
466.5
minutes
306.8 kHz
Parallel I/O:
INTERRUPTS:
COMPATIBLE CONNECTORS/CABLES:
ENVIRONMENTAL REQUIREMENTS
Operating Temperature:
Relative Humidity:
PHYSICAl
Width: Height:
Thickness:
Weight:
CHARACTERISTICS
24 programmable lines (8 lines per port); one port indudes bidirectional bus driver. IC sockets included for user installation of line drivers and/or I/O terminators as required for interface ports. Refer to table 2-1.
8086 CPU includes non-maskable interrupt (NMI) and maskable interrupt (INTR).
NMI
interrupt is provided for catastrophic event such as power failure; NMI vector address is 8-bit identifier of interrupting device to
vector address. Jumpers select interrupts from 18 sources without necessity of
external hardware. level-sensitive inputs.
Refer to table 2-2 for compatible connector details. Refer to paragraphs 2-21 and 2-22 for recommended types and lengths of
To
30.48 cm (12.00 inches).
17.15 em (6.75 inches).
1.78 cm 539 gm (19 ounces).
00008. INTR interrupt is driven by on-board 8259A PIC, which provides CPU. CPU multiplies identifier by four to derive
PIC may be programmed to accommodate edge-sensitive
I/O cables.
90% without condensation.
(0.7 inch).
or
1-5
Page 14
General
Information
POWER REQUIREMENTS:
CONFIGURATION
VCC
Table 1-1. Specifications (Continued)
=
+5V±5%
VOO = +12V±5%
VBB =
-5V±5%
V
AA
=
-12V±5%
iSBC
86/12
Without EPROM'
RAM
Only3 With iSBC With 4K EPROMs
(Using 2758) With 8K
(Using 2316E) With 8K EPROMs
(Using 2716) With 16K
(Using 2332)
Notes:
53()4
ROMS
ROMS
1.
Does not include power for optional ROM/EPROM,
2.
Does not include power required for optional ROM/EPROM,
3.
RAM chips powered via auxiliary power bus.
4. Does not include power for via serial port connector.
5.
Includes power required for four ROM/EPROM chips, and
low.
inputs
5.2A rnA 40 rnA
390
5.2A
5.5A
6.1A 450 rnA
5.5A
5.4A 450 rnA
optional ROM/EPROM,
350 rnA
450 rnA
450 rnA
450 rnA
110
drivers, and
110
drivers, and
-
1.0 rnA -
-
-
-
-
-
110
terminators.
1/0
drivers, and
110
terminators installed for16
110
terminators.
110
terminators. Power for iSBC 530
40 rnA
140 rnA
140 rnA
140 rnA
140 rnA
140 rnA
is
110
lines; all terminator
supplied
1-6
Page 15
CHAPTER 2
PREPARATION FOR USE
2-1. INTRODUCTION
This chapter provides instructions for the iSBC 86/12 Single Board Computer in the user-defined environment.
of
It is advisable that the contents
fully understood before beginning the configuration and
installation procedures provided in this chapter.
Chapters 1 and 3 be
2-2. UNPACKING AND INSPECTION
Inspect the shipping carton immediately upon receipt for
of
evidence carton is severely damaged the carrier's agent be present when the carton
If
the carrier's agent is not present when the carton opened and the contents keep the carton and packing material for the agent's inspection.
For
repairs to a product damaged in shipment, contact the Intel Technical to obtain a Return Authorization Number and further instructions. A purchase order will be required to com­plete the repair. A copy submitted to the carrier with your claim.
mishandling during transit. If the shipping
or
waterstained, request that
is
opened.
is
of
the carton are damaged,
Support Center (see paragraph 5-3)
of
the purchase order should be
2-5. POWER REQUIREMENT
The iSBC 86/12 requires
power. The dual port RAM, can be supplied by the system supply, an auxiliary battery, regulator. (The
-12V
-5V
-5V
supply.)
+5V,
-5V,
+ 12V, and
power, which is required only for the
or
by the on-board
regulator operates from the system
-12V
-5V
-5V
2-6. COOLING REQUIREMENT
The iSBC 86/12 dissipates 451 gram-calories/minute
of
(1.83 Btu/minute) and adequate circulation
provided to prevent a temperature rise above 55°C
(131°F). The
tem include fans to provide adequate intake and exhaust ventilating air.
System 80 enclosures and the Intellec Sys-
air must be
of
2-7. PHYSICAL DIMENSIONS
Physical dimensions a. Width: b.
Height:
c. Thickness:
of
the iSBC 86/12 are as follows:
30.48 cm (12.00 inches).
17.15 cm (6.75 inches). cm
1.78
(0.70 inch).
It is suggested that salvageable shipping cartons and pack­ing material be saved for future use duct must be reshipped.
in
the event the pro-
2-3. INSTALLATION CONSIDERATIONS
The iSBC 86/12 is designed for use in one ing configurations:
a. Standalone b. Bus master in a single bus master system. c. Bus master in a multiple bus master system.
Important criteria for installing and interfacing the iSBC 86/12 in these configurations are presented in
following paragraphs.
(single~board)
system.
2-4. USER-FURNISHED COMPONENTS
The user-furnished components required to configure the
iSBC86/12
2-1. Various types and vendors
in table 2-1 are listed in table 2-2.
fied
for a particular application are listed in table
of
the connectors speci-
ofthe
follow-
2-8. COMPONENT INSTALLATION
Instructions for installing optional ROM/EPROM and parallel
given in following paragraphs. When installing these chip
components, be sure to orient pin 1
to the white dot located near pin 1 IC socket. The grid zone location location diagram) is specified for each component chip to be installed.
2-9. ROM/EPROM CHIPS
IC sockets A28, A29, A46, and A47 (figure 5-1 zone C3)
accommodate 24-pin CPU jumps to location ROM/EPROM address space resides in the topmost por­tion from the top down. IC sockets A29 and A47 accom­modate the top must always be loaded; IC sockets A28 and A46 accom­modate the
stalled in A29 and A47.
I/O port line drivers and/or line terminators are
of
the chip adjacent
of
the associated
on figure 5-1 (pltrts
ROM/EPROM chips. Because the
FFFFO
on a power up
of
the I-megabyte address space and must be loaded
of
the ROM/EPROM address space and
ROM/EPROM space directly below that in-
or
reset, the
2-1
Page 16
Preparation for
Use
Table 2-1. User-Furnished and Installed Components
iSBC
86112
Item
No.
1
2
3
4
5
6
7
Item
iSBC
604
iSBC
614
Connector
(mates
with
Connector
(mates
with
Connector
(mates
with
Connector
(mates
with
ROM/EPROM
P1)
P2)
J1)
J2)
Chips
Description
Modular
cludes four
(See
Modular cludes four slots without (See
See
table
See Auxiliary table
See table
See table
Two
types:
Backplane
slots
figure
5-3.)
Backplane
figure
5-4.)
Multibus Connector
2-2.
2-2.
Parallel I/O Connector details
2-2.
Serial
2-2.
or
four
ROM
or
and
with
bus
and
bus
Connector details
I/O connector details in
each
of
EPROM
Cardcage.
terminators.
-
Cardcage.
terminators.
details in
the
following
In-
In-
in
in
Provides signal three system.
Provides
Power
face.
stalled
Auxiliary
ciated
Interfaces PPI.
Interfaces
USART.
Ultraviolet development. cated
power input
interface
additional boards
four-slot extension of
inputs
Not
required
in
an
backup
memory
parallel
serial
Erasable
program.
between
and
iSBC
protect
I/O
Masked
Use
pins
in
Multibus
if
iSBC
6041614.
battery
functions.
I/O
port
port
PROM
and
iSBC
86/12
a multiple
iSBC
signal
86/12
and
with
Intel8255A
with
Intel
(EPROM)
ROM
for
Multibus
and
board
604.
inter-
is
in-
asso-
8251A
for
dedi-
-
2316E 2332
8
9
Une
Une
Terminators
Drivers
Type
SN7403I,OC SN7400 SN7408 SN7409
Types ing, collector.
Intel Pull-Up:
I
NI
NI,
selected
NI = noninverting,
iSBC
iSBC
iSBC
901
902
OC
901
.&
0
2758 2716
-
as
typical;
Divider
A
330
Current
16mA 16mA 16mA
16mA
I =
and
invert-
OC = open
or
iSBC
+5V
220
r:v
902
0
Interface Intel IC's
Interface Intel8255A 902'sfor
parallel
8255A
for
each
parallel"VO
each
I/O
ports
PPI.
8-bit
PPI.
Requires
8-bit
CA
Requres two line driver
parallel
output
ports
CA
two 901's ortwo
parallel
and
and
input
CC
port.
CC
port.
with
with
2-2
Page 17
iSBC
Function
86/12
No.
Pairs/
Pins
Of
Table 2-2. User-Furnished Connector Details
Centers
(inches)
Connector
Type
Vendor
Vendor
Part
Preparation for
No.
Intel
Part
Use
No.
Parallel
I/O
Connector
Parallel
I/O
Connector
Parallel
I/O
Connector
Serial
110
Connector
Serial
110
Connector
Serial
110
Connector
25/50
25/50
. 24/50
13/26
13/26
13/26
0.1
0.1
0.1
0.1
0.1
0.1
3M 3M
Flat Crimp AMP
ANSLEY
SAE S06750 SERIES
AMP 2-583485-6
Soldered
Wirewrap'
Flat Crimp
Soldered
Wi
rew
rap'
VIKING
TI H312125
TI
VIKING
COO
ITICANNON
3M
AMP
ANSLEY
SAE S06726 SERIES
TI H312113
AMP
TI
3415-0000 WITH EARS 3415-0001 W/O EARS iSBC 956 88083-1 609-5015 Set
3VH25/1JV5
H311125
3VH25/1JN05
VPB01 B25000A 1
EC4A050A1A
3462-0001 88106-1 609-2615
1-583485-5
H311113
Cable
N/A
N/A
iSBC
Cable
Set
N/A
N/A
955
Multibus
Connector
Multibus
Connector
Auxiliary
Connector
Auxiliary
Connector
NOTES:
1.
2.
3.
COC3
43/86
43/86
30/60
30/60
Connector heights are not guaranteed to conform to OEM packaging equipment. Wirewrap pin lengths are not guaranteed to conform to
COC VPB01 .... VPB02 .... VPB04 .... etc. are identical connectors with different electroplating thicknesses
metal surfaces.
0.156
0.156
0.1
0.1
Soldered'
Wirewrap1.2
Soldered'
Wirewrap1.2
MICRO PLASTICS
ARCO AE443WP1 LESS EARS
VIKING 2VH43/1AV5
COO COC3
VIKING 2VH43/1AV5
TI
VIKING
COO
TI
OEM packaging equipment.
VPB01 E43000A 1 MP-0156-43-BW-4
VFB01 E43000A 1 or VPB01E43AooA1 MOS 985
H312130 3VH30/1JN5
VPB01
B30AOOA2
H311130
:,
N/A
N/A
N/A
or
2-3
Page 18
Preparation for
Use
iSBC 86/12
The low-order byte (bits 0-7)
installed (bits 8-15) must
in
sockets A29 and A28; the high-order byte
be
installed
Assuming that 2K bytes
of
ROM/EPROM must
in
sockets A47 and A46.
of
EPROM are to
be
installed
be
using two Intel 2758 chips, the chip containing the
low-order byte must
the chip containing the high-order byte must
in
IC
socket A47. ROM/EPROM address space ditional Intel 2758 chips may sockets
A28
FFOOO-FF7FF.
be
installed
In
this configuration, the usable
in
IC
socket A29 and
be
is
FF800-FFFFF. Two
be
installed later
installed
ad-
in
IC
and A46 and occupy the address space
(Even addresses read the low-order bytes
and odd addresses read the high-order bytes.)
The default (factory connected) jumpers and switch
are configured for
2K
by
8-bit ROM/EPROM chips
S 1
(e.g., two or four Intel 2716's). If different type chips are installed, reconfigure the jumpers and switch
S 1
as
listed in table 2-4.
2-10. LINE DRIVERS
AND
I/O
TERMINATORS
Table 2-3 lists the I/O ports and the location
14-pin
IC
sockets for instaHing either line drivers or I/O tenninators. (Refer Port
C8
is
factory equipped with Intel 8226 Bidirectional
Bus Drivers and requires
to
table 2-1 items 8 and 9.)
no
additional components.
of
associated
2-11. JUMPER/SWITCH CONFIGURATION
The iSBC
selectable options to allow the user for his particular application. Table 2-4 summarizes these options and lists the grid reference locations
jumpers and switches
location diagram) and figure 5-2 (schematic diagram). Because
:86/12
includes a variety
as
of
jumper- and switch-
to
configure the board
shown in figure 5-1 (parts
the schematic dIagram consists
of
11
of
the
sheets, gria
references
to
figure 5-2
may
be
either four or five alpha­numeric characters. For exampfe, grid reference 3ZB7 signifies sheet 3 Zone B7.
Study table 2-4 carefully while making reference ures
5-1
and 5-2.
If
the default (factory configured)
to
fig-
jumpers and switch settings are appropriate for a partic-
ular function, function. If, however, a different configuration
no
further action
is
required for that
is
re­quired, reconfigure the switch settings and/or remove the default jumper(s) and install an optional jumper(s) specified. For most options, the infonnation 2-4
is
sufficient for proper configuration. Additional information, where necessary for clarity, in
subsequent paragraphs.
in
is
described
table
2-12. RAM ADDRESSES (MULTIBUS
ACCESS)
The dual port RAM can
via the Multibus. selected pair
dual port RAM
of
jumper posts (113 through 128) places the
in I-megabyte address space. package (DIP) composed
single-throw switches. (Two
are used for
ROM/EPROM configuration.) Two switches (6-11 and 5-12) are configured or 32K bytes
of switches (1-16, 2-15, 3-14, and 4-13) are configured to
displace the addresses from the top
128K byte segment
Figure
2-1
provides an example RAM being made accessible from the Multibus and how the addresses are established. Note in figure 2-1 that the Multibus accesses the dual port RAM from the top down. Thus, as shown for the bottom RAM
24Kbytes
is
reserved strictly for on-board CPU access.
be
shared with other bus masters
One jumper wire connected between a
one
of
eight 128K byte segments
Switch S 1
of
eight individual single-pole,
of
these individual switches
to
allow 8K, 16K, 24K,
dual port RAM to
of
memory.
of
8K
byte access via the Multibus,
of
the iSBC 86/12 on-board
is
be
accessed. Four of
8K
bytes
of
the
a dual-inline
the selected
of
dual port
as
Table 2-3. Line Driver and
1/0
Port
C8 0-7
8255A
PPI
Interface
*Figure 5-2 is the schematic diagram. Grid reference 9ZA3, for example, denotes sheet 9 lone A3.
2-4
CA
CC
Bits
0-3
4-7
0-3
4-7
I/O
Terminator Locations
DriverlTermlnator
None Required -
A12 A13
A11 A10
Fig.
5-1
Grid Ref.
lO4 lO4
lO5 lO5
Fig. 5-2* Grid Ref.
-
9ZA3 9ZA3
9lC3
9lB3
Page 19
i8BC
86/12
Preparation for
Use
Function
ROM/EPROM
Configuration
Table 2-4.
Fig. 5-1 Fig. 5-2
Grid
Ref.
ZC3, ZB6,
ZD7
Jumper
Grid
Ref.
6ZB3,6ZC7, 2ZB6
and Switch Selectable Options
Description
Jumpers 94 through 99 and switch
four types of
ROM/EPROM
2316E/2716
Reserved
= closed switch position.
C
ROM/EPROM chips:
Type
2758 2332
S1
Jumpers
94-95, 97 -98
*94-96, *97-98
94-96, 97-99
-
may be configured to accommodate
Switch
S1
--
--
8-9
C C
*C
0 C
0 0
7-10
*0
o = open switch position.
Default jumpers and switch settings accommodate Intel 2316E/2716
chips. Disconnect existing configuration jumpers (if necessary) and
reset switch
Dual Port RAM
(Multibus Access) system bus master via the Multibus. For local CPU access, the dual port
ZB7, ZB6
3ZB6,3ZB7
The dual port RAM permits access by the local (on-board) CPU and any
RAM address space is fixed beginning at the
Multibus, one jumper and one switch can configure the dual port RAM on any 8K boundary within the 1-megabyte address space. Refer to paragraph 2-12 for configuration
S1
if reconfiguration is required.
details.
location 00000. For access via
Bus Clock
Constant Clock
Bus Priority Out
Bus Arbitration
Auxiliary Backup
Batteries
On-Board
Failsafe Timer
-5V
Regulator
ZB7
ZB7
ZB7
ZBB,
Zf)7
ZBB, 1ZC7,1ZCB
ZD3, ZB5
ZB6
ZD7
10ZA2
10ZA2
3ZD2
3ZD2,3ZC3
1ZCB
2ZB6
Default
jumper *105-106 routes Bus Clock signal BCLKI to the Multibus.
(Refer to table 2-9.) Remove this jumper only if another bus master supplies this signal.
jumper *103-104 routes Constant Clock signal CCLKI to the
Default
Multibus. (Refer to table 2-9.) Remove this jumper only if another bus master
supplies this signal.
Default jumper *151-152 routes Bus Priority
Multibus. (Refer to table 2-9.) Remove this jumper only in those systems to paragraph 2-19.)
The Common . Bus Request signal (CBRO)
ANYROST input to the Bus Arbiter chip are not presently used.
If auxiliary backup batteries are used to sustain the dual port RAM
du~ng
and *W6(A-B).
The dual port RAM requires a
the system
-5V supply.) If a system teries are not used, disconnect jumper W5(B-C). fault jumper *W5(A-B); do not connect W5(B-C).
If the on-board CPU addresses either a system
or the CPU will hang up in a wait state. A failsafe timer is triggered during T1
the wait state.
employing a parallel priority bus resolution scheme. (Refer
ac power outages, remove default jumpers *W4(A-B), *W5(A-B),
regulator. (The
I/O device and that device does not return an acknowledge Signal,
of every machine cycle and, if not retriggered within 6.2 milliseconds,
resultant time-out pulse can be used to allow the CPU to exit the
..
-5V
-5V
supply, an auxiliary backup battery,
-5V
-5V
If auxiliary backup batteries are used, disconnect de-
If this feature is desired, connect jumper 5-6.
AUX input, which can be supplied by
regulator operates from the system
supply is available and auxiliary backup bat-
default jumper *W5(A-B) and connect
Out
signal BPRO/ to the
trom
the Multibus and the
or
by the,on-board
or
an on-board memory
conter1'ts
-12V
*Default jumper connected
at
the factory.
2-5
Page 20
Preparation for
Function
Timer
Input
Frequency
Use
Table 2-4. Jumper and Switch Selectable Options (Continued)
Fig.
5-1
Grid
Ref.
ZD3 7ZB5
ZD3
Fig. 5-2
Grid
7ZA5
Ref.
Description
Input
frequencies to the 8253 Programmable Interval Timer are jumper
selectable as follows:
Counter 0
57-58: 153.6 kHz.
*57-56: 1.23 MHz.
57 -53: 2.46 MHz. 57-62:
Counter 1
*59-60: 153.6 kHz.
59-56: 1.23 MHz.
*59-53: 2.46 MHz.
59-62: 59-61: Counter
Jumper 59-61 which.the output This permits programming the clock rates to Counter 1 and thus provide
longer
(TMRO
INTR)
Extemal Clock to/from Port CC terminator/driver.
(TMR1
INTR)
External Clock to/from Port CC terminator/driver.
TMR1
0 output.
effectively connects Counter 0 and Counter 1 in series
of
Counter 0 serves as the input clock to Counter
INTR intervals.
iSBC 86/12
in
1.
ZD3
Interrupts
Priority
Serial I/O Port
Configuration
Parallel I/O Port
Configuration
*Default jumper connected at the factory.
-
- Sheet 7
- Sheet 9
The configuration for 16K, 24K,
7ZB5
Sheet 8
or
32K access
A jumper matrix provides a wide
Jumpers posts 38 through 52 are used to configure the 8251A
Jumper posts 7 through 37 are used to configure the 8255A
is
done in a similar manner. Always observe the IMPORTANT note in figure 2-1 in that the address space intended
of
for Multibus access cross a 128K
If
it
is
for local
boundary.
desired
to
CPU access, connect jumper 112-114.
the dual port RAM must not
reserve all the dual port RAM strictly
Counter 2
55-58: 153.6 kHz.
*55-54: 1.23 MHz.
55-53: 2.46 MHz. 55-62:
to the 8086 configuration.
described
scribed
(8251
Baud Rate Clock)
External Clock to/from Port CC terminator/driver.
CPU and the Multibus. Refer to paragraph 2-13 for
in
paragraph 2-14.
in
paragraph 2-15.
selection of interrupts to be interfaced
which himdles up to eight vectored priority interrupts, provides the capability to expand the number interrupts by cascading each interrupt line with another
as
8259A PIC. Figure 2-2 shows
an example the
PIC (master) with two slave PIC's interfaced by the Multi-
bus. This .arrangement leaves the master PIC with six inputs (IR2 through IR 7) that can be used to handle the various on-board interrupt functions.
USART as
PPI as de-
of
priority
on~board
2-13. PRIORITY INTERRUPTS
Table 2-5 lists the source (from)iand destination (to)
priority interrupt jumper matrix shown
8. The INTR
output'of grammable Interrupt Controller (PIC) is applied directly to the INTR input
2-6
the on-board Intel 8259A Pro-
of
the 8086 CPU. The on-board PIC,
in
figure 5 -2 sheet
of
the
The master/slave PIC arrangement illustrated in figure
2-2
is
implemented by programming the master PIC
handle
IRO
and IRI example, PIC
if
the Multibus INT3/line
1,
the master PIC will let slave PIC 1 send the restart
address to the 8086
Each interrupt input can
be
individually programmed
as
bus vectored interrupt inputs. For
is
driven low by slave
CPU.
(IRO
through IR7) to the master PIC
to
be a non-bus vectored
to
Page 21
iSBC 86/12
Preparation
for
Use
SYSTEM
128K BYTE
SEGMENT
NO ACCESS
EOOOO-FFFFF
®
JUMPER
112·114
113-114
EXPLANATION
® SELECTS X PARAMETER (128K BYTE SEGMENT)
® SELECTS Z PARAMETER (MEMORY AVAILABLE ©
SEL.ECTS
Y PARAMETER (LOCATION WITHIN 128K SEGMENT)
ADDRESS (UPPER) ~ X+Y
ADDRESS(LOWER)~
IN THE EXAMPLE SHOWN IN THE SHADED PATH, X ~ COOOO,
Z ~ 8K (01I'FF). THUS,
IMPORTA~IT
THE
SElI,CTED
BOUNDARY. THAT IS,
ABSOLUTIE VALUE
X+Y-Z
COOOO ~ X
+OBFFF ~ Y
CBFFF
~
-01FFF ~ Z (8K)
"""CAoOo
MEMORY SPACE CANNOT EXTEND ACROSS A 128K BYTE
OF
ADDRESS (UPPER)
~
ADDRESS (LOWER)
X+Y-Z
MUST BE EQUAL TO OR GREATER THAN THE
X.
TO
BUS)
Y ~ OBFFF, AND
645·2
FFFFF
00000
....
"'1-------1
C
0
0 C 0
0 C
0
0 0
0
0 0
SYSTEM
MEMORY
01FFF
03FFF
0
0
0
C
C
C
0 0
C
0
C
0
0
0
OFFFF
C
11FFF
0
13FFF
C
15FFF
0
17FFF
C
19FFF
0
1BFFF
C
1DFFF
0
1FFFF
-..-
Y PARAMETER
Figure 2-1. Dual Port RAM Address Configuration (Multibus Access)
86/12
8K
8K
8K
8K
07FFF
06000
04000
02000
00000
2-7
Page 22
Preparation for
Use
Table 2-5. Priority Interrupt Jumper Matrix
iSBC
86/12
Interrupt Request From
Source Signal Post
Multibus
Extemal Power
Failsafe Timer
8255A
8251A
8253
NOTES:
(2)
Via
J1-50
Fail
Via
Port Port B (Port CAl Any
Trans Buffer Empty
Ree
Timer 0 Out Timer 1 Out
(1) (2) (3) (4) (5)
(6)
(7) Default jumper
(8)
(9)
Logie
P2-19
PPI
A (Port
C8)
Unused
Buffer
PIT
'Requires positive-true signal at associated jumper
Bit
USART
Empty
Signal
is positive-true
INTO/
is Signal Requires
IRO sensitive.
INTR Used
highest priority;
is
ground-true at associated jumper
ground-true
is highest priority;
is connected directly to output of
to
generate
87
INTO/ INT1/ INT2I INT3/ INT4/ INT5/ INT6I INT7/
EXT PFI/
TIME
PAINTR PBINTR BUS
51TX 51RX
TMRO TMR11NTR
at
associated jumper
INT7/
Signal
IR7
-89
an
is lowest priority.
disables
interrupt
INTO/
OUT
INTR
INTR
OUT
INTR
INTR
INTR
is
lowest
at associated jumper
(grounds)
on
8259A
Multibus.
(1) (1
)
(1
)
(1
)
(1
)
(1
)
(1
)
(1
)
(1
)
(1
)
(1)
(1
)
(1)
(3)(9)
(1)
(1
)
(1
)
(1)
post.
priority.
post.
input.
The
PIC.
post.
post.
NMI
73 72
71
70 69
68
66 65
67 86
88
84 85
142
90 82
83 91
input
is highest priority,
Device
Multibus
8259A
8086
.'
Interrupt Request
(2)
PIC
(6)
CPU
non-maskable,
To
Signal Post
and
is
(4)
(4)
(4)
(4) (4) (4)
(4)
(4) (5)
(5) (5) (5)
(5)
(5) (5) (5)
(7)
(8)
both
level
and
INTO/ INT1/ INT2I INT3I INT4/ INT5/ INT6I INT7/
IRO IR1 IR2
IR3
IR4 IR5 IR6 IR7
NMI
INTR
141 140 139 138 137 136 135 134
81 80 79 78
n
76 75 74
89
-
edge
r-
-----
-
--
---
I 8086 MASTER I
I
cpu
8~~~A
I
I
I I I
I
INTR
I
I+---IINTR
I
I
I I
I
IRO
IR1
IR214---o
IR3
IR414---o
IR514---o
IR614---o
IR7
I
I I
L
_________________________
645-3
2-8
Figure 2-2. Simplified Master/Slave PIC Interconnect Example
-----
-----iSBCa6i121
81
70 I
1+--<>---0----<,
80
k---c~o_----_<:C
.....
--o
.....
--o
79
78
77
76
75
74
86
0-
0-
0-
0--
0-
0-
INPUTS FROM ON-BOARD INTERRUPT SOURCES
(NBV)
r---
I
MULTIBUS
INT3I
INT6I
INTO!
INT11
1NT2I
INT4/
INTS/
INT71
J
I PIC 1
I
I :
I
I
41
I
I
42
I
39
I
I
37
I
38
I
I
36
I BUS VECTORED (BV) I INTERRUPT SOUFICES
L
__________
-SLAve-
IRO
INTR
1o-...,.;,IR:.:;7,,---- 7
SLAVE
-
--1
,,1
J
Page 23
iSBC
86/12
(NB
V)
interrupt (the master PIC generates the restart
address) or bus vectored (B
V)
interrupt (the slave PIC generates the restart address). Thus, the master PIC can handle eight on-board (an interrupt line that to
64 interrupts with the implemention
or
single Multibus interrupt lines
is
not driven by a slave PIC) or up
of
slave PIC's.
2-14. SERIAL
Preparation
110
PORT CONFIGURATION
for
Use
Table 2-6 lists the signals, signal functions, and the jumpers required (if necessary) to input particular signal to or from the serial
VO
or
output a
port (Intel 8251 A
USART).
The iSBC 86/12 can also generate an interrupt to another
interrupt handler via the Multibus. This
by using one
of
the bits
of
the 8255A PPI to drive the
BUS INTR OUT signal. (The BUS INTR OUT signal
ground-true at jumper post 142 as footnoted
is
accomplished
in
table 2-5.)
is
Default jumper 87-89 grounds the NMI (nonmaskable intemlpt) input to the
CPU to prevent the possibility
of false interrupts being generated by noise spikes. Since the NMI is not maskable, cannot be disablyd and has the highest priority,
it
should only be used to
by
the program,
detect a power failure. For this purpose, disconnect de­fault jumper 87-89 and connect 86-89. The Power Fail Interrupt (PFI/) is an externally generated signal that
is input via auxiliary connector P2. (Refer to paragraph 2-20.)
Pin
21
:23
:26
'10 12 '13 14 '19
22
25
Table 2-6. Serial I/O Connector
1
2 4 5
6 7
8
CHASSIS GND TRANSMITIER SEC REC SIG
RECEIVER DATA 8251A TXD out REC
RaTTO CLEAR TO SEND DATASET DATA TERMINAL ROY 8251A DSR in GND
-12V TRANS SIG ELE TIMING
+12V
+5V GND SEC CTS
Signal
DATA 8251A RXD in
2
SIG ELE TIMING
SEND
ROY 8251A DTR out
2
2
J2
Pin Assignments
Protective ground
Same as
8255A STXD out (Note 3)
8251A RXC in (Note 4) 8251A TXC in (Note 4) 8251A CTS in (Note 8251A RTS out (Note
Ground
-12Vout Same as 8251ATXC 8255A STXD out (Note
+12Vout +5Vout Ground Same as
8255A STXD out (Note 3)
2-l5.
PARALLEL
110
PORT CONFIGURATION
Table 2- 7 lists the jumper configuration for three parallel
VO
ports. Note that each
CC) can be configured
of
the three ports (C8,
in
a variety
of
ways to suit the
individual requirement.
2-16. MULTIBUS CONFIGURATION
For
systems applications, the iSBC 86/12 is designed for
installation
in
a standard Intel iSBC 604/614 Modular
Backplane and Cardcage. (Refer to table 2-1 items 1 and 2.) Alternatively, the iSBC 86/12 can to
3i
user-designed system backplane by means
Vs
Configuration Jumpers
Function
Jumper
In Jumper Out
63-64
-
8261
8251
A TXC in
A TXC in
or
5)
5)
inor
3)
or
48-49, 45-46 49-50,
45-46
-
38-39
41-42
-
-
-
-
-
*W3A-8
48-49, 44-45
49-50, 44-45
*W2A-8 *W1A-8
-
48-49,45-47 49-50,45-47
*39-40
*42-43
.
CA,
be
interfaced
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
of
and
an
NOTES:
1.
All odd-numbered pins (1,3,5,
component side
2.
Only one
3. Optional jumper selected output Default jumpers
4.
Input Frequency (Counter 2)
5. For those
*Default jumpers connected at the factory.
of
the board with the extractors at the top.
of
these signal outputs (pin
*39-40
applications without CTS capability, connect jumper 51··52. This routes
and
...
*42-43
in
25) are on component side of the board. Pin 1 is the right-most pin when viewed from the
5,
21,
or
26) may
of
8255A PPI. Refer to figure 5-2 sheet 9.
connect 8253 CTR2 output to 8251A RXC and txc inputs, respectively. See
table 2-4.
be,
sele<.1ed.
8251
A RTS output to
8251 A CTS
Timer
input.
2-9
Page 24
Preparation for
Use
Table 2-7. Parallel I/O Port Configuration Jumpers
iSBC
86/12
CB
CB
CB
CB
Port
Mode
o Input
o Output
(latched)
1 Input
(strobed)
1 Output (latched)
Driver
Terminator
(D)/
B226:AB,A9
B226:AB,A9
B226:AB,A9
T:A10
0:
A11
B226:AB,A9
T:A10
0:
A11
(T)
Delete
*21-25
*21-25 24-25
*19-20 19-33
and
*32-33
*32-33 13-33
and
*13-14
Jumper
*21-25
*15-16 Connects J1-26 to
Add
24-25
Configuration
Effect
B226
= input enabled.
B226
= output enabled.
B226
= input enabled.
STBAI
input. following:
Connects IBF A output to
J1-1B.
22-32
*21-25
*17-1B
22-32
Connects interrupt matrix.
B226
Connects J1-30 to ACKAI input.
Connects OBF A output to
Connects
interrupt matrix.
INT A output to
= output enabled.
J1-1B.
INT A output to
Port
CA
CC
CA None; can be
CC
CA None; can be
CC
CA
CC
Restrictions
None; can be in mode 0 or
1,
input or output.
None; can be in Mode 0, input or output, unless Port CA is
1,
input or output.
None; can be in Mode input or output,
.Port CA is
1,
input or output.
Port CC bits perform the
• Bits 0,
• Bit 3 - Port
• Bit 4 - Port
• Bit 5 - Port
• Bits
None; can be 1, input
Port EA bits perform the following:
".
• Bit 3 - Port
1,
for Port CA if Port CA
in Mode
rupt (PA INTR) to inter­rupt jumper matrix
(STBI)
input.
put Buffer Full (IBF) output.
6,
7 - Port CC in-
or
put must
direction).
or
Bits 0,
1, 2 --
for Port CA if Port CA is
in Mode
rupt (PA
rupt jumper matrix.
in
Mode
1.
in
Mode 0
unless
in
Mode
1.
in
Mode 0
2 - Control
1. CB
Inter-
CB
Strobe
CB
output
(both,
in
be
output.
same
in
Mode 0
Control
1.
CB
INTR) to inter-
Inter-
or
0,
or
is
In-
or
*Default jumper connected at the factory.
2-10
• Bits 4, 5 - Port CC in­put or output (both must be
in
same direction).
• Bit 6 - Port knowledge input.
• Bit 7 - Port Buffer
output.
(ACKJ)
Full
CB
CB
(OBF/)
Ac-
Output
II
Page 25
iSBC
86/12
Table 2-7. Parallel I/O Configuration Jumpers (Continued)
Preparation for
Use
Port
CB
Mode
2
(bidirectional)
Driver
Terminator
B226:AB,A9 T:A10 D:
(D)I
A11
Jumper
(T)
Delete Add *21-25
*19-20
and
*26-27
*13-14 13-33 Connects
and
*32-33
17-25
*15-16 Connects J1-26 to STBtJ
19-27
*17-1B
22-32
Configuration
Effect
Allows ACKtJ input control B226 inlout direction.
input.
Connects
to J1-24.
Connects J1-30 to
ACKtJ input.
to J1-1B.
Connects
interrupt matrix.
IBFA
OBF
tJ
INT A output to
Port
to CA None; can be in Mode 0 or
CC Port
output • Bits
output
Restrictions
1,
input or output.
CC
following:
• Bit 3 - Port
• Bit 4 - Port
bits perform the
Bit 0 - Can only be
used for jumper option (see figure 5-2 zone 9ZC6).
1,2-
for input or output if Port CC is in Mode
rupt (PA INTR) to inter­rupt jumper matrix.
Can be used
(STB/) input.
• Bit 5 - Port Buffer Full (IBF) output.
• Bit 6 - Port
knowledge
input.
CB
CB
CB
CB (ACKI)
O.
Inter-
Strobe
Input
Ac-
CA-
CA-
CA
o Input
o Output
(latched)
1 Input (strobed)
T: A12, A13
D: A12, A13 None None
T:A10,A12,A13
A11
D:
None None
*2B-29 Connects IBFe output
"'13-14 14-30 Connects J1-32 to *30-31 STBei input.
26-34
to J1-22.
Connects
interrupt matrix.
INTe
• Bit 7 - Port Buffer
output.
None.
CB
None; Port
CC
Mode
0,
Port
CB
CB
None
CC
None; Port CC can be Mode 0, input or output, if Port
CB
None.
CB
Port CC
CC
following:
• Bit 0 - Port CA Inter-
output rupt jumper matrix.
rupt (PB INTR) to inter-
• Bit 1 - Port CA Input Buffer
output.
• Bit 2 - Port CA Strobe
(STB/)
CB
Full (OBF/)
input or output, if
is also in Mode
is also in Mode
bits perform the
input.
Output
CC
can be
Full (IBF)
in
O.
in
O.
'"
Default jumper connected at the factory.
2-11
Page 26
Preparation for
Use
iSBC 86/12
Table 2-7. Parallel I/O Port Configuration Jumpers (Continued)
Port
CA
Mode
1 Output (latched)
Driver
Terminator
T:A10 D: A11, A12, A13
(D)
(T)
Delete
*13-14
and
*30-31 *26-27
Jumper
*28-29
Configuration
Add
Connects output J 1 -22.
14-30 Connects J1-32 to
ACKBI input.
26-34 Connects
interrupt matrix.
Effect
OBFe! output C8
INT B output
Port
CC
to
Restrictions
• Bit 3 - If Port C8 is Mode 0, bit 3 can be in­put
or
output. Other-
wise, bit 3 is reserved.
• Bits 4, 5 ~ Depends on Port
C8
mode.
• Bits 6, 7
None. Port CC bits perform the
• Bit 0 - Port CA inter-
• Bit 1 - Port
• Bit 2 - Port
-Input put (both must be same direction).
following:
rupt (PB rupt jumper matrix.
put Buffer output.
knowledge input.
INTR) to inter-
Full (OBF!)
or out-
CA
Out-
CA
(ACK/)
in
,
in
Ac-
CC o Input
(upper)
CC o Input
(lower)
CA (upper)
CA
(lower)
o Outpl:lt
(latched)
o Output
(latched)
T:A10
T:
A11
D:A10
D:
A11
None
None *26-27
None
*15-16 Connects bit 4 to J1-26. *19-20
*17-18
*13-14 Connects bit 7 to J1-32.
*28-29 *30-31
*32-33
Same' as for Port CC (upper) mode
o Input.
None
Same as for Port CC (lower) Mode CC Same as for Port CC
o Input.
bit 5 to
Connects Connects bit 6 to J1-30.
Connects bit
Connects bit 1 to J1-22. Connects bit 2 to Connects bit 3 to J1-18.
J1--28.
0 to J1-24.
J1-20. available.
• Bit 3 - If Port Mode 0, bit 3 can be in­put or output. Other­wise, bit 3 is
Bits4,5-lnputorout­put (both must be in same direction).
• Bit
6,
7 - Depends on
C8
Port
Port
C8
C8
()
av~ilable.
CA Port
must be in Mode
for all four bits to be
CA
must be in Mode
o for all four bits to be
available. Port
C8
C8
must be in Mode
o for all four bits
CA Port
CA
must be in Mode
o for all four bits to be
available.
C8 Same
as
(upper) Mode 0 Input.
(lower) Mode 0 Input.
C8
~served.
mode.
to
for
Port CC
"'!:;'
is
in
be
*Default jumper connected at the factory.
2-12
Page 27
iSBC 86/12
Preparation for
Use
86-pin connector. (Refer to table 2-1 item 3.) Multibus
of
signal characteristics and methods serial
or
parallel priority resolution scheme for resolving bus contention in a multiple bus master system are de­scribed in following paragraphs.
Always turn fore installing the backplane. Failure caution can cause damage to the board.
off
the system power supply be-
or
removing any board from
to
implementing a
observe this pre-
2-17. SIGNAL CHARACTERISTICS
As shown
86/12 to the Multibus. Connector listed in table 2-8 and descriptions
are provided in table 2-9.
The dc characteristics
signals are provided in table 2-10. The ac character­istics mode and slave mode are provided in tables 2-11 and 2-12, respectively. Bus exchange timing diagrams are provided in figures 2-3 and 2-4.
in
figure 1-1, connector
of
the iSBC 86/12 bus interface
of
the iSBC 86/12 when operating in the master
PI
interfaces the iSBC
PI
pin assignments are
of
the signal functions
2-19. PARALLEL PRIORITY RESOLUTION
A parallel priority resolution scheme allows up masters to acquire and control the Multibus. Figure illustrates one method resolving bus contention in a system containing eight bus masters installed highest and two lowest priority bus masters are shown in­stalled
in
the iSBC 604.
In the scheme shown in figure 2-6, the priority encoder is
a 74148 and the priority decoder is an Intel 8205. Input connections to the priority encoder determine the bus priority, with input 7 having the highest priority and input master has the highest priority and the J5 bus master has the lowest priority.
IMPORT ANT: the On the iSBC 86/12 disable the BPRO/ output signal by removing jumper 151-152. removed on the other bus masters, either clip the IC pin that supplies the BPRO/ output signal to the Multibus or
cut the signal trace.
0 having the lowest priority. Here, the
BPRO/ output must be disabled on all bus masters.
of
implementing such a scheme for
in
an iSBC 604/614. Notice that the two
In
a parallel priority resolution scheme,
If
a similar jumper cannot be
to
16
J3
bus 2-6
bus
2-20. POWER FAIUMEMORY PROTECT
CONFIGURATION
2-18. SERIAL PRIORITY RESOLUTION
In a multiple bus master system, bus contention can be
resolved in an iSBC 604 Modular Backplane and Card-
cage by implementing a serial priority resolution scheme
in
as shown the BPRO/ signal path, this scheme is limited to a maxi­mum trolling the Multibus. In the configuration shown in figure 2-5, the bus master installed in slot J2 has the highest
priority and is able to acquire control any time because its (tied to ground) through jumpers
plane. (See figure 5-3.)
If
the bus master in slot 12 desires control
figure 2-5. Due to the propagation delay
of
three bus masters capable
BPRN/ input
of
acquiring and con-
is
Band
of
the Multibus at
always enabled
N on the back-
of
the Multibus',
it drives its BPRO/ output high and inhibits the BPRN/
input to all lower-priority bus masters. When finished
using the Multibus, the J2 bus master pulls its
output low and gives the
take control
desire to control the Multibus at this time,
BPRO/ output low and gives the lowest priority bus
master in slot J4 the opportunity to assume control
Multibus.
The serial priority scheme can be implemented
designed system bus
signals are wired as shown in figure 5-3.
of
the Multibus.
J3
bus master the opportunity to
If
the
J3
bus master does not
if
the chaining
of
BPRO/ and BPRN/
it pulls its
BPRO/
of
in
a user-
of
the
A mating connector must be installed in the iSBC 604/604 Modular Cardcage and Backplane to accom-
modate auxiliary
Table 2-2 lists some 60-pin connectors that can
for this purpose; flat crimp, solder, and wirewrap con­nector types are listed. Table 2-13 correlates the signals and pin numbers on the connector.
Procure the appropriate mating connector for P2 and secure it
a. Position holes in P2 mating connector over mounting
b. From top
c. Install a flat washer, lock washer, and star-type nut
When the mating connector for P2 is in place, wire the power fail signals to the appropriate pins as listed in table 2-13. The dc characteristics signals interfaced via P2 are given in table 2-14. In a typical system, these signals would be wired as follows:
a. Connect auxiliary signal common and returns for
in
holes that are in line with corresponding connector.
head screws down through connector and mounting holes.
on each screw; then tighten the nuts.
~onnector
place as follows:
of
connector, insert two 0.5-inch
P2. (Refer to figure 1-1.)
be
PI
mating
#4-40
of
the connector
of
used
pan
the
+ 5 V, - 5 V, and + 12 V backup batteries to P2 pins
1,2,21,
and 22.
2-13
Page 28
Preparation for
Use
iSBC 86/12
Table 2·8. MuItibus Connectol·
Pin*
1 2 3
4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19
20
21 22
23 24 25 26 27 28 29 30 31 32
33
34
35
36
37
38 39 40 41 42 43
*AII odd-numbered pins
component side of the board with the extractors
Signal
GND GND 45 ADRC/
+5V +5V +5V +5V +12V +12V
-5V
-5V GND GND
BClK/ INIT/ BPRN/ BPRO/ BUSY/ BREa/ MRDC/ MWTC/ Memory Write Command 10RC/ 10WC/ XACK/ INH1/
BHEN/ ADR10/ CBRa/
ADR11/ CCLK/ ADR12/
INTN
ADR13/ INT6/ INT7/ INT4/ INT5/ INT2/ INT3/ INTO/ INT1/ ADRE/
} Ground
} Ground Bus Clock 56 ADR3/
System Bus Priority Bus Priority Out Bus Busy Bus Request Memory Read Command
I/O I/O Transfer Acknowledge Inhibit
Byte High Enable Address bus bit 10 Common Bus Request Address bus bit Constant Clock 74 Address bus bit 12 75 GND Interrupt Acknowledge Address bus bit 13
Interrupt request on level 6 78
Interrupt request on level 7
Interrupt request on level 4 Interrupt request on level 5 Interrupt Interrupt request on level 3 Interrupt request on level 0 Interrupt request on level 1
\
(1,3,,5
...
Function
Power input
Initialize
In
Read Command 64 DATB/ Write Command 65 DAT8I
RAM
request on level 2
85) are on component side of the board. Pin 1 is the left-most pin when viewed from the
PI
Pin Assignments
Pin*
44
46 47 ADRA/ 48 ADRB/
49
50 51 52 ADR7/ 53 ADR4/ 54 ADR5/ 505
Eo7
58 ADR1/ 5,9
60 61 62 63
66 67 DAT6/
68
69 DAT4/ 70 DAT5/ 71 7:2
11
73
715
Tl
7!} 80
8'1 82 83
84
85 GND
86 GND
at
the top. All unassigned pins are reserved.
Signal
ADRF/
ADRD/
ADR8I ADR9/ ADR6/
ADR2/
ADRO/
DATE! DATF/ DATC/ DATD/
DATN
DAT9/
DAT7/
DAT2/ DAT3/ DATO/ DAT1/
GND
+12V
-12V +5V +5V +5V +5V
>'
Address bus
Data bus
} Ground
Power input
J
Ground
}
Function
2-14
Page 29
iSBC
86/12
Table 2-9. Multibus Signal Functions
Preparation for
Use
Signal
ADRO/ADRFI ADR10/-ADR131
BClK/
BHENI
BPRNI
BPROI
BREQI
BUSYI
CBROI
Address.
Bus Clock.
Byte High Enable.
For
memory
on
the
address
by
the
cycle.
duty
These
access,
Multibus;
bit.
Used
iSBC
86/12, BClK/
20
lines
i.e.,
to
synchronize
When
Multibus.
Bus Priority
use
Bus Priority Out.
to
Bus Request.
master with
Bus Busy.
control of
Common Bus Request.
presently raises
of the
the
BClK/.
In.
bus.
BPRN!
requires
Indicates
the
have
the
CBROI
Indicates
BPRNI
In
serial
input
In
parallel priority
control of
that
bus.
BUSYI
control.
signal.
transmit
ADROI
ADROI
to
is
(daisy
of the
the
Indicates As
Functional Description
the
address
(when
active
the
low,
chain) master
active low
bus
of
enables
bus
priority
with
for
contention
master
with
is
has a period
active
a particular
synchronized
bus
resolution
the
bus
for
one
bus
is
in
that a
as
control
use
bus
is
synchronized
soon
of
the
memory
low)
enables
all
even
108.5
nanoseconds
the
that
BCLK!.
resolution
the
next
schemes,
or
more
and
prevents
with BClK/.
master
of the
bus
location or
the
addresses.
logic
on
all
odd
byte
no
higher priority
schemes,
lower
bus
BREOI
data transfers.
all
other
wishes
control of the
is
obtained,
VO
port
to
be
even
byte
ADR131
bus
masters.
(9.22
MHz)
bank
(DAT8I-DATF/)
BPROI
bank
is
the
with a 35-65 percent
bus
master
must
accessed.
(DATO/-DAT7/)
most
significant
When
generated
onto
is
requesting
be
connected
priority.
indicates that a particular
BREOI
is
synchronized
bus
the
requesting
masters
bus
from
but
bus
does not
controller
the
bus
gaining
CCLK!
DATO/-DATFI
INH11
INITI INTN INTOl·INT7/
IORCI
IOWCI
MRDCI
MWTC/
Constant Clock.
When
generated
with a 35-65 percent duty
Data.
These
memory
DATO/-DAT71
Inhibit RAM.
overlayed CPU
access of
Initialize. Inte"upt Interrupt Request.
Acknowledge. This
handler.
110
Read Command. Indicates that the
and
that
110
Write Command. Indicates that
and
that
Memory Read Command. Indicates that the
address data
lines.
Memory Write Command.
address
Provides a clock
by
16
bidirectional data
location
or
is
the
For
system
by
ROM/PROM
its
Resets
the
These
INTO
has
the
output of that port
the
contents
lines
and
lines
and
that the
signal
the
iSBC86112,
of ronstant
CClK/
cycle.
lines
VO
even
dual
entire
port
port.
byte
applications,
or
memory
RAM.
system
signal
CATF/
and
DAT8I·DATFI
to a known
is
issued'
transmit
is
allows
mappecll/O
eight lines transmit Interrupt
the highest priority.
address
is
to
be
the
Multibus
that
on
address
data lines
of that location
the
the
that
on
the
the
Indicates contents
contents
read
Multibus data
frequency
has a period
and
for
use
of 108.5 nanoseconds
receive
data
to
by
and
other
from
system
the
modules.
(9.22
MHz)
addressed
the most-significant bit. For data byte operations,
is
the
odd
byte.
iSBC
86112
dual
port
RAM
internal
in
response
of
an
(placed)
of
an are
address
address
devices.
state.
to
Requests
VO
port
onto
VO
port
to
be
of a
memory
are
to
of a
memory
lines
This
addresses
signal
has
no
an
interrupt
is
on
the
Multibus data lines.
is
on
accepted
be
read
are
to
request.
to
the
ap}>ropriate
the Multibus address lines
the Multibus
by
the addressed
location
is
(placed)
location
on on
is
on
be written into that location.
to
be
effect of local
interrupt"
address
tines
port.
the
Multibus
the Multibus
the Multibus
XACK/
Transfer Acknowledge. Indicates that
read data
or
write
lines.
operation.
That
is,
the
data
address
has
been
memory
placed
location
onto
or
has
completed
accepted
the specified
from
the
Multibus
2·15
Page 30
Preparation
for
Use
iSBC
86/12
Signals
AACK/, XACK/
ADRO/-ADRF/ ADR10/-ADR13/
BCLK/
Table 2-10. iSBC 86/12
Symbol
VOL VOH VIL VIH IlL IIH
*CL
VOL VOH VIL VIH IlL IIH ILH ILL
*CL
VOL VOH VIL VIH IlL IIH
*CL
Output Low Voltage Output High Voltage Input Input High Voltage Input Current Input Current at High V Capacitive Load
Output Low Voltage Output High Voltage Input Low Voltage 0.8 Input High Voltage
Input Current
Input Current Output Leakage High Output Leakage Low Capacitive
Output Low Voltage Output High Voltage
Input Input High Voltage 2.0 V
Input Current
Input c.urrent Capacitive
DC
Characteristics
Parameter
Description
Low Voltage
at Low V
at
Low V
at
High V
Load 18
Low Voltage 0.8
at Low V at
High V
Load 15 pF
Test
Conditions
IOL=
16 rnA
IOH = -3
VIN = O.4V
VIN
IOL IOH = 3mA
VIN VIN Vo = 5.25V
Vo =
IOL IOH
VIN VIN
rnA
= 2.4V
= 32 rnA
= 0.45V = 5.25V
0.45V
= 59.5
rnA
=
-3
rnA
= 0.45V = 5.25V 40
Min.
2.0
2.0
2.4
2.0
2.7 V
.Max.
.04 V
0.8
-2.2
-1.4 15 pF
0.55
-0.25 50
-0.25
-0.25
0.5 V
-0.5
Units
V V
V rnA rnA'
V V V
V rnA /LA rnA rnA
pF
V
rnA /LA
BHEN/
BPRN/
BPRO/
BREQJ
BUSY/,
CBRQJ,
INTROUT/
(OPEN
COllECTOR)
*Capacitive load values are approximations.
VOL VOH VIL VIH IlL IIH
*C
VIL VIH IlL IIH
*CL
VOL VOH
.*CL
VOL VOH
*CL
VOL
*CL
L
Output Low Voltage Output High Voltage Input
Low Voltage
Input High Voltage
at
Input Current Input Current at High V
Capacitive
Low Voltage
Input Input High Voltage 2.0 V Input Current
Input Current at High V Capacitive
Output Low Voltage Output High Voltage Capacitive
Output Low Voltage Output High Voltage Capacitive
Output Low Voltage Capacitive
Low V
Load 15 pF
at
Low V
Load
Load
Load
load
IOL
= 16 rnA
IOH = -2.0
VIN VIN
VIN
VIN
IOL IOH = -0.4
IOL
IOH = -0.4
IOL
rnA
= 0.4V = 2.4V
= 0.4V = 5.25V
= 3.2 rnA
rnA
=;<
20 rnA 0.45 V
rnA
= 20 rnA 0.4 V
2.4 V
2.0
2.4
2.4 V
0.4
0.8
1.6 40
0.8
-0.5 50 18
0.45 V
15
10
20
rnA /LA
rnA /LA
pF
pF
pF
pF
V
V
V
V
V
2-16
,
I.
Page 31
iSBC
86/12
Preparation for
Use
Signals
CCLKI
DATOI-DATFI
INH11
INITI (SYSTEM RESET)
Table 2-10. iSBC 86/12
Symbol
VOL VOH
*C
L
VOL VO
H
V
IL
V
IH IlL ILH
*C
L
V
IL
V
IH IlL IIH
*CL
VOL VO
H
V
IL V
IH IlL IIH
*CL
Parameter
Description
Output Low Voltage Output High Voltage
Capacitive Load
Output Low Voltage
High Voltage
Output Input Low Voltage Input High Voltage Input Current at Low V Output Leakage High Vo = 5.25V 100 Capacitive Load
Input Low Voltage 0.8 Input High Voltage 2.0 Input Current at Low Input Current at High Capacitive Load
Output Low Voltage Output
High Voltage OPEN
Input Low \Ioltage
Input High Voltage
Current at Low V
Input Input Current at High V Capacitive Load 15
DC
Characteristics (Continued)
Test
Conditions
IOL
= 60 rnA
10H = -3
10L 10H = -5
VIN
VIN VIN
10L
COLLECTOR
VIN VIN = 2AV
rnA
= 32 rnA
rnA
= OA5V
= 0.5V
= 2.7V
= 44 rnA
= OAV
Min.
2.7
2A
2.0
2.0
Max.
0.5
15
OA5
0.80
-0.20
18
-2.0 50
OA
0.8
-4.2
-1A
18
Units
V V
pF
V V
V V
rnA
J.lA
pF
V
V rnA J.lA
pF
V
V
V
rnA
mA
pF
*C
*C
*C
V
IL
V
IH
IlL
IIH
L
VOL VO
ILH
ILL
L
VOL VOL V
IL
V
IH IlL IIH
L
H
INTOi-lNT7
IORC/. IOWCI
INTN.
MRDC/.
MWTCI
*Capacitive load values are approximations.
Input Low Voltage
Input High Voltage
Current at Low V
Input Input Current at High V Capacitive Load
Output Low Voltage Output
High Voltage
Output Leakage High Vo = 5.25V Output Leakage Low Capacitive Load
Output Low Voltage Output High Voltage
Input Low Voltage Input High Voltage 2.0 Input
Current at Low V
Input Current at High V Capacitive Load
VIN
= OAV
VIN = 2AV
IOL
= 32 mA
10H = -5
Vo = OA5V
10L 10H = -5
VIN VIN
rnA
= 30 rnA
rnA
= OA5V
= 5.25
2.0
2A
2A
0.8
-1.6 40
18
OA5
100
-100 15
OA5
0.95
-2.0
1000
25
V
V rnA J.lA
pF
V
V J.lA J.lA
pF
V
V
V
V rnA J.lA
pF
2-17
Page 32
Preparation
for
Use
iSBC
86/12
Parameter
tAS tAH tos tOHw tcy tcMOR tcMOW tcSWR tcSRR tcsww tCSRW tXACK1 tSAM lACKRo lACKWT tOHR tOXL tXKH to
XL tews tes toey
tNOO
toeo
toeo 40
tecy tew tlNIT
Minimum
(ns) (ns)
-115
3000
Table 2-11. iSBC 86/12 AC Characteristics (Master Mode)
Maximum
50 50 50 50
198
202 430 430
380 380 580 Write-to-write 580 Write-to-read
-55 202 210 115 205
0
0 0
35
00
23
55
30
35
108
35
109
74
Address
Address Data
setup
Data
hold
CPU
cycle
Read
Write
Read
-to-write
Read-to-read
Command
Time AACK AACK
Read
Read XACK AACK Bus
clock BPRN BCLK BPRN BCLK/ BCLK/ Bus
clock
Bus
clock Initialization
Description
setup
hold
to
time
time command command
to
between
to
valid
or write
data
hold
data
setup
hold
time
to
XACK
low
to
BCLK
to
BUSY
to
BPRO
to
bus
to
bus
period low
width
---- -
----"
time
to
time
from
write
CMD
from
write
width
width command command
command command XACK
sample
XACK
samples
read
data
command
time
to
XACK
tum
off
or
high
intervals setup delay
delay request priority out
(BCLK)
or
high
interval
---
command
command
CMD
separation separation
separation separation
point
inactive
delay
time
No
wait
states With 1 wait In
override
In
override
In
override
In
override
In
override
In
override
When
AACK
When
AACK
Supplied
From From After
iSBC iSBC
all
voltages
by
Remarks
state mode mode mode mode mode mode
is
used
is
used
system
86/12
when
86/12
when have
terminated terminated stabilized
Parameter
tAS tos
toeD
tACK
tCMo tAH tOHw tOHR
t)I<H
tACC tlH tlPW
tCY tRO tOXL tcs
tiS
NOTES:
1.
No
refresh, dual port
2.
Maximum = tRO + toeD + tACK,
3.
Maximum
Minimum
(ns)
50
-200 Write data
720
0 0 0 0
50
100
30
200
access =
tACC + toeD + tRO.
Table 2-12. iSBC 86/12
Maximum
(ns)
Address
RAM
not
980 720
65
640
920 555
50
busy.
On-board Command Command Address Write
Read Acknowledge Read Inhibit Inhibit Cycle Refresh Read Command
. Inhibit
AC
Characteristics (Slave Mode)
Description
setup
to
command
setup
to
command
memory
hold data data
to data
hold pulse
time
delay
data
setup
cycle
to
XACK
width
time
hold
time
hold
time
hold
time
valid
time
width
of
board
time
setup
to
separation
time
delay
XACK
From
address
Note
1
No
refresh
Notes 1 and
Note
1
Acknowledge Note
3
Blocks
AACK
Remarks
to
command
2
turnoff delay
if
tiS > tiS
min.
2-18
Page 33
iSBC86/12
Preparation for
Use
BCLKJ
BREal
BPRNI
BUSYI
BPROI
ADDRESS
WRITE DATA
BCY
t
---.\
=.7
,.,'os~"
~
tBW--1
~
_________________
tDBO
__
tOBY
H
STABLE_DATA
~tBW
I 1
---,--JX
~''"''""W
L
___
T
_
611-4
WRITE COMMANDI
WRT AACKI
READ
READ DATA
READ XACKI
READAACKJ
---~.
Figure 2-3. Bus Exchange Timing (Master Mode)
\~4'----------~MDW----------~.~/
\
TACKWT~
---,\
~---------tCMDR--------~~
STABLE DATA
'OX,~
I
~
~
I
A--
--I-l--t
XKH
b~"
I
tACKRD
=1
~
I
2-19
Page 34
Preparation
for
Use
ADDRESS
MWTCI
XACK/
DATA
iSBC
86/12
~-----------------ICMD----------------~
~-----------IACK------------"'"
----t
lAS
~I-+------------~--~~
STABLE ADDRESS
IDS
--------~)<:r----------------------S-T-A-BL-E-D-A-T-A----------------------
I
ADDRESS
MRDCI
XACK/
DATA
lAS
liS
DUAL
PORT
RAM
STABLE ADDRESS
lACK
IACC
WRITE
IAH
INHll
611·5
2·20
IIPW
DUAL
PORT
RAM
READ
Figure 2-4. Bus Exchange Timing (Slave Mode)
~I
'
Page 35
iSBC
86/12
Preparation for Use
484-2
~
PRIORITY
BPRNI
(NOTE)
NO.2
J2
~
B N
-=
BREal
HIGHEST PRIORITY MASTER
BPRNI
o1L
LOWEST PRIORITY MASTER
BPRNI
J3
BPROI
~
'--
~
E
Ll
BPRNI
J2
BPROI
~
~
'--
C
Ml
-=
Figure 2-5. Serial Priority Resolution Scheme
~
NO.1
PRIORITY
(HIGHEST)
BPRNI
(NOTE)
J3
BREal
.Jio BPRNI
o-!!-
NO.7 PRIORITY
PRIORITY (LOWEST)
J4 J5
(NOTE) (NOTE)
BREal
01!-
J4
BPROI
~
BPROIAN NOTUSED MASTERS.
~
H
Kl
-=
NO.8
BPRNI
BREal
D BPRNI
BYNON-
iSBC604
BACKPLANE
(BOTTOM)
01!-
PINS
1-
I
-
B
- - -
f-
- - - - - - - - - - - - f--
A(
C D E F H G (BOTTOM)
L------r--f-------------I-I--------
BREal
INPUTS I
i:i~~CM6~~TERS
NOT
E:
REFER
TO
TEXT
484-1
DISABLING OF BPROI OUTPUT.
REGARDING
THE
Figure 2-6. Parallel Priority Resolution Scheme
BUS
PR10RITY
RESOLVER
-<
-<
7 6
4 3 2
0
P P R R
I I
0
R
I I T T Y Y
E D N E C C 0 0 D D E E R R
L-..c
:
C'
l-<
r-<: 1
710­6
0
R
41e>--
~~~~GTS
'~}
31e>--
TO
MASTERS
IN
iSBC
21>­1 0
614
f--
- - - - -
-1ISBC604 BACKPLANE
I
2-21
Page 36
Preparation for
Use
iSBC 86/12
Table 2-13. Auxiliary Connector
Pin*
1
2
3
4 7
8
11 12
19
20
21
22
32
38
*AII odd-numbered pins (1,3,5
the component side of the board with the extractors at the top.
Signal
GND GND
+5V
AUX
+5VAUX
-5VAUX
-5V
AUX
+12V
AUX
+12V
AUX
PFI!
MEM PROT/
GND GND
ALE
AUX RESET/
...
} Auxiliary common
}
Au,;';.",
Power Fai/lnterrupt. This externally generated signal, which is input
to the priority interrupt jumper matrix, to the 8086
Memory Protect. This externally generated
to the
}
Auxi,liary common.
Address Latch Enable. The
of every CPU/ machine cycle. This signal may be used as
auxiliary address latch.
Reset. The externally generated signal initiates a power-up
sequence; i.e., system to a known
59)
are on component side of the board.
P2
Pin Assignments
Definition
"ok""
batte<y
'''''''''
CPU NMI input.
dual port RAM during backup battery operation.
iSBC 86/12 activates ALE during
initializes the iSBC 86/12 and resets the entire
internal state.
Pin
1 is the left-most pin when viewed from
should normally be connected
signal prevents access
T1
an
Table 2-14. Auxiliary Signal (Connector
Signals
ALE
PFI
PROT/
MEM
RESET/
*Capacitance load yalues are approximations.
2-22
Symbol
VOL VOH
*CL
'VIL
VIH IlL IIH
*CL
VIL VIH IlL IIH
*CL
VIL VIH IlL IIH
*CL
P2)
DC
Characte~tics
Parameter
Description
Output Low Voltage Output High Voltage Capacitive
Input
Input High Voltage
Input Current Input Current at High V Capacitive
Input Input High Voltage 2.0 V
Input Current
Input Current at High V Capacitive
Input
Input High Voltage
Input Current
Input Current at High V Capacitive
Load
Low Voltage
at Low V
Load 20
Low Voltage
at Low V
Load. 15 pF
Low Voltage
at Low V
Load
Test
Conditions
IOL=8mA IOH = -1.0
VIN = O.4V VIN
VIN VIN
VIN VIN
rnA
= 2.4V
= 0.45V = 5.25V
= 0.45V = 5.25V 10
Min. Max. Units
2.4
2.4
2.6
0.45
'.
-0.4
0.80
--6.0 250
-0.25
,V
i-V
20
0.8 V
20
0.8
10
pF
rnA
pF
rnA p,A
rnA p,A p,F
V
p,
V
V V
Page 37
iSBC
86/12
Preparation for
Use
b.
Connect
-5V battery input to W4,
+5V
battery input to P2 pins 3 and
battery input to P2 pins 7 and 8, and + 12V
P2 pins
11
and 12. Remove jumpers
W5, and W6.
4,
c. Connect MEM PROTI input to P2 pin 20. d. Connect PFII input to P2 pin 19; this signal is inverted
To
and applied to the priority jumper matrix.
the
PFII input the highest priority (8086 NMI input),
assign
remove jumper 87-89 and connect jumper 86-89.
e.
Connect RESETI input to P2 pin 38. This signal is usually supplied by a momentary-closure switch mounted
on
the system enclosure.
f. Connect ALE output signal to P2 pin 32.
2-21. PARALLEL
Parallel I/O ports C8, Intel 8255 Programmable Peripheral Interface
I/O
CABLING
CA,
and CC, controlled by the
(PPI), are interfaced via edge connector J 1. (Refer to figure 1-1.) Pin assignments for connector dc characteristics table 2-16. Table
of
the parallel I/O signals are given in
2-2
lists some 50-pin edge connectors
that can be used for interface to
J1
are listed in table 2-15;
J1
and J2; flat crimp,
solder, and wirewrap connector types are listed.
The transmission path from the I/O source to the iSBC
86/12 should be limited to 3 meters (10 feet) maximum.
The
following bulk cable types (
or
equivalent) are recom-
mended for interfacing with the parallel I/O ports: a. Cable, flat, 50-conductor, 3M 3306-50. b. Cable, flat, 50-conductor (with ground plane), 3M
3380-50.
c.
Cable, woven, 25-pair,
An Intel iSBC 956 Cable Set, consisting assemblies, is recommended for parallel Both cable assemblies consist with a 50-pin
PC
connector at one end. When attaching
3M
3321-25.
of
I/O. interfacing.
of
a 50-conductor flat cable
two cable
the cable to J 1, be sure that the connector is oriented properly with respect to pin 1
(Refer
to
the footnote in table 2-15.)
2-22. SERIAL
I/O
on
the edge connector.
CABLING
Table 2-15. Parallel I/O Connector
J1
Pin
Assignments
Pln* Function
1 Ground 3 4 Port CA bit 6 5 7
9 10 11 13 15 Ground 16
17 Ground 18 Port 19 21 23 24 Port 25 26 27 29 31
33 35 37 39 41 43 44 45 46 Port C8 bit 1 47
49 Ground 50
*AII Odd-numbered pins (1,3,5,
side of the board. Pin 1 is the right-most pin when viewed from the component side of the board with the extractors at the top.
For
OEM
Ground 32 Port CC bit 7 Ground
Ground
applications where cables will be made
Pin*
2 Port CA bit 7
6 Port CA bit 5 8 Port CA bit 4
12 14
20 Port 22 Port CC bit 1
28
30
34
36
38 40 Port C8 bit 4 42
48
...
iSBC 86/12, it is important to note that the mating con­nector for J2 has 26 pins whereas the RS232C connector has 25 pins. Consequently, when connecting the 26-pin mating connector to 25-conductor flat cable, be sure that the cable makes contact with pins 1 and 2 (!onnector and not with pin 26. Table 2-17 provides pin correspondence between connector connector. When attaching the cable to the PC connector is oriented properly with respect to pin 1 on the edge connector.·(Refer to the footnote in table
Function
Port CA bit 3 Port CA bit 2 Port CA bit 1 Port CA bit 0
CC
bit 3
CC
bit 2
CC
bit 0
CC
Port Port Port CC bit 6
Port Port C8 bit 6 Port C8 bit 5
Port C8 bit 3 Port C8 bit 2
Port C8 bit 0
EXT
49) are on component
bit 4
CC
bit 5
C8 bit 7
INTRO/
for
of
the mating
J2 and an RS232C
J2, be sure that
2-6.)
the
Pin assignments and signal definitions for RS232C serial I/O interface are listed in table 2-6. An Intel iSBC 955 Cable Set is recommended for RS232C interfacing. cable assembly consists
of
a 25-conductor flat cable with a 26-pin PC connector at one end and an RS232C inter­face connector at the other end. The second cable assem­bly includes an RS232C connector at one end and has
spade lugs at the other end; the spade lugs are used to interface to a teletypewriter. (See Appendix A for ASR33
TTY interface instructions.)
One
2-23. BOARD INSTALLATION
Always turn
supply before installing iSBC 86/12 board and before installing
off
the computer system power
or
removing the
or
2-23
ii_
Page 38
Preparation
for
Use
Table
2-16. Parallel I/O Signal (Connector J1) DC Characteristics
iSBC 86/12
Signals
Port C8 Bidirectional Drivers
8255A Driver/Receiver
INTRO/
EXT
*Capacitive
load values are approximations.
Symbol
VOL VOH VIL VIH IlL
*CL
VOL VOH
V
IL
VIH
IlL IIH
*CL
VIL VIH IlL IIH
*CL
Parameter
Description
Output Low Voltage Output High Voltage
Input
Low Voltage
Input High Voltage
Input
Current at Low V
Capacitive Load
Output Low Voltage Output High Voltage
Input Low Voltage Input High Voltage Input
Current at Low V
Input Current at High V
Capacitive Load
Low Voltage
Input Input High Voltage Input
Current at Low V
Input Current at High V
Capacitive Load
Test
Conditions
10L
= 20
mA
10H = -12
VIN
= 0.45V
10L
= 1.7 mA
IOH = -200
VIN
= 0.45
VIN
= 5.0
VIN
= 0.4V
VIN
= 2.4V
mA
p.A
Min.
2.4
2.0
2.4
2.0
2.0
Max.
0.45 V
0.95
-5.25 18
0.45 V
0.8 V
10 10 18 pF
0.8
-1.0
-0.8 30
Units
V V V
mA
pF-
V
V p.A p.A
V
V mA mA
pF
removing device interface cables. Failure to take these precautions can result in damage to the board.
Table 2-17.
PC
Conn. J3
1 2 3 4 5 6
7
8
9 18
10
11
12 13
Connector
Pin
RS232C .
Conn.
14 14
1 15
15
2 17 22
16
3
17
4 5
19
6 25
20
J2
Vs
RS232C
Correspondence
PC
Conn.
J3
16
18 19 20 21 22 23 24
26
RS232C
Conn.
N/C
21
23 10 24 11 25 12
13
NOTE
Inspect the modular backplane and cardcage and ensure that pull-up regis tors have been included
for pins 27, 28, 30, 32, 33, and 34.
Eariier backplanes did not include pull-ups on these pins.
7
In an
8
9
"
iSBC 80 Single Board Computer based system, install the for a dedicated function. In an
iSBC 86/12 in any slotthat has not
Intellec System, install the iSBC 86/12 in any odd-numbered slot except another module in the Intellec System
beeq.
slqtl.
is
to supply the
BCLK/ and CCLK/ signals, disconnect 105-106
wired
If
and. 103-104 jumpers on the iSBC 86/12. Make sure that auxiliary connector
P2 (if used) mates with the user­installed mating connector. Attach the appropriate cable assemblies to connectors
11
and 12.
2-24
Page 39
CHAPTER 3
PROGRAMMING INFORMATION
3-1. INTRODUCTION
This chapter lists the dual port RAM, ROM/EPRON, and I/O address assignments, describes the effects hardware initialization (power-up and reset), and pro­vides programming information for the following pro­grammable chips:
a.
Intel
825lA
USART (Universal Synchronous/Asyn-
chronous Receiver/Transmitter) that controls the
serial
I/O port.
b.
Intel 8253 PIT (Programmable Interval Timer) that controls various frequency and timing functions.
c. Intel 8255A
face) that controls the three parallel
d. Intel 8259A
troller) that can handle up
intenupts for the on-board microprocessor.
This
chapter also discusses the Intel 8086 Micropro:::essor (CPU) intenupt programming with Intel's assembly language is gi the 8086 Assembly Language Reference Manual, Manual Order No.
PPI (Programmable Peripheral Inter-
I/O ports.
PIC (Programmable Intenupt Con-
to
64 vectored priority
capability. A complete descripLon of
9800640.
of
ven
3-2. FAILSAFE TIMEB
The 8086 CPU expects
turned from the addressed
sponse to each Read
includes a Failsafe Timer that every machine cycle. If the Failsafe Timer hardwire jumper as described acknowledge signal milliseconds after the command Timer will time out and allow the state. As described in the Failsafe Timer output (TIME used to
If the Failsafe Timer and an acknowledge signal is not returned for any reason, the CPU will hang up in a wait state. In this situation, the only way to free the described
intenupt the CPU.
in
paragraph 3 -7 .
3-3" MEMORY ADDRESSING
The iSBC 86/12 includes 32K bytes access memory (RAM) and four
an
acknowledge signal to
I/O
or
memory device
or
W rite Command. The iSBC g6/
is
triggered during
is
enabled
in
table 2-4, and no
is
received within approximately 6
is
issued, the Failsafe
CPU to exit the wait
Chapter 2, provision
OUT/) can optionally be
is
not enabled by hardwire jumper
CPU
is
to initialize the
IC sockets to accom-
is
made
sys!:em
of
dynamic random
be
in
Tl
so
re­re-
12
of
by
that
as
mod ate memory dual port RAM access anangement RAM can be accessed
a
processor
Multibus. The CPU.
The dual port RAM can be accessed by another bus master that noted that, even though another bus master may be con· tinually accessing the dual port RAM, this does not pre­vent the When this situation occurs, memory accesses and controlling bus master are interleaved. Such inter-
leaved access will,
both for the
Dual-port RAM access by another bus master does not interfere with the CPU while it ROM/EPROM and I/O devices.
in
up
to
16K bytes
(ROM
or
EPROM). The iSBC 86/12 features a
(CPU) or by another bus master via the
ROM/EPROM can be accessed only
cunently has control
CPU from also accessing the dual port RAM.
of
CPU and for the controlling bus master.
of
user-installed read-only
in
which the on-board
by
the on-board 8086 micro-
of
the Multibus. It should
course, impose a longer wait state
is
accessing the on-board
3-4. CPU ACCESS
Addresses for CPU access
board RAM are provided ROM/EPROM addresses are assigned from the top down of
the I-megabyte address space with the bottom address being determined by the user tion. The on-board RAM addresses are assigned from the bottom up
When the ROM, automatically generated and imposes one wait state for each
memory via the Multibus, the CPU must first gain control
of
the Multibus and, after the Memory Read
Write
Acknowledge memory device. The Failsafe Timer, if enabled, will prevent a
equipment failure
It should be noted in table 3-1 that ure an illegal address Write edge signal and the ever,
of
the 1-megabyte address space.
CPU
is
addressing on-board memory (RAM,
or
EPROM), an internal acknowledge signal
CPU operation. When the CPU
Command
CPU hang-up in the event
ROM/EPROM such
Command
CPU wilI continue executing the program. How-
in
this case, enoneous data will be returned.
(XACK!)
is
to
is
generated
is
or
used
ROM/EPROM, an internal acknowl-
of
ROM/EPROM and on-
in
table 3-1. Note that the
ROM/EPROM configura-
is
addressing system
given, must wait for a Transfer
to be received from the addressed
of
a memory device
a bus failure.
it
is
possible to config-
as
to
create illegal addresses.
in
conjunction with a Memory
as
though the address was legal
by
the CPU
or
Memory
by
the
be
is
If
3-\
Page 40
Programming Information
Table 3-1. On-Board Memory Addresses (CPU Access)
iSBC
86112
Type
EPROM
ROM
RAM
Configuration
Two
2758
Four 2758 chips Two
Four 2716 chips Two
Four Two
Four
Sixteen 2117 chips
chips
2716 chips
2316E chips
2316E
chips
2332 chips
2332
chips
3-5. MUL TIBUS ACCESS
As described in paragraph 2-12, the iSBC 86/12 can be
configur~
32K bytes 8-bit and 16-bit masters to reside in the same system and, to accomplish this, the memory data banks to form one 16-bit word. The banks are organized such that all even bytes are in one bank (DATO-DAT7) and bank (DAT8-DATF).
The Byte High Enable (BHEN/) signal controls the odd data byte and, when active, enables the high (DAT8/-DATF/) onto the Multibus. Address bit controls the even data byte and, when active. enables the
low byte (DATO/-DAT7/) onto the Multibus. For
. maximum efficiency. 16-bit word operations must occur
on an even byte boundary with BHEN/ active. Address bit ADRO/ addressing requires two operations to form a 16-bit word.
to
permit Multibus access
of
on-board RAM. The Multibus allows both
alL
odd bytes are in the other
of
8K, 16K, 24K,
is
divided into two 8-bit
or
byte
ADRO/
is active for all even byte addresses. Odd byte
Legal Addresses
FF800-FFFFF FFOOO-FFFFF
FFOOO-FFFFF FEOOO-FFFFF
FFOOO-FFFFF FEOOO-FFFFF
FEOOO-FFFFF FCOOO-FFFFF
0OOO-07FFF
REF
A
B
MEMORY
DATA
PATHS
Illegal Addresses
FFOOO-FF7FF
-
FEOOO-FEFFF
-
FEOOO-FEFFF
-
FCOOO-FDFFF
-
-
BHENI
DATO/-DAT7/
DAT8/·DATF/
ADRo/
o
USED
:u"s
MASTERS
8-B1T.
16-BIT.
OR
MIXED
8-B1T
Byte operations can occur in two ways. The even byte can
be
accessed by controlling ADRO/. which places the data on the DATO/-DAT7/lines. (See figure 3-1A.) To access the odd data bank. which normally is OAT8/-DATFI lines, a new data path
thactive .slate
buner
of
ADROi
that
places the odd data barik on DATO/-DAT7/.
and BHENI enable a
(See figure 3-1B.) This permits an
access both bytes
of
a data word by controlling only
ADRO/.
Figure 3
16-bit word by a single address on an even byte boundary.
Figure 3-1A illustrates how a 16-bit bus master may
selectively address an even (low) data byte.
3-2
-1
C illustrates how a 16-bit bus master obtains a
8-Ott
placed
is
bus
jID
the
defined. The
Sloll1Ip
~te
master
to
--
c
Figure 3-1. Dual Port RAM Addressing
645-4 (Multibus Access)
o
16-BIT
Page 41
iSBC
86/12
Programming Information
3,-6.
I/O ADDRESSING
The CPU communicates with the one board programmable chips through a sequence Commands. As shown in table
recogll1izes four separate hexadecimal are used to control
VO
(The
address decoder operates
the:
of
VO
Read and
3-2,
each
VO
VO
of
these chips
addresses
Write
that
various programmable functions.
on
the lower eight bits and all addresses must be on an even byte boundary.) Where two hexadecimal addresses are listed for a single function, either address may be used. For example, an Read Command to of
the 8251A USART.
OOODA
or
OOODE
will read the status
VO
Table 3-2. I/O Address Assignments
I/O
Address*
OOOCO
or
000C4 000C2
or
000C6
Chip
Select
8259A
PIC
3-7. SYSTEM INITIALIZATION
When power
signal following:
a.
The 8086 CPU internal registers are set as follows:
PSW 0000
IP 0000 OS 0000 ES 0000 Code
This effectively causes a long
is
initially applied to the system, a reset
is
automatically generated that performs the
Relocation Register =
Function
Write: ICW1, OCW2, and OCW3
Read:
Status and Poll
Write: ICW2, ICW3, ICW4, OCW1 (Mask) Read:
OCW1
(Mask)
FFFF
JMP
to FFFFO.
000C8
OOOCA
OOOCC
OOOCE
OOODO
000D2
000D4
000D6
000D8
or
OOODC OOODA
or
OOODE
8255A
PPI
8253
PIT
8251A
USART
Write: Port A (J1) Read: Port A (J1)
Write: Port B Read: Port B (J1)
Write: Port C (J1) Read: Port
Write: Control Read: None
Write: Counter 0 (Load Count 7 Read: Counter 0
Write: Counter 1 (Load Count 7 Read:
Write: Counter 2 (Load Count 7 Read: Counter 2
Write: Control Read: None
Write: Data (J2) Read: Data (J2)
Write: Mode or Command Read: Status
(.11)
C Status
Counter 1
N)
N)
N)
*Odd addresses
(i.e,.,
000C1, 000C3,
.....
OOOD!))
are illegal.
3-3
Page 42
Programming
b.
The mode, waiting for a set
Information
825lA
US
ART serial
VO
port
is
set
of
Command Words
to
the'
'idle"
to
pro-
gram the desired function.
c. The 8255A
PPI parallel
VO
ports are set
to
the input
mode.
The 8253
PIT and the 8259 PIC are not affected by the
power-up sequence.
The reset signal
the remainder
is
also gated onto the Multibus
of
the system components
to
initialize
to
a known
internal state.
The reset signal can also be generated by an auxiliary
RESET switch. produces the same effect
Pressing and releasing the RESET switch
as
the power-up reset described
above.
I
scs
I ESD I
EP
I PFN I
L21
L,
I 0 I 0 J
I
CHARACTER LENGTH
1
0
0 0 1
5 6
BITS
BITS
PARITY ENABLE
11
c
ENABLE DISABLEI
PARITY EVEN ODD
I
(0 -
EVEN
1 -
0
iSBC 86/12
0
7
BITS
GENERA
1
1
8
BITS
nON/CHE
CK
3-8.
8251
A USART PROGRAMMING
The USART converts parallel output data into virtually
any serial output data fonnat (including IBM Bi-Sync) for
US
half- or full-duplex operation. The
ART also converts
serial input data into parallel data fonnat.
Prior
to
starting transmitting
US
ART must be loaded with a set
or
receiving data, the
of
control words. These
control words, which define the complete functional op-
of
eration
the USART, must immediately follow a reset (internal or exterrtal). The control words are either a Mode instruction or a Command instruction.
3·9. MODE INSTRUCTION FORMAT
The Mode instruction word defines
of
teristics
the USART and must follow a reset operation.
Once the Mode instruction word has been written into the
USART, sync characters
be
inserted. The Mode instruction word defines the
or
command instructions may
following: a. For Sync Mode:
(I)
Character length
(2)
Parity enable (3) Even/odd parity generation and check (4)
External
sync
detect
86/IX)
(5) Single
or
double character sync
b. For Async Mode:
(1) Baud rate factor
(Xl,
(2) Character length
Parity enabie
(3) (4) Even/odd parity generation and check
of
(5) Number
stop bits
the
general charac-
(not
supported
X16, or X64)
by
NOTE-
IN
EXTERNAL
SYNC
WILL
SYNC
AFFECT
MODE,
PROGRAMMING
ONl Y THE
EXTERNAL 1 ~ SYNDET
0
~NGLECHARACTERSYNC
1 o
Tx
$Y"JOET IS
SINGLE
SYNC
DOUBLE
DOUBLE
SYNC
IS
SYNC
Figure 3·2. USART Synchronous Mode
Instruction Word Format
CPU
BYTES
158
CHARACTFRS
SERIAL
2
-'-
DATA
BYTES
DATA
BITS/CHARI
----,
1-1
--_
DATA
OUTPUT
DATA
___
INPUT
DA
T A
158
BITS/CHARI
1-,
----,
CHARACTERS
-;1 ,..,
___
....
IhDI
CH:R~ACTERS
---I.
_---
IR,DI
CHAR~
....
....I
RECEIVE
'--
FORMAT
SYNC
CHAR
__
,...---__<11-1
'-------II
ASSEMBLED
1
CHAR
-L
___
r-----;,
'--
DATA
SYNC
SERIAL
CPU
___
DETECT
AN
INPUT
AN
OUTPUT
CHARACTER
CHARACTER
CHARACTER
C-TE-R-S
_---.oJ
.....
Instruction word and data transmission fonnats for syn­cnronous and asynchronous modes are shown in figures 3-2 through 3-5.
3-4
Figure 3-3. USART Synchronous Mode
Transmission Format
Page 43
iSBC
86112
Programming Information
'--
'-------\
'---------
_______
.;,
~IAREI~~:LNtBLoE"
~
~VEE~~~RIT~
INVALIO
IONL Y EFFECTS Tx; REQUIRES MORE THAN ONE
STOP
CHARACTER
NUMBER
BITI
LENGTH
,,;,
.;,
DISABLE
~~~~RATION/CHECK
OF STOP
BITS
"11
BiT
BITS BITS
Rx
Figure 3-4. USART Asynchronous Mode
Instruction Word Format
,,;,
2
NEVER
TRANSMITTER
RECEIVER
INPUT
RxD
TR ANSMISSION
L-_~
RECEIVE
FORMAT
STArn
'-----'-----/
·NOTE
OUTPUT
BIT
START
L-
__
FORMAT
ASSEMBLED
___
IF BITS
CHARACTER
0001
DO
D1 - -
! f \
BIT
.---------11
DATA
-'-
__
,...;
---..--'
PROGRAMMED
CHARACTER
LENGTH
CPU
BYTE
(~18
DATA
C'~~RACTER
SERIAL
~'---~---'--~[J
(lATA
CHARACTER
~~,
____
SE~IAL
DATA INPUT !AxD)
DATA
CHARACT£R
f-----'------'--i
CPU
BYTE
15 B BITS/CHARI·
DATA
CHARACTER
L------f,
LENGTH
THE
UNUSED
BITS
GENERATED
Ox
BY
8251A
DOES
NOT
ON
___
THE
DATA
IhDI
~
AS 5 6 OR 7
TO
"lERC),"
APPEAR
BUS
__
--Ox
~-r----'-~---I
BITS
r----'L-----'
BITS/CHAR)
DATA
OUTPUT
-i
~,
---..,
1-1
---~
IS
DEFINED
ARE SET
ST6;I
BrrS
L
fL
STOP
BITS
STOP
BITS
~
sl~oD
BITS
J-I0.
SYNC CHARACTERS
Sync characters are written to the USART in the syn­chronous mode only. The USART can be programmed to either one characters is at the option
~I-ll.
The Command instruction word shown in figure
trols the operation
or
two sync characters; the format
of
the programmer.
of
the sync
COMMAND INSTRUCTION FORMAT
3-6
con-
of
the addressed USAR T. A Command instruction must follow the mode and/or sync words. Once the Command instruction is written, data can be transmitted
lit
is not necessary for a Command instruction to precede
or
received by the USART.
all data transactions; only those transmissions that require a change in the Command instruction. An example change in the enable transmit
or
enable receive bus.
is
Command instructions can be written to the USART at any time after one
or
more data operations.
After initialization, always read the chip status and check 1;:>r
the TXRDY bit prior to writing either data
or
com-
mand words to the USART. This e:nsures that any prior
iJilput
is not overwritten and lost. Note that issuing a
Figure 3-5. USART Asynchronous Mode
Transmission
Command instruction with bit 6 (lR) set will return the USART to the Mode instruction format.
Format
3-12. RESET
To change the Mode instruction word, the USART must
receive a Reset command. The next word written to the USART after a Reset command
is
assumed to be a Mode instruction. Similarly, for sync mode, the next word after a Mode instruction
is
assumed to be one
or characters. All control words written into the USART after the Mode instruction (and/or the sync character) are
a
assumed to be Command instructions.
3-13. ADDRESSING
The USART chip uses address and write I/O data; address write mode and command words and read the USART status. (Refer to table 3-2.)
OOOD8
OOODA
or
or
OOODE
OOOJDC
more sync
to read
is
used to
3-5
Page 44
Programming Information
iSBC 86/12
o 0
,
I EH I
6
IR I RTS I
03 O2 0,
4
ER I SBRKI
RxE I OTR I
hEN
-
DO
L
TRANSMIT
1
'"
enable
o
'"
disable
DATA
TERMINAL
READY
"high"
will
output
RECEIVE
1 =
o
force
to
zerO
ENABLE
enable
co
dIsable
SEND
BREAK
CHARACTER
1
::
forces
lllO
o
'"
normal
operation
ERROR RESET
1
'"
reset
error
PE.
OE.
FE
REQUEST
TO
"high"
will
force
output
to
lero
INTERNAL
"high:'
returns
Mode
Instruction
ENABLE
-
OTR
"low
flags
SEND
RESET
82S1A
Format
RTS
ADDRESS
OOODA OOODA OOODA OOODA
00008
OOODA
00008
.'
OOODA
*The second sync character
programmed USART to Both sync characters
RESET
MODE
INSTRUCTION SYNC SYNC
COMMAND
COMMAND
"
COMMAND
CHARACTER CHARACTER
DATA
DATA
1 2
INSTRUCTION
110
INSTRUCTION
1/0
INSTRUCTION
is
skipped
SYNC
MODE
}
ONLY'
if
Mode instruction has
single character internal sync mode.
are
skipped if Mode instruction has
programmed USART to async mode.
Figure 3·7. Typical USART Initialization
645·5 and Data I/O Sequence
to
ENTER
1 Characters
Note:
Error
Reset
must
be
Enter
Hunt
are
programmed.
performed
whenever
Figure 3-6. USART Command
Instruction Word Format
3-14. INITIALIZATION
A typical USART initialization and
presented in figure 3 -7. The USAR T chip
four steps:
US
ART
to
a. Reset
Mode instruction fonnat.
b. Write Mode instruction word.
word
is
to specify synchronous
operation.
If
synchronous mode
c.
sync characters
as
required.
is
d. Write Command instruction word.
VO
One function
selected, write one or two
HUNT
'"
• (HAS NO EFFECT
MODE'
enable search for Sync
IN ASYNC MODE)
RxEnable
data sequence
is
initialized in
of
mode'
or
asynchronous
and
is
To avoid spurious interrupts during
US
disable the
ART interrupt. This can be done by either
US
ART initialization,
masking the appropriate interrupt request input at the
or
by
8259A PIC
by
rupts
executing a DI instruction.
First, reset the struction tolocation instruction must have bit 6 set (IR
disabling the 8086 microprocessodnter-
USART chip by writing a Command in-
OOODA
(or
OOODE).
The Command
= 1); all other bits are
immaterial.
NOTE
This reset procedure should be used only if the
USART has been completely initialized,
or
the initialization procedure has reached the point that the word. For example, if the reset command
USART
is
ready to receive a Command
is written when the initialization sequence calls for a sync character, then subsequent program­ming will be in error.
to
Next write a Mode instruction word
the USART. (See
figures 3-2 through 3-5.) A typical subroutine for writing
is
both Mode and Command instructions
given in table
3-3.
US
ART
is
If the
programmed for the synchronous mode, write one or two sync characters depending on the trans­mission fonnat.
3-6
Page 45
iSBC
86/12
Table
3-3. Typical
;CMD2 OUTPUTS CONTROL WORD TO USART. ;USES-A, STAT2; DESTROYS-NOTHING.
USART
Mode
or
Command
Instruction
Programming Information
Subroutine
PUBL.IC
EXTRN CMD2: LP:
511NT:
LAHF
PUSH
CALL.
AND
JZ POP SAHF OUT
RET
END
Finally, write a Command instruction word USART. Refer to figure
3-6
and table 3-3.
CMD2 STAT2
AX STAT2 AL,1 L.P
AX
ODAH
to
the
IMPORTANT: During initialization, the 8251A USART requires a minimum recovery time (16 clock cycles) between back-to-back writes
of
3.2 microseconds in
order to set up its internal registers. This recovery time can be satisfied by the CPU performing two byte reads and a NOP between the back-to-back writes USART
OUT
SAHF NOP
OUT
as
follows:
ODAH
ODAH
;FIRST USART WRITE ;TWO-BYTE ;ADDED WAIT ;SECOND USART WRITE
RIEAD
tOo
the 8251A
This precaution applies only to the USART initialization and does not apply otherwise.
3-15. OPERATION
Normal operating procedures use data I/O read and write, status read, and Command instruction write operations. Programming and addressing procedures for the above are summarized in following paragraphs.
NOTE
After the USART has been initialized, always
check the status writing data the
USART. The TXRDY bit prevent overwriting and subsequent loss command inactive until initialization has been completed; do not check word, which concludes the initialization dure, has been written.
of
the TXRDY bit prior to
or
writing a new command word to
must
be true to
or
data words. The TXRDY bit
TXRDY until after the command
of
is
proce-
;CHECK TXRDY ;TXRDY MUST
;ENTER HERE
Prior
to
any operating change, a new command word must
be
written with command bits changed as appropriate.
(Refer
to
figure 3-6 and table 3-3.)
3-16. DATA
BE
TRUE
FOR INITIALIZATION
INPUT/OUTPUT.
For
data receive or transmit operations, perfonn a read or write, respectively, to the
USART. Table 3-4 and 3-5 provide examples
of
typical character read and write subroutines.
During normal transmit operation, the USART generates
a Transmit Ready (TXRDY) signal that indicates that the
USART sion.
character into the
Similarly, during normal receive operation, the
is
ready to accept a data character for transmis-
TXRDY
is
automatically reset when the CPU loads a
US
ART.
USART generates a Receive Ready (RXRDY) signal that indicates that a character has been received and
CPU. RXRDY
the is
read by the CPU.
is
automatically reset when a character
The TXRDY and RXRDY outputs
is
ready for input to
of
the USART are
available at the priority interrupt jumper matrix. If, for
instance,
TXRDY and RXRDY are input
to
the 8259A PIC, the PIC resolves the priority and interrupts the CPU. TXRDY and RXRDY are also available
in
the status
word. (Refer to paragraph 3-16.)
3-17.
STATUS
of
status
a serial I/O port to the upper address chip. The format
A typical status read subroutine
READ" The CPU can determine the
by
issuing an I/O Read Command
(OOODA
of
the status word
or
OOODE)
is
is
shown
given
of
the USART
in
figure 3-8.
in
table 3-6.
3-7
Page 46
Programming Information iSBC 86/12
Table 3-4. Typical USART Data Character Read Subroutine
;RX1
READS DATA CHARACTER FROM USART.
;USES-STATO; DESTROYS-A,FLAGS.
RX1,RXA1 STATO
STATO AL,2 RX1 ODCH
RX1
:
RXA1:
PUBLIC EXTRN
CALL AND JZ IN RET
END
Table 3-5. Typical USART Data Character Write Subroutine
;TX1
WRITES DATA CHARACTER FROM REG A TO US ART.
;USES-STATO; DESTROYS-FLAGS.
TX1
:
TX11 :
TXA1:
PUBLIC EXTRN
PUSH CALL AND JZ POP
OUT
RET
TX1,TXA1
STATO
AX
STATO AL,1
TX11
AX
OD8H
;CHECK FOR RXRDY TRUE ;ENTER HERE
;CHECK FOR TXRDY TRUE
;ENTER HERE
IF RXRDY IS TRUE
IF TXRDY IS TRUE
END
3-18. 8253 PIT PROGRAMMING
A 22.1184-MHz crystal oscillator supplies the basic clock frequency for the programmable chips. This clock fre-
is
quency
divided by 9, 18, and 144
jumper-selectable clocks: 2.46 MHz, 1.23 MHz, and
153.6 kHz. These clocks are available for input to Counter
0,
Counter
1,
and Counter 2
of
the 8253 PIT. The default
(factory connected) and optional jumpers for selecting the
to
clock inputs
the three counters are listed in table 2-4.
Default jumpers connect the output TXC and RXC inputs
included so that Counters interrupts to the 8259A
of
the 8251A
0 and 1 can provide real-time
PIC.
Before programming the 8253 PIT, ascertain the input
clock frequency and the output function
three counters. These factors are determined and estab-
by
lished
the user during the installation.
to
produce three
of
Counter 2
US
ART. Jumpers are
of
each
to
of
the
the
3-19. MODE CONTROL WORD AND COUNT
All three counters must be initializc:d prior to their'use.
of
The initialization for each counter consists
a.'
A mode control word (figure 3-9) is written to the
control register for each individual counter.
b.
A down-count number the down-count number
as
determined by mode control word.
is
loaded into each counter;
is
in one
The mode control word (figure 3-9) does the following: a. Selects counter to be loaded. b. Selects counter operating mode. c. Selects one
of
the following four counter read/load
functions:
(1) Counter latch (for stable read operation)
(2) Read
or
load most-significant byte only.
two steps:
or
two 8-bit bytes
3-8
Page 47
iSBC
86/12
DSR
I
SYNDET
I
When
set
"""m,,
cates
that
achieved
FE I DE
FRAMING
FE
flag detected is
reset tion.
FE
8251.
for
internal
character
and
8251
OVERRUN
The not one the OE
8251;
character
--
ERROR
is
set
when a valid
at
end
by
ER
does
sync
sync
is
fIlady
PE
I
ERROR
OE
fla!l
is
set read a character becomes
available.
ER
bit
of
the
does
not
inhibit
howllver,
the
is
lost.
(ASYNC
ONLY)
stop
of
every
character.
bit
of
Command
not
inhillit
operaton
detect,
indio
a
has
bel,n
for
data.
TXE
I
when
the
before
It
Command
operation previously
bit
is
not It
instruc-
of
I
CPU
the
is
reset
instruction.
of
overrun
is
next
DO
RSRDY I TXRDY
I
does
by
the
~
I
'---
~
TRANSMITIER
RECEIVER
TRANSMIITER
PARITY
PE detected.
operation
Indicates
data
character
Indicates
acter
on
to
transfer
Indicates verter
ERROR
flag
mand
instruction.
USART
READY
USART
its
it
that
in
transmitter
is
set
It
is
of
Programming Information
READY
is
ready
to
accept
and
serial
bit not
is
error
of
ready
con·
is
Com-
inhibit
a
or
command.
has
received a char-
selrial
input
t~1
the
CPU.
EMPTY
parallel
is
when a parity
reset
by
PE
does
8251.
to
empty.
ER
DSR
is
general
purpose.
"''' m ""'"'
used
to
test
Set
modem
Ready.
Data
Nonnally
conditions
~
such
as
Figure 3-8. USART Status Read Format
---------------------------
(3) Read (4) Read or load least-significant byte first, then
d.
Sets counter for either binary or BCD count.
The mode control word and the count register bytes for any given counter must be entered
sequence:
a..
Mode control word.
b,
Least-significant count register byte.
_.
Most-significant count register byte,
or
load least-significant byte only,
most-significant byte.
;STATO READS STATUS FFlOM USART. ;DESTROYS-A.
in
the following
Tabh!
3-6. Typical USART Status Read Subroutine
As
long
as
the above procedure
counter, the chip can
be
programmed
is
followed for each
in
any convenient sequence, For example, mode control words can be loaded first into each by the least-significant byte, etc. Figure
of
three counters per chip, followed
3-10 shows the two programming sequences described above.
Since
all
counters
value loaded
in
the PIT chip are downcounters, the
in
the count registers
is
decremented, Load­ing all zeroes into a count register results in a maximum countof2
16
for binary numbers
of
104 for BCD numbers.
PUBLIC
STATO:
IN
RET END
STATO ODEH
;GET STATUS
3-9
Page 48
Programming Iuf'onnation
iSBC
86/12
I
"
"
~
(BI NARY/BCD)
o Binary Counter (16-bits)
M2
0 0 0 0
X 1 X
RL1
a
0
Binary Coded (4 Decades)
M1
MO
(MODE)
a Mode a
1 Mode 1
Mode 2
0
1
1 Mode 3
0 0
RLO
Mode 4
a
Mode 5
(READ/LOAD)
0 Counter Latching operation (refer
to paragraph 3-29).
0 Read/Load most significant byte only.
1 1 Read/Load least significant byte first.
Read/Load
then most significant byte.
Decimal (BCD) Counter
~
Use Mode 3 for Baud Rate Generator
least significant byte only.
SC1
0 0
611-7
Figure 3-9. PIT
Mode
When a selected count register is to be loaded, it mUst be
loaded with the number control word.
One
on the appropriate down count. These two bytes can
of
bytes programmed in the mode
or
two bytes can be loaded, depending
be
programmed at any time following the mode control
of
bytes
is
word, as long as the correct number
loaded in
order.
The count mode selected in the control word controls the counter output. As shown in figure 3-9, the PIT chip can
of
operate in any a. Mode
Counters 1 and 2 can such
as
six modes: .
0:
Interrupt on terminal count. In this mode,
be used for auxiliary functions,
generating real-time interrupt intervals. After
SCO
a Select Counter a
1 1 1
a Select Counter 2
1
Control Word Fonnat
the count value is loaded into the count register, the counter output goes low and remains low until the terminal count is reached. The output then goes high until either the count register register
b.
Mode
1:
of
output the count following the rising edge
from Port CC (assuming Port CC jumpers are so configured). The output will go high on the terminal
If
count. is
low, it will not affect the duration shot pulse until the succeeding trigger. The current count can be read at any time without affecting the
(SELECT COUNTER)
Select Counter 1
Illegal
or
the mode control
is
reloaded.
Programmable one-shot. In this mode, the
Counter 1 and/or Counter 2 will go low on
of
the GATE input
a new count value
is
loaded while the output
of
the one-
3-10
Page 49
isnc
86/12
Programming Information
PROGRAMMING
Step
1
2
3
LSB
MSB
FORMAT
Mode ( ;ontrol Word
Cc
Count F
Count F
legister Byte lunter n
Cc
~egister
(~(
)unter n
,unter n
Byte
ALTERNATE
Step
1
2
3
4 LSB
5 MSB
6
7 MSB
8 LSB
9
PROGRAMMING
Mode
Mode
Mode
Counter Register Byte
Count Register Byte
LSB
MSB
Count Register Byte
Count Register Byte
Count Register Byte
Count Register Byte
FORMAT
Control Word
Counter
Counter 1
Counter 2
Counter 1
Counter 1
Counter 2
Counter 2
Counter
Counter
0
Control Word
Control Word
0
0
450-18
one-shot pulse. The one-shot
Figure 3-10.
is
retriggerable, hence
PIT
the output will remain low for the full count after any rising edge
c. Mode
of
the gate input.
2:
Rate generator. In this mode, the output Counter 1 and/or Counter 2 will be low for one period of
the clock input. The period from one output pulse to the next equals the number count register.
If
the count register
of
input counts
is
reloaded be-
tween output pulses, the present period will not be
affected but the subsequent period will reflect the new value. The gate input, when low, will force the output
high. When the gate input goes high, the counter will
start from the initial count. Thus, the gate input can be used to synchronize the counter. When Mode 2 the output will remain high until after the counter register is loaded; thus, the count can be synchronized by software.
d. Mode
3:
Square wave generator
..
Mode 3, which the primary operating mode for Counter 2, generating Baud rate clock signals.
In
this mode, the counter output remains high until one-half count value
in
the count register has been dec­remented (for even numbers). The output then goes low for the other half count register is odd, the counter output (N + 1 )/2 counts, and low for
of
the count. If the value
(N
- 1 )/2 counts.
is
Programming Sequence Examples
e. Mode
4:
Software triggered strobe. After this mode set, the output will be high. When the count the counter begins counting. On terminal count, the
of
output will go low for one input clock period and then go high again. If the count register tween output pulses, the present count will not be
in
the
affected, but the subsequent period will reflect the new value. The count will be inhibited while the gate input
is
low. Reloading the count register will restart
the counting for the new value.
f.
Mode
5:
Hardware triggered strobe. Counter 0 and/or Counter 1 will start counting on the rising edge gate input and the output will go low for one clock
is
set,
period
counter
when.
is
retriggerable. The output will not go low
until the full count after the rising edge
input.
is
is
used for
of
the
Table 3-7 provides a summary
versus the gate inputs. The gate inputs
in
the
high for
are tied high
by
default jumpers; these gates may option­ally be controlled is
not optionally controlled.
the terminal count
of
by
Port
Cc.
The gate input to Counter 2
is
is
loaded,
is
reloaded be-
of
the
is
reached. The
of
the gate
the counter operation
to
Counters 0 and 1
3-11
Page 50
Programming Information
iSBC
86/12
Table 3-7.
Modes
~
Status
0
1
2
3
4
5
PIT
Counter Operation
Low
Or Going
Low
Disables
counting
- 1 )
1)
Disables
counting
2)
Sets output
immediately high
1 )
Disables
counting
2)
Sets output
immediately high
Disables counting
-
Rising
-
Initiates
counting
2)
Resets output
after next clock
Initiates counting
Initiates counting
-
Initiates counting
Vs
Gate Inputs
High
Enables counting
-
Enables counting
Enables
counting
Enables counting
-
3-20. ADDRESSING
As
listed
in
Addresses
used
in
loading and reading the count
2.
Address
word
to
table 3-2, the PIT uses four
00000,
00006
00002,
is
and
00004,
used in writing the mode control
the desired counter.
I/O
addresses.
respectively, are
in
Counters 0, I, and
3-21. INITIALIZATION
To initialize the PIT chip, perform the following:
a. Write mode control word for Counter
Note that all mode control words are written 00006, counter
since mode control word must specify which is
being programmed. (Refer
Table 3-8 provides a sample subroutine for writing
mode control words
b.
Assuming mode control word has selected a 2-byte load, load least-significant byte Oat 00000. (Count value
to
all three counters.
of
to
be
loaded paragraphs 3-23 through 3-25.) Table 3-9 provides a sample subroutine for loading 2-byte count value.
of
c. Load most-significant byte
count into Counter 0
00000.
0 to 00006.
to
figure 3-9.)
count into Counter
is
described
to
in
at
;INTIMR ;COUNTERS 0 ;COUNTER ;ALL THREE ;DESTROYS-A.
INTIMR:
INITIALIZES COUNTERS 0,1,2.
2
COlJWTERS ARE SET UP FOR 1S-BIT OPERATION.
PUBLIC MOV
OUT MOV OUT MOV OUT RET
END
Table 3-8. Typical PIT Control Word Subroutine
AND 1 ARE INITIALIZED
IS
INITIALIZED AS BAUD RATE GENERATOR.
INTIMR AL,30H
ODSH AL,70H ODSH AL,B6H OD6H
AS
INTERRUPT TIMERS.
;MODE CONTROL WORD FOR COUNTER 0 ;MODE CONTROL WORD FOR COUNTER ;MODE CONTROL WORD FOR COUNTER 2
Table 3-9. Typical PIT Count Value Load Subroutine
;LOADO ;USES-D,E;
LOADO: MOV AL,EL ;GET LSB
LOADS COUNTER 0 FROM D&E. D IS MSB, E IS LSB.
DESTROYS-A.
PUBLIC
OUT
MOV AL,DL ;GET MSB
OUT
RET
LOADO
OOOH ODOH
1
3-12
END
Page 51
iSBC 86/12
NOTE
Be
sure to enter the down count bytes if the counter was programmed for a two-byte entry Similarly, enter the downcount value in
BCD if the counter was so programmed.
d. Repeat steps b, c, and d for Counters 1 and 2.
in
the mode control word.
in
two
3-22. OPERATION
The following paragraphs describe operating procedures for a counter read, clock frequency divide/ratio selection,
and interrupt timer counter selection.
3-23.
COUNTER
can be used to read the contents The first method involves a simple read counter. The only requirement with this method
order to ensure stable count reading, the desired counter
must be
Counter 0 and Counter I can be read using this method
because the gate input to Counter 2
inhibited by controlling its gate input. Only
READ.
There are two methods that
of
a particular counter.
of
the desired
is
that,
in
is
not controllable.
Programming Information
a.
Write counter register latch control word (figure
3-11) to
counter and selects counter latching operation.
b.
Perform a read operation table 3-2 for counter addresses.
3-24. SELECTION.
timer input frequencies to Counters input frequencies are divided
TMRO lNTR OUT (Counter! 0), TMR 1 INTR OUT
(Counter 1), and the
00006.
Be sure whichever was specified tion mode control word. For two bytes, read
in
CLOCK
Control word specifies desired
of
desired counter; refer to
NOTE
to
read one
thc order specified.
FREQUENCY
Table 2-4 lists the default and optional
8251
A Baud Rate Clock (Counter 2).
or
two bytes,
in
the initializa-
IDIVIDE
0 through 3. The timer
by
the counters to generate
RATIO
The second method allows the counter to be read
the-
fly."
The recommended procedure control word to latch the contents ens,ures that the count reading
of
latched value
If
a counter mandatory to complete the read procedure; that is, if two bytes were programmed to the counter,
then two bytes operations are performed with that counter.
To read the count follows (a typical counter read subroutine 3-10):
the count can then be read.
NOTE
is
read during the down count, it
must be read before any other
of
a particular counter, proceed
of
is
accurate and stable. The
Table 3-10. Typical
;READ1 READS COUNTER 1 ON-THE-FLY INTO D&E. MSB
;DESTROYS-A.D.E.
PUBLIC
is
to use a mode
the count register; this
is
given in table
PIT
READ1
"on-
is
as
Counter
c1
G,
1
sca
I a I a I x I x I x
L'---.---'i'
L L Don't Cam
Selects Counter Latching Operation
L--
__
Specifies Counter
Figure 3-11. PIT Counter Register
450-1911 Latch Control
Read Subroutine
IN
D,
LSB
IN
E.
to
be Latched
Word
I
Format
READ1:
MOV OUT IN MOV IN MOV RET
END
AL,40H OD6H OD2H E.A OD2H D.A
;MODE WORD FOR LATCHING COUNTER 1 VALUE ;LSB OF COUNTER ;MSB OF COUNTER
3-13
Page 52
Programming Information
iSBC
86/13')
Each counter must be programmed with a down-count number,
or
count value N. When count value N
is
loaded
into a counter, it becomes the clock divisor. To derive
N for either synchronous or asynchronous RS232C
in
operation, use the procedures described
following
paragraphs.
3
-25.
Synchronous Mode. In the synchronous mode, the
TXC and/or RXC rates equal the Baud rate. Therefore,
is
the count value
N = C/B N
B
is is
where
Cis
Thus, for a
determined by:
the count value,
the desired Baud rate, and
1.23 MHz, the input clock frequency.
4800 Baud rate, the required count value
(N)
is:
N=
1.23 X 4800
If the binary equivalent into Counter 2, then the output frequency
is
which
the desired clock rate for synchronous mode
6
10
= 256.
~
of
count value N = 256
is
is
4800 Hz,
loaded
operation.
3-26. Asynchronous Mode. In the asynchronous mode,
the TXC and/or RXC rates equal the Baud rate times
of
one
the following multipliers:
Therefore, the count value
is
XI,
X16,
determined by:
or
X64.
N = C/BM N is the copnt value,
where
B
is
the desired Baud rate, M is the Baud rate multiplier C
is
1.23 MHz, the input clock frequency.
Thus, for a
4800 Baud rate, the required count value (N)
(1, 16,
or
64), and
is:
N=
If
the binary equivalent
1.23 X 10
4800 x
into Counter 2, then the output frequency
Hz, which
is
the desired clock rate for asynchronous mode operation. Count values each Baud rate are listed in
6
=
16
of
(N) versus rate multiplier (M) for
16
='
count value N =
16
is
4800 x
is
loaded
table3-IL
Table 3·11.
Baud Rate:
·Count Count Values (N) for 2.46 MHz clock. Count Values (N) and Rate Multipliers
3·27.
PIT
Count
Value Vs
Each
Baud
Rate
·Count Value (N) For
(B)
75
110 150 300 4096
600 2048
1200 1024 64 2400 512 32 8 4800 256 16 4
9600 128 8 2 19200 64 4 38400
76800 16
Values
RATE
M = 1 M = 16
16384 11171
8192 512
32 2
(N)assume
(M)
are
GENERATOR/INTERVAL
Rate
1024
698 256 64
128
clock is 1.23 MHz. Double
in
decimal.
Table 3-12 shows the maximum and minimum rate generator frequencies and timer intervals for Counters
and I when these counters, respectively, have 1.23-MHz and 153.6-kHz clock inputs. The table also provides the maximum and minimum generator frequencies and time intervals that may be obtained by connecting Counters and I in series.
3·28.
INTERRUPT
TIMER.
To program an il!terval timer for an interruption terminal count, program the appropriate timer for the correct operating mode (Mode in the control word. Then load the count value (N), which is
derived by
N
=TC
where
N
is
the count value for Counter 2,
T is the desired interrupt time interval in seconds,
and
is
the internal clock frequency (Hz).
C
Table
3-13
shows the count value (N) required for several
time intervals (T) that can be generated for Counters
16
and I.
3-29. 8255A PPI PROGRAMMING
Multiplier
M=64
256 175 128
32
16
TIMER.
for
0
0
0)
0
NOTE
During initialization, be sure to load the count value
(N)
into the appropriate counter and the Baud rate multiplier (M) into the 8251A USART.
3-14
The three parallel
I/O
ports interfaced to connector
J1
are
controlled by an Intel 8255A Programmable Peripheral Interface. Port A includes bidirectional data buffers and
of
Ports B and C include IC sockets for installation input terminators
or
output drivers depending on the
either
user's application.
Page 53
iSBC
86/12
Programming Information
Table 3-12. PIT Rate Generator Frequendes and Timer Intervals
Single
Minimum Maximum
RatE!
Generator (frequency)
Real-Time Interrupt (interval)
NOTES:
1.
Assuming a 1.23-MHz clock input.
2.
Assuming a 153.6-kHz clock input.
3.
Assuming Counter 0 has 1.23-MHz clock input.
Table 3-13. PIT Time Intervals
T
10
/-Lsec
100
I-Lsec
1 msec 10 msec 50 msec
*Count Values
MHz.
Count Values (N) are
18.75 Hz 614.4 kHz
1.63/-Lsec
Vs
(N) assume clock is 1.23
in
Timer'
(Counter 0)
53.3 msec
Timer Counts
N*
12 123 1229 12288
61440
decimal.
Single Timer2 (Counter 1) Dual Timer3
Minimum
2.344 Hz
13/-Lsec
I
D71
Maximum
76.8 kHz
426.67 msec 3.26/-Lsec
D,;
D5 I D41 D31
CONTROL
WORD
Minimum Maximum
0.00029
D] 1 D, 1 Do
Hz
I
1-.-1
'---
(O
and 1 in Serie's)
307.2 kHz
58.25 minutes
GROUP B
/
PORT C
(LOWER)
1 =
INPUT
0=
OUTPUT
\
Default jumpers set the Port A bidirectional data buffers to
the input mode. Optional jumpers allow the bidirectional
or
allow
data buffers to be set to the output mode of
the eight
tional data buffers to the input
POIt
C bits to selective set the Port A bidirec-
or
output mode.
anyone
Table 2-11 lists the various operating modes for the three PPI parallel I/O ports. Note that Port A (C8) can be operated in Modes
can be operated in Mode °
Port B (CA) and Port e
or
1.
(eq
0, 1,
or
2;
3-30. CONTROL WORD FORMAT
The:
control word format shown
initialize the PPI to define
in
figure 3-12
tl}e
operating mode
is
used to
of
the three ports. Note that the ports are separated into two groups. Group A (control word bits 3 through operating mode for Port C
(cq.
defines the operating mode for four bits
of
Port C
Port A (C8) and the upper four bits
Group B (control word bits 0 through 2)
Port B (CA) and the lower
(cq.
Bit 7
of
the control word controls
6)
defines the
of
the mode set nag.
3-31. ADDRESSING
/
.
PORT B
INPUT
1 = 0=
OUTPUT
MODE
SELECTION
0=
MODE
0
1 =
MODE
1
GROUP A
PORT C (UPPER) 1 =
INPUT
0=
OUTPUT
PORT A
1
=
INPUT
0=
OUTPUT
MODE
SELECTION 00 = MODE 01 = MODE
lX=MODE2
MODE 1 =
SET
ACTIVE
0
1
FLAG
\
The PPI uses four consecutive even addresses through Port C
OOOCE)
(cq,
for data transfer, obtaining the status
and for port control. (Refer to table 3-2.)
(OOOC8
of
Figure 3-12. PPI Control Word Format
3-15
Page 54
Programming Information
iSBC 86/12
3-32. INITIALIZATION
To initialize the PPI, write a control word to
figure 3-12 and table 3-14 and assume that the control
word
is
92 (hexadecimal). This initializes the PPI
follows:
a.
Mode Set Flag active
b.
Port A (C8) set to Mode 0 Input
c.
Port C (CC) upper set
d. Port B (CA) set
Port C (CC) lower set to Mode 0 Output
e.
to
Mode 0 Output
to
Mode 0 Input
Table 3-14. Typical PPI Initialization Subroutine
;INTPAR INITIALIZES PARALLEL PORTS. ;DESTROYS-A.
PUBLIC
INTPAR:
MOV OUT
RET
to
OOOCE.
INTPAR A,92H
OCEH
Refer
as
3-33. OPERATION
After the PPI has been initialized, the operation
performing a read or a write
3-34. READ
Port A
for
3-35.
routine for figure 3-13, any cleared
;MODE WORD TO PPI PORT A&B IN,C OUT
OPERATION.
is
given
in
WRITE
by
OPERATION.
Port C
is
given
of
the Port C bits can be selectively set or
writing a control word to
to
A typical read subroutine
table 3 -15.
in
table 3-16.
the appropriate port.
A typical write sub-
As
OOOCE.
is
simply
shown in
END
Table 3·15. Typical PPI
;AREAD READS A BYTE FROM PORT.A INTO REG ;DESTROYS-A.
AREAD
AREAD:
IN RET
END
Table 3·16. Typical PPI
;COUT OUTPUTS A BYTE FROM REG A TO PORT ;USES-A; DESTROYS-NOTHING.
PUBLIC COUT
OC8H
Port
Read
Port
Write Subroutine
Subroutine'
A.
;GET BYTE
C.
COUT;
3-16
OUT RET
END
OCCH
;OUTPUT BYTE
Page 55
iSBC 86/12
Programming Information
CONTROL
WORD
7
I 0
\ 06 \
Os
I 04 I 03 I O2 I
I
I
x
I
x
I
DON'T
CARE
Figure 3-13.
I
x
I
0, I DO
PPI
Port
Control
I
BIT
L
---
C Bit Set/Reset
Word
SET/RESET
1 = SET
0=
RESET
BIT
SELECT o 1 2 3 4 5 6 7 o 1 o 1 o 1 o 1
11
o 0 00
00
BIT
SET/RESET
= o
ACTIVE
Format
00
11 11
11
FLAG
Bol B,I B21
3-36. 8259A PIC PROGRAMMING
The on-board master 8259A PIC handles up
vectored priority interrupts and has the capability panding the number priority interrupts by cascading one or more
of
its interrupt input lines with slave 8259A
PIC's. (Refer to paragraph 2-13.)
to
eight
of
ex-
CPU. Lower priority interrupts are inhibited; higher prior­ity interrupts will
be
acknowledged if the CPU has enabled its own interrupt
input through software. The
command from the
be
CPU
able
to
generate
an
interrupt that will
End-Of.·Interrupt (EO!)
is
required to reset the PIC for the
next interrupt.
is
3-39. FULLY NESTED MODE. This mode
only when one or more in
which case the priority
PIC's are slaved to the master PIC,
is
conserved within the slave
used
PIC's.
The operation nested mode except
a.
When that particular PIC priority logic. That is, further interrupts priority within this slave
in
the fully nested mode IS the same
as
follows:
an
interrupt from a slave PIC
PIC
is
not locked out from the master
PIC will be recognized and
as
is
being serviced,
of
higher
the
the master PIC will initiate an interrupt to the CPU.
b.
When exiting the interrupt service routine, the soft­ware must check pending from the same slave PIC. This
sending slave
an
PIC and then reading its In-Service (IS) register. If the command
is
not clear (interrupt pending),
should
be
to
determine
if
another interrupt
End-of-Interrupt (EO!) command
IS
is
sent
register
to
is
clear (empty), an EOI
the master PIC. If the
no
EO! command
sent to the master PIC.
is
done by
IS
register
to
the
is
of
The basic functions priority request to the
of
interrupt requests, (2) issue a single interrupt
CPU based on that priority, and (3) send the
the PIC are to (1) resolve the
CPU a vectored restart address for servicing the interrupt­ing device.
3-37. INTERRUPT PRIORITY MODES
The PIC can be programmed following modes:
a.
Nested Mode
b.
Fully Nested Mode
c. Automatic Rotating Mode d.
Specific Rotating Mode e. Special Mask f.
Poll Mode
3-38.
NESTED
Mode
MODE. signals are assigned a priority from operates in this mode unless specifically programmed otherwise. Interrupt
IRO has the lowest priority. When an interrupt ledged, the highest priority request
to
operate
In
this mode, the PIC input
0 through
in
one
7.
The PIC
of
has the highest priority and
is
acknow-
is
available
to
the
IR
the
3-40. AUTOMATIC ROTATING
mode the interrupt priority given input priority. Thus,
is
serviced, that interrupt assumes the lowest
if
there are a number
rotates. Once an interrupt on a
MODE.
of interrupts, the priority will rotate among the interrupts in numerical order. For example, if interrupts IR4 and IR6 request service simultaneously, IR4
will receive the high­est priority. After service, the priority level rotates so that IR4
has the lowest priority and IR5 assumes the highest
In
priority.
the worst case, seven other interrupts are serviced before IR4 again has the highest priority, course, if IR4 The priority shifts when the
is
the only request, it is serviced promptly.
PIC receives an End-of-
Interrupt (EO!) command.
3-41.
SPECIFIC
ROTATING
MODE.
In this mode, the software can change interrupt priority by specifying the bottom priority, which automatically sets the highest
priority. For example, if ity, IR6 assumes the highest priority. mode, the priority can be rotated Rotate at EO! (SEO!) command mand contains the BCD code viced; that interrupt
7
is
IR5
reset
is
assig!1ed
of
as
the bottom prior-
In
specific rotating
by
writing a Specific
to
the PIC. This com-
the interrupt being ser-
the bottom priority. addition, the bottom priority interrupt can be fixed at any time
by
writing a command word to the appropriate PIC.
In
this
simultaneous
Of
In
3-17
Page 56
Programming Information
iSBC 86/I!
3-42.
SPECIAL
MASK
MODE.
One or more
of
the eight interrupt request inputs can be individually masked during the PIC initialization an interrupt is masked while it
or
at any subsequent time.
is
being serviced, lower
If
priority interrupts are inhibited. There are two ways to enable the lower priority interrupts:
a. Write an End-of-Interrupt (EOI) command.
b. Set the Special Mask Mode.
The Special Mask Mode is useful when one
interrupts are masked. while it
is
being serviced, the lower priority interrupts are
If
for any reason an input
or
is
masked
more
disabled. However, it is possible to enable the lower priority interrupt with the Special Mask Mode. In this
mode, the lower priority lines are enabled until the Special Mask Mode
3-43.
Intenitpt Enable flip-flop
a software subroutine
In the Poll Mode, the addressed PIC treats an Command flip-flop the priority level. This mode
is
reset. Higher priorities are not affected.
POLL
MODE.
as
an interrupt acknowledge, sets its In -Service
if
there is a pending interrupt request, and reads
In this mode the CPU internal
is
clear (interrupts disabled) and
is
used to initiate a Poll command.
is
useful
if
there
is
I/O Read
a common
service routine for several devices.
. c. Bits 2, 5, 6, and 7 are don't care and are normally
0'
coded as
s.
d. Bit 3 establishes whether the interrupts are requested
by
a positive-true level intput
or
requested by a low­to-high transition input. This applies to all input re­quests handled
3
= 1, a low-to-high transition
an interrupt on any
by
the PIC.
In
is
of
the eight levels handled
other words, if bit
required to request
by
the
PIC.
The second Initialization Command Word (ICW2), which
is
also required in all modes
of
operation, consists
of
the
following:
OOH
no
in
in-
a. For programming the master PIC, write
ICW2. Although formation, either ICW3
in
this case ICW2 conveys
it
is
required to prepare the master PIC for
or
ICW4 (or both) to follow.
1 = SINGLE
o = NOT SINGLE
3-44. STATUS READ
07
D6
Interrupt request inputs is handled by the following two internal PIC registers:
I 0 I 0 1
a. Interrupt Request Register (IRR), which stores all
interrupt levels that are requesting service.
b. In-Service Register (ISR), which stores all interrupt
levels that are being serviced.
Either register can be read by writing a suitable command
word and then performing a read operation.
3-45. INITIALIZATION COMMAND WORDS
The on-board master PIC and each slave PIC requires a separate initialization sequence to work in a particular
mode. The initialization sequence, depending on the hardware configuration, requires either three Initialization Command Words (ICW's) shown in figure
3-14.
The first initialization Command Word (lCW1), which
is
required in all modes
of
operation, consists
following: a. Bits
0 and 4 are both
l'
s and identify the word
ICWI for an 8086 CPU operation.
b. Bit 1 denotes whether
or
not the PIC
multiple PIC configuration. In other words, code bit 645-6 Figure 3-14.
1 = 1
if
no slave PIC(s)
is
interfaced to the master
PIC via the Multibus.
or
four
of
of
is
employed in a
the
the
is
05 04 03 02 10
'--'----'-----L_'---'----'-----L_~
10
21
1 1100 I 0 I 0 I 0 I
ICW4
PIC
Word
01
DO
Initialization
Formats
SLAVE 10
0
1 2 0 1 0 1 0 0 1 1
0 0 0 0
,. =
IR
INPUT IS SLAVE
0=
IR
INPUT IS NOT SLAVE
1 = AUTO END-OF.fNTERRUPT
o = NOT AUTO EOI
4
3
0 1 o 1
0 1 1 1 1
5'
6
1
0
Command
7
1
3-18
Page 57
iSBC 86/12
Programming
Information
b.
For
programming
slave identification (10) number.
unless there are eight master
by the slave
The only
are used; board master PIC. IRO-IR7 bits PIC is
3 =
The
required for all modes following:
a. Bits
b. Bit
c. Bit 2 specifies
ct..
In
summary,
the master and
PIC.
acknow
third Initialization Control
if
fourth Initialization Control
ICW4
configured for buffered operation.
Code executed (hardware).
mand from the service routine.
a slave the
Bit 4 (Refer
ledge.)
bit I = 0 in
i.e.,
one
of
connected
l.
0 and 3 are both
for
I programs the
bit 1 = 1
is
to be generated by software before returning
PIC.
master
programs
to paragraphs
three
a slave PIC,
PIC
(These
10 bits are retained and returned
PIC
in
response to a
lCWI,
the master PIC.
to the master PIC IR3 input,
an 8086
if
For
PIC.
or
each
specifying that multiple
or
more
The
SO-S7
of
I'
CPU
End-of-Interrupt
if
an
Code
ICW4
is
example,
the nested
3-38
four
ICW'
slave PIC. Specifically:
code
bits
3-5
with a
Do
not use 000
s slaved to the on-board
CPU
interrupt
Word
(lCW3)
PIC's
are slaved to the
bits correspond to the
For
example,
Word
operation, consists
s to identify that the word
and that the hardware is
EOI
is to
bit I = 0
addressed to a master PIC
code bit 2 = 1
or
fully nested mode.
and
3-39.)
s are required to initialize
is
required
PIC's
if a slave
code
(ICW4),
be
which is
of
(EOI) function.
automatically
if
an
EOI
in
ICW 4 for
com-
on-
bit
the
3-47. ADDRESSING
The
master PIC uses addresses initialization and operation dresses bytes. Addresses for the specific functions are provided in table 3-2.
Slave
and their addresses are determined by the hardware
designer.
000C4
PIC's,
or
000C6
if
employed,
OOOCO
or
command
to read status, poll, and mask
are accessed via the Multibus
words and ad-
3-48. INITIALIZATION
To
initialize the follows (table subroutine for a mode; tables 3 -18 and 3 -19 are typical master
slave
is
PIC initialization subroutines for the bus vectored
mode): a. Disable system interrupts by executing a
Interrupt Flag) instruction.
b. Initialize master
ing sequence:
(1) Write
(2)
or
c. Initialize each slave PIC by writing
d. Enable system interrupts by execlJting an STI (Set
If
000C2. and write
following sequence:
Interrupt Flag) instruction.
PIC's
3-17
provides a typical
PIC operated in the
PIC by writing
ICWI
to
slave
PIC's
are used, write
If
no slave
ICW4
(master and slaves), proceed as
PIC
non-bus
ICW'
OOOCO
PIC's
only to
ICWI,
and
ICW2
are used,
000C2.
ICW2,
ICW3
and
000C2
to write
initialization
vectored
PIC and
CLI
(Clear
s in the follow-
to
000C2.
and
ICW4
omit
ICW3
ICW's
in the
ICW4.
to
Master
Master
Each
PIC ­ICWI ICW2 ICW4
PIC - With Slave(s) ICWI ICW2 ICW3 ICW4
Slave
ICW! ICW2 ICW4
No
PIC
Slaves
3-46. OPERATION COMMAND WORDS
After
being initialized, the programmed Operation
figure
Command
3-15
and discussed in paragraph
at any
time
master
and slave
for various operating modes.
Word
(OCW)
fornlats are
PIC's
3-49.
shown
can
be
The
in
NOTE
Each
PIC independently operates in the nested mode (paragraph ization and before an Word
(OCW)
programs it otherwise.
3-38)
after initial-
Operation Control
3-49. OPERATION
After initialization, the master PIC and slave independently be tion
Command
operations:
a. Auto-rotating priority.
Specific rotating priority.
b. c.
Status read d. Status read e. Interrupt mask bits are set, reset,
f.
Special mask mode set
programmed
Word
of
Interrupt
of
In-Service Register (ISR).
at any time by an Opera-
(OCW)
or
for the following
Request
Register (IRR).
reset.
or
read.
PIC's
can
3-\9
Page 58
Programming Information
0
7
I R I
SEOI I EOI
1\
OCW2
Os
D.
I
o I 0 I LZ I
03 DZ 0,
iSBC
86/1t
0"
L,
I
Lo
I
BCD
LEVEL
TO
BE
OR
PUT
INTO 0 1 2 3 0 1 0 0
0
1 1
0 0 0 0 1 1 1 1
LOWEST
4
1 0 1
O'
RESET PRIORITY
6 7
5
0 1
0 1
1
I -
DOLT CARE
IESMMI
SMM
I 0 I 1 I
OCW3
P I
ERIS I RIS
I
I
NON·SPECIFIC 1 -
RESET BITOF
0-
NO
SPECIFIC 1 • O-NOACTION
0 1 0 1
0
ACTION
Lz.
L,.
ROTATE 1­O·
READ
1
I
NO
ACTION
POLLING A
HIGH
TO
READ
EST
LEVEL
END
THE
HIGHEST
ISR
END
OF
Lo
BITS
ROTATE NOT
ROTATE
IN-SERVICE
0
ENABLES
THE
REOUESTING
OF
INTERRUPT
PRIORITY
INTERRUPT
ARE
PRIORITY
READ IRREG
ON
RDPULSE
THE
BCD
CODE
USED
REGISTER
1
NEXT
NEXT
OF INTERRUPT.
1
READ IS
REG
ON
NEXT
RDPULSE
AD
PULSE
THE
HIGH·
3-20
SPECIAL
MASK
MOOE
NO
1
1
ACTION
1
0
0 1
1
RESET
SPECIAL
SPECIAL
MASK MASK
0
0
Figure 3-15. PIC Operation Control Word Formats
1
SET
Page 59
iSBC 86/12
Programming Information
Table 3-17. Typical PIC Initializatiion Subroutine (NBV Mode)
;INT59 INITIALIZES THE PIC. A 64-BYTE ADDRESS BLOCK BEGINNING WITH
;OOOOOH ;PIC ;PIC ;USES-SETI,
IS
SET UP FOR INTERRUPT SERVICE HOUTINES.
MASK
IS
IS
SET, DISABLING ALL PIC INTERRUPTS.
IN
FULLY NESTED MODE, NON-AUTO EOI.
SMASK; DESTROYS-A.
PUBLIC INT59
EXTRN SETI,
SMASK
INT59:
CALL MOV OUT MOV OUT MOV OUT MOV CALL SMASK RET
END
SETI
AL,13H
OCOH AL,OOH OC6H AL,1DH OC2H AL,OFFH
;ICW1 TO PIC ;ICW2 TO PIC ;ICW4 TO PIC
Table 3-18. Typical Master PIC Initialization Subroutine (BV Mode)
;INTMA INITIALIZES MASTER PIC WITH A SINGE SLAVE ATTACHED
;IN THE 0 LEVEL INTERRUPT. ;PIC MASK ;PIC ;USES-SETI, SMASK
INTMA: CALL SETI
IS
SET
WITH
IS
FULLY NESTED, NON-AUTO EOI.
PUBLIC EXTRN
MOV OUT MOV OUT MOV AL,01H
OUT
MOV AL,1DH OUT MOV CALL SMASK RET
ALL PIC
INTMA SETI,
AL,11H OCOH AL,OOH OC2H
OC2H OC2H
AL,OFFH
INTEI~RUPTS
SMASK
DISABLED.
;ICW1 ;ICW2 ;ICW3 ;ICW4
Table 3 -20 lists details
of
the above operations. Note that an End-Of-Interrupt (EOI) or a Special End-Of-Interrupt (SEOI) command
is
required at the end service routine to reset the ISR. The in
the fully nested and auto-rotating priority modes and the SEOI command, which specifies used in the specific rotating priority mode. Tables 3-21 through 3-25 provide typical subroutines for the following:
END
of
each interrupt
EOI command
Ithe
bit
to
be reset,
is
used
is
a.
Read IRR (table 3-21).
b.
Read ISR (table 3-22).
c.
Set mask register (table 3-23).
d. Read mask register (table 3-24).
e.
Issue EOI command table (3-25).
3-21
Page 60
Programming Information
iSBC
86/12
Operation
Table 3-19. Typical Slave PIC Initialization Subroutine
;INTSL
INITIALIZES A SLAVE ;BEGINNING ;PIC
IS
FULLY
;USES-SETI,
INTSL:
WITH
0200H.
NESTED,
DESTROYS-A.
PUBLIC EXTRN
CALL
MOV OUT MOV OUT MOV OUT RET
END
PIC
LOCATED
NON-AUTO
INTSL SET
I
SETI AL,11H OCOH AL,08H OC2H AL,19H OC2H
EOI.
AT
ADDRESS
;ICW1 ;ICW2 ;ICW4
Table 3-20. PIC Operation Procedures
Procedure
BLOCK
(BV
Mode)
Auto-Rotating
Spedfic
Priority
Priority
Mode
Rotating
Mode
To
set:
In
OCW2,
write a
Terminate interrupt
In
OCW2,
To
set:
In
OCW2,
OOOCO:
To terminate interrupt
In
OCW2,
To
rotate
priority without
In
OCW2,
write
write a
write
write
and
EOI
an
,a
Rotate
Priority
rotate
command
Rotate
Priority
I
BCD
and
rotate
SEQI
command
I
BCD
EOI:
command
at
EOI
command
priority:
(20H)
to
OOOCO.
at
SEOI
D7
D6 I D5 I D4
I
1 1 1 0 0
I
of
IR
line to
be
priority:
in
the
following format to
D7 I D6 1 D5 1 D4 1 D3
0 1 1
I
of
ISR
flip-flop
word
in
the
following
command
reset
and/or
0 0
to
be
format
(AOH)
in
D3
I
reset.
to
OOOCO.
the following format to
I
D2 I D1 I DO
L2
L1
I
D1
L1
I
LO
DO
1
LO
~
put
into lowest priority.
OOOCO.
1
D21
L2
--.,...-.
to
OOOGO:
I
I
3-22
D7
I
BCD
1
D6 1 D5
1
1
I
of
bottom
D4
1
1
0 0 0
priority
IR
line.
D3
1
--.,...-.
D21
L2
D1 L1
I
I
DO LO
I
Page 61
iSBC 86/12
Table
;J-20.
PIC Operation Procedures (Continued)
Programming Information
Operation
Interrupt Request
Register Status
In-Service
Register (ISR) Status
(IRR)
Procedure
The IRR stores a
an interrupt. To read the (1) Write
(2) Read
The ISR stores a
The
ISR is updated when an EOI command is issued. To read the ISR (refer
to footnote): (1) Write
(2) Read
Be sure to reset ISR bit at end-of-interrupt when
Auto-Rotating (both types)
"1"
in the associated bit for each IR input line that is requesting
IRR (refer to footnote):
OAH
to
OOOCO.
OOOCO.
Status is as follows:
~7
IR Line: 7 6
"1"
in the associated bit for priority inputs that are being serviced.
OBH
to
OOOCO.
DOOCO.
Status is as follows:
E·"-I
IR Line:
7 6 5 4 3
and Special Mask. To reset ISR in OCW2, write:
06
I
-06-'"1-
04 1 03 1 02 1 01
05
1
1
5 4 3
-'--1
-04---'1-0-3 -'--1
0-5
2 1
-02---'1--0-1 -'--1
2 o
in
the following modes:
1
00
0
-00--'1
1
Interrupt
Special Mask
NOTE:
Mask
Register
Mode
If previous operation
~I
To set mask bits in
OCW1, writl3 the following mask byte to 000C2:
~
IR Bit Mask: M7 M6 M5 M4 M3 M2
1 = Mask Set, o = Mask Reset
To read mask bits, read
The Special Mask Mode enables desired bits that have been previously masked;
lower priority bits are also enabled. To set, write 68H to To
reset, write 48H to
was
addressed to same register, it is not necessary to rewrite the OCW.
000C2.
DOOCO.
OOOCO.
06 I 05
1 1
0
I
BCO identifies bit to be reset.
1061051
I
04
03
I
0
0
04 1 03
I
02
I 01 I
L2
L1
--...-.-
-.l
1 021
01 M1
I
00
LO
00
MO
I
I
3-23
Page 62
Programming Information
Table 3-21. Typical PIC Interrupt Request Register Read Subroutine
;RRO ;USES-SETI;
READS
PIC
INTERRUPT
DESTROYS-A.
REQUEST
REG.
iSBC
86/12
RRO:
PUBLIC EXTRN
CALL MOV OUT
IN
RET END
RRO SETI
SET
I AL,OAH OCOH
OCOH
;OCW3
RR
INSTRUCTION
Table 3-22. Typical PIC In-Service Register Read Subroutine
;RISO
READS
;USES-SETI;
RISO:
PIC
IN-SERVICE
DESTROYS-A.
PUBLIC EXTRN
CALL
MOV
OUT
IN RET
END
REGISTER.
RISO SETI
SETI AL,OSH OC4H OC4H
;OCW3
RIS
INSTRUCTION
TO
TO
PIC
PIC
Table 3-23. Typical PIC Set Mask Register Subroutine
;SMASK ;A ;USES-A,SETI;
SMASK:
STORES A REG
ONE
MASKS
INTO
OUT
AN
DESTROYS-NOTHING.
PUBLIC EXTRN
CALL OUT RET
END
PIC
INTERRUPT, A ZERO
SMASK SETI
SETI OC2H
MASK
REG.
ENABLES
IT.
Table 3-24. Typical PIC Mask Register Read Subroutine
;RMASK ;USES-SETI;
RMASK:
READS
PIC
DESTROYS-A.
PUBLIC
EXTRN
CALL
IN RET
END
MASK
SETI
OC2H
REG
RMASK
.
SETI
INTO A REG.
3-24
Page 63
iSBC
86/12
Table
3-25.
Typical
PIC
End-of-][nterrupt
Command
Programming Information
Subroutine
EOI ISSUES END-OF-INTERRUPT TO
;USES-SETI; DESTROYS-A.
PUBLIC EOI
EOI:
EXTRN CALL SETI
MOV OUT
F~ET
END
SETI
A,20H
OCOH
3-50. HARDWARE INTERRUPTS
The
8086 CPU includes two hardware interrupts inputs,
NMI and INTR,
able, respectively.
3-51. NON-MASKABLE
The NMI input has the higher priority inputs. A low-to-high transition on the NMI input will be serviced at the end whole moves
sponse to NMI
shift instruction.
When
the NMI input goes active, the
following:
classified as
of
the current instruction
of
a block-type instruction. Worst-case re-
is
during a multiply, divide,
non·maskable
lNTERRUPT
of
the two interrupt
or
or
CPU
performs the
and mask-
(NMI)
between
variable
PIC.
;NON-SPECIFIC
When
INTR goes active, the CPU pertorms the following
(assuming the Interrupt Flat
a. Issues two acknowledge signals; upon receipt
EOI
is
set):
of
the second acknowledge signal, the interrupting device (master
or
slave PIC) will respond with a one-byte
interrupt identifier.
b. Pushes the Flag registers onto
th.e
stack (same as a
PUSHF instruction).
c. Clears the Interrupt Flag, thereby disabling further
maskable interrupts.
d. Multiplies by four (4) the binary value (X) contained
in the one-byte identifier from the interrupting device.
e. Transfers control with an indirect call through
Upon completion
of
the service routine, the
CPU
4X.
automat-
ically restores its flags and returns to the main program.
a. Pushes the Flag registers onto the stack (same
PUSHF
instruction).
b. If not already clear, clears the Interrupt Flag (same as
a
CLI instruction); this disables maskable interrupt.
c. Transfers control with an indirect call through
The
NMI input
is
intended only for catastrophic handling such as a system power failure. Upon comple­tion
of
the service routine, the
CPU
the flags and returns to the main program.
3-52. MASKABLE
The
INTR input has the lower priority
INTERRUPT
inputs. A high level on the INTR input will be serviced at the
end
of
the current instruction
or
move for a block -type instruction.
as
00008.
error
automatically restores
(INTR)
of
the two interrupt
at the
end
of
a whole
a
3-53.
MASTER
PIC
BYTE
IDENTIFIER. ter (ol1-board) PIC responds to the second acknowledge signal from the nOIll-slaved device; to one
of
eight IR inputs numbered
idel1tified by a 3-bit binary number. request occurs on IRS, the master second acknowledge signal from the the byte 00000
CPU
only
if
the interrupt request
i.e.,
a device that liS connected directly
the master PIC IR inuts.
IRO
through IR 7, which are
1012 (OSH).
The
CPU
The
master PIC has
Thus,
if
PIC responds to the
CPU
mUltiplies this value by four and transfers control with an indirect call through 000
101002 (l4H)'
3-54"
SLAVE
PIC
is
initialized with a
These
three bits will form a part
transferred to the
PIC
BYTE
CPU
IDENTIFIER.
3-bit
identifier
in
response to the second
(ID)
of
the byte identifier
acknowledge signal.
The
mas-
is
from a
an interrupt
by outputting
Each
slave
in ICW2.
3-25
Page 64
Programming
Information
iSBC
861l~
The slave PIC requests an interrupt by driving the as­sociated master
drives the
first
of
two acknowledge signals. In response to the first
PIC IR line. The master PIC,
CPU INTR input high and the CPU outputs the
acknowledge signal, the master
code to slaved
priate slave signal from the
PIC's; this 3 -bit code allows the appro-
PIC to respond to the second acknowledge
CPU.
PIC outputs a 3-bit binary
in
tum,
Assume that the slave PIC has the ID code
.
in
ICW2, and that the device requesting service is driving
the
IR2 line (010). Thus,
in
response to the
acknowledge signal, the slave PIC outputs
(3AW.
fers control with
(E8
The CPU multiplies this value by four and trans-
an
indirect call through
H
1112
assigned
OOIIIOIO~
1ll0lOOO2
secon<l
3-26
Page 65
C
4-1. INTRODUCTION
---
CHAPTER 4
PRINCIPLES OF OPERATION
4-4.
CENTRAL
PROCESSOR UNIT
This chapter provides a functional description and a
of
circuit analysis
puter. Figures 4-1 and chapter, are simplified foldout logic diagrams that
illustrate the functional interface between the
microprocessor (CPU) and the on-board facilities and
between the Multibus. Also shown
Control Logic that allows the iSBC 86/12 to function
master/slave relationship with the Multibus aHother bus master to access the on-board dual port RAM.
the iSBC 86/12 Single Board Com-
4-2,
located
CPU and the system facilities via the
in
figure 4-2
at
the end
is
the Dual Port
to
of
8086
allow
this
in
4-2. FUNCTIONAL DESCRIPTION
A brief description
comprising the
graphs. A operational circuit analysis with paragraph 4-13.
4-3.
CLOCK
The clock circuit composed
stabilized by a 22.1184-MHz crystal. This circuit pro­vides nominal IS3.7-kHz, 1.23-MHz , and
optional clock frequencies to the 82S3 Programmable
Interval Timer (PIT); 8251A Universal Synchronous/Asynchronous Receiver/
Transmitter
to
the Dual Port Control Logic and RAM Controller.
The clock circuit composed
by an 18.432-MHz crystal. This circuit divides the crystal frequency by two to provide the nominal
9.22-MHz (CCLK/) signals to the Multibus. (The BCLK/ signal is also used by the Bus Arbiter Assembly.) Remove­able jumpers are provided to allow this clock circuit to be disabled CCLK/
Clock A38 a nominal S-MHz clock to A81, the Bus Arbiter Assembly, and Bus Command Decoder A83. Clock A38 also provides a reset signal on power-up and when commanded to do so by an optional signal supplied via auxiliary connector signal initializes the system components to a known internal state.
(USART); and a 22.12-1\1Hz clock frequency
Bus Clock (BCLK/) and Constant Clock
if
to
the Multibus.
is
stabilized by a
of
the functional blocks
iSBC 86/12
is
given in following para-
is
given beginning
of
logic
CIRCUITS
of
A16,
Al7,
and
Al8
2.46-MHz
2.46-MHz
some other source supplies BCLK/ and
Baud rate clock
of
A80 and A63
IS-MHz
CPU A39, Status Decoder
as
crystal and provides
P2. The RESET
well
as
certain iSBC 86/12
is
stabilized
to
the
The 8086 Microprocessor (CPU A39),
of the single board computer, pcrforn1s the system pro-
cessing functions and generates the address and control
signals required to access memory and trol signals decoded signals required to control the board. The AD1S pins are used data and the lower l6-bits
a
part
of (ADO-ADIS) and the upper 4-bits strobed into Address Latch Latch Enable (ALE) signal. (The ALE signal by
decoding puts form the ABO­machine cycle, the to form the 16-bit data bus
4-5. INTERVAL
The 8253 PIT provides three independently controlled counters that derive their optional basic timing inputs from
is
Counter 2 provides timing for the serial
(82SIA
USART, can provide programmable Baud rates from 110 to 9600. Counter 0 can be used in one clock generator it can be buffered to provide an external
user-defined clock
CPU interrupt. Counter 1, which
timer and can also generate an interrupt.,. has a range
microseconds to
needed., Counters
single timer with a maximum delay
SO,
S I, and S2 are driven by the CPU and
by
Status Decoder
to
a machine cycle, for example, the lower 16-bits
SO,
SI,
20-bit address bus ABO-ABI3;
ABF and
AB
I 0-
ADO-ADIS pins
A81
multiplex the Hi-bit input/output
of
the address. During the first
A40/41/S7 by the Address
and S2.) The Address Latch out-
AB
13. During the remainder
ADO-ADF.
TIMER
the clock circuit composed
USART). This counter,
or
(2) as an interval timer to generate a
8S3.3 milliseconds.
0 and 1 can be cascaded to provide a
INhich
I/O devices. Con-
to develop the various
(ADl6-ADl9)
of
the CPU are used
of
AI6/17/18.
in
conjunction with the
of
two ways:
is
the system interval
If
longer times are
of
over
4-6. SERIAL 110
The 8251A USART provides RS232C compatibility and
is
configured
chronous mode, character size, parity bits, stop bits, and
Baud rates are all programmable. Data, clocks and control lines
to
as
a data terminal. Synchronous
and from connector
12
are buffered.
4-7. PARALLEL 110
The 825SA Programmable Peripheral Interface provides
24 programmable so that, depending on the application,
I/O
lines. Two IC sockets are provided
TTL
is
the heart
CPU
is
I/O
SO
hours.
or
drivers
ADO-
are
derived
i.e.,
of
the
port
(I)
as
of
1.6
ansyn-
or
I/O
a
4-1
Page 66
Principles
of
Operation
iSBC 86/12
tenninators connector J of
eight lines each; these ports can be programmed simple I/O ports, strobed or
one port can be programmed with control lines. The iSBC 86/12 includes various optional functions controlled such lines, bus override, strobed I/O port interrupts, and one MuItibus interrupt.
may
be installed
1.
The 24 lines are grouped into three ports
as
an
RS232C interface line, timer gate control
to
complete the interface
VO
ports with handshaking,
as
a bidirectional port
by
the parallel I/O lines
to
to
be
4-8. INTERRUPT CONTROLLER
The 8259A Programmable Interrupt Controller (PIC) handles 8259A of
another 8259A programming the master that PIC (the one interfaced to the master PIC via the Multibus). PIC, it will allow the slave PIC
vector address master
bus vectored (NBV) interrupt line (master the restart address) or a bus vectored (BV) interrupt
(cascaded to a slave
dress). The
single Multibus interrupt lines (an interrupt line which
does not have a slave
aid
rupts to 64. All 64 interrupts must be processed through
the slave
iSBC 86/12.
There are nine jumper-selectable interrupt sources: serial
I/O
ternal viaJ1
The eight Multibus interrupt lines
be connected to the master
interrupt levels. The user interrupt levels by hardware jumpers. The iSBC 86/12 can also generate one Multibus interrupt that by
up
to
eight vectored priority interrupts. The
PIC provides the capability
priority interrupts
an
interrupt line (e.g., IR3)
If
PIC can be individually programmed
iSBC
of
eight slave PIC's, expand the number
PIC's
port
(2),parallel
(1), power fail (1), and MuItibus time out (1).
an 8255A PPI output bit.
by
cascading each interrupt line with
PIC. (Refer to figure 2-2.) This
PIC (the one on the iSBC 86/12)
an IR3 interrupt
to
the CPU. Each interrupt line into the
PIC which generates the restart ad-
86/12 can handle eight on-board or
PIC connected
and must therefore be external to the
VO
interface (2), timers (2), ex-
cap map interrupt sources into
PIC
is
is
to
to
sensed
expand the number
is
done by
connected
to
to
(INTO/-INT7/) can
provide 8
to
a slave
by
the master
send the restart
to
be a non-
PIC generates
it) or, with the
of
inter-
to
64 bus
is
controlled
4-10. RAM CONFIGURATION
The iSBC 86/12 includes 32K bytes composed
8202 RAM Controller.
The Dual
Multibus
RAM device when not acting
port faulting control time a bus master generates a memory request to the dual port RAM via the Multibus, the RAM must be
taken away from the When the slave request
RAM returns
The dual port consists and decoder; bidirectional address and data bus (Multibus) drivers; slave RAM address decoder/translator; control logic; and the RAM and RAM controller.
The
bus On-board RAM addresses (as seen by the CPU) are
(assigned from the bottom up)
The address bus drivers and data bus drivers separate the
dual port bus from the Multibus. The slave RAM address
decoder
to
provide independent Multibus address selection ,that can be located throughout the I-megabyte address space. The slave RAM address
address and memory size. The base address can be on any space cannot extend across a I28K boundary. The memory size specifies the amount accessible by the Multibus and increments. This provides the capability tions and frees address an (Refer
of
sixteen 2117 Dynamic RAM chips and
Port Control Logic interfaces the RAM with the so
that the iSBC 86/12 can perfonn
is
designed
CPU address and data buffers separate the on-board (I/O and ROM/EPROM) from the dual port bus.
is
8K
of
is
on-board RAM address (as seen
to
to
maximize the CPU throughput by de-
to
the CPU when not in demand. Each
CPU (when the CPU
is
completed, the control
to
the CPU.
of
CPU address and data buffers
separate from the CPU RAM address decoder
is
selected by specifying the base
boundary with the exception that the memory
the dual port RAM for
up
the address space. Regardless
selected, the slave RAM address
figure 2-1.)
of
read/write memory
as
as
a bus master. This dual
is
not using it).
00000-07FFF.
of
Dual Port RAM
is
switch selectable in 8K
to
reserve. sec-
u\e
only by
the'CPU
of
what base
is
mapped into
by
the CPU).
an
a slave
of
the
4-9.
ROM/EPROM
IC sockets A28, A29, A46, and A47 are provided for user installation provided to accommodate either 2K, 4K, The
ROM/EPROM address space
the I-megabyte memory space because the 8086 CPU
branches to the different (using 2K chips), (using
8K
4-2
of
FFFFO
ROM/EPROM configurations are
chips).
CONFIGURATION
ROM
or
EPROM chips; jumpers are
after a reset. Starting addresses for
FEOOO
(using 4K chips), and
or
8K
is
located at the top
chips.
of
FFOOO
FCOOO
4-11.
BUS
STRUCTURE
The iSBC 86/12 architecture
bus hierarchy: the on-board bus, the dual port bus, and the Multibus. (Refer municate only within itself and
bus can operate independently fonnance bus it must go to perfonn the
of
the iSBC 86/12
bus
to
the on-board bus, the better the perfonnance.
is
organized around a three-
to
figure 4-3.) Each bus can com-
an
adjacent bus, and each
of
each other. The per-
is
directly related to which
an
operation; that is, the closer
Page 67
iSBC
86/12
Principles of Operation
is
RAM perfonnance
designed to equal that activity (if the dual port bus is not busv when the board bus requests it). The dual port returns This level bus activity
Ito
State I when the CPU completes its operation. of
bus activity operates independently
(if
the Multibus does not need the dual
of
b~s
control logic
on-board
on-
of
Multi-
port bus).
When
the Multibus requests the dual port bus, the control logic goes from State in about to independent
150 nanoseconds and, upon completion, returns
State
:I.
The Multibus use
of
the on-board activity.
I to 3 (it will wait if busy)
of
the dual port bus
is
When the on-board bus needs the Multibus, it must go
through the dual port bus to the Multibus. bus uses the dual port bus only
to
communicate with the Multibus and leaves the dual port bus in State at this level requires a minimum
200-nanosecond over-
The
I.
on-board
Activity
head for Multibus exchange.
645-9
The
requires (Exception: a
However,
"h~des"
The the on-board bus, which connects the I/O devices, Ac:tivity buses, thus permitting independent execution
Figure
4-3_
Internal
iSBC 86/12 operates at a
one
wait state for all on-board system accesses.
RAM
write requilres two wait states.)
the pipeline effect
of
these wait states.
core
of
the iSBC 86/12 series bus architecture is
ROM/EPROM,
on
this bus does not require control
and the dual port RAM bus.
nus
Structure
5-MHz
the 8086
CPU
CPU
cycle and
CPU
effectively
to all on-board
of
the outer
of
on-board activities. Activities at this \evel re:quirc no bus overhead and operate at
The
next bus in the hierarchy is the dual port bus. This
maximum
bus controls the dynamic the
on-board
be
in
a.
State 1 - On-board bus
one
bus
and
of
three states:
board perfonnance.
RAM
and communicates with
the Multibus
..
is
conltrolling it but not
The
dual port bus can
using it (not busy).
b_
State 2 - On-board bus is controlling it and using
it (busy).
c_
State 3 - Multibus is controlling it and using it
(busy).
State 1 is the idle state in control the
of
the on-board bus to minimize delays when
CPU
needs it. When the
dual port bus to access
logic will go from
of
the dual port bus and is left
on-board
RA\1,
the dual port bus control
State I to State
bus requires the
2.
(If
the dual port bus is busy, it will wait until it is not busy). Activity at this level requires a minimum
of
bus overhead and the
4-12. \1ULTIBUS
The
iSBC 86/12 supports both 8-bit and 16-bit interface includes the Bus Arbiter Command
data bus drivers, and interrupt drivers and receivers. Bus Arbiter allows the iSBC 86/12 to operate masters in the system in which the
Decoder A83, bidirectional address bus and
INTERFACE
is
completely Multibus compatible and
operations.
8086
The
Multibus
i
....
ssembly, Bus
as
CPU
can request
The
a bus
the Multibus when a bus resource is needed.
The Bus Arbiter Assembly mounts on the is electrically interfaced
to the board via connector
iSBC 86/12 and
J\
2.
4-13. CIRCUIT ANALYSIS
The
schematic diagram for the iSBC 86/12 figure 5-2. each
traverse from
The
schematic diagram consists
of
which includes grid coordinlftes. Signals that
one
sheet to another are assigned grid coordinates at both the signal source and signal tination. a signal source (or signal destination
For
example,
the grid coordinates 2ZB I locate
as
on sheet 2 Zone B 1 .
Both active-high and active-low signals are used. A signal mnemonic that ends with a virgule that the signal
is
active low
signal mnemonic without a virgule
. that the signal
Figures 4-1 and simplified logic diagrams
is
active high
4-2
at the end
of
(e.g.,
(~0.4
V). Conversely, a
(e.g.,
C?2.0V).
of
the input/output, interrupt, and memory sections. These diagrams will be helpful understanding both the addressing scheme and the in­ternal bus structure
of
the board.
is
given in
of
II
sheets,
des-
the
cas~
may be)
DAT7/) denotes
ALE) denotes
this chapter are
in
4-3
Page 68
Principles
of
Operation
iSBC
86/12;
4-14. INITIALIZATION
When power is applied
of
contents
the 8086 CPU program counter, program status word, interrupt enable flip- flop, etc., are subject to random factors
and cannot be predicted. For this
reason, a power-up sequence
Bus Arbiter, and
When power
VO
is
initially applied to the iSBC 86/IX,
capacitor C26 (2ZD6) begins to charge through resistor
R9. The charge developed across C26 Schmitt trigger, which is internal to Clock Generator A38. The
Schmitt trigger converts the slow transition appearing
at pin
12
into a clean, fast-rising synchronized RESET signal at pin 11. The RESET signal to develop matically sets the
RESET/ and INIT/. The RESET/ signal auto-
8086 CPU program counter to FFFFO
and clears the interrupt enable flip-flop; resets the
VO
ports
parallel I/O port to the
to
"idle" (outputs are tristated). The INIT/ signal over the Multibus to set the entire system to a known internal state.
The initialization described above can be performed at any time by inputting a connector
P2.
in
a start-up sequence, the
is
used to set the CPU,
ports to a known internal state.
is
sensed by a
is
inverted
by
A48-6
the input mode; resets the serial
mode; and resets the Bus Arbiter
is
transmitted
RESET/ signal via auxiliary
4-16. CENTRAL PROCESSOR UNIT
The 8086 CPU uses the 5-MHz clock input to develop
the timing requirements for various time-dependent func­tions described
4-17. BASIC
of
at
least four clock (CLK) cycles referred to T2, T3 and T4. The address during
Tl T3 and T4; T2 direction
that a
"not
device,
"wait"
T4. Each inserted TW state
a CLK cycle. Periods can occur between CPU-driven bus
cycles; these periods are referred to as
(TI) or inactive CLK cycles. The processor uses states for internal housekeeping.
4-18. BUS
SO,
S 1, and S2 during T I status signals are used Arbiter Assembly, and Bus Command Decoder A83 to identify the following types
S2
in
following paragraphs.
TIMING.
Each CPU bus cycle consists
as T 1,
is
emitted from the CPU
and data transfer occurs on the bus during
is
used primarily for changing the
of
the bus during read operations. In the event
ready" indication
is
given
by
the addressed
states (TW) are inserted between T3 and
is
of
the same duration
.•
idle" states
TIMING.
S1
The CPU generates status signals
of
every machine cycle. These
by
Status Decoder A81, Bus
of
machine cycles.
CPU
SO
Machine Cycle
as
TI
4-15. CLOCK CIRCUITS
The 5-MHz CLK (2ZC6)
in the time base for CPU A39, Status Decoder Arbiter Assembly and Bus Command Decoder A83.
The time base for Bus Clock BCLK! and Constant Clock CCLK!
is and crystal divided by A63 and driven onto the Multibus through
jumpers 105-106 and 103-104. The BCLK! signal
used as a clock input to the Bus Arbiter Assembly.
The time base for the remaining functions on the board
provided
by The nominal the
OSC output
Dual
Port Control Logic and to RAM Controller A70. Clock Generator A by nine to develop a 2.46-MHz clock at its output. The 2.46-MHz clock clock input AI8
to provide a selectable clock for the 8253 PIT.
Divider A16 also divides the 2.46-MHz clock by two
and by nine, respectively, to produce 1.23-MHz and
153.6-kHz selectable clocks for the 8253
is
developed by Clock Generator A38
conjunction with crystal Y2. This clock
A8I,
the Bus
provided by Clock Generator A80
Y3.
The 18.432-MHz crystal frequency
(1
OZA5)
is
clock Generator A
22.I2-MHz of
AI7
17
also divides the crystal frequency
17
(7ZA
7)
and crystal Y
crystal frequency appearing at
is
buffered and supplied to the
<l>2TTL
is
applied directly to the
of
the
825lA
USART and applied through
PIT.
is
also
0 0
0 0 1 0 1
1 1 0 1
1 1
0
0 0 Code Access
1
A read cycle begins
Address Latch Enable (ALE) signal and the emission
is
the address. (Refer to figure
0
1
0
'1
1 Memory Read
0
1
in
Interrupt Acknowledge
1/0
Read
1/0
Write
Halt
Memory Write Passive
T I with the assertion
4-4.~
The trailing edge
ALE signal latches. the address into Address Latch
A40/41/57 (2ZB2). (The BHEN/ signal and address bit ADO
address the low byte, high byte,
or
both bytes.) The
Data Transmit/Receive (DT/R) signal, which
at the end
is
and data bus drivers for a
1. Memory Read Command (MRDC/)
of T 1,
is used
to
set up the various data buffer:
CPU read operation. The
or
I/O Read Com­mand (IORC/) is asserted from the beginning beginning lines the Data Enable (DEN) signal signal enables the data buffers.) The state READY input
ofT4.
At the beginning
of
the local bus are switched to the
ofT3,
is
asserted. (The DEN
CPU examines the
of
its READY input during the last half
is
high (signifying that the addressed
the ADO-ADI5
"data"
device has placed data on the data lines), the proceeds into T4; if its READY input
is
enters a wait (TW) state and stays there until READY
of
the
of of
is
asserted
of
T2 to the
mode and
of
T3. If its
CPU
low, the CPU
4-4
Page 69
iSBC
86/12
Principles
of
Operation
5-MHZ CLK
S2/, S1/,
SOl
BHEN/, AD16-AD19
,
,"
ALE
ADO-AD15
.".
DT/R
,
..
,.
MRDC/'
IORCI
\
~
11
1\
\
VALID
STATUS
ADDRESS
12
n
,
J
T3
1\
DATA
14
f\
~-
I--
-
\
'-
--
I FLOAT
IN
FLOAT
."*
DEN
NOTE: INTAI, AMWC/, MWTC/, AIOWC/, IOWCI ~ VOH
OR
"DENOTES CPU INPUT
**DENOTES STATUS DECODER
645-10
goes high. The external effect
is
to preserve the exact state for an integral number the machine cycle. This in
effect, increases the allowable access time for memory
or
I/O devices, By inserting TW states, the CPU can accommodate slower memory or slower CPU accepts the data and terminates the command
OUTPUT
AS1
OUTPUT SIGNAL
Figure 4-4. CPU Read Timing
of
using the READY input
of
the CPU at the end
of
clock periods before finishing
• stretching'
of
the system timing,
I/O devices. The
of
in
T3
T4; the DEN signal then goes false and the data buffers are tristated.
A write cycle begins
signal and the emission 4-5.) The trailing edge
address latch as described for a write cycle. The
in
T I with the assertion
of
the address. (Refer to figure
of
ALE latches
the
address into the
of
the ALE
DT/R signal remains high throughout the entire read cycle to set up
the data buffers and data bus buffers for a CPU write operation. Status Decoder of
write strobe signals: advanced (AMWT/ and and normal (MWTC/ and 10WC/). 4-5, the advanced memory and
A8l
provides two types
AIOWq
As
shown
in
figure
I/O write strobes are
issued one clock cycle earlier than the normal memory
VO
and advanced
write strobes. (The iSBC 86/12 doesn't use
VO
write strobe AIOWC/.) At the beginning T2, the advance write and DEN signals are asserted and the ADO-ADI5 lines
of
the local bus are switched to the
"data" mode. (The DEN signal enables the data buffers.)
..
The
CPU then places the data on the ADO-ADI5 lines
at
and,
the beginning
issued. The CPU examines the state
during the last half
of
T3, the normal write strobe
of
its READY input
of
T3. When READY goes high (signifying that the addressed device has accepted the data), the
CPU enters T4 and terminates the write strobe.
DEN then goes false and the data buffers are tristated.
The
CPU interrupt acknowledge
shown
in
figure 4-6. Two back-to-back INTA cycles are
(I
NT
A)
cycle timing
required for each interrupt initiated by the 8259A by
a slave 8259A PIC cascaded to the master PIC. The
cycle
is
INT A
is
that
an
10RC/ signal and the address bus
similar to a read cycle. The basic difference
INT N signal
is
asserted instead
is
of
an MRDC/ or
floated. In the second
PIC
of
is
is
or
4-5
Page 70
Principles
of
Operation
iSBC86.
5-MHZ
ClK
* 52/. 51/.
** ALE
••
••
501
BHEN/. AD16-AD19
* ADO-AD15
DEN
AMWTI + AlOWCI
\
~
~
'i
T1
n
VALID
ADDRESS
STATUS
T2 T3 T4
n
n
DATA OUT
n
~
I FLOAT
I,
~
~--
--
FLOAT
(NOTE 2)
...
~
••
MWTCI + IOWCI
NOTES: _
1. INTAI. IORC/. MRDC/. DTIR = VOH.
2.
FLOATS ONLY IF ENTERING A
'DENOTES
"DENOTES
641H1
INT A cycle, a byte PIC) which identifies the interrupting source,
four by the
vector look-up table.
4-19. ADDRESS
The address bus
and4-2. CPU A39 during the first clock cycle or
I/O instruction. The 'trailing edge Enable (ALE) signal, output by ing T 41/57. The latched address
a. AB3-ABF to
(6ZA7).
b. ABB-AB13
A18/68 (6ZB6).
CPU INPUT OR OUTPUT STATUS DECODER
of
infonnation (supplied
is
read from
"dat~"
CPU and used
BUS
is
shown in weighted lines in figures 4-1
The 20-bit address (ADO-ADI9)
1,
strobes and latches the address into Latch A40/
I/O Address Decoder A54/55/56
to
PROM Address Decode Logic
"HOLD"
CONDITION.
A81
OUTPUT
lines ADO-AD7. This byte,
as
a pointer into an interrupt
(T
of
Status Decoder
is
distributed as follows:
Figure 4-5. CPU Write Timing
by
the 8259A
is
multiplied by
c. ABI-ABC d. AB13 to on-board RAM address recognition gate
A53-6 (6ZD6).
4-20. DATA
At the beginning
pins become the source
ADF. Data can be sourced to
is
output
by
a. Data Buffer A44/45 (4ZD4).
I)
of
the memory
the Address Latch
A81
dur-
b. Data Buffer A60/61 (4ZD5).
4-21.
Bus Time Out one-shot
signal. If jumper 5-6
BUS
leading edge hung
lJP
nanoseconds,
to
PROM A28/29/46/47 (6ZC3).
BUS
of
clock cycle T2, the CPU
or
destination
or
input from the following:
of
data bus
ADO"
TIME OUT
A5
(lOZA6)
of
the ALE signal.
in a wait state for approximately 6.2
A5
times out and asserts the TIMEOUT/
is
installed, the TIMEOUT/ signal
is
triggered by the
If
the CPU halts,
AD
ADO-
or
15%)
15
is
4-6
Page 71
iSBC
86/12
Principles
of
Operation
5-MHZ CLK
S2/, S1/,
SOl
BHEN/, AD16-AD19
*"
ALE
"
AD8-AD15
'\
--;
\
U
-
FLOAT
(NOTE
T1
CASCADE ADDRESS
2)
n
VALID
A8-A10
STATUS
T2
n
FLOAT
T3
n
T4
n
J FLDAT
FLOAT
(NOTE
10-
1--
\
\
\
-
2)
FLOAT (NOTE
" ADO-AD7
** MCE
-
IJ
\
*'"
DT/A
*'
INTAI
*'
DEN
NOTES:
1. MRDC/, IORCI, AMWC/, MWTC/, AIOWCI, IOWCI = VOH; BHENI =
2.
THE TWO INTA CYCLES IS FLOATING WHEN THE SECOND INTA CYCLE IS ENTERED.
'DENOTES CPU INPUT OR OUTPUT
**DENOTES STATUS DECODER
RUN
BACK-TO-BACK. THUS, THE LOCAL BUS
A81
OUTPUT
2)
Vol.
POINTER
FLOAT
645-12 Fligure 4-6. CPU
Interrupt
Acknowledge Cycle Timing
4-7
Page 72
Principles
of
Operation
iSBC 86'1i_
drives the CPU READY line high through A7-12 and A38-5 to allow the TIMEOUT/ signal signal to the interrupt
CPU to exit the wait state. The
is
also routed as a TIMEOUT INTR
jumper
matrix
(8ZDl).
4-22. INTERNAL CONTROL SIGNALS
Status Decoder A81 (3ZB3) receives the signal from Clock Generator A38 and status signals
from
CPU
A39. The
CLK
signal establishes when the
command signals are generated as a result
SO-S2. The following signals are output from Status De­coder A81:
Signal
ALE Address Latch Enable. Strobes address into Ad-
AIOWCI
AMWCI
DEN
DT/R
IORCI
10WCI
INTA/
MCE
MRDCI
W"VTCI
dress Latch
Advanced I/O
is issued earlier than avoid imposing a CPU wait state.
Advanced Memory
Write Command that is issued earlier than MWTCI in an attempt to avoid imposing a CPU wait state.
Data Enable. Enables Data Buffers A44 and
A60/61.
Data Transmit/Receive. Establishes direction of
data transfer through Data Buffers
A60/61 and Data Bus Buffers A69/89/90.
I/O Read Command to on-board PPI, USART,
PIT,
and PIC.
I/O Write Command to on-board PPI, USART,
PIT,
and PIC.
Interrupt Acknowledge. Provides on-board con-
trol during INTA cycle.
Master Cascade Enable. Enable cascade ad-
dress from master 8259A
slave PIC address can be latched.
that
Memory Read Command. Memory
Write
Definition
A40/41/57.
Write.
An I/O Write Command that
10WCI
Write
Command. A Memory
Command.
5-MHz
CLK
SO-S2
of
decoding
in
an
attempt to
A44/45 and
PIC onto local bus so
4-23. DUAL PORT CONTROL LOGIC
The Dual Port Control Logic (figure
the dual port RAM facilities to be shared by the on-board CPU
or
by
another bus master via the Multibus. When not acting as a bus master RAM,
the iSBC 86/12
or
when not accessing the dual port
can
act as a in a multiple bus master system. When accessing the dual port
RAM,
the on-board
CPU tempt to access the dual port RAM via the Multibus. In this situation, the bus access
is completed its particular read bus access is enters the will be held 4-7
and
in
progress, the Dual Port Control Logic
"slave"
4-8
mode
aodany
off
until the slave mode
are timing diagrams for the Dual Port Control
Logic.
5-2
sheet 11) allQws
"slave"
RAM device
has priority over any at-
held
off
until the
or
write operation. When a
CPU
subsequent CPU request
is
terminated. Figures
has.
4-24. MULTIBUS ACCESS TIMING. Figure
lustrates the Dual Port Control Logic timing RAM access via the Multibus. (P-periods
PO
4-7
for
dual port
through
it
Pl1 are used only for descriptive purposes and have no rela­tionship to the
BD RAM A49-7 goes low on the next rising edge
of
PO
end
22.12-MHz
CMD
signal goes high, A49-10 goes high and
(assuming that
clock signal.) When the OFF
of
the clock at the
ON
BD RAM RQT/ and RAM
XACK! are both high).
At the end
A50-6 asserts the
of
PI,
A50-5 goes high and
SLA
VE MODE/ signal.
A50-6
The
goes low;
outputs
A50-6 and A49- 7 are ANDed to hold A50-5 in the preset
of
(high) state. At the end asserts the or
DP
WRT/
SLA VE
CMD
to RAM Controller A 70 (lOZB6); SLA VE
P2, A49-14 goes low and
EN/ signal, which gates
DP
RD/
CMD EN/ also gates the subsequently generated RAM
CPU
XACK! to the
READY input. (RAM XACK!
generated by the RAM Controller when data has been read
or
from
written into RAM.)
The RAM Controller asserts RAM XACK! during P13
of
and A49-10 goes low on the next rising edge The bus master then terminates the signal and the
OFF
BD
CMD
signal.
DP
The
RD/
the clock.
or
DP
WRT/
RAM controller next terminates RAM XACK! and then A49- 7 goes high on the next rising edge
of
the clock. At the end
of
P16, A50-5 goes low and A50-6 goes high (terminating the SLA VE MODE/ signal). high and terminates the
At
SLA
the end
VE
CMD
ofPl7,
EN/
A49-14 goes
signal.
The foregoing discussion pertains only to the operation
the Dual Port Control Logic for Multibus access dual port RAM. The actual addressing and transfer are discussed in paragraph
4-25. CPU ACCESS TIMING. Figure
4-35.
4-8
of
the
of
data
illustrates the Dual Port Control Logic timing for dual port. RAM access by the on-board P13 are used only for descriptive relationship to the 22.12-MHz clock signal.) demonstrate that the CPU has priority in the access dual port RAM, figure
8086 CPU. (P- periods
~urposes
4-8
shows the
OFF
PO
~rough
and
hJve
of
BD
RAM
no
To
the
CMD signal active when the CPU access is initiated by the ON
BO
RAM RQT/ signal. The timing has progressed
through
PO,
during which time A49-10 has been clocked
·high and A49-7 has been clocked low.
Rip-Rop asserts the ALE! signal at the beginning instruction cycle. When the asserted, the is now low, A49-10 goes low on the next rising edge clock. Flip-flop clocked high and therefore keeps the
signal asserted;
SLA
A50-9
is
preset (high) when the Status Decoder
EXT
ALE/ signal goes low
A50-5
A50-6 remains high and suppresses the
VE MODE/ signal.
of
T1 in the
ON
BD RAM RQT/ signal
and,
since
is
thus prevented from being
DP
ON
BD
CPU
A51-6
of
the
ADR/
of
is
of
is
4-8
Page 73
iSBC
86/12
Principles of Operation
DUAL PORT
22.12 MHZ
ON
OFF BD RAM CMD
FF A49-10 a
FF
FF
ClK
ClK
BD RAM RaTI
ASO-S
a
ASO-6
a o
P-PERIODS
o
o
o
o
PO
P1
P2
P3
P4
P13
I P14 I
P1S
P16 I P17
FF A49-14 a
FF A49-7 a o
SLAVE CMD
DP
RAMXACKI
8086 CPU CONTROL 0
645-13
RDI
OR
DP
ENI
WRTI
o
o
o
o
CPU CONTROL
Figure 4-7. Dual
L-
____________________
Port
With CPU Lockout
~M~U~lT~IB~U~S~C~O~N_T_R_O_l
______________________
Control Multibus Access Timing
~~
4-9
Page 74
Principles of Operation
iSBC 861,.
-.
DUAL PORT
22.12 MHZ
ON
OFF
FF
FF A49-10 a
FF
FF
ClK
P-PERIOOS
ClK
BO
RAM ROT! o
BO
RAM CMD o
ASO-9 a
ASO-S a 0
ASO-6 Q 0
PO
P1
P2
P12
P13
PO
P1
P2
P3
P4
~--------~(~'------~
o
o
DP
ON
BD CMD EN!
FF
A49-14 Q 0
FF A49-7 a 0
ON BD CMD EN! 0
SLAVE
CMD EN! 0
DP RD! OR DP WRT! 0
ADV MEM RD!
RAM
a086 CPU CONTROL
"FOR REMAINDER OF
MUlTIBUS SEE WITH
OR
MEM WRT! 0
XACK/
ACCESS TIMING,
FIG. 4-7 BEGINNING
P3.
o
o
l·~
CPU
CONTROL
L-
________________________
MUlTIBUS
CONTROL
~?
*
645;-14
Figure 4-8. Dual Port Control CPU Access Timing With Multibus Lockout
4-10
Page 75
iSBC
86/12
Principles of Operation
The ON BD as the The
ADV Status Decoder is ORed with the signal to prevent A50-5 and A50-6 from changing states when ALE/ goes false at the end (A49-10 the clock after ALE/ goes false.)
The subsequently generated
gated by the asserted mitted to RAM Controller A or
write is completed, the RAM Controller asserts RAM
XACK!
ofP13, RAM MEM then terminated and A49-10 goes high at the end the end goes high and A50-6 goes low.
The
foregoing discussion pertains only to the operation
the Dual Port Control Logic for CPU access
RAM. The actual addressing and transfer
discussed in paragraph 4-34.
CMD
EN/ signal
ON
BD RAM RQT/ signal since A49-14
MEM RD/
is
allowed to go high on the next rising edge
ON
and A49-1O goes low at the end
the CPU terminates the instruction and the ON BD
RQT/,
DP
RD/
WRT/
signals go false.
of
PI
, the SLA VE MODE/
is
asserted at the same time
or
MEM WRT/ signal from the
ON
BD RAM RQT/
of
Tl
in the instruction.
DP RD/
BD
70 (lOZB6). When the read
or
DP
WRT/, and
or
DP WRT/ signal,
CMD
EN/ signal,
ofPl2.
ADV
The
RAM
XACK!
is
entered when A50-5
of
of
is
high.
is
trans-
At the end
MEM/ or
signal
of
PO.
on-board
data are
of
At
of
With AEN2/ enabled, the Clock Generator
recognize the ensuing acknowledge signal (AACK! XACK!) transmitted by the addressed system device.
ensure adequate setup for the address and data, counter A4
(2ZB5) asserted. When ALE/ goes false, A4-3 the 5-MHz driven through gate A2-11 Decoder.
The false Command Decoder, which decodes appropriate command low on the Multibus when T21/ occurs. The Bus Command Decoder also drives DEN high Bus Driver
"receive"
is
output
After the command addressed device driving the Multibus XACK! line low), the Arbiter and Bus Command Decoder, respectively, termi­nate relinquishes control high and
is
held in the clear state as long as ALE/
is
clocked low by
clo~k
to generate T21/. This signal (T21/)
to
enable the Bus Command
ON BD ADR/ signal also enables the Bus
SO-S2 and drives the
to
enable Data Bus Driver A69/89.
is
switched
mode depending on the state
of
Status Decoder A81.
CPU terminates the appropriate command. The Bus
BUS ADEN/ and BUS DEN; the Bus Arbiter also
BPRO/ low and then raising BUSY/.
to
the appropriate
is
acknowledged (signified by the
of
the Multibus by driving BREQ/
is
prepared to
BUS
The
Data
"transmit"
of
the DT/R
or
To
is
is
or
4-26. MULTIBUS INTERFACE
The
Multibus interface consists Assembly (3ZD3), Bus Command Decoder A83 (3ZC3), bidirectional Address Bus Driver A87/88 (5ZC3), bi­directional Data Bus Driver A69/89/90 (4ZB3), and the Slave RAM Decode Logic (figure
The
falling edge
ence for the Bus Arbiter, which allows the
assume the role signal is false (high) and the either a read BREQ/ low and BRPO/ high. The BREQ/ output from each bus master in the system is used by the Multibus when the bus priority is resolved by a parallel priority scheme as described in paragraph 2-19. The put is used by the Multibus when the bus priority resolved by a serial priority scheme as described paragraph 2-18.
The
iSBC 86/12 gains control BPRN/ input to the Bus Arbiter falling edge BUS ADEN/ low. The BUSY/ output indicates that the bus is in use and that the current bus master in control will not relinquish control until it raises its BUSY/ signal.
The
BUS ADEN/ output, which can be thought "master input Driver (sheet 5), and the input
bus
of
Clock Generator A38 (2ZC6), the Bus Address
of
BCLK! provides the bus timing refer-
of
a bus master. When the
or
write operation, the Bus Arbiter drives
of
BCLK!, the Bus Arbiter drives BUSY/ and
control"
signal, is applied to the AEN2/
of
the Bus Arbiter
5-2
sheet 3).
iSBC 86/1X to
ON
BD ADR/
SO-S2 status signals indicate
BPRO/ out-
of
the Multibus when the
is
driven low.
of
gate A2-11 (3ZC4).
On
the next
of
as a
It
should be noted that, after gaining control tibus, the to prevent losing control at a critical time. (For instance, it
may be desired to execute several consecutive commands
without having to contend for the bus after each command
is driving the Bus Arbiter ways:
a. b.
During an interrupt from the 8259A PIC, the LOCK input is signals issued by Status Decoder A81. (Refer to paragraphs 4-37 through
is
4~27.
in
The following paragraphs describe on-board and system
VO
specific read and write commands to on -board are described in Chapter 3.
4-28.
.
AB3-ABF are applied to the posed developed by flip-flop A63-5 (2ZA2) when the ALE
signal latches the ADR AACK! when AB8-ABF are false, AB6-AB7 are true,
iSBC 86/12 can invoke a
executed.)
By executing a software LOCK XCNG command. By
automatically driven low by the first
The
"'bus
lock"
LOCK input low
clearing an option bit via
4-39.)
"bus
lock"
condition is invoked by
VO
Port
I/O OPERATION
operations. The actual functions performed by
ON-BOARD
of
A54/55/56 (6ZA 7). The
is
true, the
I/O
OPERATION.
VO
Address Decoder ,com-
ADV
I/O ADR signal is
CPU inverted S2 signal. When
VO
Address Decoder develops 10
of
the Mul-
condition
in
one
of
Cc.
of
two INT
VO
devices
Address bits
ADV
two
AI
I/O
4-11
Page 76
Principles
of
Uperation
iSBC
86/12
and AB5 is either true
AACK!
signal
or
false.
The
I/O enables decoder A54, which then decodes AB3-AB4. (The
I/O AACK signal also drives the CPU READY input
high.) Assuming AB8-ABF are false, AB3-AB7 are
de-
coded to generate the following chip select signals:
are
10
Chip Select
Signal
8259CSI
8255CSI
8253CSI 8251CSI
invalid.)
EN/ and
of
ON
BD
Status De-
of
data
Bits
7 6
543
1
000
1 1 1 0 0 1 1
101
1 1 0 1 1 08,
*Odd address
The
10
0
AACK!
respectively, to develop ADR/. (4ZD4) and
PROM
ON
Bus Command Decoder. The
Addresses*
CO,C2
C8,
CA,
CC,
02, 04,
~C,
C3,
....
CE
06
DE
~O)
(Le.,
signal
~O,
OA,
C1,
is
driven through A32-8 and A6-8,
PROM
10
EN/ enables Data Buffer A44/45
BD
ADR/ inhibits the Bus Arbiter and
DT/R output coder A81 is inverted to select the proper direction transfer through the Data Buffer.
Mter
the proper I/O device is enabled, the specific func­tion for the device is selected by address bits ABO-AB1 and the
10RC/
or
10WC/
output
of
Status Decoder A81.
4-29. SYSTEM I/O OPERATION. Address bits
. AB3-ABF are decoded by the I/O Address Decoder as
described in paragraph 4-27. on-board
I/O device, the (high) and enables the Bus Arbiter Assembly and Bus Command Decoder A53. (Refer to figure The
Bus Arbiter and Bus Command Decoder, which are
clocked by the
signals
5-MHz
SO-S2, then acquire control
described in paragraph 4-26.
If
the address is not for an
ON
BD ADR/ signal is false
5-2
sheet
3.)
clock to latch in and decode status
of
the Multibus as
IC sockets A29 and A47 accommodate the top
of
ROM!
EPROM; IC sockets A28 and A46 accommodate the ROM/EPROM space directly below that installed in A29 and A47. The low-order bytes (bits DBO-DB7) are
in­stalled in A29 and A28; the high-order bytes (bits DB8-DBF) are installed in A47 and A46.
ADV
10
ADR
is
When
false, a custom (6ZB6) decodes address bits ABB-AB 12. within the limit specified above, the pins will be low and the depend half
on
whether the address is in the upper half
of
the address block. For instance, chips are installed and the address FF7FF, the tively;
and
02
and
01
if
the address is in the range FF800-FFFFF, the
01
pins will both are compared with address bit AB PROM
AACK!
signal
02
and
01
is
pins will be high and low, respec-
be
high.
The
04
13.·
is
asserted;
if
AB13
ROM
If
the address
04
and
03
output pins will
or
if
2758 EPROM
in the range
and
03
output pins
If
AB
13
is
high, the
is
low, the ON
(A68)
output
lower
FFOOO-
02
BD RAM RQT/ signal is asserted.
When ALE goes false, Decoder A18 (6ZC4) is enabled and decodes the inputs presented by the of
A68.
If
02/01
A28 and A46;
= 10, PCS2! is asserted and enables
if
02
and
01
= 11, PS3/ is asserted and
enables A29 and A47. Each chip
02
and
01
of
the selected pair
output
of chips are individually addressed by AB1-ABA. Thus, when the associated enable signal asserted, the contents ABA are transferred to the
of
the address specified by AB1-
CPU via Data Buffer A44/45 .
(PCS2/
or
PCS3/) is
4-31. RAM OPERATION
As described in paragraph logic allows the on-board RAM facilities to be shared by the
8086 CPU and another bus master via the Multibus. The following paragrapbs describe the RAM chip arrays, and the overall operation RAM is addressed for read/write ooeration.
4-22,
the Dual
RAM
Port
Control
Controller, of
how the
is
4-30. ROM/EPROM OPERATION
The
four ROM/EPROM chips are installed by the user in IC sockets A28/29/46/47. (Refer to figure The
ROM/EPROM addresses are assigned from the top down in the I-megabyte address space; the bottom dress is determined by the user configuration follows:
ROM
-
2316E
2332
Jumper posts edy
configured to accommodate the type
EPROM
4-12
installed. (Refer to table
EPROM
2758 2716
-
94
through 99 and switch S 1 must
5-2
Address
FFOOO-FFFFF FEOOO-FFFFF FCOOO-FFFFF
2-4.)
sheet
of
chips as
Block
be
of
6.)
ad-
prop-
ROM/
4-32. RAM CONTROLLER. All address
RAM
inputs to the on-board
is supplied by
and
RAM
control'
Control­ler A70 (IOZB6). The RAM Controller automatically provides a 64-cycle RAS/CAS refresh timing cycle to the dynamic RAM composed
of
RAM chips A 72- 79 and
A92-99.
The RAM Controller, when enabled by a low input to its PeS/
pin, multiplexes the address to the
Low-order address bits
AO-A6 are presented at the RAM
address lines and RAS/ is driven low at the beginning
RAM
chiRs.
of
the first memory clock cycle. High-order address bits
A 7 -A13 are presented at the RAM address lines and
CASt
is driven low during the second memory clock cycle. The
WE/
RAM Controller drives its whether the operation, the WT/ input
CPU instruction is a read
is
output pin according to
or
write.
low to the
RAM
For
a write
Controller, in
Page 77
iSBC 86/12
Principles of Operation
which case the WEI output operation, the WR/ input
is
driven low. For a write
is
low and the WEI output remains high. When the memory cycle (read or write) starts, the RAM Controller drives its SACK/ output low; when the memory cycle
is
complete, it drives its XACK!
output low. The SACK/ and XACK!· go high when the
RD/ or WR/ input goes high.
RAM
4-33.
CHIPS.
A72-A79 and odd bytes
The WE/ input pin to A72-A79
Even bytes
of
data are stored
is
of
data are stored
in
controlled
A92-A99.
by
ANDing
in
the RAM Controller WEI output and memory address bit
AMO.
The WEI input pin to A92-A99
ANDing the RAM Controller WEI output,
is
controlled
AMO,
by
and
MBHEN/ (Memory Byte High Enable).
ON BOARD
4-34. When the
04
output
are both low, the output
READ/WRITE
of
A68 (6ZB6) and address bit
of
AS3-6 goes low and asserts the
OPERATION.
AB
13
ON BD RAM RQT/ signal. When ON BD RAM RQT/ goes low,
BD CMD EN/ DPRD/ or 4-8.) The RAM Controller then multiplexes the address
AS2-3
(llZA3)
to
generate RAMCS via AS2-11 and to gate
DRWr/
to
is
enabled and generates ON
the RAM Controller. (See Figure
to RAM and, depending on which input command it true (DPRD/ or DPWT/), drives its WEI output high or low.
is
(The WE/ output for a read.) The by
the RAM Controller
The
CPU completes the read
XACK!
During the
is
asserted.
CPU access
driven low for a write; it remains high
SACK! and XACK! signals are generated
as
described in paragraph 4-33.
or
write operation when
of
on-board RAM, the Address Bus Drivers and Data Bus Drivers are disabled and the Address Buffer and Data Buffer are enabled.
A49-10 goes low, develops the RAMCS. and SLAVE CMD EN/ signals. RAMCS enables RAM Controller A 70 and SLA
VE
CMD EN/ gates DPRD/ or DPWT/
to
the RAM Controller. The RAM Controller then multiplexes the address to RAM and, depending on which input mand
is
true (DPRD/ or DPWT/), drives its WEI output
is
high or low. (The WEI output
driven low for a write; it
com-
remains high for a read.) The SACK! and XACK! signals are generated
by
the RAM Controller
as
described
in paragraph 4-34. The CPU completes the read or write operation when
XACK!
During the Multibus access SLA
VE
MODE/ signal enables the Address Bus Drivers
(A86/87/88); the
ON BD ADR/ signal
is
asserted.
of
on-board RAM, the
is
false and enables
the Data Bus Drivers (A69/89).
BYTE
4-36.
the on-board RAM all even byte data
odd byte data
to
figure 3
operation
OPERATION.
is
organized
is
in
one bank (DATO/-DAT7/) and all
is
in
the other bank (DAT8/-DATF/). Refer
-1
which shows the data path for Multibus
by
8-bit and 16-bit bus masters.
For Multibus operation,
as
two 8-bit data banks;
The Byte High Enable (BHEN/) signal. when asserted.
(odet)
access the high
access the low
byte; address bit ADRO/, when low,
(~ven
l
h.¥te.
All
word operations must
occur on an even byte address boundary with BHEN/
in
one
of
asserted. Byte operations can occur a.
The even bank can be accessed by controlling ADRO/, lines. (Refer
b. To access the odd bank, which
which places the data on the DATO/-DAT7/
to
figure 3-1A.)
is
normally placed on
two ways:
DAT8/-DATF/, the data path shown in figure 3-1B
is
implemented. This requires that BHEN/ be false
and
ADRO/
to
be low.
BUS
4-35. another bus master has control
READ/WRITE
OPERATION.
of
the Multibus, that bus
master can address the iSBC 86/12
device. The bus master first places the address on the
Multibus and then asserts MRDC/ or MWTC/. Address bits ADRD/-ADRlO/ and switch
SI
dress to a special ROM (A67) (3ZB6); address bits
ADRD/-ADRI3/ are decoded tings
of
S I represent the base address and memory bus
size; the
01-03
which are multiplexed
outputs
by
by
A66. The switch set-
of
A67 are ATRD/-ATRF/,
A86 (SZC4) into memory ad­dress bits AMC-AMF when the SLA subsequently activated The
04
output
of 128K byte matches) to develop the RQT signal, which Logic.
If
no
CPU access
by
the Dual Port Control Logic.
A67
is
driven through A23-4 (when the
OFF BD RAM ADR
is
applied to the Dual Port Control
is
in
progress, the Dual Port
Control Logic then enters the slave mode and, when
When
as
a slave RAM
present a lO-bit ad-
VB
MODE/ signal
These operations permit the access
by
16-bit data word ADRO/
of
therefore specifies a unique byte and is
a 16-bir word operatIon.
controlling
Shown below are the states
of
AD~/.
of
BHEN/ and
both bytes
8-bit and 16-bit operations and the effects on transceiver control and memory block chip select.
is
Bus Control
Lines Chip
BHENI
ADROI
1 1 1
0 1 0 0
Data Bus Driver
A69
On Off
0
On On Off Off
Select
A89
A90 A72-A79
On Off
Off On Off
On
Memory
Yes
No
Yes
No
of
the
In other words,
nota
part
Chip
ADRO/
Select
for
Block
A92-A99
No
Yes Yes
Yes
4-13
Page 78
Principles
of
Operation
iSBC8~
4-37. INTERRUPT OPERATION
The 82S9A PIC can support both bus vectored (BV) and non-bus vectored (NBV) interrupts. For both BV and NBV interrupts, the on-board the master PIC. (Refer to paragraph 2-13;) The master
PIC drives the CPU INTR input high to initiate an inter­rupt request and the CPU then enters the intel11lpt timing
in
cycle NB
which two INTA cycles occur back-to-back. The
V and B V interrupts are described in following
paragraphs.
NBV
4-38. rupt
is
INTERRUPT.
initiated by an on-board function driving the line high to the on-board PIC; if no higher interrupt progress, the PIC then drives the CPU INTR input high. Assuming that the NMI interrupt CPU interrupt enable flip-flop the current operation and proceeds with the first back-to-back INTA cycles. (Refer to figure nals activated during the first and subsequent INT A cycle.)
The Bus Arbiter acquires control
MCE signal drives the tibus control until the second INT A cycle is complete. The Bus Command Decoder drives the INTAI signal low. receipt
of
the first INT the internal state INTN
signal also sets flip-flop A63-S (8ZA2), which
generates the 1st
of
its priority resolution logic. The first
ACK!
input high.
CPU then proceeds with the second INT A cycle. On
The
receipt
of
the second INT an 8-bit identifier for IRS on the data bus, and drives its DEN/ output low. The resultant signal enables Data Buffer A44 and drives the READY input high. (The second
PIC (A24) (8ZB6) serves
as
Assume that a NBV inter-
IRS
is
is
inactive and that the
is
set, the CPU suspends
of
two
4-6
for sig-
of
the Multibus and the
LOCK! signal low to ensure Mul-
On
AI
signal, the master PIC freezes
signal to drive the CPU READY
AI
signal, the master PIC places
LOCAL INTA DEN/
CPU
INTN
signaI' clears
in
flip-flop A63-S.) The CPU then inputs the 8-bit
identifi~
and terminates the interrupt timing cycle.
The
CPU multiplies the 8-bit identifier by four to derivq, the restart address service routine
of
the interrupting device. After the·
is
completed, the CPU automatically re
sets all its affected flags and returns to the main program.
BV
4-39.
INTERRUPT.
cerned, BV interrupts are handled exactly the same
As
far as the CPU
is
con-
as NBV interrupts. Assume that the IR6 line to the master PIC
is
driven by a slave PIC on the Multibus. When IR6 goes high, the master as previously described.
PIC drives the CPU INTR input high
On receipt
of
the first
INTN
signal, the master PIC generates BUS INTA DEN/ via its
DEN/ output and places the interrupt address code for IR6
CO-C2
on its output
pins; since QMCE/
of
the Status Decoder, the CO-C2
is
enabled
by
the MCE
is
transferred to the Address Latch via address lines AD8-ADA. (These bits are latched when the ALE signal goes false.) The
BUS INTA DEN/ signal enables the Data Bus Driver in prep­aration to receive the 8-bit identifier from the slave PIC. (The interrupt address code lines
ADR8/-ADRN.)
is
now on Mu\tibus address
The first INT N signal sets flip-flop A63-S to drive the CPU READY input high. The CPU then proceeds with the
second INT A cycle. When the second INT A/ signal
driven onto the Multibus and the slave PIC recognizes its
address,
-DAT7/ lines and drives the Multibus (The second INT A63-S.) The
it
outputs an 8-bit identifier onto the
XACK!
N also toggles and clears flip-flop
CPU then inputs the 8-bit identifier and
DATO/
line low.
terminates the interrupt timing cycle.
The
CPU multiplies the 8-bit identifier by four to derive
of
the restart address
service routine is completed, the
the interrupting device. After the
CPU automatically re-
sets all its affected flags and returns to the main program.
..
is
4-14
Page 79
APPENDIX
A
TELETYPEWRITER
A-1.
INTRODUCTION
This appendix provides information required to
modify a Model certain Intel
A-2. INTERNAL
ASR-33 Teletypewriter for use with
iSBC
80
computer systems.
MODIFICATIONS
''4hW!Uf
Hazardous voltages are exposed when the top cover To prevent accidental shock, disconnect the teleprinter power cord before proceeding beyond this point.
Remove the top cover and modify the teletypewriter as follows:
of
the teletypewriter
is
removed.
MODIFICATIONS
substituted card has been assembled, mount shown using two self-tapping screws. Connect the relay cir­cuit to the distributor trip magnet and mode switch
follows:
a. Refer to figure A-4 and connect a wire (Wire
from relay circuit card to terminal L2 on mode switch. (See figure A-6.)
b. Disconnect brown wire shown in figure A-7 from
plastic connector. Connect this brown wire to ter­minal to be extended.)
c.
Refer to figure A-4 and connect a wire (Wire from relay circuit board to terminal switch.
'for the thyractor.) After the relay circuit
it
in position as
in
figure A-5. Secure the card to the base plate
L2
on mode switch. (Brown wire will have
Ll
on
as
'A')
'B')
mode
a. Remove blue lead from
source register; reconnect this lead to
tap. (Refer
b.
On
terminal block, change two wires as follows to
(:reate an internal full-duplex loop (refer to figures
A-I and A-3):
1.
Remove brown/yellow lead from terminal reconnect this
Remove
2. reconnect
On
c.
terminal changes the receiver current level' from 60 rnA 20 rnA.
A relay circuit card must be fabricated and connected
to the paper tape reader driver circuit. The relay cir-
cuit card to be fabricated requires a relay, a diode, a
thyractor·, a small 'vector'
components, and suitable hardware for mounting the
assembled relay card.
circuit diagram
A in
figure A-4; this diagram also includes the part numbers that a 470-ohm resistor and a 0.1
to
figures A-I and A-2.)
lead
white/blue lead from terminal 4;
this lead to terminal 5.
terminal block, remove violet lead from
8;
reconnect this lead
of
of
the relay, diode, and thyractor. (Note
750-ohm tap on current
to terminal 5.
to
terminal 9. This
board
the relay circuit card
for mounting the
I1F
capacitor may be
1450-ohm
to
is
included
3;
A-3. EXTERNAL
Connect a two-wire receive loop, a two-wire send loop, and a two-wire tape reader control loop to the external device as shown in figure A-4. The extetnal connector pin numbers shown in figure A-4 are for interface with an
CONNECTIONS
RS232C device.
A-4. iSBC 530 TTY ADAPTER
The iSBC 530, which converts RS232Csignai l£vels to an optically isolatt:d provides signal translation for· transmitted received data, and a paper tape reader relay. The iSBC 530 interfaces
to
system
The 98
rnA.
80 diagram The following auxiliary power connector (or equivalent) must be procured by the user:
a teletypewriter as shown in figure A-8.
iSBC 530 requires +12V
An
auxiliary supply must be used if the iSBC
system does
of
Connector, Molex Pins, Polarizing
not
the iSBC 530
Molex 08-50-0106
20mA
an
supply this power. A schematic
Key, Molex 15-04-0219
curreut100p interface,
Intel iSBC
at
98
is
supplied with the unit.
09-50-7071
mA
80
computer
and
-12V
data,
at
A-I
Page 80
Teletypewriter
Modifications
MODE
SWITCH MOUNT
CIRCUIT
CARD
CAPACITOR
CURRENT
SOURCE
RESISTOR
POWER
SUPPLY
TERMINAL
BLOCK
KEYBOARD
PRINTER
DISTRIBUTOR
TRIP
MAGNET
ASSEMBLY
FloCARD
lQJ
TELETYPE
TOP
VIEW
UNIT
GOTOV
MODEL
33TC
TAPE
READER
TAPE
PUNCH
Figure A-2.
Current
Figure
A-I.
Teletype
Component
Layout
Source Resistor Figure A-3.
Terminal
Block
A-2
Page 81
TERMINAL
BLOCK 151411
Teletypewriter Modifications
"
..
25·PIN
EXTERNAL
CONNECTOR
RECEIVE
SEND 3
9
8
7
6
5
4
r-r-----i-~;.~l=f-=-
2
VIO VEL
--
-
----
BLK/GRN WHT/BRN
RED/GRN
WHT/VEL WHT/BLK WHT/BLU
BRN/VEl
GRN
RED
-~https://manualmachine.com/R~;--
BLK BLK
WHT
WHT
TAPE
READER
CONTROL
20MA
60MA
- -
------'"
FULL
DUPLEX
-
--
--
CONNECTOR r-t...._,
L...r
0.11#lF
~
..,.
--
117VAC
DISTRIBUTOR
I
MAGNET
L..-·U----'lIVv----l
4700
TRIP
117
VAC
COMMON
*ALTERNATE
.-Jr--1-47-0-Q-y"~W
L
TO.1200V
CONTACT
CIRCUIT
PROTECTION
I
IJR.1006
I OPEN
lW-~~Il!LC~
Figure A-4. Teletypewriter Modifications
~2VDC;600Q
~~RMAL
COIL
CONTACTS
_
WIRE'B'
,S
Figure
A-S.
Relay Circuit
Figure A-6.
Mode
Switch
A-3
Page 82
Teletypewriter
Modifications
FROM
SERIAL
PORT
IN/OUT
CINCH OB-25S
Figure A-7.
P3 TTY
Figure A-S.
Distributor
J1
iSBC 530
ADAPTER
J2
TTY
Adapter
Trip
Cabling
Magnet
TO
TERMINAL
(SEE
FIGURES
CINCH OB-25P
A-3
BLOCK
AND
A-4)
A-4
Page 83
CHAPTER 5
SERVICE INFORMATION
5-1. INTRODUCTION
This chapter provides a list diagrams, and service and repair assistance instructions for the iSBC 86/12 Single Board Computer.
of
replaceable parts, service
5-2. REPLACEABLE PARTS
Table 5-1 provides 86/12. Table 5-2 identifies and locates the manufacturers specified in the MFR
parts that are available on the open market are listed in the
MFR
CODE column
made to procure these parts from a local (commercial)
distributor.
alist
of
replaceable parts for the iSBC
CODE column in
as
"COML";
table5-I.
Intel
every effort should be
5-3. SERVICE DIAGRAMS
The iSBC 86/12 parts location diagram and schematic
diagram are provided in figures 5-1 and 5-2, respectively. On the schematic diagram, a signal mnemonic that ends with a slash (e.g., signal mnemonic without a slash (e.g., INTR)
10WC/)
is
active low. Conversely, a
is
active
high.
5-4. SERVICE AND REPAIR
ASSISTANCE
United States customers can obtain service and repair assistance from Intel by contacting the MCD Technical Support Center in Santa Clara, California, at one following numbers:
of
the
Telephone:
From Alaska or Hawaii call -
(408)
987-8080
From locations within California call toll free -
(800) 672-3507
From all other
U.S. locations call toll
free-
(800) 538-8014 TWX: 910-338-0026 TELEX:.
34-6372
Always contact the MCD Technical Support Center be­fore returning a product to Intel for service will be given a
"Repair
Authorization Number", ship-
or
repair. You
ping instructions, and other important information which will help Intel provide you with fast, efficient service. If the product during shipment from Intel, warranty, a purchase order MCD
In preparing the product for shipment to the MCD
is
being returned because
is
of
damage sustained
or
if the product is out
necessary in order for the
Tlechnical Support Center to initiate the repair.
Techni-
of
cal Support Center, use the original factory packaging material,
if
available.
If
the original packaging
is
not available, wrap the product in a cushioning material such as
Air Cap TH-240 (or equivalent) manufactured by the
Sealed Air Corporation, Hawthorne, N.J. , and enclose in
a heavy-duty corrugated shipping carton. Seal the carton securely, mark
it
"FRAGILE"
to ensure careful han­dling, and ship it to the address specified by MCD Techni­cal Support Center personnel.
NOTE
Customers outside tact their sales source (Intel Sales Office thorized Intel Distributor) for directions on obtain­ing service
of
the United States should con-
or
repair assistance.
or
Au-
Reference Designation
A1,37,62 A2,21 ,53 A3,7
M,49
A5
A6,51 A8,9 A14
A15
A16 A17,80
A18,54
A19,32
A20,34
A22,59
A23 A24
IC, 74125, Quad Bus Buffer (3-state) SN74125 IC, 74S32, Quad 2-lnput Positive-OR. IC, 74S10, Triple 3-lnput Positive-NAND Gate IC, 74S175, Hex Quad D-Type Flip-Flop IC, 9602, Dual One-Shot Multivibrator IC, 74S11, Triple 3-lnput Positive-AND Gate IC, Intel 8226, 4-Bit Bidirectional Bus Driver 8226 IC, 75189, Quad Une Receivers SN75189 IC, 75188, Quad Une Drivers SN75188 IC, 74163, Sync 4-Bit Counter . SN74163 IC, Intel 8224, Clock Generator and Driver 8224
IC, 74S139, Decoder/Multiplexer SN74S139 IC, 74S08, Quad 2-lnput Positive-AND Gate IC,
74S04, Hex Inverters
IC, 7432, Quad 2-lnput Positive-OR Gate SN7432 IC, 74S02, Quad 2-lnput Positive-NOR Gate IC, Intel 8259A, Programmable Interrupt Controller 8259A COML
Table 5-1. Replaceable Parts
Description Mfr. Part No.
Gate
SN74S32 SN74S1 0 SN74S175 9602PC SN74S11
SN74S08
SN74S04 SN74S02
Mfr.
Code
TI TI TI TI
FAIR TI 2 COML TI 1 TI 1 TI 1
COML
TI
TI
TI 2 TI TI
Qty.
3 3 2 2
1
2
2 2
2 2
1 1
5-1
Page 84
Service
Information
Table 5-1. Replaceable Parts (Continued)
iSBC
86/12
Reference
A25 A26 A27 A30, 57 A31,33,43,52 A35,84,85 A36 A38 A39 A40,41,71,91 A42,44,45,58,60,61 A48 A50,63 A55 A56 A64 A65 A66 A67 A68 A69,87-90 A70 A 72-79,92-99 A81,83 A86
CR1,2 C1
,2,4-11 ,13,15-19, 21-25,28-51,65-75, 91
C3 C12,27,64 C20,98 C26 C52,54,55,57,58,60,61
63,76,78,79,81,82,84,
85,87,92
C53,56,59,62,77,80,
83,86
C88-90,93-97 Cap., tant.
Designation
IC, Intel 8255A, Programmable Peripheral Interface IC,
Intel 8253, Programmable Interval Timer IC, Intel 8251A, Programmable Comm. Interface IC,
74LS75, 4-Bit Bistable Latch IC,
74S00, Quad 2-lnput Positive-NAND Gate IC,
74LS04,
IC,
7400, Quad 2-lnput Positive-NAND Gate IC, Intel 8284, 18-Pin Clock Generator IC,
Intel 8086, 16-Bit Microprocessor IC,
74S373, Octal D-Type Latches IC,
Intel 8286, 8-Bit Non-Inverting Transceiver
IC,
7438, Quad 2-lnpu1 Positive-NAND Gate
IC,
74S74 IC, 74S30, 8-lnput Positive-NAND Gate IC,
7425, Dual4-lnput Positive-NOR Gate w/Strobe
IC,
74S140, Dual 4-lnput Positive-NAND Gate IC,
8097, 3-State Hex Buffers IC,
Intel 8205, 1 -of-8 Decoder
IC,
PROM, Address Decoder IC,
PROM, Address Decoder
IC,
Intel IC,
Intel 8202, Dynamic IC,
Intel 2117-4, Dynamic
IC,
Intel 8288, Bus Controller for 8086
IC,
74S240, Octal Buffer/Line Driver/Line Receiver
Oiode,1N9148
Cap., mono,
Cap., mono,
Cap., mica, 1 Cap., mono, Cap., tant. Cap., mono,
Cap., mono,
Description
Hex
Inverters
..
Dual D-type Edge-Triggered Flip Flop
8287,8-Bit
10JLF,
22JLF,
Inverting Transceiver
RAM
C;ontroller 8202
RAM
0.1JLF,
+80
-20°0, 50V
1.0JLF,
±1000, 50V OBO
OpF,
±5~,0,
0.001JLF,
0.33JLF,
0.01JLF,
500V OBO
+20~'0,
±10O,o,
+80
+X()
±100,0,
50V
20V
-20~0,
50V OBO
-20°'°, 50V OBO COML
15V
Mfr.
Part
8255A 8253 8251A SN74LS75 SN74S00 SN74LS04 SN7400 8284L 8086
SN74S373 8286 SN7438
SN74S74
SN74S30
SN7425
SN74S140
DM8097
8205
INTEL
INTEL
8287
2117-4
8288
SN74S240
OBO
OBO
OBO OBO
OBO
No.
Mfr.
Code
COML 1 COML COML 1 TI TI TI TI COML COML TI COML 6
aty.
TI TI
TI TI TI NAT COML 9100134 9100129 COML COML COML COML 2 TI
COML COML
COML COML COML COML COML
COML
16
57
17
1 2
4
3
1 1 1
4
1 2 1 1 1 1 1 1 1 5 1
1
2
1
3 2
1
8 8
J12
- *IC, Bus Controller
-
- *Resistor, fxd, comp, 270 ohm,
-
-
-
RP1 RP2 RP3 RP4 R1,
11,16,17 Res., fxd, comp, 10K,
R2,22 R3-5,13,20 R7,8,1
0,
14, 18, 19,21,23 Res., fxd, comp, 1 R9 R12 R15
S1
VR1
5-2
Assembly, Bus Arbiter 1001794 INTEL 1 *IC, 74S00, Quad 2-lnpu1 Positive-NAND Gate SN74S00 *Resistor, fxd, comp, 2.2K,
*Capacitor, mono',
*Capacitor, mono, 220pF, ±5°'0, 500V
Res" pack, 8-pin, 1 Res., pack, 14-pin, 1K: Res" pack, 16-pin; 10K, Res"
pack, '6-pin, 2.2K,
Res., fxd, comp, Res"
fxd, comp,
Res., fxd, comp, Res" fxd, comp, 330 ohm, '±5%, %W Res., fxd, comp,
Switch, 8-position, DIP 206-8
Voltage regulator
0.1JLF,
K,
±5'\0,
±5%,
20K,
±5%,
5.1
K,
±5%,
K,
5%,
100K,
5%,
210 ohm,
+80
±2%,
±5%,
±5%,
Y4W
±5%,
±50/0,
±5%,
-20°'0, 50V
2W.
PP
1.~W
2W PP
1W %W %W
%W
%W
%W
%W OBO COML
%W
PP
PP
OBO
OBO COML
OBO COML
OBO OBO OBO aBO OBO OBO OBO OBO OBO COML OBO OBO COML
MC79L05AC MOT
INTEL
TI COML
COML COML COML
COML
COML COML COML
COML
COML
CTS
1 1
1 1 1
1 1 1
1 4 2 5 8
1
1 1
1
1
Page 85
iSBC
86/12
Table 5-1. Replaceable Parts (Continued)
Service
Information
Reference
XA8,9
XA10·13 XA27 XA28,29,46,47
XA39,70
XA67,68
XA71,91 Y1
Y2 Y3
MFR. CODE AMP
AUG
Designation
Socket, 16-pin, DIP Socket, Socket, 28-pin, DIP C-93·28-02 Socket, 24-pin, DIP
Crystal, 22.1184·MHz, fundamental Crystal, 15-MHz, fundamental Crystal, 18.432·MHz, fundamental Extractor,
14-pin, DIP
Socket, 40-pin, Socket, 18-pin, Socket, 20-pin, DIP
Cardt Post, Wire Wrap Plug, Shorting, 2-position
Description
DIP DIP
Table 5-2. List of Manufacturers' Codes
MANUFACTURER ADDRESS MFR. CODE AMP, Inc.
Augat,
Inc.
Harrisburg, PA
Attleboro, MA SCA
NAT
Mfr. Part No.
C·93-16-02 C-93-14-02
C-93-24·02
540-A37D C-93·18-02
C-93-20-02 OBD
OBD CTS OBD CTS S-203 SCA 89531-6
530153-1
MANUFACTURER
National Santa Clara, CA Semiconductor
Scanbe, Inc.
Mfr.
Code
TI TI TI TI AUG TI TI
CTS
AMP
AMP
ADDRESS
EI
Qty.
2 4 1
4
2 2 2
1 1 1 2
126
1
Monte, CA CTS FAIR
MOT
CTS
Corp.
Fairchild Semiconductor
Motorola Semiconductor
TX
Elkhart, Mt. View, CA OBD Order by Description; available from any
Phoenix, AZ
IN
TI Texas Instruments
commercial (COML)
Dallas,
source.
5-3/5-4
Page 86
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