Intel iSBC 86/12 Hardware Reference Manual

rr

iSBC 86/12

SINGLE BOARD COMPUTER

HARDWARE

REFERENCE MANUAL

Manual Order Number: 9800645A

I

Intel Corporation, 3065 Bowers

Av.~nue,

Intel

Corporation

Santa Clara, California 95051

.

L

The infonnation in this manual kind with regard to this manual, including, but not limited to, the implied warranties

is

subject to change without notice. Intel Corporation makes

no

warranty

of

merchantability and

of

any

fitness for a particular purpose. Intel Corporation assumes no responsibility for any errors that may appear in this manual. Intel Corporation makes no commitment to update nor to keep current the infonnation contained in this manual.

No

part

of

this manual may be copied or reproduced

Intel Corporation. The following are trademarks

in

any fonn

or

of

by any means without the prior written consent

Intel Corporation and may be used only

to

describe

Intel products:

ICE·

30

ICE·gO

INSITE INTEL INTEU.EC

iSBC

LIBRARY

MANAGER MCS MEGACHASSIS MICROMAP

MULTIBUS PROMPT UPI RMX

ii

Printed in

U.S,A./B66/0778(TL

7.SK

PREFACE

This manual provides general information, installation, programming information, principles of operation, and service information for the Intel iSBC 86/12 Single Board

Computer. Additional information

is

available in the following documents:

• 8086 Assembly Language Reference

• Intel MCS-85 User's Manual, Order No. 98-366

• Intel 8255A Programmable Peripheral 1 nterface , Application Note AP-15

• Intel 8251 Universal Synchronous/Asynchronous Receiver/Transmitter, Application

AP-16

Note

• Intel MULTIBUS Interfacing, Application Note AP-28

• Intel 8259 Programmable Interrupt

Ma~ual,

Cm~troller,

Order No. 9800640

Application Note AP-31

iii

CHAPTER 1 GENERAL INFORMATION

Introduction Description System Software Development Equipment Equipment Required Specifications

....................................

.....................................

.....................

Supplied . . . . . . . . . . . . . . . . . . . . . . . . . . . .

..............................

...................................

CHAPTER 2 PREPARATION

Introduction

Unpacking and Inspection

Installation Considerations . . . . . . . . . . . . . . . . . . . . . . .

User-Furnished Components Power Requirement Cooling Requirement Physical Dimensions

Component Installation. . . . . . . . . . . . . . . . . . . . . . . . . .

ROM/EPROM Chips Line Drivers and

Jumper/Switch Configuration

RAM Addresses (Multibus Access) Priority Interrupts

Serial I/O Port Configuration. . . . . . . . . . . . . . . . . . .

Parallel I/O Port Configuration

Multibus Configuration

Signal Characteristics Serial Priority Resolution

Parallel Priority Resolution Power Fail/Memory Protect Configuration Parallel I/O Cabling Serial I/O Cabling Board Installation

.....................................

FOR USE

.........................

.....................

............................

...........................

............................

...........................

I/O Terminators

...

. . . . . . . . . . . . . . . . . . . . . . . . .

...........................

..........................

.......................

.............................

...............................

.................

.......................

................

...................

.....................

...........

CHAPTER 3

PROGRAMMING INFORMATION

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Failsafe Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Memory Addressing

CPU Access

Multibus Access I/O Addressing System Initialization 8251A

USART Programming

Mode Instruction Fonnat Sync CharaCters Command Instruction Fonnat

........................................

Reset

Addressing

Initialization Operation

.....................................

Data

Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . .

Status Read

..............................

..................................

................................

..................................

..............................

......................

........................

...............................

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PAGE

,

1-1 I-I 1-3

..

1-3 1-3 1-3

2-1 2-1

..

2-1 2-1 2-1 2-1 2-1

..

2-1 2-1

2-4

..

2-6

..

2-9 2-9

2-9 2-13 2-13

2-13 2-13 2-23 2-23 2-23

..

3-1

..

3-1 3-1 3-1

3-2 3-3 3-3

3-4

3-5

3-5 .

3-5

3-6

3-7

..

3-7 3-7

CONTENTS]

8253 PIT Programming

Mode Control Word and Count Addressing Initialization

Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Counter Read Clock Frequency/Divide Ratio Selection Rate Generator/Interval Interrupt Timer

8255;\

Control Word Fonnat Addressing Iniitialization

Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Read Write

8259A

Interrupt

Nested Mode Fully Nested Mode Automatic Rotating Mode Specific Rotating Mode Special Mask Mode Poll Mode

Status Read

Initialization Command Words

Operation Command Words. . . . . . . . . . . . . . . . . . .

Addressing Initialization

Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Hardware Interrupts

Non-Maskable Interrupt (NMI) Maskable Interrupt (lNTR)

Master

Slave PIC Byte Identifier

..................................

.................................

ppl

Programming . . . . . . . . . . . . . . . . . . . . . . .

..................................

.................................

Operation

PIC-Programming

Priority Modes. . . . . . . . . . . . . . . . . . . . . .

.................................

..................................

.................................

PIC Byte Identifier

CHAPTER 4 PRINCIPLES

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Functional Description

Clock Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Central

Processor Unit . . . . . . . . . . . . . . . . . . . . . . . .

Interval Timer Serial I/O Parallel I/O Interrupt Controller

ROM/EPROM Configuration

RAM Configuration

Bus Structure Multibus Interface

.....................................

.................

...........................

...................

..............................

Timer.

.............................

..........................

.............................

............................

.........................

...............................

..........................

.........................

.............................

. . . . . . . . . . . . . .

....................

......................

..................

.....................

....................

....................•

OF OPERATION

............................

.................................

. . . . . . . . . . . . . . . .

.............•...............

.....................

............................

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PAGE

3-8

3-8 3 -12 3 -12

..

3-1"3 3-13 3-13

..

3 -14 3-14

..

3 -14

3-15 3-15 3-16

..

3 -16 3-16 3-16 3-17

..

3 -17 3-17 3-17 3 -17 3-17

3-18 3-18 3-18

3 -18

..

3 -19

..

3 -19 3-25

3-25

..

4-1

4-1 .. ..

..

, 4-3

4-1 4-1 4-1 4-1 4-1 4-2 4-2 4-2 4-2

iv

I,

CONTENTS (Continued)

Circuit Analysis

Initialization Clock Circuits Central Processor Unit

Basic Timing

Bus Timing Address Bus Data Bus Bus Time Out Internal Control Signals

Dual Port Control Logic

Multibus Access Timing

CPU Access Timing

Multibus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O Operation

On-Board I/O Operation System I/O

ROM/EPROM Operation . . . . . . . . . . . . . . . . . . . . . . .

.................................

..........................

................................

.................................

..................................

.....................................

...............................

.........................

...........................

........................

............................

..................................

.......................

Operation.

. . . . . . . . . . . . . . . . . . . . . . .

PAGE

"

..

4-11 4-11 4-11

..

4-12

..

4-12

4-3

4-4 4-4

4-4 4-4 4-4 4-6 4-6

4-6

4-8 4-8 4-8 4-8

RA\1 Operation

RA\1 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

RA\1 Chips On-Board Read/Write Operation Bus Read/Write Operation Byte Operation

Interrupt

Operation. NBVlnterrupt B V Interrupt

................................

..................................

.................

......................

.............................

. . . . . . . . . . . . . . . . . . . . . . . .

................................

...............................

" 4-13

.. " 4-14

"

CHAPTER 5 SERVICE INFORMATION

Introduction Replaceable Service Diagrams

Service and Repair Assistance. . . . . . . . . . . . . . . . . .

.....................................

Parts

.............................

............................

APPENDIX A TELETYPEWRITER MODIFICATIONS

PAGE

4-12

4-13 4-13 4-13

4-14

5-1 5-1 5-1 5-1

v

I

TABLES

TABLE

1·1

2·1

2~2

2·3

2·4 2·5 2·6

2·7

2·8

2·9

2·10

2·11

2·12

2·13

2·14

2·15

2·16

2·17

3·}

3·2

3·3

3·4

3·5

TITLE

Specifications

User-Furnished- and Installed Components

Furnished Connector Details

User· Line Driver and Jumper and Switch Selectable Options Priority Interrupt Jumper Matrix Serial

I/O Connector J2 Pin Assignments

Configuration Jumpers Parallel Multibus Connector Multibus Signal Functions

iSBC 86/12 DC Characteristics iSBC 86/12 AC Characteristics

(Master Mode)

iSBC 86/12 AC Characteristics

(Slave Mode) Auxiliary Connector P2 Pin Assignments Auxiliary Signal (Connector P2)

DC Characteristics

Parallel

Pin Assignments Parallel

DC Characteristics Connector J2 Vs RS232C Pin

Correspondence On -Board Memory Addresses

(CPU Access) I/O Address Assignments Typical

Instruction Subroutine Typical USART Data, Character Read

Subroutine Typical

Subroutine

...........................

...........

I/O Terminator Locations . .

............

....... : ..........

I/O Port Configuration Jumpers

PJ.

Pin Assignments

................

............

.......................

........ : ...............

.............

I/O Connector I/O Signal (Connector 11)

USART Mode

............................

USART Data Character Write

............................

11

......................

....................

.......................

.........................

..................

or

Command

..................

.......

'

.......

Vs

.....

....

PAGE

....

..

1-4 2-2 2-3

2-4 2-5 2-8

2-9

2-10 2-14 2-15

2-16

2-18

2-22

2-22 2-23

2-24

3-2

3-3

3 -7

3-8

TABLE

3-6

3-7

3-8 3-9

3-10

3-11

3-12

3-13 3-14 3-15 3-16

3-17

3-18

3-19 3-20

3-21

3-22

3-23 3·24

3-25 5-1

5-2

TITLE

Typical PIT Counter Operation Typical PIT Control Word Subroutine Typical PIT Count Value Load

Typical PIT Counter Read Subroutine PIT Count Value

PIT Rate Generator Frequencies and

PIT Time Intervals

Typical PPI Initialization Subroutine. . . . . .

Typical PPI Port Read Subroutine Typical PPI Port Write Subroutine Typical PIC Initialization Subroutine

Typical Master PIC Initialization Subroutine

Typical Slave PIC Initialization Subroutine

PIC Operation Procedures Typical PIC Interrupt Request

Typical PIC In-Service Register

Typical PIC Set Mask Register Subroutine Typical PIC Mask Register Read

Typical PIC End-of-Interrupt Command

Replaceable Parts List

US

ART Status Read Subroutine

Vs

Gate Inputs

Subroutine

Each Baud Rate

Timer Intervals . . . . . . . . . . . . . .

(NBV Mode)

(BV Mode)

Register Read Subroutine

Read Subroutine

Subroutine

of

...........................

Vs

Rate Multiplier for

......................

Vs

Timer Counts

.........................

..........................

...........................

........................

Manufacturers' Codes

................

......................

...............

..............

......

..

. . . . .

.......

..........

.........

.....

PAGE

..

...

3-9 3·12 3-12

3·12 3-13

3-14

3 -15 3-15 3-16 3-16 3-16

3-21

3-22 3-22

3-24

3-24 3-24

3-24

3-25

5-1

5·3

vi

Ij'

ILLUSTRATIONS

FIGURE

I-I

2-1

2-2

2-3 2-4

2-5

2-6 3-1

3-2

3-3

3-4

3-5

3-6

3-7

3-8 3-9 3-10

TITLE

iSBC 86/12 Single Board Computer Dual Port RAM Address Configuration

(Multibus Access)

Simplified Master/Slave

Interconnect Example Bus Exchange Timing (Master Mode) Bus Exchange Timing (Slave Mode) Serial

Priority Resolution Scheme Parallel Priority Resolution Scheme Dual Port RAM Addressing

(Multibus Access)

USART Synchronous

Word Format

USART Synchronous

...............................

Format

US

ART Asynchronous Mode Instruction

Word Format

USART

USART Word Format Typical USART Initialization and

USART Status PIT Mode Control Word Format

PIT Programming Sequence Examples

Asynchronous Mode Transmission

Format

...............................

Command Instruction

I/O Data Sequence

......................

PIC

...................

......................

Mode Instruction

..........................

Mode Transmission

..........................

............................

.....................

Read Format

.........

........

..........

........

...............

...........

......

PAGE

I-I

2-7

2-8 2-19 2-20 2-21 2-21

3-2

3-4

3-5

3-6

3-9 3-10 3-11

FIGURE

3-11

3-12 3-13

3-14

3-15 4-1

4-2

4-3 4-4 4-5 4-6

4-7

4-8

5-1 5-2 5-3 5-4

TITLE

PIT Counter Register Latch Control

Word Format PPI Control Word Format PPI Port C Bit Set/Reset Control

Word Format. PIC Initialization Command

Word Formats PIC Operation Control Word Formats iSBC 86/12 Input/Output and Interrupt

Simplified

86/12 ROM/EPROM and Dual Port RAM

iSBC

Simplified Logic Diagram " Internal Bus Structure CPU

Read Timing

CPU

Write Timing

CPU Interrupt Acknowledge

Cycle Timing

Dual Port Control Multibus Access

Timing With

Dual Port Control CPU Access Timing

With Multibus Lockout

iSBC

86/12 86/12 Schematic Diagram

iSBC iSBC 604 Schematic iSBC

614 Schematic Diagram

.....................

...................

Logic

Diagram.

...................

...........

.......................

.........................

CPU Lockout

PaJ1s

Location Diagram

Diagram

...............

. . . . . . . . . 4-15

............

,

...........

..

. . . . . . . . . .

................

.........

............

.............

...

PAGE

.

3-13

.

3-15

.

3-17

3-18

.

3-20

4-17

" 4-3

4-5 4-6

4-7

..

4-9

4-10

5-6

5-7 5-29 5-31

vii/viii

CHAPTER 1

1-1. INTRODUCTION

The iSBC 86/12 Single Board Computer, which member products, printed-circuit assembly. The

16-bit central processing unit (CPU), 32K bytes dynamic RAM, a serial communications interface, three programmable parallel priority interrupt control, Multibus control logic, and bus expansion drivers for interface with other compatible expansion boards. Also included control logic to allow the RAM device to other Multibus masters Provision is made for user installation of

of

Intel's complete line

is

a complete computer system on a single

read only memory.

of

iSBC 80/86 computer

iSBC 86/12 includes a

I/O ports, programmable timers,

is

iSBC 86/12 to act

in

the system.

of

up to 16K bytes

is

Multibus-

dual port

as

a slave

of

1-2. DESCRIPTION

The iSBC 86/12 Single Board Computer (figure 1-1) controlled by an Intel 8086 The

8086 CPU includes four 16-bit general purpose regis-

ters that may also be addressed as eight 8-bit registers. In

16-

B it Microprocessor (CPU) .

is

GENERAL

addition, the CPU contains two 16-bit pointer registers and two 16-bit index registers. Four 16-bit segment ters allow extended addressing to a full megabyte

a

memory. The CPU instruction set supports a wide range of

addressing modes and data transfer operations, signed and unsigned 8-bit and 16-bit arithmetic including hardware mUltiply and divide, and logical and string ations. The CPU architecture features dynamic code relocation, reentrant code, and instruction lookahead.

iSBC 86/12 has an internal bus for all on-board

The

memory and (Multibus) for all external memory and Hence, local (on-board) operations do not involve the Multibus, processing when several bus masters (e. and other single board computers) are used in a ter scheme.

Dual port control logic dynamic RAM with the Multibus so that the can function the Multibus. The CPU has priority when accessing onboard RAM. After the CPU completes its read

I/O operations and accesses the system bus

making the Multibus available for true parallel

as

a slave RAM device when not in control

INFORMATION

I/O operations.

g.,

D MA devices

is

included to interface the

regis-

of

oper-

multimas-

iSBC 86/12

of

or

write

(MULTIBUS)

645-1

f4'igure

(AUXIUARy)

1-1. iSBC 86/12 Single Board Computer

1-1

General Information

iSBC 86/12

operation, the controlling bus master is allowed RAM and complete its operation. Where both the

and the controlling bus master have the need to write or

read several bytes

their operations ary interleaved. For CPU access, the

on-board RAM addresses are assigned from the bottom up

of

the I-megabyte address space;

The slave RAM address decode logic includes jumpers

and switchers to allow partitioning the on-based RAM into any 128K segment space.

The slave RAM can be configured to allow either 8K, 16K

or

24K, RAM can be configured to allow other bus masters to access a segment another segment strictly for on-board use. The addressing scheme accommodates both 16-bit and 20-bitaddressing.

Four IC sockets are included bytes jumpers allow read only memory to be installed in 2K, 4K,

The lines implemented by means grammable software tion The

peripheral requirements and, in order to take full advantage sockets are provided for interchangeable

and terminators. Hence, the flexibility

interface the appropriate combination terminators'to and drive/termination characteristics for each application.

The 24-programmable

are brought with flat, woven,

32K access by another bus master. Thus, the

of

user-installed read only memory. Configuration

or

8K increments.

iSBC 86/12 includes 24 programmable parallel I/O

is

used to configure the I/O lines in any combina-

of

unidirectional input/output and bidirectional ports.

I/O interface may be customized to meet specific

of

the large number

is

or

words to

of

the on-board RAM and still reserve

Peripheral Interface (PPI). The system

of

further enhanced by the capability

provide the required sink current, polarity,

I/O ,lines and signal ground lines

out to a 50-pin edge connector

or

round cable.

or

from on-board RAM,

i.e.,

the 1-megabyte system address

to

accommodate up to 16K

of

an Intel 8255A Pro-

possible I/O configurations, IC

of

optional line drivers and

to

access

CPU

0OOOO-07FFFH·

I/O line drivers

the parallel I/O

of

selecting

(11)

that mates

In the asynchronous mode the following are programmable:

a.

Character length,

b.

Baud rate factor (clock divide ratios

c.

Stop bits, and Parity.

d.

In both the synchronous and asychronous modes, the

serial

I/O port features halffered transmit and receive capability. In addition, error detection circuits can check for parity, overrun, and framing errors. The rates are supplied by a programmable baud rate/time generator. These clocks may optionally be supplied from an external source. The RS232C command lines, serial data lines, and signal ground lines are brought out to a 50-pin edge connector cable.

Three independent, fully programmable 16-bit interval timer/event counters are provided by an Intel 8253 Programmable Interval Timer of

operating in either BCD

counters are available

accurate time intervals under software control. Routing

for the outputs and gate /trigger inputs counters may rammable Interrupt Controller

of

puts associated with the 8255A

the two counters may

from the 8255A

programmable baud rate generator for the serial

In utilizing the

configures, via software, each counter independently to

meet system requirements. Whenever a given time delay

is

or count

select the desired function. The contents

may

simple operations special commands are each counter·can

needed, software commands to the 8253 PIT

be

read at any time during system operation with

USART transmit and receive clock

be

independently routed to the 8259A Prog-

PPI. The third counter is used as a

iSBC 86/12, the systems designer simply

for event counting applications, and

be

read

or

full-duplex, double buf-

(12)

that mates with flat

(PIT). Each counter is capable

or

binary modes; two

to

the systems designer to generate

(PIC). The gate/trigger in-

be

routed to I/O terminators

PPI

or

included ~ that the contents

"on

the

of

1, 16,

or

64),

USART

or

round

of

these

of

two

of

these

as input connections

I/O

port.

of

each counter

fly".

of

The RS232C compatible serial I/O port is controlled arid

interfaced by an Intel 8251A

Syncronous/Asynchrortous

The

USART in most synchronous mission formats

In the synchronous mode the following are programma- . ble:

a. Character length,

Sync character (or chlU1lcters), and

b. c.

Parity.

1-2

is

individually programmable for operation

(including· iBM Bi-Sync).

ReceiverlTransmitter) chip.

or

asynchronous serial data trans-

US

ART (Universal

..

The iSBC 86/

~ruid

non-bus vectored (NBY) interrupts. An on-board

In.tel 8259A Programmable Interrupt Controller (PIC)

handles up to eight NBV interrupts. By using external PIC's slaved. to the on-board PIC (master), the interrupt structure can ityof

PIC, which can

The sensitive

signal condition as an interrupt request. After resolving the interrupt priority, the request to the programmable under software control. The program-

mable interrupt priority modes are:

12

provides vectoring for bus vectored (B V)

be

expanded to handle and resolve the prior-

upto

64 BV sources.

be

programmed to respond to edge-

or

level-sensitive inputs, treats each true input

PIC issues a single interrupt

·CPU. Interrupt priorities are independently

iSBC

86/12

a.

Fully Nested Priority. Each interrupt request has a

0

is

fixed priority: input

b.

Auto-Rotating Priority. Each interrupt request has

highest, input 7

is

lowest.

equal priority. Each level, after receiving service, becomes the lowest priority level until the next interrupt occurs.

c. Specific priority. Software assigns lowest priority.

Priority

of

all other levels

is

in

numerical sequence

based on lowest priority.

CPU includes a non-maskable interrupt (NMI) and a

The

is

maskable interrupt (lNTR). The NMI interrupt to be used for catastrophic events such that require immediate action

is

interrrupt

driven by the 8259A PIC which, on demand,

provides an 8-bit identifier

C~U

multiplies the 8-bit identifier

of

the interrupting source. The

as

the CPU. The INTR

by

four to derive a

intended

power outages

pomter to the service routine for the interrupting device.

18

Interrupt requests may originate from the necessity

of

external hardware. Two jumper-

sources without

selectable interrupt requests can be automatically gener-

by

ated when a byte

~086

tIOn output buffer requests can be automatically generated when a character CPU character

data buffer request can be generated by two

the Programmable Peripheral Interface (PPI)

of

information

CPU (i.e., input buffer is full) or a byte

is

ready to be transferred to the

of

informa-

has been transferred to a peripheral device (i.e.,

is

empty). Two jumper-selectable interrupt

by

the

US

ART

is

ready to be transferred

(i.e., receive channel buffer

is

ready to be transmitted (i.e., transmit channel

is

empty.) A jumper-selectable interrupt

is

of

to

the 8086

full)

or

when a

the programmable counters and eight additional interrupt request lines are ava.ilable to the user for direct interfaces to user-designated penpheral devices via the Multibus.

One interrupt request

line may be jumper routed directly from a peripheral via

th~

~arallel

VO

driverlterminator section and one power

fall mterrupt may be input via auxiliary connector P2.

Th~

iSBC 86/12 includes the resources for supporting a

~anety

tIOns benefits

of

OEM system requirements. For those applica-

requiring additional processing capacity and the

of

multiprocessing (Le., several

CPU's

and/or controllers logically sharing systems tasks with communication over the Multibus), the

iSBC 86/12 provides

full bus arbitration control logic . This control logic allows up to three bus masters (e.g., combination DMA controller, diskette controller, etc.) Multibus

in

serial (daisy-chain) fashion

of

iSBC 86/12

to

or

up to

share the

16

bus

masters to share the Multibus using an external parallel priority resolving network.

General

lers

to

share resources on the same bus,. and transfers via

~he

bus proceed asynchronously. Thus, the transfer speed

IS

dependent on transmitting and receiving devices only.

Information

This design prevents slower master modules from being handicapped in their attempts

gain control

of

the bus,

to but does not restrict the speed at which faster modules can transfer data via the same bus. The most obvious applica-

of

tions for the master-slave capabilities

the bus are multiprocessor configurations, high-speed direct memory access (DMA) operations, and high-speed peripheral

by

no

control, but are

means limited to these three.

1-3. SYSTEM SOFTWARE

DEVELOPMENT

The development cycle may be significantly reduced using an Intel Intellec Mic-

rocomputer Development and system monitor greatly simplify the design, develop-

~ent,

and

deb~g

dIskette operatmg system provides a relocating loader and linkage editor, and a library manager.

Intel's high level programming language, available

ment

program

the need PUM

as

a resident Intellec Microcomputer Develop-

System option.

in

a natural, algorithmic language and eliminates

to

manage register usage

86 programs can be written in a much shorter time

than assembly language programs for a given application.

of

iSBC 86/12 based products

System. The resident text editor

of

iSBC system software.

PUM

86 provides the capability to

or

An

optional

PUM86,

is

also

allocate memory.

1-4. EQUIPMENT SUPPLIED

The following are supplied with the iSBC 86/12 Single

Board Computer:

a.

Schematic diagram, dwg no. 2002259

b. Assembly drawing, dwg no. 1001801

1-5. EQUIPMENT REQUIRED

Because the iSBC 86/12 is designed to satisfy a variety applications, the user must purchase and install only those components required to satisfy his particular needs. A list of

components required to configure all the intended ap-

plications

of

the iSBC86/12

is

provided in table 2-1.

of

T~e

Multibus arbitration logic operates synchronously

WIth

the bus clock, which

86/12

or

can be optionally generated

master. Data, however,

is

derived either from the iSBC

is

transferred via a handshake between the controlling master and the addressed slave module. This arrangement allows different speed control-

by

some other bus

1-6. SPECIFICATIONS

Specifications are listed

of

the iSBC 86/12 Single Board Computer

in

table 1-1.

1-3

General Information

WORD SIZE

iSBC 86/12

Table 1-1. Specifications

Instruction: Data

CYCLE TIME:

MEMORY CAPACITY On-Board ROM/EPROM:

On-Board Dynamic RAM: Off-Board Expansion:

MEMORY

On-Board ROM/EPROM:

On-Board RAM:

SERIAL COMMUNICATIONS

Synchronous:

ADDRESSING

(CPU Access)

(Multi bus Access)

8,

16,

24,

or

8/16 bits.

800 nanosecond for fastest executable instruction (assumes instruction is

1.2 microseconds for fastest executable instruction (assumes instruction is not

queue).

Up to 16K bytes; user installed in 1 32K bytes. Integrity maintained during power failure with user-furnished batteries. Up to 1 megabyte of user-specified combination of RAM,

FFOOO-FFFFFH

FEOOO-FFFFFH

FCOOO-FFfFFH (using 2332 ROM's).

00000-07FFFH .

Jumpers and switches allow board to act as slave RAM device for access by another bus master. Addresses may 1-megabyte system address space. Access is selectable for

5-, 6-, 7-,

Intemal; 1

Automatic sync insertion.

32 bits.

(using 2758 EPROM's), (using 2316E ROM's

or

8-bit characters.

or

2 sync characters.

in

the queue).

K,

2K,

or

4K byte increments.

ROM, and EPROM.

or

2716 EPROM's), and

be

set within any 8K boundary of any 128K segment of the

8K,

16K, 24K,

or32K

in

bytes.

the

Asynchronous:

Sample Baud Rate:

5-, 6-, 7-, Break character generation. 1, 1 Y2, False start bit detection.

Notes:

or

8-bit characters.

or

2 stop bits.

Frequency'

(kHz, Software Selectable)

153.6

76.8

38.4

19.2

9.6

4.8

2.4

1.76

1.

Frequency selected by I/O writes of appropriate 16-bit freq uency factor to Baud Rate Register.

2.

Baud rates shown here are only a sample subset of possible softwareprogrammable rates available. Any frequency from 18.75 Hz to 613.5 kHz may

be generated utilizing on-board crystal oscillator and 16-bit Program-

mable Interval T'imer (used here as frequency divider).

Baud Rate (Hz)2

Synchronous Asynchronous

+16

-

38400 2400 19200

9600 4800 300 2400 1760 110

9600 2400

4800 1200

1200

600 150 150

+64

600 300

-

75

1-4

JSBC

86/12

General Information

Table 1-1. Specifications (Continued)

INTERVAl GENERATOR

Input Frequency (selectable):

Output Frequencies:

SYSTEM CLOCK (8086 CPU):

I/O ADDRESSING:

INTERFACE COMPATIBILITY

Serial I/O:

TIMER AND BAUD RATE

2.46 MHz

1.23 MHz

153.6 kHz

5.0 MHz ±0.1%.

All communication to Parallel I/O and Serial I/O Ports, Timer, and InterruptControlier is via read and write commands from on-board

EIA Standard RS232C signals provided and supported:

±0.1% (0.41 ±0.1% (0.82

±0.1% (6.5

Function

Real-Time Interrupt Interval

Rate Generator 2.342 (Frequency)

Clear to Send Receive Data Data Set Ready Secondary Receive Data* Data Terminal Ready Secondary Request to Send Transmit Clock* Receive Clock Transmit Data

jLsec jLsec

jLsec

Min.

1.63

period nominal), period nominal), and

period nominal).

Single Timer

Max.

jLsec

Hz

427.1 msec

613.5 kHz

*Can support only one.

(Two Timers Cascaded)

Min. Max.

3.26

0.000036 Hz

8086 CPU. Refer to table 3-2.

CTS*

Dual Timers

jLsec

466.5

minutes

306.8 kHz

Parallel I/O:

INTERRUPTS:

COMPATIBLE CONNECTORS/CABLES:

ENVIRONMENTAL REQUIREMENTS

Operating Temperature:

Relative Humidity:

PHYSICAl

Width: Height:

Thickness:

Weight:

CHARACTERISTICS

24 programmable lines (8 lines per port); one port indudes bidirectional bus driver. IC sockets included for user installation of line drivers and/or I/O terminators as required for interface ports. Refer to table 2-1.

8086 CPU includes non-maskable interrupt (NMI) and maskable interrupt (INTR).

NMI

interrupt is provided for catastrophic event such as power failure; NMI vector address is 8-bit identifier of interrupting device to

vector address. Jumpers select interrupts from 18 sources without necessity of

external hardware. level-sensitive inputs.

Refer to table 2-2 for compatible connector details. Refer to paragraphs 2-21 and 2-22 for recommended types and lengths of

To

30.48 cm (12.00 inches).

17.15 em (6.75 inches).

1.78 cm 539 gm (19 ounces).

00008. INTR interrupt is driven by on-board 8259A PIC, which provides CPU. CPU multiplies identifier by four to derive

PIC may be programmed to accommodate edge-sensitive

I/O cables.

90% without condensation.

(0.7 inch).

or

1-5

General

Information

POWER REQUIREMENTS:

CONFIGURATION

VCC

Table 1-1. Specifications (Continued)

=

+5V±5%

VOO = +12V±5%

VBB =

-5V±5%

V

AA

=

-12V±5%

iSBC

86/12

Without EPROM'

RAM

Only3 With iSBC With 4K EPROMs

(Using 2758) With 8K

(Using 2316E) With 8K EPROMs

(Using 2716) With 16K

(Using 2332)

Notes:

53()4

ROMS

1.

Does not include power for optional ROM/EPROM,

2.

Does not include power required for optional ROM/EPROM,

3.

RAM chips powered via auxiliary power bus.

4. Does not include power for via serial port connector.

5.

Includes power required for four ROM/EPROM chips, and

low.

inputs

5.2A rnA 40 rnA

390

5.2A

5.5A

6.1A 450 rnA

5.5A

5.4A 450 rnA

optional ROM/EPROM,

350 rnA

450 rnA

110

drivers, and

110

drivers, and

-

1.0 rnA -

-

110

terminators.

1/0

drivers, and

110

terminators installed for16

110

terminators.

110

terminators. Power for iSBC 530

40 rnA

140 rnA

is

110

lines; all terminator

supplied

1-6

CHAPTER 2

PREPARATION FOR USE

2-1. INTRODUCTION

This chapter provides instructions for the iSBC 86/12 Single Board Computer in the user-defined environment.

of

It is advisable that the contents

fully understood before beginning the configuration and

installation procedures provided in this chapter.

Chapters 1 and 3 be

2-2. UNPACKING AND INSPECTION

Inspect the shipping carton immediately upon receipt for

of

evidence carton is severely damaged the carrier's agent be present when the carton

If

the carrier's agent is not present when the carton opened and the contents keep the carton and packing material for the agent's inspection.

For

repairs to a product damaged in shipment, contact the Intel Technical to obtain a Return Authorization Number and further instructions. A purchase order will be required to complete the repair. A copy submitted to the carrier with your claim.

mishandling during transit. If the shipping

or

waterstained, request that

is

opened.

is

of

the carton are damaged,

Support Center (see paragraph 5-3)

of

the purchase order should be

2-5. POWER REQUIREMENT

The iSBC 86/12 requires

power. The dual port RAM, can be supplied by the system supply, an auxiliary battery, regulator. (The

-12V

-5V

supply.)

+5V,

-5V,

+ 12V, and

power, which is required only for the

or

by the on-board

regulator operates from the system

-12V

-5V

2-6. COOLING REQUIREMENT

The iSBC 86/12 dissipates 451 gram-calories/minute

of

(1.83 Btu/minute) and adequate circulation

provided to prevent a temperature rise above 55°C

(131°F). The

tem include fans to provide adequate intake and exhaust ventilating air.

System 80 enclosures and the Intellec Sys-

air must be

of

2-7. PHYSICAL DIMENSIONS

Physical dimensions a. Width: b.

Height:

c. Thickness:

of

the iSBC 86/12 are as follows:

30.48 cm (12.00 inches).

17.15 cm (6.75 inches). cm

1.78

(0.70 inch).

It is suggested that salvageable shipping cartons and packing material be saved for future use duct must be reshipped.

in

the event the pro-

2-3. INSTALLATION CONSIDERATIONS

The iSBC 86/12 is designed for use in one ing configurations:

a. Standalone b. Bus master in a single bus master system. c. Bus master in a multiple bus master system.

Important criteria for installing and interfacing the iSBC 86/12 in these configurations are presented in

following paragraphs.

(single~board)

system.

2-4. USER-FURNISHED COMPONENTS

The user-furnished components required to configure the

iSBC86/12

2-1. Various types and vendors

in table 2-1 are listed in table 2-2.

fied

for a particular application are listed in table

of

the connectors speci-

ofthe

follow-

2-8. COMPONENT INSTALLATION

Instructions for installing optional ROM/EPROM and parallel

given in following paragraphs. When installing these chip

components, be sure to orient pin 1

to the white dot located near pin 1 IC socket. The grid zone location location diagram) is specified for each component chip to be installed.

2-9. ROM/EPROM CHIPS

IC sockets A28, A29, A46, and A47 (figure 5-1 zone C3)

accommodate 24-pin CPU jumps to location ROM/EPROM address space resides in the topmost portion from the top down. IC sockets A29 and A47 accommodate the top must always be loaded; IC sockets A28 and A46 accommodate the

stalled in A29 and A47.

I/O port line drivers and/or line terminators are

of

the chip adjacent

of

the associated

on figure 5-1 (pltrts

ROM/EPROM chips. Because the

FFFFO

on a power up

of

the I-megabyte address space and must be loaded

of

the ROM/EPROM address space and

ROM/EPROM space directly below that in-

or

reset, the

2-1

Preparation for

Use

Table 2-1. User-Furnished and Installed Components

iSBC

86112

Item

No.

1

2

3

4

5

6

7

Item

iSBC

604

iSBC

614

Connector

(mates

with

Connector

(mates

with

Connector

(mates

with

Connector

(mates

with

ROM/EPROM

P1)

P2)

J1)

J2)

Chips

Description

Modular

cludes four

(See

Modular cludes four slots without (See

See

table

See Auxiliary table

See table

Two

types:

Backplane

slots

figure

5-3.)

Backplane

figure

5-4.)

Multibus Connector

2-2.

Parallel I/O Connector details

2-2.

Serial

2-2.

or

four

ROM

or

and

with

bus

and

bus

Connector details

I/O connector details in

each

of

EPROM

Cardcage.

terminators.

-

Cardcage.

terminators.

details in

the

following

In-

in

Provides signal three system.

Provides

Power

face.

stalled

Auxiliary

ciated

Interfaces PPI.

Interfaces

USART.

Ultraviolet development. cated

power input

interface

additional boards

four-slot extension of

inputs

Not

required

in

an

backup

memory

parallel

serial

Erasable

program.

between

and

iSBC

protect

I/O

Masked

Use

pins

in

Multibus

if

iSBC

6041614.

battery

functions.

I/O

port

PROM

and

iSBC

86/12

a multiple

iSBC

signal

86/12

and

with

Intel8255A

with

Intel

(EPROM)

ROM

for

Multibus

and

board

604.

inter-

is

in-

asso-

8251A

for

dedi-

-

2316E 2332

8

9

Une

Terminators

Drivers

Type

SN7403I,OC SN7400 SN7408 SN7409

Types ing, collector.

Intel Pull-Up:

I

NI

NI,

selected

NI = noninverting,

iSBC

901

902

OC

901

.&

0

2758 2716

-

as

typical;

Divider

A

330

Current

16mA 16mA 16mA

16mA

I =

and

invert-

OC = open

or

iSBC

+5V

220

r:v

902

0

Interface Intel IC's

Interface Intel8255A 902'sfor

parallel

8255A

for

each

parallel"VO

each

I/O

ports

PPI.

8-bit

PPI.

Requires

8-bit

CA

Requres two line driver

parallel

output

ports

CA

two 901's ortwo

parallel

and

input

CC

port.

CC

port.

with

2-2

iSBC

Function

86/12

No.

Pairs/

Pins

Of

Table 2-2. User-Furnished Connector Details

Centers

(inches)

Connector

Type

Vendor

Part

Preparation for

No.

Intel

Part

Use

No.

Parallel

I/O

Connector

Parallel

I/O

Connector

Parallel

I/O

Connector

Serial

110

Connector

Serial

110

Connector

Serial

110

Connector

25/50

. 24/50

13/26

0.1

3M 3M

Flat Crimp AMP

ANSLEY

SAE S06750 SERIES

AMP 2-583485-6

Soldered

Wirewrap'

Flat Crimp

Soldered

Wi

rew

rap'

VIKING

TI H312125

TI

VIKING

COO

ITICANNON

3M

AMP

ANSLEY

SAE S06726 SERIES

TI H312113

AMP

TI

3415-0000 WITH EARS 3415-0001 W/O EARS iSBC 956 88083-1 609-5015 Set

3VH25/1JV5

H311125

3VH25/1JN05

VPB01 B25000A 1

EC4A050A1A

3462-0001 88106-1 609-2615

1-583485-5

H311113

Cable

N/A

iSBC

Cable

Set

N/A

955

Multibus

Connector

Multibus

Connector

Auxiliary

Connector

Auxiliary

Connector

NOTES:

1.

2.

3.

COC3

43/86

30/60

Connector heights are not guaranteed to conform to OEM packaging equipment. Wirewrap pin lengths are not guaranteed to conform to

COC VPB01 .... VPB02 .... VPB04 .... etc. are identical connectors with different electroplating thicknesses

metal surfaces.

0.156

0.1

Soldered'

Wirewrap1.2

Soldered'

Wirewrap1.2

MICRO PLASTICS

ARCO AE443WP1 LESS EARS

VIKING 2VH43/1AV5

COO COC3

VIKING 2VH43/1AV5

TI

VIKING

COO

TI

OEM packaging equipment.

VPB01 E43000A 1 MP-0156-43-BW-4

VFB01 E43000A 1 or VPB01E43AooA1 MOS 985

H312130 3VH30/1JN5

VPB01

B30AOOA2

H311130

:,

N/A

or

2-3

Preparation for

Use

iSBC 86/12

The low-order byte (bits 0-7)

installed (bits 8-15) must

in

sockets A29 and A28; the high-order byte

be

installed

Assuming that 2K bytes

of

ROM/EPROM must

in

sockets A47 and A46.

of

EPROM are to

be

installed

be

using two Intel 2758 chips, the chip containing the

low-order byte must

the chip containing the high-order byte must

in

IC

socket A47. ROM/EPROM address space ditional Intel 2758 chips may sockets

A28

FFOOO-FF7FF.

be

installed

In

this configuration, the usable

in

IC

socket A29 and

be

is

FF800-FFFFF. Two

be

installed later

installed

ad-

in

IC

and A46 and occupy the address space

(Even addresses read the low-order bytes

and odd addresses read the high-order bytes.)

The default (factory connected) jumpers and switch

are configured for

2K

by

8-bit ROM/EPROM chips

S 1

(e.g., two or four Intel 2716's). If different type chips are installed, reconfigure the jumpers and switch

S 1

as

listed in table 2-4.

2-10. LINE DRIVERS

AND

I/O

TERMINATORS

Table 2-3 lists the I/O ports and the location

14-pin

IC

sockets for instaHing either line drivers or I/O tenninators. (Refer Port

C8

is

factory equipped with Intel 8226 Bidirectional

Bus Drivers and requires

to

table 2-1 items 8 and 9.)

no

additional components.

of

associated

2-11. JUMPER/SWITCH CONFIGURATION

The iSBC

selectable options to allow the user for his particular application. Table 2-4 summarizes these options and lists the grid reference locations

jumpers and switches

location diagram) and figure 5-2 (schematic diagram). Because

:86/12

includes a variety

as

of

jumper- and switch-

to

configure the board

shown in figure 5-1 (parts

the schematic dIagram consists

of

11

of

the

sheets, gria

references

to

figure 5-2

may

be

either four or five alphanumeric characters. For exampfe, grid reference 3ZB7 signifies sheet 3 Zone B7.

Study table 2-4 carefully while making reference ures

5-1

and 5-2.

If

the default (factory configured)

to

fig-

jumpers and switch settings are appropriate for a partic-

ular function, function. If, however, a different configuration

no

further action

is

required for that

is

required, reconfigure the switch settings and/or remove the default jumper(s) and install an optional jumper(s) specified. For most options, the infonnation 2-4

is

sufficient for proper configuration. Additional information, where necessary for clarity, in

subsequent paragraphs.

in

is

described

table

2-12. RAM ADDRESSES (MULTIBUS

ACCESS)

The dual port RAM can

via the Multibus. selected pair

dual port RAM

of

jumper posts (113 through 128) places the

in I-megabyte address space. package (DIP) composed

single-throw switches. (Two

are used for

ROM/EPROM configuration.) Two switches (6-11 and 5-12) are configured or 32K bytes

of switches (1-16, 2-15, 3-14, and 4-13) are configured to

displace the addresses from the top

128K byte segment

Figure

2-1

provides an example RAM being made accessible from the Multibus and how the addresses are established. Note in figure 2-1 that the Multibus accesses the dual port RAM from the top down. Thus, as shown for the bottom RAM

24Kbytes

is

reserved strictly for on-board CPU access.

be

shared with other bus masters

One jumper wire connected between a

one

of

eight 128K byte segments

Switch S 1

of

eight individual single-pole,

of

these individual switches

to

allow 8K, 16K, 24K,

dual port RAM to

of

memory.

of

8K

byte access via the Multibus,

of

the iSBC 86/12 on-board

is

be

accessed. Four of

8K

bytes

of

the

a dual-inline

the selected

of

dual port

as

Table 2-3. Line Driver and

1/0

Port

C8 0-7

8255A

PPI

Interface

*Figure 5-2 is the schematic diagram. Grid reference 9ZA3, for example, denotes sheet 9 lone A3.

2-4

CA

CC

Bits

0-3

4-7

0-3

4-7

I/O

Terminator Locations

DriverlTermlnator

None Required -

A12 A13

A11 A10

Fig.

5-1

Grid Ref.

lO4 lO4

lO5 lO5

Fig. 5-2* Grid Ref.

-

9ZA3 9ZA3

9lC3

9lB3

i8BC

86/12

Preparation for

Use

Function

ROM/EPROM

Configuration

Table 2-4.

Fig. 5-1 Fig. 5-2

Grid

Ref.

ZC3, ZB6,

ZD7

Jumper

Grid

Ref.

6ZB3,6ZC7, 2ZB6

and Switch Selectable Options

Description

Jumpers 94 through 99 and switch

four types of

ROM/EPROM

2316E/2716

Reserved

= closed switch position.

C

ROM/EPROM chips:

Type

2758 2332

S1

Jumpers

94-95, 97 -98

*94-96, *97-98

94-96, 97-99

-

may be configured to accommodate

Switch

S1

--

8-9

C C

*C

0 C

0 0

7-10

*0

o = open switch position.

Default jumpers and switch settings accommodate Intel 2316E/2716

chips. Disconnect existing configuration jumpers (if necessary) and

reset switch

Dual Port RAM

(Multibus Access) system bus master via the Multibus. For local CPU access, the dual port

ZB7, ZB6

3ZB6,3ZB7

The dual port RAM permits access by the local (on-board) CPU and any

RAM address space is fixed beginning at the

Multibus, one jumper and one switch can configure the dual port RAM on any 8K boundary within the 1-megabyte address space. Refer to paragraph 2-12 for configuration

S1

if reconfiguration is required.

details.

location 00000. For access via

Bus Clock

Constant Clock

Bus Priority Out

Bus Arbitration

Auxiliary Backup

Batteries

On-Board

Failsafe Timer

-5V

Regulator

ZB7

ZBB,

Zf)7

ZBB, 1ZC7,1ZCB

ZD3, ZB5

ZB6

ZD7

10ZA2

3ZD2

3ZD2,3ZC3

1ZCB

2ZB6

Default

jumper *105-106 routes Bus Clock signal BCLKI to the Multibus.

(Refer to table 2-9.) Remove this jumper only if another bus master supplies this signal.

jumper *103-104 routes Constant Clock signal CCLKI to the

Default

Multibus. (Refer to table 2-9.) Remove this jumper only if another bus master

supplies this signal.

Default jumper *151-152 routes Bus Priority

Multibus. (Refer to table 2-9.) Remove this jumper only in those systems to paragraph 2-19.)

The Common . Bus Request signal (CBRO)

ANYROST input to the Bus Arbiter chip are not presently used.

If auxiliary backup batteries are used to sustain the dual port RAM

du~ng

and *W6(A-B).

The dual port RAM requires a

the system

-5V supply.) If a system teries are not used, disconnect jumper W5(B-C). fault jumper *W5(A-B); do not connect W5(B-C).

If the on-board CPU addresses either a system

or the CPU will hang up in a wait state. A failsafe timer is triggered during T1

the wait state.

employing a parallel priority bus resolution scheme. (Refer

ac power outages, remove default jumpers *W4(A-B), *W5(A-B),

regulator. (The

I/O device and that device does not return an acknowledge Signal,

of every machine cycle and, if not retriggered within 6.2 milliseconds,

resultant time-out pulse can be used to allow the CPU to exit the

..

-5V

supply, an auxiliary backup battery,

-5V

If auxiliary backup batteries are used, disconnect de-

If this feature is desired, connect jumper 5-6.

AUX input, which can be supplied by

regulator operates from the system

supply is available and auxiliary backup bat-

default jumper *W5(A-B) and connect

Out

signal BPRO/ to the

trom

the Multibus and the

or

by the,on-board

or

an on-board memory

conter1'ts

-12V

*Default jumper connected

at

the factory.

2-5

Preparation for

Function

Timer

Input

Frequency

Use

Table 2-4. Jumper and Switch Selectable Options (Continued)

Fig.

5-1

Grid

Ref.

ZD3 7ZB5

ZD3

Fig. 5-2

Grid

7ZA5

Ref.

Description

Input

frequencies to the 8253 Programmable Interval Timer are jumper

selectable as follows:

Counter 0

57-58: 153.6 kHz.

*57-56: 1.23 MHz.

57 -53: 2.46 MHz. 57-62:

Counter 1

*59-60: 153.6 kHz.

59-56: 1.23 MHz.

*59-53: 2.46 MHz.

59-62: 59-61: Counter

Jumper 59-61 which.the output This permits programming the clock rates to Counter 1 and thus provide

longer

(TMRO

INTR)

Extemal Clock to/from Port CC terminator/driver.

(TMR1

INTR)

External Clock to/from Port CC terminator/driver.

TMR1

0 output.

effectively connects Counter 0 and Counter 1 in series

of

Counter 0 serves as the input clock to Counter

INTR intervals.

iSBC 86/12

in

1.

ZD3

Interrupts

Priority

Serial I/O Port

Configuration

Parallel I/O Port

Configuration

*Default jumper connected at the factory.

-

- Sheet 7

- Sheet 9

The configuration for 16K, 24K,

7ZB5

Sheet 8

or

32K access

A jumper matrix provides a wide

Jumpers posts 38 through 52 are used to configure the 8251A

Jumper posts 7 through 37 are used to configure the 8255A

is

done in a similar manner. Always observe the IMPORTANT note in figure 2-1 in that the address space intended

of

for Multibus access cross a 128K

If

it

is

for local

boundary.

desired

to

CPU access, connect jumper 112-114.

the dual port RAM must not

reserve all the dual port RAM strictly

Counter 2

55-58: 153.6 kHz.

*55-54: 1.23 MHz.

55-53: 2.46 MHz. 55-62:

to the 8086 configuration.

described

scribed

(8251

Baud Rate Clock)

External Clock to/from Port CC terminator/driver.

CPU and the Multibus. Refer to paragraph 2-13 for

in

paragraph 2-14.

in

paragraph 2-15.

selection of interrupts to be interfaced

which himdles up to eight vectored priority interrupts, provides the capability to expand the number interrupts by cascading each interrupt line with another

as

8259A PIC. Figure 2-2 shows

an example the

PIC (master) with two slave PIC's interfaced by the Multi-

bus. This .arrangement leaves the master PIC with six inputs (IR2 through IR 7) that can be used to handle the various on-board interrupt functions.

USART as

PPI as de-

of

priority

on~board

2-13. PRIORITY INTERRUPTS

Table 2-5 lists the source (from)iand destination (to)

priority interrupt jumper matrix shown

8. The INTR

output'of grammable Interrupt Controller (PIC) is applied directly to the INTR input

2-6

the on-board Intel 8259A Pro-

of

the 8086 CPU. The on-board PIC,

in

figure 5 -2 sheet

of

the

The master/slave PIC arrangement illustrated in figure

2-2

is

implemented by programming the master PIC

handle

IRO

and IRI example, PIC

if

the Multibus INT3/line

1,

the master PIC will let slave PIC 1 send the restart

address to the 8086

Each interrupt input can

be

individually programmed

as

bus vectored interrupt inputs. For

is

driven low by slave

CPU.

(IRO

through IR7) to the master PIC

to

be a non-bus vectored

to

iSBC 86/12

Preparation

for

Use

SYSTEM

128K BYTE

SEGMENT

NO ACCESS

EOOOO-FFFFF

®

JUMPER

112·114

113-114

EXPLANATION

® SELECTS X PARAMETER (128K BYTE SEGMENT)

® SELECTS Z PARAMETER (MEMORY AVAILABLE ©

SEL.ECTS

Y PARAMETER (LOCATION WITHIN 128K SEGMENT)

ADDRESS (UPPER) ~ X+Y

ADDRESS(LOWER)~

IN THE EXAMPLE SHOWN IN THE SHADED PATH, X ~ COOOO,

Z ~ 8K (01I'FF). THUS,

IMPORTA~IT

THE

SElI,CTED

BOUNDARY. THAT IS,

ABSOLUTIE VALUE

X+Y-Z

COOOO ~ X

+OBFFF ~ Y

CBFFF

~

-01FFF ~ Z (8K)

"""CAoOo

MEMORY SPACE CANNOT EXTEND ACROSS A 128K BYTE

OF

ADDRESS (UPPER)

~

ADDRESS (LOWER)

X+Y-Z

MUST BE EQUAL TO OR GREATER THAN THE

X.

TO

BUS)

Y ~ OBFFF, AND

645·2

FFFFF

00000

....

"'1-------1

C

0

0 C 0

0 C

0

0 0

0

0 0

SYSTEM

MEMORY

01FFF

03FFF

0

C

C·

0 0

C

0

C

0

OFFFF

C

11FFF

0

13FFF

C

15FFF

0

17FFF

C

19FFF

0

1BFFF

C

1DFFF

0

1FFFF

-..-

Y PARAMETER

Figure 2-1. Dual Port RAM Address Configuration (Multibus Access)

86/12

8K

07FFF

06000

04000

02000

00000

2-7

Preparation for

Use

Table 2-5. Priority Interrupt Jumper Matrix

iSBC

86/12

Interrupt Request From

Source Signal Post

Multibus

Extemal Power

Failsafe Timer

8255A

8251A

8253

NOTES:

(2)

Via

J1-50

Fail

Via

Port Port B (Port CAl Any

Trans Buffer Empty

Ree

Timer 0 Out Timer 1 Out

(1) (2) (3) (4) (5)

(6)

(7) Default jumper

(8)

(9)

Logie

P2-19

PPI

A (Port

C8)

Unused

Buffer

PIT

'Requires positive-true signal at associated jumper

Bit

USART

Empty

Signal

is positive-true

INTO/

is Signal Requires

IRO sensitive.

INTR Used

highest priority;

is

ground-true at associated jumper

ground-true

is highest priority;

is connected directly to output of

to

generate

87

INTO/ INT1/ INT2I INT3/ INT4/ INT5/ INT6I INT7/

EXT PFI/

TIME

PAINTR PBINTR BUS

51TX 51RX

TMRO TMR11NTR

at

associated jumper

INT7/

Signal

IR7

-89

an

is lowest priority.

disables

interrupt

INTO/

OUT

INTR

OUT

INTR

is

lowest

at associated jumper

(grounds)

on

8259A

Multibus.

(1) (1

)

(1

)

(1

)

(1

)

(1

)

(1

)

(1

)

(1

)

(1

)

(1)

(1

)

(1)

(3)(9)

(1)

(1

)

(1

)

(1)

post.

priority.

post.

input.

The

PIC.

post.

NMI

73 72

71

70 69

68

66 65

67 86

88

84 85

142

90 82

83 91

input

is highest priority,

Device

Multibus

8259A

8086

.'

Interrupt Request

(2)

PIC

(6)

CPU

non-maskable,

To

Signal Post

and

is

(4)

(4) (4) (4)

(4)

(4) (5)

(5) (5) (5)

(5)

(5) (5) (5)

(7)

(8)

both

level

and

INTO/ INT1/ INT2I INT3I INT4/ INT5/ INT6I INT7/

IRO IR1 IR2

IR3

IR4 IR5 IR6 IR7

NMI

INTR

141 140 139 138 137 136 135 134

81 80 79 78

n

76 75 74

89

-

edge

r-

-----

-

--

---

I 8086 MASTER I

I

cpu

8~~~A

I

I I I

I

INTR

I

I+---IINTR

I

I I

I

IRO

IR1

IR214---o

IR3

IR414---o

IR514---o

IR614---o

IR7

I

I I

L

_________________________

645-3

2-8

Figure 2-2. Simplified Master/Slave PIC Interconnect Example

-----

-----iSBCa6i121

81

70 I

1+--<>---0----<,

80

k---c~o_----_<:C

.....

--o

.....

--o

79

78

77

76

75

74

86

0-

0--

0-

INPUTS FROM ON-BOARD INTERRUPT SOURCES

(NBV)

r---

I

MULTIBUS

INT3I

INT6I

INTO!

INT11

1NT2I

INT4/

INTS/

INT71

J

I PIC 1

I

I :

I

41

I

42

I

39

I

37

I

38

I

36

I BUS VECTORED (BV) I INTERRUPT SOUFICES

L

__________

-SLAve-

IRO

INTR

1o-...,.;,IR:.:;7,,---- 7

SLAVE

-

--1

,,1

•

J

iSBC

86/12

(NB

V)

interrupt (the master PIC generates the restart

address) or bus vectored (B

V)

interrupt (the slave PIC generates the restart address). Thus, the master PIC can handle eight on-board (an interrupt line that to

64 interrupts with the implemention

or

single Multibus interrupt lines

is

not driven by a slave PIC) or up

of

slave PIC's.

2-14. SERIAL

Preparation

110

PORT CONFIGURATION

for

Use

Table 2-6 lists the signals, signal functions, and the jumpers required (if necessary) to input particular signal to or from the serial

VO

or

output a

port (Intel 8251 A

USART).

The iSBC 86/12 can also generate an interrupt to another

interrupt handler via the Multibus. This

by using one

of

the bits

of

the 8255A PPI to drive the

BUS INTR OUT signal. (The BUS INTR OUT signal

ground-true at jumper post 142 as footnoted

is

accomplished

in

table 2-5.)

is

Default jumper 87-89 grounds the NMI (nonmaskable intemlpt) input to the

CPU to prevent the possibility

of false interrupts being generated by noise spikes. Since the NMI is not maskable, cannot be disablyd and has the highest priority,

it

should only be used to

by

the program,

detect a power failure. For this purpose, disconnect default jumper 87-89 and connect 86-89. The Power Fail Interrupt (PFI/) is an externally generated signal that

is input via auxiliary connector P2. (Refer to paragraph 2-20.)

21

:23

:26

'10 12 '13 14 '19

22

25

Table 2-6. Serial I/O Connector

1

2 4 5

6 7

8

CHASSIS GND TRANSMITIER SEC REC SIG

RECEIVER DATA 8251A TXD out REC

RaTTO CLEAR TO SEND DATASET DATA TERMINAL ROY 8251A DSR in GND

-12V TRANS SIG ELE TIMING

+12V

+5V GND SEC CTS

Signal

DATA 8251A RXD in

2

SIG ELE TIMING

SEND

ROY 8251A DTR out

2

J2

Pin Assignments

Protective ground

Same as

8255A STXD out (Note 3)

8251A RXC in (Note 4) 8251A TXC in (Note 4) 8251A CTS in (Note 8251A RTS out (Note

Ground

-12Vout Same as 8251ATXC 8255A STXD out (Note

+12Vout +5Vout Ground Same as

8255A STXD out (Note 3)

2-l5.

PARALLEL

110

PORT CONFIGURATION

Table 2- 7 lists the jumper configuration for three parallel

VO

ports. Note that each

CC) can be configured

of

the three ports (C8,

in

a variety

of

ways to suit the

individual requirement.

2-16. MULTIBUS CONFIGURATION

For

systems applications, the iSBC 86/12 is designed for

installation

in

a standard Intel iSBC 604/614 Modular

Backplane and Cardcage. (Refer to table 2-1 items 1 and 2.) Alternatively, the iSBC 86/12 can to

3i

user-designed system backplane by means

Vs

Configuration Jumpers

Function

Jumper

In Jumper Out

63-64

-

8261

8251

A TXC in

or

5)

inor

3)

or

48-49, 45-46 49-50,

45-46

-

38-39

41-42

-

*W3A-8

48-49, 44-45

49-50, 44-45

*W2A-8 *W1A-8

-

48-49,45-47 49-50,45-47

*39-40

*42-43

.

CA,

be

interfaced

-

of

and

an

NOTES:

1.

All odd-numbered pins (1,3,5,

component side

2.

Only one

3. Optional jumper selected output Default jumpers

4.

Input Frequency (Counter 2)

5. For those

*Default jumpers connected at the factory.

of

the board with the extractors at the top.

of

these signal outputs (pin

*39-40

applications without CTS capability, connect jumper 51··52. This routes

and

...

*42-43

in

25) are on component side of the board. Pin 1 is the right-most pin when viewed from the

5,

21,

or

26) may

of

8255A PPI. Refer to figure 5-2 sheet 9.

connect 8253 CTR2 output to 8251A RXC and txc inputs, respectively. See

table 2-4.

be,

sele<.1ed.

8251

A RTS output to

8251 A CTS

Timer

input.

2-9

Preparation for

Use

Table 2-7. Parallel I/O Port Configuration Jumpers

iSBC

86/12

CB

Port

Mode

o Input

o Output

(latched)

1 Input

(strobed)

1 Output (latched)

Driver

Terminator

(D)/

B226:AB,A9

T:A10

0:

A11

B226:AB,A9

T:A10

0:

A11

(T)

Delete

*21-25

*21-25 24-25

*19-20 19-33

and

*32-33

*32-33 13-33

and

*13-14

Jumper

*21-25

*15-16 Connects J1-26 to

Add

24-25

Configuration

Effect

B226

= input enabled.

B226

= output enabled.

B226

= input enabled.

STBAI

input. following:

Connects IBF A output to

J1-1B.

22-32

*21-25

*17-1B

22-32

Connects interrupt matrix.

B226

Connects J1-30 to ACKAI input.

Connects OBF A output to

Connects

interrupt matrix.

INT A output to

= output enabled.

J1-1B.

INT A output to

Port

CA

CC

CA None; can be

CC

CA None; can be

CC

CA

CC

Restrictions

None; can be in mode 0 or

1,

input or output.

None; can be in Mode 0, input or output, unless Port CA is

1,

input or output.

None; can be in Mode input or output,

.Port CA is

1,

input or output.

Port CC bits perform the

• Bits 0,

• Bit 3 - Port

• Bit 4 - Port

• Bit 5 - Port

• Bits

None; can be 1, input

Port EA bits perform the following:

".

• Bit 3 - Port

1,

for Port CA if Port CA

in Mode

rupt (PA INTR) to interrupt jumper matrix

(STBI)

input.

put Buffer Full (IBF) output.

6,

7 - Port CC in-

or

put must

direction).

or

Bits 0,

1, 2 --

for Port CA if Port CA is

in Mode

rupt (PA

rupt jumper matrix.

in

Mode

1.

in

Mode 0

unless

in

Mode

1.

in

Mode 0

2 - Control

1. CB

Inter-

CB

Strobe

CB

output

(both,

in

be

output.

same

in

Mode 0

Control

1.

CB

INTR) to inter-

Inter-

or

0,

or

is

In-

or

*Default jumper connected at the factory.

2-10

• Bits 4, 5 - Port CC input or output (both must be

in

same direction).

• Bit 6 - Port knowledge input.

• Bit 7 - Port Buffer

output.

(ACKJ)

Full

CB

(OBF/)

Ac-

Output

II

iSBC

86/12

Table 2-7. Parallel I/O Configuration Jumpers (Continued)

Preparation for

Use

Port

CB

Mode

2

(bidirectional)

Driver

Terminator

B226:AB,A9 T:A10 D:

(D)I

A11

Jumper

(T)

Delete Add *21-25

*19-20

and

*26-27

*13-14 13-33 Connects

and

*32-33

17-25

*15-16 Connects J1-26 to STBtJ

19-27

*17-1B

22-32

Configuration

Effect

Allows ACKtJ input control B226 inlout direction.

input.

Connects

to J1-24.

Connects J1-30 to

ACKtJ input.

to J1-1B.

Connects

interrupt matrix.

IBFA

OBF

tJ

INT A output to

Port

to CA None; can be in Mode 0 or

CC Port

output • Bits

output

Restrictions

1,

input or output.

CC

following:

•

• Bit 3 - Port

• Bit 4 - Port

bits perform the

Bit 0 - Can only be

used for jumper option (see figure 5-2 zone 9ZC6).

1,2-

for input or output if Port CC is in Mode

rupt (PA INTR) to interrupt jumper matrix.

Can be used

(STB/) input.

• Bit 5 - Port Buffer Full (IBF) output.

• Bit 6 - Port

knowledge

input.

CB

CB (ACKI)

O.

Inter-

Strobe

Input

Ac-

CA-

CA

o Input

o Output

(latched)

1 Input (strobed)

T: A12, A13

D: A12, A13 None None

T:A10,A12,A13

A11

D:

None None

*2B-29 Connects IBFe output

"'13-14 14-30 Connects J1-32 to *30-31 STBei input.

26-34

to J1-22.

Connects

interrupt matrix.

INTe

• Bit 7 - Port Buffer

output.

None.

CB

None; Port

CC

Mode

0,

Port

CB

None

CC

None; Port CC can be Mode 0, input or output, if Port

CB

None.

CB

Port CC

CC

following:

• Bit 0 - Port CA Inter-

output rupt jumper matrix.

rupt (PB INTR) to inter-

• Bit 1 - Port CA Input Buffer

output.

• Bit 2 - Port CA Strobe

(STB/)

CB

Full (OBF/)

input or output, if

is also in Mode

bits perform the

input.

Output

CC

can be

Full (IBF)

in

O.

in

O.

'"

Default jumper connected at the factory.

2-11

Preparation for

Use

iSBC 86/12

Table 2-7. Parallel I/O Port Configuration Jumpers (Continued)

Port

CA

Mode

1 Output (latched)

Driver

Terminator

T:A10 D: A11, A12, A13

(D)

(T)

Delete

*13-14

and

*30-31 *26-27

Jumper

*28-29

Configuration

Add

Connects output J 1 -22.

14-30 Connects J1-32 to

ACKBI input.

26-34 Connects

interrupt matrix.

Effect

OBFe! output C8

INT B output

Port

CC

to

Restrictions

• Bit 3 - If Port C8 is Mode 0, bit 3 can be input

or

output. Other-

wise, bit 3 is reserved.

• Bits 4, 5 ~ Depends on Port

C8

mode.

• Bits 6, 7

None. Port CC bits perform the

• Bit 0 - Port CA inter-

• Bit 1 - Port

• Bit 2 - Port

-Input put (both must be same direction).

following:

rupt (PB rupt jumper matrix.

put Buffer output.

knowledge input.

INTR) to inter-

Full (OBF!)

or out-

CA

Out-

CA

(ACK/)

in

,

in

Ac-

CC o Input

(upper)

CC o Input

(lower)

CA (upper)

CA

(lower)

o Outpl:lt

(latched)

o Output

(latched)

T:A10

T:

A11

D:A10

D:

A11

None

None *26-27

None

*15-16 Connects bit 4 to J1-26. *19-20

*17-18

*13-14 Connects bit 7 to J1-32.

*28-29 *30-31

*32-33

Same' as for Port CC (upper) mode

o Input.

None

Same as for Port CC (lower) Mode CC Same as for Port CC

o Input.

bit 5 to

Connects Connects bit 6 to J1-30.

Connects bit

Connects bit 1 to J1-22. Connects bit 2 to Connects bit 3 to J1-18.

J1--28.

0 to J1-24.

J1-20. available.

• Bit 3 - If Port Mode 0, bit 3 can be input or output. Otherwise, bit 3 is

•

Bits4,5-lnputoroutput (both must be in same direction).

• Bit

6,

7 - Depends on

C8

Port

C8

()

av~ilable.

CA Port

must be in Mode

for all four bits to be

CA

must be in Mode

o for all four bits to be

available. Port

C8

must be in Mode

o for all four bits

CA Port

CA

must be in Mode

o for all four bits to be

available.

C8 Same

as

(upper) Mode 0 Input.

(lower) Mode 0 Input.

C8

~served.

mode.

to

for

Port CC

"'!:;'

is

in

be

*Default jumper connected at the factory.

2-12

Intel iSBC 86/12 Hardware Reference Manual

Specifications and Main Features

Frequently Asked Questions

User Manual