Intel DG33FBC Schematics Rev3.03

CR-1 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE1

8 2

PAGE #

COMPONENT/FUNCTION

[1. INDEX]
[2. BLOCK DIAGRAM]
[3. RESET MAP]
[4. CLOCK DISTRIBUTION]

D

[5. GPIO, IRQ, IDSEL MAP]
[6. CPU-SOCKET 1 OF 2]
[7. CPU SOCKET 2 OF 2]
[8. CPU TERMINATION & MISC P/U P/D]
[9. CPU PLL FILTERED SUPPLY]
[10. MCH SECTIONS PAGE 1 OF 6]
[11. MCH SECTIONS PAGE 2 OF 6]
[12. MCH SECTIONS PAGE 3 OF 6]
[13. MCH SECTIONS PAGE 4 OF 6]
[14. MCH SECTIONS PAGE 5 OF 6]
[15. MCH SECTIONS PAGE 6 OF 6]

C

[16. PLL & CRT FILTERS]
[17. MCH DECOUPLING AND COMP]
[18. MCH DCPL & VGA TERMINATION]
[19. MCH VREFS & TERMINATION]
[20. VGA CONNECTOR]
[21. PCI EXPRESS X16]
[22. PCI EXPRESS X16]
[23. PCI EXPRESS X16 COUPLING]
[24. 240P CONN DDR2, CH A]
[25. 240P CONN DDR2, CH B]
[26. DDR VTT TERMINATION]
[27. DDR VTT DECOUPLING]

B

[28. CK505 PAGE 1 OF 2]
[29. CK505 PAGE 2 OF 2]
[30. ICH9 1 0F 6 CONTROL]
[31. ICH9 2 OF 6 CONTROL]
[32. ICH9 3 OF 6 CONTROL]
[33. ICH9 4 OF 6 - CONTROL]
[34. ICH 5 OF 6 - CONTROL]
[35. ICH 6 OF 6 - GROUND BODY]
[36. GPIO TERMINATION & RST STRAPS]
[37. ICH PIN STRAPS]
[38. ICH DECOUPLING]
[39. ME & CONTROL BUFFERS/ICH CIRCUITS]
[40. SERIAL FLASH PRIMARY]
[41. SATA CONNECTORS]
[42. USB FP HDR 1]
[43. USB FP HDR 2]
[44. USB FP HDR 2]
[45. BACK PANEL USB]
[46. BACK PANEL USB WITH ESATA]
[47. PCI EXPRESS X1 #1]

[48. PCI CONN 1]
[49. PCI CONN 2]

8

7

PAGE #

6

COMPONENT/FUNCTION

[50. PCI TERMINATION]
[51. STD FRONT PANEL HDR]
[52. USB_FP_HEADER_POWER]
[53. 1394 CONTROLLER]
[54. 1394 BP REV1]
[55. 1394 PWR/DCPL]
[56. LAN NINEVEH]
[57. LAN NINEVEH]
[58. LAN NINEVEH]
[59. AUDIO CODEC]
[60. AUDIO DECOUPLING & JACK SENSE]
[61. AUDIO SPDIF]
[62. AUDIO JACK (BLUE GREEEN PINK]

45

PAGE #

COMPONENT/FUNCTION

[97. PRIMARY XDP-LITE]
[98. PATA]

[99. PATA]
[100. TEST SITE CAPS]
[101. PCI EXPRESS X1 #2]
[102. PCI EXPRESS X1 #3]
[103. PCI CONN 3]
[104. AUX FAN CONFIGURATION]
[105. HARDWARE MANAGEMENT: HECETA]
[106. ITE IT8211F 1 OF 2]
[107. PATA 2ND CONNECTOR]

3

REVISIONS

REV

REV

2.02

DESCRIPTION

DESCRIPTION

DESIGN

REVISIONS

DFT

DATE

DFT

DATE

2006

CHK APVD

CHK

1

DATE DATE

DATE

APVD

DATE

D

[63. AUDIO JACK (BLACK ORANGE]
[64. AUDIO FP HEADERS & HDA HEADER]
[65. AUDIO MIC BIAS]
[66. AUDIO VREG]
[67. SPDIF HEADER]
[68. TPM 1.2]
[69. PORT ANGELES 1 OF 2]
[70. PORT ANGELES 2 OF 2]
[71. FDD CONN]

BEARLAKE-B ATX

CLASSIC SKU

FROSTBURG

DRAGONTAIL PEAK

FAB C

C

[72. PS/2 CONNECTOR]
[72. LPT SIGNALS]
[73. LPT SIGNALS]
[74. SERIAL PORT A]
[75. STUDIES PURPOSE]
[76. SST SENSOR]
[77. FAN CONFIGURATION]
[78. MTG HOLES/LABELS]
[79. CORE VREG]
[80. CORE VREG]

TAPE-OUT: WWXX-2006
FAB A

REV

CONROE, BEARLAKE, DDR?, ICH9,
2-CHANNEL DDR2, PCIEXPRESS GFX, ATX
CUSTOMER REFERENCE BOARD

POWER SYMBOLS USED:
VCC3

VCC
+12V

-12V

3.03

B

[81. VREG_SM_VTT]
[82. VREG_1P25_CORE MCH]
[83. MCH DCPL]
[84. CORE VREG]
[85. VREG_FSB VTT & SFR]
[86. VREG 1.25 MCH CL]
[87. CORE VREG]
[88. CORE VREG]
[89. CORE VREG]
[90. NO PAGE TITLE FOUND!!!]
[91. WAKE CONTROL SWITCH PS2/USB (BP RIGHT)]
[92. VREG: DECOUPLING AND STITCHING]
[93. VCCP VREG]
[94. VCCP VREG]
[95. VCCP VREG]

[96. VREG: VCCP DECOUPLING / 2X2 CONN]

7

65

[PAGE_TITLE=INDEX]

BPAGE DRAWING

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4 2

NOTES:

1. THIS SCHEMATIC DOCUMENTS THE GENERIC PRODUCT WITH

2. RESISTORS ARE IN OHMS UNLESS OTHERWISE SPECIFIED.

3. VCC = +5V UNLESS OTHERWISE SPECIFIED.

4. * SUFFIX INDICATES ACTIVE LOW SIGNAL.

5. \I SUFFIX INDICATES SIGNAL EXITS HIERARCHICAL BLOCK.

6. THIS DOCUMENT ALSO EXISTS ON ELECTRONIC MEDIA.

BOM_RELEASE_DATE

SIGNATURE

DRN_BY

?

?

CHK_BY
ENGR_APVD

?

CUSTOM TEXT B-PAGE

3

ALL POSSIBLE CONFIGURATIONS.
PLEASE REFER TO SPECIFIC PRODUCT PBA EPL FOR
ITEMS SHOWN AS OPTIONAL IN THE SCHEMATIC.

?

PB_NUMBER

inte

?

TITLE

?

?

?

CONFIDENTIAL

INTEL

?

DOCUMENT_NUMBER

xxxxxx

S

3065 BOWERS AVEDATE
SANTA CLARA, CA

1

95051

PAGE REV

1/107

3.01

AA

POWER
SUPPLY CONN

XDP SSA

D

FRONT PANEL

USB PORT 1

C

USB PORT 2

FRONT PANEL

USB PORT 3

USB PORT 4

BACK PANEL

USB PORT 1

USB PORT 2

USB PORT 3

USB PORT 4

B

USB PORT 5

USB PORT 6

CR-2 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE2

8

7

VREG

(BACKSIDE)

PECI

SM BUS S3

SATA CONN

PCIE SLOT 1

E

PCI 1X16

GRFX CONN

VGA CONN

SPI FLASH

1&2

3&4

5&6

SM BUS S3

LPC BUS

6

SPI

PCIE X1

LAND GRID ARRAY (LGA) CONNECTOR

LGA775

PROCESSOR SOCKET

FSB

GMCH:

GRAPHICS MEMORY

CONTROLLER HUB

DMI

ICH9: I/O

CONTROLLER HUB

45

CHANNEL A DDR2 667/800

CHANNEL B DDR2 667/800

GLCI

LCI

(LAN CONNECT INTERFACE)

PCI (33MHZ)

PCI (33MHZ)

SST_CTL

3

CORE

DUAL DATA RATE SDRAM

(2-DDR SDRAM DIMMS)

DUAL DATA RATE SDRAM

(2-DDR SDRAM DIMMS)

NINEVEH
OR EKRON

SM BUS S3

THERMAL SENSOR

THERMAL SENSOR

LAN

SM BUS S0

SM BUS S3

SM BUS S0

1394

2

CK_505 CLOCK

DIMM 0:1

DIMM 0:1

RJ45

PCI SLOT 1

PCI SLOT 2

1

MODULE REV DETAILS

MODULE NAME

FP HDR

2 PER

BACK PANEL

REV

DATE

D

C

B

BROADWATER

HIGH DEF AUDIO LINK

HD AUDIO

2X8 HDR

CHIPSET

SM BUS S3

A

SM BUS S0

PS2 MOUSE &
KEYBOARD

BLOCK DIAGRM UPDATED: 09/06/2005

8

PORT
ANGELES

SIO

PARALLEL (1)

SERIAL HEADER (2)

7

FLOPPY DISK
DRIVE CONN

SM BUS S3 = RESUME WELL

SM BUS S0 = MAIN POWER WELL

6

TPM: SECURITY

CD IN (ATAPI, BLACK)

5

MIC IN

LINE IN

SP/DIF IN

HD 10 CH

AUDIO CODEC

FRONT PANEL
LINE OUT
SP/DIF OUT
LINE OUT (SURR)
LINE OUT (SURR)
LINE OUT (LFE/CENTER)

BPAGE DRAWING

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3

PC_SPKR

[PAGE_TITLE=BLOCK DIAGRAM]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

2

1

A

3.01

CR-3 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE3

8

D

7

6

AFTER P_PCIRST*, HANDSHAKE (ON HL BUS) BETWEEN ICH/MCH MUST
HAPPEN BEFORE H_CPURST* WILL BE ASSERTED/DE-ASSERTED

MCH: MEMORY

CONTROLLER HUB

P_PCIRST*
PWRGD_3V

H_CPURST*

DB_RESET*

45

ICH

FP_RST*

SIO

RES:H_CPURST

3

XDP T_RST

XDP-SSA 30-PIN

2

MODULE REV DETAILS

MODULE NAME

TRST*

H_CPURST*

LGA775 SOCKET

H_PWRGD

CPU\DBR*

1

REV

DATE

FP_RST*

D

PORT ANGELES

PCIRST_OUT*

RES: PA_PLTRST*

C

RES:5V_STBY - PS ON

RES: PS_ON_ HEADER*

POWER (2X12)

SUPPLY CONN

PS_ON*

PWRGD_PS

PCI_RST*
SLP_S4/S5*
SLP_S3*
FP_RST*

PWRGD_PS

PWRGD_3V

RSMRST*

KBRST*
PS_ON*

RES:PLTRST - PCIE

E

PCI GRAPHICS

PWRGD

1X16 CONN

X1-PORT (2)

E

PCI CONN

X1-PORT (1)

PWRGD

TPM (SECURITY)

LRESET*

PCI SLOT 2

PCI SLOT 1

C

P_PCIRST*

B

RESET*

FRONT PANEL CONN

2X8 HEADER

PWR ON SWITCH

A

H_CPURST*

XDP-SSA 31-PIN

DBR*

RESET SWITCH

FP_RST*

FP_RST*

SW_ON*

SW_ON*

JUMPER-STRAP-GND

PULL-UP TERMINATION

PWRGD_3V
RSMRST*

RCIN*
SYS_RESET*

RTC_RST*

SW_ON*

CKT: G_RST*

P_PCIRST*

JRSTSYNC

ICH9: I/O

CONTROLLER HUB

H_PWRGD

ACZ_RST*

S4_STATE

SLP_S4*
SLP_S3*

1394

PLTRST*

RES: SLP_S3*

RES: 1394_PCI_RST*

CKT: G_RST*

RES:JRSTSYNC

RES: CDC_DOWN_RST*

RES: AUD_LINK_RST_HDR*

P_PCIRST*

G_RST*

1394

LAN

JRSTSYNC

AC04 AUDIO CODEC

RESET*

2X8 HDR

AUD_LINK_RST_HDR*

B

A

RESET MAP UPDATED: 09/06/2005

8

7

BPAGE DRAWING

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6

5

4 2

3

[PAGE_TITLE=RESET MAP]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

3

1

3.01

CR-4 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE4

8

7

14.318MHZ

RES: 14MHZ

6

JORDAN

LAN

33MHZ

D

3.3 VOLT

33MHZ
33MHZ
33MHZ
33MHZ

RES: 33MHZ

LPC BUS 2X10 (TPM)

PCI SLOT 1

RES: 33MHZ

1394

32.7KHZ

TPM

CLK14

PCICLK

RTCCLK
USBCLK

DMICLK
SATACLK
AUD_BCLK

45

ICH

SUSCLK

SMBUS CLK

32.7KHZLANCLK

SCLK

3

SCLK

2

MODULE REV DETAILS

MODULE NAME

CLK14
SUSCLK

PORT
ANGELES

KBCLK

MCLK

REV

1

DATE

D

MS/KB

AUDIO

CODEC

AUD_BCLK

3.3 VOLT

C

CK505

48MHZ

25MHZ

CRYSTAL

LAN

JORDAN

ICH

12.288 MHZ

33M

C

SRC CLOCK PAIRS

B

A

14.318MHZ

SRC CLOCK PAIR

HOST CLOCK PAIRS

CLOCK DISTRIBUTION UPDATED: 09/07/2005

8

100MHZ
100MHZ
100MHZ

100MHZ
100MHZ
100MHZ
100MHZ
100MHZ
100MHZ

SCLK

96MHZ

100/133/167/200 MHZ CPU_CK

100/133/167/200 MHZ CPU_CK

100/133/167/200 MHZ CPU_CK

7

X1 PCI-EXPRESS #1

X1 PCI-EXPRESS #2

SPARE

SPARE

SPARE

XDP PORT

CPU

CORE

6

XDP

CLK-OUT

XDP CLK-OUT OPTION

5

X16 PCI-EXPRESS

GCLKIN
REFCLKIN
HOST

PCI - GRAPHICS

MCH

DUAL CHANNEL

DDR
2X200/266/333 MHZ

E

BPAGE DRAWING

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Sun Mar 18 18:42:56 2007

4 2

3

CHAN A

DIMM0

DIMM1

CHAN B

DIMM0

DIMM1

[PAGE_TITLE=CLOCK DISTRIBU T I ON]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

1

B

A

4

3.01

CR-5 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE5

ICH

D

C

B

PORT ANGELES

GPXX
GPXX
GPXX
GPXX
GPXX
GPXX
GPXX
GPXX

A

GPXX
GPXX
GPXX
GPXX
GPXX
GPXX
GPXX

8

PIN NAME

GP[0]
GP[1]
GP[2]
GP[3]
GP[4]
GP[5]
GP[6]
GP[7]
GP[8]
GP[9]
GP[10]
GP[11]
GP[12]
GP[13]
GP[14]
GP[15]
GP[16]
GP[17]
GP[18]
GP[19]
GP[20]
GP[21]
GP[22]
GP[23]
GP[24]
GP[25]
GP[26]
GP[27]
GP[28]
GP[29]
GP[30]
GP[31]
GP[32]
GP[33]
GP[34]
GP[35]
GP[36]
GP[37]
GP[38]
GP[39]
GP[48]
GP[49]

(PIN 103/118)
(PIN 104/119)
(PIN 105/120)
(PIN 106/121)
(PIN 108/124)
(PIN 109/126)
(PIN 111/127)
(PIN 112/128)
(PIN 116)
(PIN 114)
(PIN 74/115/122)
(PIN 75/113/125)
(PIN 101)
(PIN 100)
(PIN 102)

7

POWER
WELL

MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
RESUME (STBY)
RESUME (STBY)
RESUME (STBY)
RESUME (STBY)
RESUME (STBY)
RESUME (STBY)
RESUME (STBY)
RESUME (STBY)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
RESUME (STBY)
RESUME (STBY)
RESUME (STBY)
RESUME (STBY)
RESUME (STBY)
RESUME (STBY)
RESUME (STBY)
RESUME (STBY)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)

CPU

(BASED ON NATIONAL PA3.0, MAY 2004, REV 1.1; MULTI-PLEXED/PROGRAMMABLE GPIO PINS)

STBY/VCC3

STBY/VCC3

STBY/VCC3

STBY/VCC3

STBY/VCC3

STBY/VCC3

STBY/VCC3

STBY/VCC3

STBY

STBY

STBY/STBY/VCC3

STBY/STBY/VCC3

STBY

STBY

N/C (P A30)

USAGE

FP AUD DETECT
FRONT FAN TACH
P_INTE
P_INTF
P_INTG
P_INTH
REAR FAN TACH
EV FAN TACH
SATA/HOT-SWAP
WOL
NOT USED (RVP)
PORT 80 LED
BOARD ID 3
LPC_SIO_PME
NOT USED (RVP)
LAN DISABLE
BOARD ID 1
CPU FAN TACH
BOARD ID 2
SATA1GP

NOT USED (TP): SATA HOTSWAP CTL

SATA0GP
NOT USED
LDRQ1
V_SM LED CONTROL
BOARD ID 4
S4_STATE
NOT USED (TP)
NOT USED (TP)
OC5
OC6
OC7
BOARD ID 0
MFG_MODE (RVP)
ICH CFG JUMPER
NOT USED (TP)
SATA2GP
SATA3GP
NOT USED
NOT USED
NOT USED
CPUPWRGD

NOT USED (TP)
1394 ENABLE
NOT USED (TP)
1 WATT VREG CONTROL
1 WATT VREG CONTROL+

MEM. OVERVOLTAGECONTROL1

MEM. OVERVOLTAGE CONTROL2 (TP)

BOARD ID 5

5V_DDCSDA 2.2K P/U TO VCC
5V_DDCSCL
3V_DDCSDA
3V_DDCSCL
2X12 HDR DETECT
NOT USED (TP)
NOT USED (PA30)

AFTER
PLTRST

IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT

OUT(ALERT)

IN
IN
IN
OUT
IN
IN
IN
IN
OUT
IN
IN
OUT
OUT
IN
OUT
LOW
LOW
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

N/C (PA30)

6

GPIO SIGNALS NOT USED: GP40-47

S3/S5

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

NOTES

10K P/U TO VCC3

3.3K P/U TO +12V (THRU 15K)

8.2K P/U TO VCC

8.2K P/U TO VCC

8.2K P/U TO VCC

8.2K P/U TO VCC

3.3K P/U TO +12V (THRU 15K)

3.3K P/U TO +12V (THRU 15K),10K VCC3
10K P/U TO V_3P3_STBY
100K P/D TO GND
10K P/U TO V_3P3_STBY
10K P/U TO V_3P3_STBY
10K P/U TO V_3P3_STBY, 10K P/D
10K P/U TO V_3P3_STBY

10K P/U TO VCC3, 10K P/D

3.3K P/U TO +12V (THRU 15K)
10K P/U TO VCC3, 10K P/D
10K P/U TO VCC3

10K P/U TO VCC3
10K P/U TO VCC3
10K P/U TO VCC3
1K P/U TO V_SM (THRU EMPTY 0 OHM RES)
10K P/U TO V_3P3_STBY, 10K P/D
10K P/U TO V_3P3_STBY (EV DESIGN ONLY)
ENERGY LAKE STATUS LED: GREEN
ENERGY LAKE STATUS LED: YELLOW
NOA SHARED WITH OVER-CURRENT
NOA SHARED WITH OVER-CURRENT
NOA SHARED WITH OVER-CURRENT
10K P/U TO VCC3, 10K P/D

4.7K P/U TO VCC3
1K P/U TO VCC3 (SUITCASE JMPR); 4.7K P/D TO GND: BIOS NORMAL, RECOVER, CONFIGURE

10K P/U TO VCC3
10K P/U TO VCC3
10K P/U TO VCC3
10K P/D TO GND
10K P/U TO VCC3
EMPTY 100 OHM P/U (VTT)

1K P/D TO GND

10K EMPTY P/U TO V_3P3_STBY (1.8/1.9 VREG CTL)

2.2K P/U TO VCC

2.2K P/U TO VCC3

2.2K P/U TO VCC3

AUDIO

A

LAN

2

MODULE REV DETAILS

MODULE NAME

PCI X1

USB2

USB1

2.0

2.0

#2

#1

B

A

C

A

A

2420

45

3

IRQ ROUTING TABLE (EXCERPT FROM ICH BIOS BKM REV 0.72)

P_INTA*

P_INTB*

P_INTC*

P_INTD*

P_INTE*

P_INTF*

P_INTG*

P_INTH*

REQ/GNT

IDSEL

SLOT1

IRQD
IRQA
IRQB
IRQC

16

SLOT2

IRQC
IRQB
IRQA
IRQD

1

0

SLOT3
IRQD
IRQC
IRQA
IRQB

2

1817

SLOT4

SLOT5

IRQC

IRQB IRQA
IRQA

IRQD
IRQC
IRQD

IRQB

3

19

SLOT6

IRQA

IRQB
IRQD
IRQC

21

SMBUS ADDRESS LINES SA [2-0] SMBUS ADDRESS
MEMORYSLOT-0 (CHANNEL-A: SLOT-0) 0000A1H0A0H
MEMORYSLOT-1 (CHANNEL-A: SLOT-1) 0010A3H0A2H
MEMORYSLOT-2 (CHANNEL-B: SLOT-0) 0100A5H0A4H
MEMORYSLOT-3 (CHANNEL-B: SLOT-1) 0110A7H0 A6H
CK410 - - - 0D3H 0D2H

DB800/DB400 - - - 0DDH 0DCH

SMBUS DATA (EXCERPT FROM ICH BIOS BKM REV 0.72)

#3

C

1

REV

PCI X16

#1

A

DATE

D

SMBUS

#2

C

C

B

A

MULTI-PLEXED GPIO PINS ON PORT ANGELES WHICH ARE USED FOR SPECIFIC FUNCTIONS (NOT AS GPIO) ARE NOT IDENTIFIED HERE
UN-USED GPIO PINS ON PORT ANGELES ARE NOT IDENTIFIED HERE
TOTAL OF (33) POSSIBLE GPIO PINS ON PORT ANGELES (POWER WELL: STBY OR V_3P3_STBY = RESUME, VCC3 = MAIN).
NOTE: (0-4) GP'S FROM THE FWH WERE NOT USED (POWER WELL = CORE, INPUT ONLY)

8

7

6

5

4 2

BPAGE DRAWING

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Sun Mar 18 18:42:57 2007

3

[PAGE_TITLE=GPIO, IRQ, IDSEL MAP]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

5

1

3.01

CR-6 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE6

8

BI

BI

BI
BI

BI

H_ADSTB1_N

H_A_N<16..3>

H_REQ_N<4..0>

H_ADSTB0_N
H_A_N<35..17>

TP_CPU_AC4
TP_CPU_AE4

3
4
5
6
7
8
9
10
11
12
13
14
15
16

TP_RSVD_N4
TP_RSVD_P5

0
1
2
3
4

17
18
19
20
21
22
23
24
25
26
27
28
29
30

31

32
33
34
35

10

D

10

10

10

C

10

B

105

1

VTT_OUT_RIGHT

6

7

IN

89397

2

R128PR

51
5%

CH

402

VTT_OUT_RIGHT

7893

97

105

A

6

IN

1

C1PR

.1UF
20%
25V

2

EMPTY
603

DESIGN NOTE:

INTERNAL PU AVAILABLE

R1BU

ATX DESIGN ONLY

1K
5%

EMPTY
402

CPU_BOOT

1

DESIGN NOTE:

STUFF R128PR TO PREVENT

2

PSC,SMF,CDM & PSL CPU
FROM BOOTING

R7PR

1

49.9
1%

2

CH
402

8

1

2

AB6

AA4
AD6
AA5
AB5
AC5
AB4
AF5
AF4
AG6
AG4
AG5
AH4
AH5
AJ5
AJ6
AC4
AE4
AD5

L5
P6
M5
L4
M4
R4
T5
U6
T4
U5
U4
V5
V4
W5
N4
P5
K4
J5
M6
K6
J6
R6

W6
Y6
Y4

R16PR

49.9
1%

CH
402

A<3>*
A<4>*
A<5>*
A<6>*
A<7>*
A<8>*
A<9>*
A<10>*
A<11>*
A<12>*
A<13>*
A<14>*
A<15>*

RSVD
RSVD
REQ<0>*
REQ<1>*
REQ<2>*
REQ<3>*
REQ<4>*
ADSTB<0>*

A<17>*
A<18>*
A<19>*
A<20>*
A<21>*
A<22>*
A<23>*
A<24>*
A<25>*
A<26>*
A<27>*
A<28>*
A<29>*
A<30>*
A<31>*
A<32>*
A<33>*
A<34>*
A<35>*
RSVD
RSVD
ADSTB<1>*

OUT

7

6

1

R8PR

130
1%

EMPTY
402

2

H_COMP6
H_COMP7

7

J1PR

LGA775_C

REV=1.8

H_FORCEPH_N

ADS*
BNR*
HIT*

RSP*
BPRI*
DBSY*
DRDY*
HITM*
IERR*
INIT*
LOCK*
TRDY*

BINIT*
DEFER*A<16>*

MCERR*
AP<0>*

AP<1>*

BR<0>*
TESTHI_8
TESTHI_9

TESTHI_10

DP<0>*

DP<1>*

DP<2>*

DP<3>*

GTLREF0
GTLREF1
GTLREF2

GTLREF_SEL

RESET*

RS<0>*

RS<1>*

RS<2>*

1of 4

IC

OUT
OUT
OUT

6

H_ADS_N

D2
C2
D4
H4
G8
B2
C1
E4
AB2
P3
C3
E3
AD3
G7

AB3
U2

U3
F3

G3
G4
H5

J16
H15
H16
J17

H1
H2
E24
H29

G23
B3

F5
A3

TP_RSP_N

TP_BINIT_N

TP_MCERR_N

TP_AP<0>
TP_AP<1>

TP_CPU_J16
TP_CPU_H15
TP_CPU_H16
TP_CPU_J17

0

1

2

H_BNR_N
H_HIT_N

H_BPRI_N
H_DBSY_N
H_DRDY_N
H_HITM_N
H_IERR_N
H_INIT_N
H_LOCK_N
H_TRDY_N

H_DEFER_N

H_BR_N<0>
H_BPM3_2
H_BPM2_2
H_TESTHI_10

CPU_GTLREF0
CPU_GTLREF1

CPU_MCH_GTLREF

TP_GTL_DET

H_CPURST_N

H_RS_N<2..0>

OUT

BI
BI
BI

IN
BI
BI
BI

IN
BI
IN

IN

BI
BI
BI
BI

IN
IN

OUT

IN

IN

10
10
10

10

10
10

10
8
32

10

10

10

8

10
97
97
8

8
8

17

8

10 97

10

R19PR

PRECISION FSB COMPENSATION RESISTORS

69

16

6

95
6
6

6

7897

IN

IN

VTT_OUT_LEFT

1

C2PR

.1UF
20%
25V

2

EMPTY
603

H_VCCPLL

1

2

C18PR

10UF
20%

6.3V
EMPTY
805

1

2

5

C3PR

.01UF
20%
50V
X7R
603

32

16

93

70

949596105

H_CPU_PD_F6

1

51
5%

2

CH

402

1

R14PR

49.9
1%

CH
402

2

32
32

8
32
32
32
33

9
9
9
69

93

8

29
29

33

76

76

93
93
93
93

76

DESIGN NOTE:

50OHM ON 1080
TP ON 2116

45

ICH_H_SMI_N H_TESTHI_0

IN

H_A20M_N

IN

H_FERR_N

OUT

H_INTR

IN

H_NMI

IN

H_IGNNE_N

IN

H_STPCLK_N

IN

H_VCCA

IN

H_VSSA

IN

H_VCCIOPLL

IN

H_VCCPLL

IN

H_VID<7..0>

2

1

OUT

OUT

IN
IN

OUT

IN

OUT

OUT
OUT
OUT
OUT

IN

105

R18PR

49.9
1%

CH
402

VRD_VIDSEL
CK_H_CPU_DP

CK_H_CPU_DN
H_SKTOCC_N

H_TEMP_SRC_DP
H_TEMP_RET_DN

VCC_SENSE
VSS_SENSE
VCC_PKGSENSE
VSS_PKGSENSE

TP_VTT_PKGSENSE

TP_SLEW_CTRL

H_PECI

BI

TP_MPG_NOBOOT

1

R17PR

49.9
1%

CH
402

2

2

1

VCCP

R20PR

49.9
1%

CH
402

0
1
2
3
4
5

6

7

6

IN

6

IN

1

1

R12PR

49.9
1%

CH
402

2

2

Sun Mar 18 18:42:58 2007

4 2

3

J1PR

LGA775_C

P2
K3
R3
K1
L1
N2
M3

A23
B23
C23
D23

AM2
AL5
AM3
AL6
AK4
AL4
AM5
AM7
AN7

F28
G28

AE8
AL1

AK1
AJ7
AH7

AN3
AN4
AN5
AN6
AL8
AL7
F29

F6
G6
G5

AL3

DESIGN NOTE:

STUFF R15PR FOR 95W YORKFIELD

DESIGN NOTE:

STUFF R13PR FOR 65W CPU:CNR/WOLFDALE

1

R22PR

49.9
1%

2

CH
402

BPAGE DRAWING

frostburg_fabc.sch_1.6

REV=1.8

SMI*
A20M*
FERR*/PBE*

LINT0
LINT1
IGNNE*

STPCLK*
VCCA

VSSA
VCCIOPLL
VCC_PLL

VID<0>
VID<1>
VID<2>
VID<3>
VID<4>
VID<5>
VID<6>
VID<7>
VID_SELECT

BCLK<0>
BCLK<1>

SKTOCC*
THERMDA

THERMDC
RSVD
RSVD

VCC_SENSE
VSS_SENSE
VCC_MB_REGULATION
VSS_MB_REGULATION
VCC
VSS
RSVD

IMPSEL
RSVD
PECI

NC

105

H_MSID0
H_MSID1

R21PR

24.9
1%

CH
402

H_COMP8
H_COMP0
H_COMP1
H_COMP2
H_COMP3
H_COMP4
H_COMP5

0

402

R13PR

1

EMPTY

3of 4

6789397

5%

3

TESTHI_0
TESTHI_1
TESTHI_2
TESTHI_3
TESTHI_4
TESTHI_5
TESTHI_6

TESTHI_7
TESTHI_11
TESTHI_12
TESTHI_13

FORCEPR*

PWRGOOD

PROCHOT*

THERMTRIP*

COMP<0>
COMP<1>
COMP<2>
COMP<3>
COMP<4>
COMP<5>
COMP<6>
COMP<7>
COMP<8>

MSID<1>
MSID<0>

BOOTSELECT

LL_ID<0>

LL_ID<1>

IN

R15PR

0

2

402

OUT
OUT
OUT
OUT
OUT
OUT
OUT

2

MODULE REV DETAILS

MODULE NAME

F26

H_TESTHI_1

W3

H_TESTHI_2_7

F25
G25
G27
G26
G24
F24

H_TESTHI_11

P1

H_TESTHI_M

W2

H_TESTHI_13

L2

H_FORCEPH_N

AK6

H_PWRGD

N1

H_PROCHOT_N

AL2

H_THERMTRIP_N

RSVD
RSVD
RSVD
RSVD

FC5

RSVD
RSVD

M2
A13

T1
G2
R1
J2
T2
Y3
AE3
B13

G1
U1
A24
E29

F2
G10

AH2
V1

W1

Y1
V2
AA2

H_COMP0
H_COMP1
H_COMP2
H_COMP3
H_COMP4
H_COMP5
H_COMP6
H_COMP7
H_COMP8

H_BPM0_2
H_TESTHI_M
H_DCKLPH2
TP_SFRANAD2

CPU_GTLREF2
CPU_GTLREF3

TP_CPU_AH2

H_MSID1
H_MSID0

CPU_BOOT

TP_V2
TP_LL_ID1

BI

OUT

OUT

97
6

8

8

IN

8

IN

OUT
OUT

IC

VTT_OUT_RIGHT

R131PR

1

R130PR

1

1K
5%

EMPTY

2

1

2

5%

EMPTY

DESIGN NOTE:

EMPTY Q1PR FOR VTT TOOL TEST

6
6
6
6
6
6
6

[PAGE_TITLE=CPU-SOCKET 1 OF 2]

CONFIDENTIAL

CUSTOM TEXT BPAGE

402

H_MSID_XSTR_BASE_1

INTEL

680
5%

2

CH

VRD_ENABLE

402

3

Q1PR

1

MMBT3904
EMPTY

2

DOCUMENT_NUMBER

xxxxxx

REV

IN
IN
IN

IN
IN
IN
IN

IN
IN

IN
IN
IN
IN
IN
IN
IN
IN
IN

IN

402

1

R112PR

1

1K

8
8
8

8
68
8
6

8
837
8

6
6
6
6
6
6
6
6
6

6
6

6

1

DATE

95

33

95

32

2

5%

EMPTY

OUT

PAGE REV

6

D

C

B

93

A

3.01

CR-7 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE7

8

R124PR

2

VR_READY

8

39

IN

93

0CH5%

402

1

D

CAD NOTE:

H_VR_READY

7

7

OUT

6

97
97
97

97
97

97

PLACE CLOSE TO VR CONTROLLER

333651

7097

C

R33PR

1

1K
5%

EMPTY

2

402

DESIGN NOTE:

FOR DEBUG ONLY

J1PR

H_D_N<15..0>

10

BI

B

H_DBI_N<0>

10

BI

H_STBN_N<0>

10

BI

H_STBP_N<0>

10

BI

H_D_N<31..16> H_D_N<63..48>

10 10

BI

A

H_DBI_N<1>

10

BI

H_STBN_N<1> H_STBN_N<3>

10 10

BI

H_STBP_N<1> H_STBP_N<3>

10 10

BI

B4

0

C5

1

A4

2

C6

3

A5

4
5

B6

6

B7
A7

7

A10

8

A11

9

B10

10

C11

11

D8

12

B12

13
14

C12
D11

15

A8
C8
B9

G9

16

F8

17
18

F9

19

E9

20

D7

E10

21

D10

22

F11

23

F12

24

D13

25

E13

26
27

G13

28

F14

29

G14

30

F15

31

G15
G11
G12
E12

D<0>*
D<1>*
D<2>*
D<3>*
D<4>*
D<5>*
D<6>*
D<7>*
D<8>*
D<9>*
D<10>*
D<11>*
D<12>*
D<13>*
D<14>*
D<15>*
DBI<0>*

DSTBN<0>*
DSTBP<0>*

D<16>*
D<17>*
D<18>*
D<19>*
D<20>*
D<21>*
D<22>*
D<23>*
D<24>*
D<25>*
D<26>*
D<27>*
D<28>*
D<29>*
D<30>*
D<31>*
DBI<1>*

DSTBN<1>*
DSTBP<1>*

LGA775_C

REV=1.8

D<32>*
D<33>*
D<34>*
D<35>*
D<36>*
D<37>*
D<38>*
D<39>*
D<40>*
D<41>*
D<42>*
D<43>*
D<44>*
D<45>*
D<46>*
D<47>*

DBI<2>*
DSTBN<2>*
DSTBP<2>*

D<48>*
D<49>*
D<50>*
D<51>*
D<52>*
D<53>*
D<54>*
D<55>*
D<56>*
D<57>*
D<58>*
D<59>*
D<60>*
D<61>*
D<62>*
D<63>*

DBI<3>*
DSTBN<3>*
DSTBP<3>*

G16
E15
E16
G18
G17
F17
F18
E18
E19
F20
E21
F21
G21
E22
D22
G22
D19
G20
G19

D20
D17
A14
C15
C14
B15
C18
B16
A17
B18
C21
B21
B19
A19
A22
B22
C20
A16
C17

32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47

48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

H_D_N<47..32>

H_DBI_N<2>
H_STBN_N<2>
H_STBP_N<2>

H_DBI_N<3>

2of 4

IC

8

7

6

OUT

81328
81328
81328

IN
IN

OUT

IN
IN

BI

OUT
OUT
OUT

97
97

H_TCK
H_TDI
H_TDO
H_TMS
H_TRST_N

H_BPM_N<5..0>

FP_RST_N

XDP_CLKOUT_DP

OUT

XDP_CLKOUT_DN

OUT

H_FSBSEL0
H_FSBSEL1
H_FSBSEL2

97

891417 34 38

IN

2

MODULE REV DETAILS

MODULE NAME

85

7

IN

689397

105

68

97

85

DESIGN NOTE:

ENG FEATURE: 1K RES (EMPTY)

R32PR

2

5%

EMPTY

R31PR

2

5%

EMPTY

OUT
OUT
OUT

1

1K

402

1

1K

402

45

J1PR

LGA775_C

TCK
TDI
TDO
TMS
TRST*

BPM<0>*
BPM<1>*
BPM<2>*
BPM<3>*
BPM<4>*
BPM<5>*

DBR*
ITPCLK<0>

ITPCLK<1>
BSEL<0>

BSEL<1>
BSEL<2>

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD

RSVD

REV=1.8

VTT_OUT_RIGH T

VTT_OUT_LEFT

VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT

VTT_PWRGD

VTT_SEL

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

4of 4

AE1
AD1
AF1
AC1
AG1

AJ2

0

AJ1

1

AD2

2

AG2

3

AF2

4

AG3

5

AC2
AK3

AJ3
G29

H30
G30

CPU_N5

N5

H_BPM1_2

BI

TP_CPU_E7
TP_CPU_AE6

TP_CPU_D16
TP_ACLKPH2

TP_SFRANAC2

10

BI

10

BI

10

BI

10

BI
BI

C9
E7

AE6
D16

A20
E23

VCCP=AG22,K29,AM26,AE12,AE11
VCCP=W23,W24,W25,T25,Y28,AL18,AC25,W30,Y30,AN14,AD28,Y26,AC29,M29,U24,J23,AC27,AM18,AM19,AB8
VCCP=AC26,J8,J28,T30,AM9,AF15,AC8,AE14,N23,W29,U29,AC24,AC23,Y23,AN26,AN25,AN11,AN18,Y27,Y25
VCCP=U27,AD24,AE23,AE22,AN19,V8,K8,AE21,AM30,AE19,AC30,AE15,M30,K27,M24,AN21,T8,AC28,N25,AE18,W26
VCCP=AD25,M8,N30,AD26,AJ26,AM29,M25,M26,L8,U25,Y8,AJ12,AD27,U23,M23,AG29,N27,AM22,U28,K28
VCCP=U8,AK18,AD8,K24,AH28,AH21,AK12,AH22,T29,AM14,AM25,AE9,Y29,AK25,AK19,AG15,J22,T24,AG21,AM21
VCCP=J25,U30,AL21,AG25,AJ18,J19,AH30,J15,AG12,AJ22,J20,AH18,AH26,W27,AL25,AN8,AH14,T23,R8
VCCP=AK22,AN29,AG11,AK26,J10,AJ15,AG26,AN9,AH15,AF18,AL15,J26,J18,J21,AG27,AK15,AF11,AD23,AM15,AF8
VCCP=AK21,AG30,AJ21,AM11,AL11,AJ11,K30,AL14,AN30,AH25,AL12,AJ9,AK11,AG14,N29,AL30,AJ25,AH9,J29,J11
VCCP=K25,P8,K23,AL19,AM8,T26,N28,AH12,AL22,AN15,AJ8,U26,AJ19,T27,AK8,AN12,AG9,N26,AF9,AF22
VCCP=AH11,AJ14,AH19,AH29,AH27,AG28,AL26,AM12,J24,J13,T28,W28,J12,J27,AG19,AL9,AD30,AF21,Y24,AK14
VCCP=J9,M27,AF14,J30,AG18,AA8,AG8,AL29,AD29,W8,AH8,N24,AN22,J14,K26,AF19,N8,AF12,M28,AK9
GND=C10,D12,C24,K2,C22,AN1,B14,K7,AE16,B11,AL10,AK23,H12,AF7,AK7
GND=H7,E14,L28,Y5,E11,AL16,AL24,AK13,D21,AL20,D18,AN2,AK16,AK20,AM27,AM1,AL13,AL17,C19
GND=E28,AK30,D24,AL23,A12,L25,J7,AE28,AE29,K5,J4,AE30,AN20,AF10,AE24,AM24,AN23,H9,H8
GND=H13,AC6,AC7,AH6,C16,AM16,AE25,AE27,AJ28,F19,AH13,AD7,AH16,AK17,E17,AH17,AH20,AE5,AH23
GND=AE7,AM13,AH24,AJ30,AJ10,AF3,AK5,AJ16,AF6,AK29,AJ17,F22,AH3,AK10,AM10,F16,AJ23,F13,AG7,F10
GND=L26,AD4,H11,L24,L23,AM23,A15,AH10,B24,L3,H27,A21,AE2,AJ29,AK27,AK28,B20,AM20
GND=H26,B17,H25,H24,AA3,AA7,H23,AA6,H10,H22,H21,H20,H19,H18,AB7,H17,AJ24,AM17,AC3,H14
GND=P28,V6,AK2,P27,P26,AM28,AJ13,W4,P25,AJ20,W7,P23,C7,L30,L29,D15,AL27,Y7,L27
GND=AA29,N6,N7,AA28,AN13,AA27,AA26,P4,AA25,AA24,P7,E26,V30,R2,V29,V28,R5,V27,R7,E20
GND=AN10,V25,T3,V24,V23,T6,E25,R29,R28,R27,R26,R25,U7,R24,R23,P30,V3,P29
GND=AF16,AE10,AF13,H6,A18,A2,E2,D9,C4,A6,D6,D5,A9,D3,B1,B5,B8,AJ4,AE26,AH1
GND=V7,C13,AK24,AB30,L6,L7,AB29,M1,AB28,AN17,AB27,AB26,AN16,M7,AB25,AB24,AB23,N3,AA30
GND=F4,AG10,AE13,AF30,H28,F7,AF29,AF28,AF27,AF26,AF25,AN28,AN27,AF24,AF23,AG24,AF17,AN24,H3
GND=Y2,P24,AE20,AE17,E27,T7,R30,AJ27,AB1,AM4,V26,AA23,AL28,AF20,AG23,AG20,E8,AG17,AG16,AG13

3

A29
B25
B29
B30
C29
A26
B27
C28
A25
A28
A27
C30
A30
C25
C26
C27
B26
D27
D28
D25
D26
B28
D29
D30
AM6

VTT_OUT_RIGHT

AA1

VTT_OUT_LEFT

J1

VTT_SEL

F27

TP_EXTBGREF

F23
D14

TP_SFRANAD

E6

TP_SFRANAC

E5

H_DCLKPH

J3

H_ACLKPH

D1

TP_HFPLL

CAD NOTE:

PLACE A GND VIA

IC

NEAR TP ON
PIN D1

V_FSB_VTT

H_VR_READY

1

REV

DATE

D

1

1

C4PR

2

X7R
603

.1UF
10%
16V

C5PR

C

.1UF
10%
16V

2

X7R
603

B

A

10

BI
BI
BI

BPAGE DRAWING

frostburg_fabc.sch_1.7

Sun Mar 18 18:42:59 2007

5

4 2

3

[PAGE_TITLE=CPU SOCKET 2 OF 2]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

7

1

3.01

D

C

B

A

CR-8 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE8

8

105

VTT_OUT_RIGHT

6

7

8

IN

93

97

97
8
6

IN

7
93

105

9

DESIGN NOTE:

PRODUCT MAY
TIE GTLREFS
TOGETHER

6

IN

8

97

678

97

9

IN

VTT_OUT_RIGHT

IN

CPU_GTLREF1

678

IN

IN

DESIGN NOTE:

PRODUCT MAY
TIE GTLREFS
TOGETHER

1

2

1

2

VTT_OUT_LEFT

VTT_OUT_LEFT

1

R59PR

115
1%

CH
402

2

CPU_GTLREF0_DIVIDER

1

R65PR

200

1%

CH
402

2

R60PR

115
1%

CH
402

CPU_GTLREF1_DIVIDER

R56PR

200
1%

CH
402

1

0

402

1

2

1

2

1

R117PR

115
1%

CH
402

2

CPU_GTLREF3_DIVIDER

1

R118PR

200
1%

CH
402

2

R62PR

R114PR

115
1%

CH
402

CPU_GTLREF2_DIVIDER

R115PR

200
1%

CH
402

8

7

DESIGN NOTE:

GTLREF VOLTAGE SHOULD BE 0.67*VTT

(67% OF 1.2V) = 0.80V
<FOR THIS DESIGN>
100OHM OVER 200 OHM RESISTORS

R63PR

1

5%

10

CH

1

C9PR

1.0UF
20%
10V

2

Y5V
603

DESIGN NOTE:

GTLREF VOLTAGE SHOULD BE 0.67*VTT

(67% OF 1.2V) = 0.80V
<FOR THIS DESIGN>
100OHM OVER 200

1

C10PR

1.0UF
20%
10V

2

Y5V
603

2

CPU_GTLREF0

5%

EMPTY

DESIGN NOTE:

GTLREF VOLTAGE SHOULD BE 0.67*VTT

(67% OF 1.2V) = 0.80V
<FOR THIS DESIGN>
100OHM OVER 200 OHM RESISTORS

1

C14PR

1.0UF
20%
10V

2

Y5V
603

DESIGN NOTE:

GTLREF VOLTAGE SHOULD BE 0.67*VTT

(67% OF 1.2V) = 0.80V
<FOR THIS DESIGN>
100OHM OVER 200

402

OHM RESISTORS

R57PR

2

1

5%

10

CH

402

OUT

R116PR

1

10

402

OHM RESISTORS

R119PR

1

402

1

C16PR

1.0UF
20%
10V

2

Y5V
603

DESIGN NOTE:

KF CPU GTLREF: DEFAULT EMPTY

7

6

CPU GTLREF

CPU_GTLREF0

2

1

C8PR
220PF

50V

2

EMPTY
402

CPU_GTLREF1

1

C7PR
220PF
10%
50V

2

EMPTY
402

68

2

5%
CH

2

CPU_GTLREF3

5%10
CH

6

10%

CPU_GTLREF2

1

2

1

2

C15PR

220PF
10%
50V
EMPTY
402

C17PR

220PF
10%
50V
EMPTY
402

OUT

OUT

68

68

OUT

OUT

45

V_FSB_VTT

7

89141734

IN

85

38

R67PR

2

470
4025%CH

R69PR

2

470
402

105
6

7

8

93

97

678

97

1

R55PR

62
5%

CH
402

2

1

1

5%
CH

IN
IN

R68PR

2

470
402

VTT_OUT_RIGHT
VTT_OUT_LEFT

1

R52PR

100

5%
EMPTY

402

2

H_FSBSEL0

1

H_FSBSEL1

5%
CH

H_FSBSEL2

FSB SELECTS

R51PR

62
5%

CH
402

1

2

1

2

OUT

OUT

OUT

R75PR

680
5%

CH
402

CPU SIGNAL TERMINATION

3

71328

71328

71328

CAD NOTE:

PLACE AT CPU END OF

1

R76PR

330
5%

CH
402

2

ROUTE

1

2

R66PR

130
1%

EMPTY
402

2

MODULE REV DETAILS

MODULE NAME

CAD NOTE:

3438

85

17

V_FSB_VTT

7

89

IN

14

PLACE AT ICH END OF
ROUTE

1

1

R71PR

R72PR

62

62
5%

5%

CH

CH

402

2

402

2

H_THERMTRIP_N

H_FERR_N

H_PROCHOT_N
VR_READY
VRD_VIDSEL
H_CPURST_N
H_PWRGD
H_BR_N<0>

1

REV

DATE

D

C

6

32

OUT

32

6

OUT

6

37

IN

OUT
OUT

73993

6

93

6

10 97

6

33

6

10

95

OUT

OUT
OUT

B

V_FSB_VTT

7

89

1

2

105

R54PR

51
5%

CH
402

14173438

VTT_OUT_LEFT

1

R49PR

51
5%

CH
402

2

789397

1

2

IN

6

IN

R53PR

51
5%

CH
402

VTT_OUT_RIGHT

1

R64PR

51
5%

CH
402

2

1

2

R50PR

51
5%

CH
402

1

2

R48PR

62
5%

CH
402

1

2

R70PR

51
5%

CH
402

85

6

7

6

IN

8

97

TESTHI PULLUPS

[PAGE_TITLE=CPU TERMINATION & MISC P/U P/D]

BPAGE DRAWING

frostburg_fabc.sch_1.8

Sun Mar 18 18:43:01 2007

5

4 2

3

CONFIDENTIAL

CUSTOM TEXT BPAGE

TESTHI PIN NAME MAPPING
TESTHI[0]

TESTHI[1]
TESTHI[5:2]
TESTHI[7:6]

1

TESTHI[10:8]

R35PR

TESTHI[11]

51
5%

TESTHI[12]

CH

TESTHI[13]

402

2

H_TESTHI_0
H_TESTHI_2_7
H_IERR_N
H_TESTHI_1

H_TESTHI_10
H_TESTHI_11
H_TESTHI_M

H_TESTHI_13

INTEL

BYPASSEN
ODT
MCLK[3:0]
MCLKIO[1:0]
BR#[3:1]
DPSLP#
DT_SVR#
SLP#

DESIGN NOTE:

6

OUT
OUT
OUT
OUT

OUT
OUT
OUT

OUT

CHANGE TO H_TESTHI_2-7
FOR CRB

6
6
6

6
6
6

66

DOCUMENT_NUMBER

xxxxxx

PAGE REV

8

1

A

3.01

CR-9 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE9

8

D

C

105

101

9092
848586
596469

47

48

39
333436

V_3P3_STBY\G

92122

IN

32

28
3738
4953
70

82

87

88

102103

B

SIO_PIN_108

69

IN

DESIGN NOTE:

PULL UP FOR PIN 106 IS AVAILABLE ON SIO PAGE

1

2

7

VCCPLL SUPPLY

V_SFR_OUT

87

IN

V_1P5_ICH

3438

829298

IN

R146PR

10K

5%
EMPTY

402

R137PR

SIO_PIN_108_R SIO_PIN_106_R

1

2

5%

1K

EMPTY

402

MBT3904DUAL

Q4PR

5

R90PR

1

0

603

DESIGN NOTE:

DO NOT STUFF
BOTH R90PR, R87PR

DESIGN NOTE:

COST REDUCTION EXP

R87PR

1

0

603

VCC3

R139PR

1

1K

1

5%

2

EMPTY
402

2

3

4

1A

CH

1A

EMPTY

R140PR

1K

5%
EMPTY

402

6

EMPTY

1

2

H_VCCPLL

2

GTLREF_FET0
GTLREF_FET1

2

R138PR

1

1K

402

6

OUT
OUT

EMPTY

OUT

5%

45

3

PLL SUPPLY FILTER

V_FSB_VTT

7

85

6

16

7

87

88 90
32 33

82 84 85

IN

8914173438

IN

DESIGN NOTE:

L3PR: DUAL CORE SUPPORT

47

CAD NOTE:

PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET

69

TRACE WIDTH TO CAPS MUST BE NO SMALLER THAN 12 MIL

85

105
86

IN

SIO_PIN_106

484953 59

212228

9

34 36 37 38 39

64 69

70

101

102 103

92

V_3P3_STBY\G

R145PR

1

10K

5%

2

EMPTY
402

9

9

2

8914173438

V_FSB_VTT

10UH

1

L3PR
EMPTY

721891-026

2

IN

1

2

1

2

693286-014
FB1PR

EMPTY

693286-014

FB2PR
EMPTY

10UH

1

L1PR
EMPTY

721891-026

2

DESIGN NOTE:

INDUCTOR: 125 MA
0805 PACKAGE

DESIGN NOTE:

COST REDUX EXPERIMENT
EMPTY ONE INDUCTOR
TO EVALUATE

10UH

1

L2PR
EMPTY

721891-026

2

DESIGN NOTE:

INDUCTOR: 125 MA
0805 PACKAGE

1

C13PR

2

1

2

33UF
20%
25V
EMPTY
RDL

R86PR

0
5%

EMPTY
402

1

C11PR

1.0UF
20%
10V

2

EMPTY
603

1

C12PR

1.0UF
20%
10V

2

EMPTY
603

2

H_VSSA

MODULE REV DETAILS

MODULE NAME

H_VCCIOPLL

H_VCCA

OUT

OUT

6

OUT

6

1

REV

DATE

D

6

C

B

3

CPU_GTLREF0_DIVIDER_R CPU_GTLREF1_DIVIDER_R

Q3PR

D

BSS138N

GTLREF_FET0

9

A

1

EMPTY

S

G

2

GTLREF_FET0_Q

R143PR

1

1.3K
1%

EMPTY

2

402

8

R142PR

2

1

CPU_GTLREF0_DIVIDER

0

5%

EMPTY

402

CAD NOTE:

PLACE CLOSE TO THE GTLREF DIVIDER

7

8 8

GTLREF_FET1

9

ININ

6

3

Q2PR

D

BSS138N

1

EMPTY

S

G

2

GTLREF_FET1_Q

R144PR

1

576

1%

2

EMPTY
402

5

R141PR

1

2

0

402

CPU_GTLREF1_DIVIDER

5%

EMPTY

OUTOUT

CAD NOTE:

PLACE CLOSE TO THE GTLREF DIVIDER

BPAGE DRAWING

frostburg_fabc.sch_1.9

Sun Mar 18 18:43:02 2007

4 2

[PAGE_TITLE=CPU PLL FILTERED SUPPLY]

CONFIDENTIAL

3

CUSTOM TEXT BPAGE

INTEL

DOCUMENT_NUMBER

xxxxxx

PAGE REV

9

1

A

3.01

CR-10 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE10

8

EXP_A_RX_0_DP EXP_A_TX_0_DP

21

22 23

IN

EXP_A_RX_0_DN

21

22

IN

EXP_A_RX_1_DP

21

22

D

C

IN

EXP_A_RX_1_DN

21

22

IN

EXP_A_RX_2_DP

21

22

IN

EXP_A_RX_2_DN

21

22

IN

EXP_A_RX_3_DP

21

22

IN

EXP_A_RX_3_DN

21

22

IN

EXP_A_RX_4_DP

21

22

IN

EXP_A_RX_4_DN

21

22

IN

EXP_A_RX_5_DP

21

22

IN

EXP_A_RX_5_DN

21

22

IN

EXP_A_RX_6_DP

21

22

IN

EXP_A_RX_6_DN

21

22

IN

EXP_A_RX_7_DP

21

22

IN

EXP_A_RX_7_DN

21

22

IN

EXP_A_RX_8_DP

21

22

IN

EXP_A_RX_8_DN

21

22

IN

EXP_A_RX_9_DP

21

22

IN

EXP_A_RX_9_DN

21

22

IN

EXP_A_RX_10_DP

21

22

IN

EXP_A_RX_10_DN

21

22

IN

EXP_A_RX_11_DP

21

22

IN

EXP_A_RX_11_DN

21

22

IN

EXP_A_RX_12_DP

21

22

IN

EXP_A_RX_12_DN

21

22

IN

EXP_A_RX_13_DP

21

22

IN

EXP_A_RX_13_DN

21

22

IN

EXP_A_RX_14_DP

21

22

IN

EXP_A_RX_14_DN

21

22

IN

EXP_A_RX_15_DP

21

22

IN

EXP_A_RX_15_DN

21

22

IN

29
29

DMI_IT_MR_0_DP

BI

DMI_IT_MR_0_DN

BI

DMI_IT_MR_1_DP

BI

DMI_IT_MR_1_DN

BI

DMI_IT_MR_2_DP

BI

DMI_IT_MR_2_DN

BI

DMI_IT_MR_3_DP

BI

DMI_IT_MR_3_DN

BI

CK_PE_100M_MCH_DP

IN

CK_PE_100M_MCH_DN

IN

SDVO_CTRL_DATA

BI

SDVO_CTRL_CLK

BI

31
31
31
31
31
31
31
31

21

22

21

22

B

SIGNAL NAMING CONVENTION

EXP: PCI EXPRESS
DMI: DIRECT MEDIA INTERFACE
ITP: ICH TRANSMIT POSITIVE
ITN: ICH TRANSMIT NEGATIVE
IRP: ICH RECEIVE POSITIVE
IRN: ICH RECEIVE NEGATIVE
MTP: MCH TRANSMIT POSITIVE
MTN: MCH TRANSMIT NEGATIVE
MRP: MCH RECEIVE POSITIVE

A

MRN: MCH RECEIVE NEGATIVE

8

7

F13
E13
K15
J15
F12
E12
J12
H12
J11
H11

F7
E7
E5
F6
C2
D2
G6
G5
L9
L8
M8
M9
M4
L4
M5
M6
R9

R10

T4
R4
R6
R7

W2
V1
Y8

Y9
AA7
AA6
AB3
AA4

B12
B13

G17
E17

J3UB

1

NC NC

HDR

C85376-001

7

6

U1UB

BRLK_B

REV=1
PEG_RXP_0
PEG_RXN_0
PEG_RXP_1
PEG_RXN_1
PEG_RXP_2
PEG_RXN_2
PEG_RXP_3
PEG_RXN_3
PEG_RXP_4
PEG_RXN_4
PEG_RXP_5
PEG_RXN_5
PEG_RXP_6
PEG_RXN_6
PEG_RXP_7
PEG_RXN_7
PEG_RXP_8
PEG_RXN_8
PEG_RXP_9
PEG_RXN_9
PEG_RXP_10
PEG_RXN_10
PEG_RXP_11
PEG_RXN_11
PEG_RXP_12
PEG_RXN_12
PEG_RXP_13
PEG_RXN_13
PEG_RXP_14
PEG_RXN_14
PEG_RXP_15
PEG_RXN_15

DMI_RXP_0
DMI_RXN_0
DMI_RXP_1
DMI_RXN_1
DMI_RXP_2
DMI_RXN_2
DMI_RXP_3
DMI_RXN_3

EXP_CLKINP
EXP_CLKINN

SDVO_CTRLDATA
SDVO_CTRLCLK

PEG_TXP_0
PEG_TXN_0
PEG_TXP_1
PEG_TXN_1
PEG_TXP_2
PEG_TXN_2
PEG_TXP_3
PEG_TXN_3
PEG_TXP_4
PEG_TXN_4
PEG_TXP_5
PEG_TXN_5
PEG_TXP_6
PEG_TXN_6
PEG_TXP_7

PCIE

PEG_TXN_7
PEG_TXP_8
PEG_TXN_8
PEG_TXP_9

PEG_TXN_9
PEG_TXP_10
PEG_TXN_10
PEG_TXP_11
PEG_TXN_11
PEG_TXP_12
PEG_TXN_12
PEG_TXP_13
PEG_TXN_13
PEG_TXP_14
PEG_TXN_14
PEG_TXP_15
PEG_TXN_15

DMI_TXP_0

DMI_TXN_0

DMI_TXP_1

DMI_TXN_1

DMI_TXP_2

DMI_TXN_2

DMI

DMI_TXP_3

DMI_TXN_3

EXP_COMPO

EXP_COMPI

2OF8

SDVO CTRL DATA

1 SDVO CARD PRESENT, PEG DISABLED

0 SDVO DISABLED (DEFAULT)

1

J2UB

1

HDR

J9UB

NC

1

HDR

J7UB

NC

HDR

6

D11

EXP_A_TX_0_DN

D12
B11

EXP_A_TX_1_DP
EXP_A_TX_1_DN

A10

EXP_A_TX_2_DP

C10

EXP_A_TX_2_DN

D9
B9

EXP_A_TX_3_DP
EXP_A_TX_3_DN

B7

EXP_A_TX_4_DP

D7

EXP_A_TX_4_DN

D6

EXP_A_TX_5_DP

B5

EXP_A_TX_5_DN

B6

EXP_A_TX_6_DP

B3

EXP_A_TX_6_DN

B4

EXP_A_TX_7_DP

F2

EXP_A_TX_7_DN

E2
F4

EXP_A_TX_8_DP
EXP_A_TX_8_DN

G4

EXP_A_TX_9_DP

J4

EXP_A_TX_9_DN

K3

EXP_A_TX_10_DP

L2

EXP_A_TX_10_DN

K1

EXP_A_TX_11_DP

N2

EXP_A_TX_11_DN

M2
P3

EXP_A_TX_12_DP
EXP_A_TX_12_DN

N4
R2

EXP_A_TX_13_DP
EXP_A_TX_13_DN

P1

EXP_A_TX_14_DP

U2
T2

EXP_A_TX_14_DN
EXP_A_TX_15_DP

V3
U4

EXP_A_TX_15_DN

V7

DMI_MT_IR_0_DP

V6

DMI_MT_IR_0_DN

W4

DMI_MT_IR_1_DP

Y4

DMI_MT_IR_1_DN

AC8

DMI_MT_IR_2_DP

AC9

DMI_MT_IR_2_DN

Y2

DMI_MT_IR_3_DP

AA2

DMI_MT_IR_3_DN

AC11

GRCOMP

AC12

CAD NOTE:

MCH COMP0/1 SIGNALS:
TIE TOGETHER AT PINS.

IC

HS1UB

BRDWTR_ATX_HS

1

NC_3

NC_1

2

NC_4

NC_2

8

NC_5

NC_8

7

NC_6

NC_7

5

3
4

5
6

HEATSINK

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

45

23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23

31

BI

31

BI

31

BI

31

BI

31

BI

31

BI

31

BI

31

BI

17

IN

H_A_N<35..3>

6

BI

H_REQ_N<4..0>

6

BI

H_ADSTB0_N

6

BI

H_ADSTB1_N

6

BI

H_STBP_N<0>

7

BI

H_STBN_N<0>

7

BI

H_DBI_N<0>

7

BI

H_STBP_N<1>

7

BI

H_STBN_N<1>

7

BI

H_DBI_N<1>

7

BI

H_STBP_N<2>

7

BI

H_STBN_N<2>

7

BI

H_DBI_N<2>

7

BI

H_STBP_N<3>

7

BI

H_STBN_N<3>

7

BI

H_DBI_N<3>

7

BI

H_ADS_N

6

BI

H_TRDY_N

6

OUT

H_DRDY_N

6

OUT

H_DEFER_N

6

OUT

H_HITM_N

6

OUT

H_HIT_N

6

OUT

H_LOCK_N

6

IN

H_BR_N<0>

68

OUT

H_BNR_N

6

BI

H_BPRI_N

6

OUT

H_DBSY_N

6

BI

H_RS_N<2..0>

6

BI

H_CPURST_N

68

97

OUT

3

U1UB
BRLK_B

J42

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

32
33
34
35

0
1
2
3
4

0
1
2

AA37

AA42

AA41

L39
J40
L37
L36
K42
N32
N34
M38
N37
M36
R34
N35
N38
U37
N39
R37
P42
R39
V36
R38
U36
U33
R35
V33
V35
Y34
V42
V38
Y36
Y38
Y39

F40
L35
L38
G43
J37

M34
U34

M42
M43
M40
G35
H33
J33
G27
H27
G29
B38
C38
E33

W40
Y40
W41
T43
Y43
U42
V41

W42
G39
U40
U41

U39
C31

FSB_AB_3
FSB_AB_4
FSB_AB_5
FSB_AB_6
FSB_AB_7
FSB_AB_8
FSB_AB_9
FSB_AB_10
FSB_AB_11
FSB_AB_12
FSB_AB_13
FSB_AB_14
FSB_AB_15
FSB_AB_16
FSB_AB_17
FSB_AB_18
FSB_AB_19
FSB_AB_20
FSB_AB_21
FSB_AB_22
FSB_AB_23
FSB_AB_24
FSB_AB_25
FSB_AB_26
FSB_AB_27
FSB_AB_28
FSB_AB_29
FSB_AB_30
FSB_AB_31
FSB_AB_32
FSB_AB_33
FSB_AB_34
FSB_AB_35

FSB_REQB_0
FSB_REQB_1
FSB_REQB_2
FSB_REQB_3
FSB_REQB_4

FSB_ADSTBB_0
FSB_ADSTBB_1

FSB_DSTBPB_0
FSB_DSTBNB_0
FSB_DINVB_0
FSB_DSTBPB_1
FSB_DSTBNB_1
FSB_DINVB_1
FSB_DSTBPB_2
FSB_DSTBNB_2
FSB_DINVB_2
FSB_DSTBPB_3
FSB_DSTBNB_3
FSB_DINVB_3

FSB_ADSB
FSB_TRDYB
FSB_DRDYB
FSB_DEFERB
FSB_HITMB
FSB_HITB
FSB_LOCKB
FSB_BREQ0B
FSB_BNRB
FSB_BPRIB
FSB_DBSYB
FSB_RSB_0
FSB_RSB_1
FSB_RSB_2
FSB_CPURSTB

REV=1

1OF8

BPAGE DRAWING

frostburg_fabc.sch_1.10

Sun Mar 18 18:43:03 2007

4 2

3

[PAGE_TITLE=MCH SECTIONS PAGE 1 OF 6]

2

MODULE REV DETAILS

MODULE NAME

H_D_N<63..0>

0

INTEL

R40
P41
R41
N40
R42
M39
N41
N42
L41
J39
L42
J41
K41
G40
F41
F42
C42
D41
F38
G37
E42
E39
E37
C39
B39
G33
A37
F33
E35
K32
H32
B34
J31
F32
M31
E31
K31
G31
K29
F31
J29
F29
L27
K27
H26
L26
J26
M26
C33
D35
E41
B41
D42
C40
C35
B40
D38
D37
B33
D33
C34
B35
A32
D32

B25
D23
C25
D25

D24
B24

R32
U32

IC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

HXSWING
HXRCOMP
HXSCOMP

HXSCOMPB

MCH_GTLREF

CK_H_MCH_DP
CK_H_MCH_DN

DOCUMENT_NUMBER

xxxxxx

FSB_DB_0
FSB_DB_1
FSB_DB_2
FSB_DB_3
FSB_DB_4
FSB_DB_5
FSB_DB_6
FSB_DB_7

FSB

FSB_DB_8

FSB_DB_9
FSB_DB_10
FSB_DB_11
FSB_DB_12
FSB_DB_13
FSB_DB_14
FSB_DB_15
FSB_DB_16
FSB_DB_17
FSB_DB_18
FSB_DB_19
FSB_DB_20
FSB_DB_21
FSB_DB_22
FSB_DB_23
FSB_DB_24
FSB_DB_25
FSB_DB_26
FSB_DB_27
FSB_DB_28
FSB_DB_29
FSB_DB_30
FSB_DB_31
FSB_DB_32
FSB_DB_33
FSB_DB_34
FSB_DB_35
FSB_DB_36
FSB_DB_37
FSB_DB_38
FSB_DB_39
FSB_DB_40
FSB_DB_41
FSB_DB_42
FSB_DB_43
FSB_DB_44
FSB_DB_45
FSB_DB_46
FSB_DB_47
FSB_DB_48
FSB_DB_49
FSB_DB_50
FSB_DB_51
FSB_DB_52
FSB_DB_53
FSB_DB_54
FSB_DB_55
FSB_DB_56
FSB_DB_57
FSB_DB_58
FSB_DB_59
FSB_DB_60
FSB_DB_61
FSB_DB_62
FSB_DB_63

FSB_SWING
FSB_RCOMP
FSB_SCOMP

FSB_SCOMPB

FSB_DVREF

FSB_ACCVREF

HPL_CLKINP
HPL_CLKINN

DESIGN NOTE:

MCH GTLREF0/1: SEPARATE SIGNALS ON EV ONLY;
TIE TOGETHER AT PINS ON CRB.

CONFIDENTIAL

CUSTOM TEXT BPAGE

REV

1

BI

17

IN

17

IN

17

IN

17

IN

17

IN

29

IN

29

IN

PAGE REV

10

1

DATE

7

D

C

B

A

3.01

CR-11 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE11

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

D

M_DQS_A_DP<7..0>
M_DQS_A_DN<7..0>

M_DQM_A<7..0>

M_DATA_A<63..0>

111

101112

13

8

AV4

DDR_A_DQ_8

DDR_A_WEB

BA33

9

AV3

DDR_A_DQ_9

DDR_A_CASB

AW35

BA4

DDR_A_DQ_10

DDR_A_RASB

AY33

BB3

DDR_A_DQ_11

AU2

AU1

DDR_A_DQ_12

DDR_A_BS_0

BA31

AY31

1

0

DDR_A_DQ_13

DDR_A_BS_1

14

AY2

DDR_A_DQ_14

DDR_A_BS_2

AY20

2

AN3

DDR_A_DQ_1

DDR_A_MA_5

BB22

AR2

DDR_A_DQ_2

DDR_A_MA_6

BA22

AR3

AL3

DDR_A_DQ_3

DDR_A_MA_7

BB21

AW21

7

8

DDR_A_DQ_4

DDR_A_MA_8

AM2

AR5

DDR_A_DQ_5

DDR_A_DQ_6

DDR_A_MA_10

DDR_A_MA_9

BA21

BB31

101113

9

7

AR4

DDR_A_DQ_7

DDR_A_MA_11

AY21

BC20

DDR_A_MA_12

12

AW2

AY38

DDR_A_DQS_1

DDR_A_MA_13

AW1

DDR_A_DQSB_1

DDR_A_MA_14

BA19

14

AW3

DDR_A_DM_1

000

0123456

C

AP2

AP3

AN2

AM1

DDR_A_DQ_0

DDR_A_DM_0

DDR_A_DQS_0

DDR_A_DQSB_0

BRLK_B

U1UB

REV=1

B

DDR_A_MA_4

DDR_A_MA_3

DDR_A_MA_2

DDR_A_MA_1

DDR_A_MA_0

BA23

BB23

AY23

AY25

BB30

1

05923456

A

15

2

AY3

AY7

DDR_A_DQ_15

BA34

01230

161718

2

2

BA6

BB6

BB5

AY6

BA9

DDR_A_DM_2

DDR_A_DQ_18

DDR_A_DQ_17

DDR_A_DQ_16

DDR_A_DQS_2

DDR_A_DQSB_2

DDR_A_CKE_1

DDR_A_CKE_0

DDR_A_CSB_3

DDR_A_CSB_2

DDR_A_CSB_1

DDR_A_CSB_0

AY35

BB33

BB38

AY19

AW18

1

19

BB9

DDR_A_DQ_19

DDR_A_CKE_2

BB19

2

202122

BA5

BB4

DDR_A_DQ_21

DDR_A_DQ_20

DDR_A_CKE_3

BA18

3

BC7

DDR_A_DQ_22

DDR_A_ODT_0

BB35

0

23

AY9

DDR_A_DQ_23

DDR_A_ODT_1

BA38

1

333

AT20

AU18

AN18

DDR_A_DM_3

DDR_A_DQS_3

DDR_A_DQSB_3

DDR_A_ODT_3

DDR_A_ODT_2

BA35

BA39

3

2

2425262728

AT18

AR18

AU21

AT21

DDR_A_DQ_27

DDR_A_DQ_26

DDR_A_DQ_25

DDR_A_DQ_24

DDR_A_CK_0

DDR_A_CKB_0

DDR_A_CK_1

AU31

AP27

AR31

AP17

AN27

DDR_A_DQ_28

DDR_A_CKB_1

29

AN17

DDR_A_DQ_29

DDR_A_CK_2

AV33

30

AP20

DDR_A_DQ_30

DDR_A_CKB_2

AW33

31

AV20

AP29

DDR_A_DQ_31

DDR_A_CK_3

444

AR41

DDR_A_DQS_4

DDR_A_CK_4

DDR_A_CKB_3

AM26

AP31

32333435363738

AR40

AU43

AV42

DDR_A_DM_4

DDR_A_DQSB_4

DDR_A_CKB_4

DDR_A_CK_5

DDR_A_CKB_5

AM27

AU33

AT33

AU40

AP42

AN39

AV40

AV41

DDR_A_DQ_37

DDR_A_DQ_36

DDR_A_DQ_35

DDR_A_DQ_34

DDR_A_DQ_33

DDR_A_DQ_32

CK_M_DDR0_A_DP
CK_M_DDR0_A_DN
CK_M_DDR1_A_DP
CK_M_DDR1_A_DN
CK_M_DDR2_A_DP
CK_M_DDR2_A_DN
CK_M_DDR3_A_DP
CK_M_DDR3_A_DN
CK_M_DDR4_A_DP
CK_M_DDR4_A_DN
CK_M_DDR5_A_DP
CK_M_DDR5_A_DN

39

555404142434445464766648495051525354755

AR42

AP41

AL41

AL40

AM43

AN41

AM39

AK42

AK41

AN40

AN42

AL42

AL39

AG42

AG41

AG40

AJ40

DDR_A_DQ_38

DDR_A_DQ_39

DDR_A_DM_5

DDR_A_DQ_44

DDR_A_DQ_43

DDR_A_DQ_42

DDR_A_DQ_41

DDR_A_DQ_40

DDR_A_DQS_5

DDR_A_DQSB_5

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

24

BI

DDR_A_DQ_45

DDR_A_DQ_46

DDR_A_DQ_47

DDR_A_DM_6

DDR_A_DQ_48

DDR_A_DQS_6

DDR_A_DQSB_6

AH43

AF39

AE40

AJ42

AJ41

AF41

AF42

DDR_A_DQ_55

DDR_A_DQ_54

DDR_A_DQ_53

DDR_A_DQ_52

DDR_A_DQ_51

DDR_A_DQ_50

DDR_A_DQ_49

DDR_A

7

AC42

AC41

DDR_A_DQS_7

DDR_A_DQSB_7

RSVD

AN21

7

565758

60

61

62

63

AC40

AD40

AD43

AB41

AA40

AE42

AE41

AC39

AB42

DDR_A_DM_7

DDR_A_DQ_56

DDR_A_DQ_57

DDR_A_DQ_58

DDR_A_DQ_59

DDR_A_DQ_60

DDR_A_DQ_61

DDR_A_DQ_62

DDR_A_DQ_63

3OF8

IC

OUT
OUT
OUT

BI

24
24
24
24

D

C

B

A

M_ODT_A<3..0>

M_SCKE_A<3..0>

M_SCS_A_N<3..0>

M_SBS_A<2..0>

M_RAS_A_N
M_CAS_A_N

M_WE_A_N

M_MAA_A<14..0>

8

7

6

5

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

24 26
24 26
24 26
24 26
24 26
24 26
24 26

4 2

BPAGE DRAWING

frostburg_fabc.sch_1.11

Sun Mar 18 18:43:04 2007

3

[PAGE_TITLE=MCH SECTIONS PAGE 2 OF 6]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

11

1

3.01

TP_A_RCVEN_N

CR-12 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE12

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

D

M_DQS_B_DP<7..0>
M_DQS_B_DN<7..0>

M_DQM_B<7..0>

M_DATA_B<63..0>

111

10111213146115

9

8

AR12

AP12

AW9

AT11

AU11

AP13

AR13

AR11

AU9

AV12

AU12

AN8

7

AW5

AW7

AN5

AN6

AN9

AU7

059000123456

C

AV6

AU5

AR7

AN7

18

17

16

222

AP15

AR15

AW13

AU15

AV13

AU17

333

19

202221

23

AT17

AU13

AM13

AV15

AW17

AT24

AU26

AP23

2524262728

AV24

AT23

30

31

29

AT26

AP26

AU23

AW23

AR24

AN26

444

AW39

AU39

AU37

AW37

33323435363738539

AV38

AN36

AN37

AU35

AR35

AN35

554140424344464564766484950515253

AR37

AL35

AL34

AM37

AM35

AM38

AJ34

AL38

AR39

AM34

AL37

AL32

AG35

AG36

AG39

7

7

7

54

55

56

60

62

63

AG38

AJ38

AF35

AF33

AJ37

AJ35

AG33

AF34

AC36

AC37

AD38

AD36

AC33

AA34

AA36

AD34

AF38

AC34

AA33

OUT
OUT
OUT

BI

25
25
25
25

D

C

IC

DDR_B_DQ_37

DDR_B_DQ_38

DDR_B_DQ_39

DDR_B_DM_5

DDR_B_DQ_44

DDR_B_DQ_43

DDR_B_DQ_42

DDR_B_DQ_41

DDR_B_DQ_40

DDR_B_DQS_5

DDR_B_DQSB_5

RSVD

RSVD

RSVD

BA2

AN32

AW42

AV32

DDR_B_DQ_29

DDR_B_CK_2

DDR_B_DQ_30

DDR_B_CKB_2

AT32

DDR_B_DQ_31

DDR_B_CK_3

AR29

DDR_B_DM_4

DDR_B_DQ_36

DDR_B_DQ_35

DDR_B_DQ_34

DDR_B_DQ_33

DDR_B_DQ_32

DDR_B_DQS_4

DDR_B_DQSB_4

DDR_B_CK_5

DDR_B_CKB_4

DDR_B_CK_4

DDR_B_CKB_3

DDR_B_CKB_5

AU29

AV29

AP32

AN33

AW27

DDR_B_DQ_13

DDR_B_BS_1

AY17

DDR_B_DQ_14

DDR_B_BS_2

AY11

DDR_B_DQ_15

DDR_B_DQS_2

DDR_B_DQSB_2

DDR_B_CSB_1

DDR_B_CSB_0

BA25

BA29

1

0

DDR_B_DM_2

DDR_B_DQ_17

DDR_B_DQ_16

DDR_B_CKE_0

DDR_B_CSB_2

DDR_B_CSB_3

BA26

BA30

AW11

23012

DDR_B_DQ_18

DDR_B_CKE_1

BC12

DDR_B_DQ_19

DDR_B_CKE_2

BA10

DDR_B_DQ_20

DDR_B_CKE_3

BB10

3

DDR_B_DQ_5

DDR_B_MA_9

AY13

DDR_B_DQ_7

DDR_B_DQ_6

DDR_B_MA_11

DDR_B_MA_10

BA17

AY12

1058111312

DDR_B_MA_12

BA11

AY27

DDR_B_DQS_1

DDR_B_MA_13

DDR_B_DQSB_1

DDR_B_MA_14

BB11

14

DDR_B_DM_1

DDR_B_DQ_12

DDR_B_DQ_11

DDR_B_DQ_10

DDR_B_BS_0

DDR_B_RASB

DDR_B_CASB

DDR_B_WEB

BB25

AW26

AY24

BB17

012

DDR_B_DQ_1

DDR_B_DQ_0

DDR_B_DM_0

DDR_B_DQ_4

DDR_B_DQ_3

DDR_B_DQ_2

DDR_B_DQS_0

U1UB

B

DDR_B_DQSB_0

BRLK_B

REV=1

DDR_B_MA_8

DDR_B_MA_7

DDR_B_MA_6

DDR_B_MA_5

DDR_B_MA_4

DDR_B_MA_3

DDR_B_MA_2

DDR_B_MA_1

DDR_B_MA_0

AW15

BB15

BA15

AY15

BA14

BB14

AW12

BA13

BB13

01234575

679

8

DDR_B_DQ_9

DDR_B_DQ_8

DDR_B_DQ_21

DDR_B_DQ_22

DDR_B_ODT_0

BB27

032

DDR_B_DQ_23

DDR_B_ODT_1

AW29

1

DDR_B_DM_3

DDR_B_DQ_28

DDR_B_DQ_27

DDR_B_DQ_26

DDR_B_DQ_25

DDR_B_DQ_24

DDR_B_DQS_3

DDR_B_DQSB_3

DDR_B_CKB_1

DDR_B_CK_1

DDR_B_CKB_0

DDR_B_CK_0

DDR_B_ODT_2

DDR_B_ODT_3

BA27

AY29

AW31

AV31

AT27

AU27

DDR_B_DQ_46

DDR_B_DQ_45

RSVD

RSVD

AG32

AM31

DDR_B_DQ_47

RSVD

RSVD

AP21

AF32

DDR_B_DQS_6

DDR_B_DQSB_6

RSVD

AA39

DDR_B_DM_6

DDR_B_DQ_52

DDR_B_DQ_51

DDR_B_DQ_50

DDR_B_DQ_49

DDR_B_DQ_48

DDR_B

DDR_B_DQ_53

DDR_B_DQ_54

DDR_B_DQ_55

DDR_B_DQS_7

DDR_B_DQSB_7

RSVD

AM21

DDR_B_DM_7

DDR_B_DQ_56

DDR_B_DQ_57

DDR_B_DQ_58

DDR_B_DQ_59

DDR_B_DQ_60

DDR_B_DQ_61

DDR_B_DQ_62

DDR_B_DQ_63

4OF8

B

DDR_RCOMPVOH

DDR_RCOMPVOL

DDR_RCOMPYPU

DDR_RCOMPYPD

DDR_RCOMPXPU

DDR_RCOMPXPD

DDR_VREF

AM6

AM8

AL4

AL2

BB40

BA40

AM10

TP_DDR_SLEWYDB

TP_DDR_SLEWXDB

TP_DDR_OBSERV_1

TP_DDR_OBSERV_0

TP_DDR_ANALOG_1

TP_DDR_ANALOG_0

TP_DDR_RCOMPYPAD

CK_M_DDR0_B_DP
CK_M_DDR0_B_DN
CK_M_DDR1_B_DP
CK_M_DDR1_B_DN

A

M_ODT_B<3..0>

M_SCKE_B<3..0>

M_SCS_B_N<3..0>

M_SBS_B<2..0>

M_RAS_B_N
M_CAS_B_N

M_WE_B_N

M_MAA_B<14..0>

8

7

6

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

5

CK_M_DDR2_B_DP
CK_M_DDR2_B_DN
CK_M_DDR3_B_DP
CK_M_DDR3_B_DN
CK_M_DDR4_B_DP
CK_M_DDR4_B_DN
CK_M_DDR5_B_DP
CK_M_DDR5_B_DN

25

26

25

26

25

26

25

26

25

26

25

26

25

26

4 2

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

TP_DDR_RCOMPXPAD

25
25
25
25
25
25
25
25
25
25
25
25

BPAGE DRAWING

frostburg_fabc.sch_1.12

Sun Mar 18 18:43:05 2007

MCH_VREF

19

IN

MCH_DDR_RCOMPXPD

19

IN

MCH_DDR_RCOMPXPU

19

IN

MCH_DDR_RCOMPYPD

19

IN

MCH_DDR_RCOMPYPU

19

IN

MCH_DDR_RCOMPVOL

19

IN

MCH_DDR_RCOMPVOH

19

IN

CAD NOTE:

BTX SPECIFIC: TESTPOINT ON DDR_RCOMPY_PAD (U1UB)
ATX SPECIFIC: DO NOT TESTPOINT (U1UB_PIN AW42)

3

TP_B_RCVEN_N

[PAGE_TITLE=MCH SECTIONS PAGE 3 OF 6]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

12

1

A

3.01

CR-13 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE13

8

13

33

53

70

IN

PWRGD_3V

7

R10UB

1

2

5%

0

CH

402

D

DESIGN NOTE:

0 OHM ISOLATION RESISTOR (R10UB) ON PWRGD_3V TO PWRGD_3V_R

DESIGN NOTE:

FAB A/B ONLY: DEFAULT STUFF (R12UB) FOR BOTH AMT AND NON-AMT
AND FOR NON-AMT ADD 0 OHM SOLDER BLOB ACROSS R11UB

C

53

70

CAD NOTE:

86

DEFAULT STUFF (R10UB): DEFENSIVE DESIGN (ENG. EXP)

BOM NO TE:

STUFF R12UB FOR AMT

2

1

39

1333

IN

IN

MCH_CLPWROK

PWRGD_3V

R12UB

5%

0

EMPTY

402

R11UB

1

2

0

5%
CH

402

BOM NO TE:

STUFF R11UB FOR NON AMT

OVERLAP PADS ON R11UB, R12UB

B

NOA H L DESCRIPTION

0 SEE BSEL TABLE BSEL0
1 SEE BSEL TABLE BSEL1
2 SEE BSEL TABLE BSEL2

4:3 SEE DFT MODE TABLE DFT MODE

5 DDR2 DDR3 MEMORY TYPE

A

6 NORM REVERSE PCI-EXPRESS LANE REVERSAL
7 DISABLE ENABLE FSB HARDWARE STRAPS
8 CONCURRENT NON-CONCURRENT PCI-E / SDVO CO-EXISTENCE
9 DISABLE ENABLE ITPM HOST INTERFACE
11 ENABLE DISABLE ME CRYPTO

3,4,5,6,7,8,9 ALL HAVE INTERNAL PULL-UPS

8

7

1

2

MCH_CLPWROK_R

6

PWRGD_3V_R

C147UB
220PF

10%
50V
X7R
402

13

OUT

32

6

OUT

45

13

13

13

32
32
19
32

32

13

13

IN

13

IN

13

IN

13

IN

13

IN

13

IN

OUT

BI

BI
BI

IN

BI

IN

MCH_BSEL0
MCH_BSEL1
MCH_BSEL2
TP_MCH_K20
TP_MCH_F20
MCH_PIN_G18
MCH_EXP_SLR
TP_MCH_K17
MCH_EXP_EN
MCH_RFU_G15

TP_MCH_L17
MCH_RFU_E20
TP_MCH_N18
TP_MCH_N15
TP_MCH_N17
TP_MCH_L15
TP_MCH_L18
TP_MCH_M18

CL_N_DATA
CL_N_CLK
CL_N_VREF_MCH
CL_RST
MCH_CLPWROK_R

TP_MCH_JTAG_TDI
TP_MCH_JTAG_TDO
TP_MCH_JTAG_TCK
TP_MCH_JTAG_TMS

TP_HPLLMON1_DP
TP_HPLLMON1_DN
TP_HPLLMON2_DP
TP_HPLLMON2_DN

TP_DPLLMON1_DN
TP_DPLLMON1_DP
TP_DPLLMON2_DN
TP_DPLLMON2_DP

G20
J20
J18
K20
F20
G18
E18
K17
J17
G15

L17
E20
N18
N15
N17
L15
L18
M18

AD12
AD13

AM5
AA12
AM15

AA10

AA9
AA11

Y12

U30

U31

R29

R30

U12

U11

R12

R13

BSEL0
BSEL1
BSEL2
ALLZTEST
XORTEST
MTYPE
EXP_SLR
RSVD
EXP_EN
RFU_G15

RSVD
RFU_E20
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

CL_DATA
CL_CLK
CL_VREF
CL_RSTB
CL_PWROK

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD

3

U1UB

BRLK_B

REV=1

VGA

CRT_DDC_DATA

DPL_REFCLKINP
DPL_REFCLKINN

MISC

5OF8

CRT_HSYNC
CRT_VSYNC

CRT_RED

CRT_GREEN

CRT_BLUE
CRT_REDB

CRT_GREENB

CRT_BLUEB

CRT_DDC_CLK

CRT_IREF

RSVD
RSVD
RSVD

RSTINB

PWROK

ICH_SYNCB

RSVD

DESIGN NOTE:

7828

IN

7828

IN

7828

IN

VCC
VSS

NC

IC

ENG FEATURE: NOA STRAPS AND FSBSEL ISOLATION

H_FSBSEL0

H_FSBSEL1

H_FSBSEL2

BSEL TABLE

2 1 0 PSB FREQUENCY

0 0 0 267 MHZ (1067)
0 0 1 133 MHZ (533)
0 1 0 200 MHZ (800)
0 1 1 167 MHZ (133)
1 0 0 333 MHZ (1333)
1 0 1 100 MHZ (133)
110400 MHZ (RSVD)
1 1 1 533 MHZ (133)

5

21

22

BPAGE DRAWING

frostburg_fabc.sch_1.13

Sun Mar 18 18:43:08 2007

4 2

[PAGE_TITLE=MCH SECTIONS PAGE 4 OF 6]

3

EXP_PRSNT_N

IN

2

C15

VGA_HSYNC

E15

VGA_VSYNC

B18
C19
B20
C18
D19
D20

L13
M13

A20
C14

D13
L12
M11

H18
F17
A14
AM18
AM17
J13

A42
R20

CUSTOM TEXT BPAGE

VGA_RED

VGA_GREEN

TPEV_PM_EXTTS_N

TP_PM_BMBUSY_N

TPEV_XDP_TESTIN_N

PLTRST_N
PWRGD_3V_R
ICH_SYNC_N

TPEV_MCH_DET_N

INTEL

CONFIDENTIAL

MODULE REV DETAILS

MODULE NAME

VGA_BLUE

VGA_MCH_DDCSDA
VGA_MCH_DDCSCL

VGA_DACREFSET
CK_96M_DREF_DP

CK_96M_DREF_DN

V_1P25_CORE

TP_FSB_OBS

R23BC

1

0

2

5%
CH

2

CH

2

2

5%

EMPTY

2

5%

2

5%

EMPTY

2

5%

EMPTY

2

4025%EMPTY

MCH_BSEL0

MCH_BSEL1

MCH_BSEL2

MCH_RFU_G15

MCH_RFU_E20

MCH_PIN_G18

MCH_EXP_SLR

MCH_EXP_EN

DESIGN NOTE:

DEBUG PURPOSE, ALWAYS EMPTY

R13UB

1

10K
402

R15UB

1

10K 5%
402

R14UB

1

10KCH5%
402

R101UB

1

1K

402

R102UB

1

1K

EMPTY

402

R17UB

1

1K

402

R18UB

1

1K

402

R16UB

1

0CH5%

402

DOCUMENT_NUMBER

xxxxxx

OUT
OUT

OUT
OUT
OUT

IN

OUT

REV

BI
BI

IN
IN

IN

IN
IN

2

OUT

OUT

OUT

1

17
17

17 19
17 19
17 19

17

20

17

20

17

17

29

17

29

14 161718

76

38

33

68 69 98

13

33

13

13

13

OUT

OUT

OUT

OUT

OUT

PAGE REV

1

20
20
20

105
82 83 86

13

13

13

13

13

13

DATE

21 34

3.01

D

98

C

B

A

98105
7682
18

21

13

14

16

17

3438

83

86

D

C

B

14

16

1986

DESIGN NOTE:

A

ENG FEATURE: R22BC

16
16

16
16
16

CR-14 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE14

8

VCC3

IN

IN
IN

IN
IN
IN

V_1P25_CORE

V_1P25_CL_MCH

ETCH

R22BC

0OHM

VCCA_GPLL
VCCA_HPLL

TP_MCH_VCCA_HPLL

VCCA_MPLL
VCCA_DPLLA
VCCA_DPLLB

1

SM

2

V_1P25_HPL

AJ12
AJ11
AJ10

AJ9
AJ8
AJ7
AJ6
AJ5
AH4
AH2

AH1
AG14
AG13
AG12
AG11
AG10

AG9

AG8

AG7

AG6

AG5

AG4

AG3

AG2
AF14
AF13
AF12
AF11

AF3

AF2

AF1
AE25
AE23
AE21
AE19
AD24
AD22
AD20
AD14
AC25
AC23
AC21
AC19
AC14
AC13

AC6
AB24
AB22
AB20
AA25
AA23
AA21
AA19
AA14
AA13

AA3

Y24

Y22

Y20

Y14

Y13

W25

W23

W21

W19

V14

V13

V12

V10

U14

U13

U10

P20

Y11

Y32

B15

C23

V31

A24

A22

C22

B17

Y6

V9

U9
U6
U3

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCC
VCC_CL_PLL
VCCAPLL_EXP
VCCA_HPL
RSVD
VCCA_MPL
VCCA_DPL_A
VCCA_DPL_B

VCC3_3

8

7

6OF8

7

U1UB

BRLK_B

REV=1

POWER

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

AG24
AG23
AG22
AG21
AG20
AG19
AG18
AG17
AG15
AF26
AF25
AF24
AF22
AF20
AF18
AF17
AF15
AE27
AE26
AE17
AD27
AD26
AD18
AD15
AC26
AC15
AB26
AB17
AA26
AA15
Y26
Y17
W27
W18
V27
V25
V23
V21
V19
V17
U26
U24
U22
U20
U18
U15
R17
AD17
AC27
AC17
AB27
AB18
AA27
AA17
Y27
Y18
Y15
W26
W17
V26
V24
V22
V20
V18
V15
U25
U23
U21
U19
U17
R18
R15

R14
P15
P14
N12
N11
N9
N8
N6
N3
L6
J6
J3
J2
G2
F11
F9
D4
C13
C9

IC

6

6

V_1P25_CORE

89

173438

85

2425

27

81

8286

18

BOM NO TE:

DEFAULT (M22UB): 1 OHM 0402 5%
OPTION (M22UB): 600 OHM FB (A51464-006)

DESIGN NOTE:

EMPTY M22UB FOR NON-GRAPHIC SKU'S

V_3P3_DAC_FB

14

IN

16

DESIGN NOTE:

STUFF R92UB FOR NON-GRAPHIC SKU'S

BOM NO TE:

DEFAULT (M24UB): 1 OHM 0402 5%
OPTION (M24UB): 600 OHM FB (A51464-006)

V_3P3_DAC_FB

14

IN

16

ININ

7

IN

141819

IN

80
17

IN

16

IN

16

IN

13 14
38

V_SM

V_1P25_PCIEXPRESS

1

CH1402

1

CH

VCCD_CRT
VCCDQ_CRT

5

16 171821 34

76 82

83 86 98 105

V_FSB_VTT

M22UB

MULTI

R92UB

2

1

0

5%

EMPTY

402

M24UB

MULTI

402

1

2

2

V_3P3_VCCABG_EXP

V_3P3_DAC_FILTERED

45

BRLK_B

P29

VTT_FSB

P27

VTT_FSB

P26

VTT_FSB

P24

VTT_FSB

P23

VTT_FSB

N29

VTT_FSB

N26

VTT_FSB

N24

VTT_FSB

N23

VTT_FSB

M29

VTT_FSB

M24

VTT_FSB

M23

VTT_FSB

L24

VTT_FSB

L23

VTT_FSB

K24

VTT_FSB

K23

VTT_FSB

J24

VTT_FSB

J23

VTT_FSB

H24

VTT_FSB

H23

VTT_FSB

G26

VTT_FSB

G24

VTT_FSB

G23

VTT_FSB

F26

VTT_FSB

F24

VTT_FSB

F23

VTT_FSB

E29

VTT_FSB

E27

VTT_FSB

E26

VTT_FSB

E23

VTT_FSB

D29

VTT_FSB

D28

VTT_FSB

D27

VTT_FSB

C30

VTT_FSB

C29

VTT_FSB

C27

VTT_FSB

B30

VTT_FSB

B29

VTT_FSB

B28

VTT_FSB

B27

VTT_FSB

A30

VTT_FSB

A28

VTT_FSB

R27

VTT_FSB

R26

VTT_FSB

R24

VTT_FSB

R23

VTT_FSB

BC39

VCC_DDR

BC34

VCC_DDR

BC30

VCC_DDR

BC26

VCC_DDR

BC22

VCC_DDR

BC18

VCC_DDR

BC14

VCC_DDR

BB39

VCC_DDR

BB37
BB32
BB28
BB26
BB24
BB20
BB18
BB16
BB12
AY32
AW24
AW20
AV26
AV18

AC3
AC4
AD4
AD5
AD6
AD7
AD8

AD9
AD10
AD11

AC2

AD1

AD2

C17

B16

A16

C21

B21

D16

VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR

VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP

VCC_EXP
VCC_EXP
VCC_EXP

VCCA_DAC
VCCA_DAC
VCCA_EXP
VCCD_CRT
VCCDQ_CRT
VSS

POWER

VCC_CKDDR
VCC_CKDDR
VCC_CKDDR
VCC_CKDDR
VCC_CKDDR

Sun Mar 18 18:43:09 2007

4 2

3

VSS

AL26
AL24
AL23
AL21
AL20
AL18
AL17
AL15
AK30
AK29
AK27
AJ31
AJ30
AG31
AG30
AF31
AF30
AD32
AD30
AC32
AA32
AJ29
AJ27
AG29
AG27
AG26
AF29
AF27
AD29
AC30
AC29

AL12
AL11
AL10
AL9
AL8
AL7
AL6
AL5
AK26
AK24
AK23
AK21
AK20
AK18
AK17
AK15
AK3
AK2
AK1
AJ14
AJ13
AJ4
AJ3
AJ2
AD31
AC31
AA31
AA30
Y31
Y30
AJ26
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AJ15
AG25
AA29
Y29

V30
AL13

AK14
AL29

AL27
BB41

BA42
AY42
BB42
BA43

VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL

VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL

VCC_CL
VCC_CL

VCC_CL
VCC_CL

BPAGE DRAWING

frostburg_fabc.sch_1.14

3

V_1P25_CL_MCH

2

MODULE REV DETAILS

MODULE NAME

19
14

IN

16
86

CAD NOTE:

PLACE BACKSIDE RESISTOR R19BC CLOSE TO MCH BALL/PIN

R19BC

1

0

DESIGN NOTE:

1A

2

EMPTY

ENG FEATURE: 0 OHM RES R19BC (EMPTY)

603

1

C7BC

.1UF
10%
16V

2

EMPTY
603

CAD NOTE:

PLACE CAPS AND MULTI-SITE
CLOSE TO MCH BALLS FOR V_CKDDR

V_CKDDR

1

C3UB

.1UF
20%
25V

2

Y5V
603

BOM NO TE:

DEFAULT: MULTI SITE M1UB TO USE 721891-022 (1UH INDUCTOR)

DESIGN NOTE:

FOR CRB, TIE THIS PIN TO VSS
EV: CONNECT TO EVMC OR VREG ( TBD )

[PAGE_TITLE=MCH SECTIONS PAGE 5 OF 6]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

27

80

81

MCH_V_CKDDR_R

1

C2UB

22UF
20%

6.3V

2

X5R
805

DOCUMENT_NUMBER

402

402

R94UB

1

1

R95UB

1

1

xxxxxx

1

REV

V_SM

14

1819

2425

2

5%
CH

2

5%
CH

86

82

1

IN

M1UB

MULTI

SMIND

PAGE REV

14

1

DATE

D

C

B

2

A

3.01

CR-15 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE15

8

BC37
BC32
BC28
BC24

D

C

B

A

BC10

BC5
BB7

AY41

AY4
AW43
AW41
AV37
AV35
AV27
AV23
AV21
AV17
AV11

AV9

AV7

AV2
AU42
AU38
AU32
AU24
AU20

AU6

AU4
AT31
AT29
AT15
AT13
AT12
AR38
AR33
AR32
AR27
AR26
AR23
AR21
AR20
AR17

AR9

AR6
AP43
AP24
AP18

AP1
AN38
AN31
AN29
AN24
AN23
AN20
AN13
AN12
AN11

AN4
AM42
AM40
AM36
AM33
AM29
AM24
AM23
AM20
AM11

AM9

AM7

AM4
AL36
AL33
AL31
AK43
AJ39
AJ36
AJ33
AJ32
AH42
AG37
AG34
AF43
AF37
AF36
AF10

AF9

AF8

AF7

AF6

AF5

8

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

7

U1UB

BRLK_B

REV=1

7OF8

7

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AE24
AE22
AE20
AE4
AE3
AE2
AD42
AD39
AD37
AD35
AD33
AD25
AD23
AD21
AD19
AC38
AC35
AC24
AC22
AC20
AC10
AC7
AC5
AB43
AB25
AB23
AB21
AB19
AB2
AB1
AA38
AA35
AA24
AA22
AA20
AA8
AA5
Y42
Y37
Y35
Y33
Y25
Y23
Y21
Y19
Y10
Y7
Y5
Y1
W24
W22
W20
W3
V43
V39
V37
V34
V32
V11
V8
V5
V2
U38
U35
U8
U7
U5
T42
T1
R36
R33
R31
R11
R8
R5
R3
P43
P30
P21
P18
P17
P2
N36
N33
N31
N27
N21
N13
N10
N7

6

BRLK_B

M37
M35
M33
M27
M21
M20
M17
M15
M10

L40
L33
L32
L31
L29
L21
L20
L11

K43
K26
K21
K18
K13
K12

J38
J35
J32
J27
J21

H31
H29
H21
H20
H17
H15
H13
G42
G38
G32
G21
G13
G12
G11

F37
F35
F27
F21
F18
F15

E43
E32
E24
E21
E11

D40
D31
D21
D17
D15

C26
C11

B37
B32
B31
B26
B23
B22
B19
B14

N5

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

M7

VSS

M1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

L7

VSS

L5

VSS

L3

VSS
VSS
VSS
VSS
VSS
VSS
VSS

K2

VSS
VSS
VSS
VSS
VSS
VSS

J9

VSS

J7

VSS

J5

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

G9

VSS

G7

VSS

G1

VSS
VSS
VSS
VSS
VSS
VSS
VSS

F3

VSS
VSS
VSS
VSS
VSS
VSS

E9

VSS

E3

VSS
VSS
VSS
VSS
VSS
VSS

D3

VSS
VSS
VSS

C6

VSS

C5

VSS

C4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GND

B10
A39
A34
A26
A18
A12
A7
BC41
BC3
BA1
AY40
AF23
AF21
AF19
AE18
AC18
AA18
V29
U29
U27
R21
E1
C43
C1
A41
A5
A3

IC

6

5

45

U1UB

BRLK_B

REV=1

DDR3_DRAMRSTB

DDR3_DRAM_PWROK

DDR3_A_CSB1

DDR3_A_MA0
DDR3_A_WEB

DDR3_B_ODT3

DDR3

NC

8OF8

4 2

TEST0
TEST1
TEST2

BC16
AN15

AY37
BB29
BB34
AW32

BC43
BC1
A43

N20

NC

BC42

NC

BC2

NC

BB43

NC

BB2

NC

BB1

NC

B43

NC

B42

NC

B2

NC

IC

Sun Mar 18 18:43:10 2007

3

TP_DDR_DRAMRST

DRAM_PWROK_DDR3

DDR3_SCS_A_N1
DDR3_MAA_A0
DDR3_WE_A_N
DDR3_B_ODT_B3

DESIGN NOTE:

NO TESTPOINT NEEDED ON DDR2 SKEW

TP_CGC_NCTF_BC43
TP_CGC_NCTF_BC1
TP_CGC_NCTF_A43

[PAGE_TITLE=MCH SECTIONS PAGE 6 OF 6]

BPAGE DRAWING

frostburg_fabc.sch_1.15

3

2

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

1

MODULE REV DETAILS

MODULE NAME

1

2

DESIGN NOTE:

DDR2 BOARDS,STUFF R109UB= 0OHM

R109UB

0
5%

CH
402

REV

DOCUMENT_NUMBER

xxxxxx

1

DATE

PAGE REV

15

3.01

D

C

B

A

D

C

B

A

CR-16 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE16

8

R127PR

2

1A
CH

IV_3P3_DAC

R31UB

1

32.4K
1%

2

EMPTY
402

R30UB

1

102K
1%

2

EMPTY
402

BOM NO TE:

STUFF FOR FAB A VALIDATION

1

0

603

DESIGN NOTE:

24 OHM 805 1/8W
USE A93555-010

69

IN

H_VCCPLL

BOM NO TE:

DEFAULT (H_VCCPLL, R127PR): USE 0 OHM,
NON-GRAHPHIC SKU:EMPTY

1

VCC

R29UB

1

24
5%

2

EMPTY
805

2

Q1UB

MMBT3904
EMPTY

3

V_3P3_DAC_FILTERED_FB

7

VCC3

M19UB

1

MULTI

M18UB

1

1

C12UB

4.7UF
20%

10V

BOM NO TE:

2

EMPTY
805

DEFAULT (M18UB): FB 0603 (693286-015)
OPTION: STUFF FB 0603 (693286-015)

BOM NO TE:

DEFAULT (H_VCCPLL, M3UB): FB 0603 (693286-015)
OPTION (M3UB) TBD

M3UB

1

MULTI

FB

MULTI

2

EMPTY

2

VCCDQ_CRT_PN1

BOM NO TE:

DEFAULT (VCCDQ, M16UB) GRAPHIC SKU: MULTI SITE TO USE 1 UF (602433-052)
OPTION (VCCDQ, M16UB) NON-GRAPHIC SKU: MULTI SITE TO US E 0 OHM

M16UB

1

MULTI

603

6

BOM NO TE:

DEFAULT (M19UB)STUFF FB 0603 (693286-015)

2

FB

V_3P3_DAC_FB

1

C25UB

220UF

20.0%
25V
ELEC

2

RDL

213438

76

82838698105

DEFAULT (M23UB): 1 OHM 0402 5%

BOM NO TE:

OPTION (M23UB): 600 OHM FB (A51464-006)

M23UB

1

CH

DEFENSIVE OPTION (VCCDQ, M16UB): USE 600 OHM FB (A51464-006)

2

X5R

MULTI

1

2

VCCDQ_CRT

402

2

MODULE REV DETAILS

MODULE NAME

VCCA_HPLL

C16UB

1

2

603

X5R

10%

2.2UF

6.3V

VCCA_MPLL

VCCA_MPLL_R_PAIR

1

2

2

1

C20UB

10UF

20%

2

6.3V

2

X5R
805

C10UB

10UF

20%

6.3V
X5R
805

R96UB

1

1

402

R97UB

1

1

402

VCCA_GPLL

1

C17UB

.1UF
10%
16V

2

X7R
603

2

5%
CH

2

5%
CH

VCCA_DPLLA

1

C21UB

1

C23UB

220UF
20%

6.3V
ALUM

2

RDL

.1UF
10%
16V

2

X7R
603

VCCA_DPLLB

1

C19UB

1

C18UB

220UF
20%

6.3V
ALUM

2

RDL

.1UF
10%
16V

2

X7R
603

M6UB

M8UB

M9UB

3

M2UB

1

EMPTY

1

1

EMPTY

1

IND SM

2

VCCA_GPLL_PN1

2

2

SMIND

2

MULTI

SM

M10UB

2

MULTI

SMIND

M4UB

2

MULTI

SM

M11UB

2

MULTI

R37UB

1

1

5%
CH

402

R28UB

1

5%

1

CH

402

BOM NO TE:

C21UB, C19UB: 220 UF CAN BE EMPTY
IF USING RT9199 OR FOR NON-GRPHICS
SKUS W/SERIES RES

45

14

16

19

86

CAD NOTE:

14

16

19

86

14

OUT

1

C22UB

1.0UF
20%
10V

2

Y5V
603

V_1P25_CORE

131417

18

OUT

IN

14

CAD NOTE:

BOM NO TE:

DEFAULT (VCCA_GPLL, M6UB): USE 1 UH 721891-022
OPTION: MULTI SITE TO USE 0 OHM A93552-002
CHANGE TO OPTIONAL PART IF RT9199 I S ENABLED AND
SOURCING PWR.

BOM NO TE:

DEFAULT (VCCA_DPLLA, M8UB): USE 10 UH 721891-026
OPTION: MULTI SITE TO USE 0 OHM A93552-002
CHANGE TO OPTIONAL PART IF RT9199 I S ENABLED AND SOURCING PWR
CHANGE TO 0 OHM RESISTOR FO R NON-GRAPHICS SKU.

BOM NO TE:

DEFAULT (VCCA_DPLLB, M9UB): USE 10 UH 721891-026
OPTION: MULTI SITE TO USE 0 OHM A93552-002
CHANGE TO OPTIONAL PART IF RT9199 I S ENABLED AND SOURCING PWR
CHANGE TO 0 OHM RESISTOR FO R NON-GRAPHICS SKU.

V_1P25_CL_MCH

IN

PLACE MULTI-SITES M2UB AND
M10UB IN OVERLAP PATTERN

V_1P25_CL_MCH

IN

PLACE MULTI-SITES M4UB AND
M11UB IN OVERLAP PATTERN

1

IND SM

1

IND SM

1

MULTI

MULTI

MULTI

OUT

OUT

OUT

OUT

OUT

1

REV

DATE

D

14

14

C

14

14

B

14

A

VCCD_CRT

1

C4UB

4.7UF
10%

6.3V

2

X5R
603

8

7

M17UB

1

MULTI

603

BOM NO TE:

2

DEFAULT (VCCD, M17UB) GRAPHIC SKU: MULTI SITE TO USE 0.1UF (602433-056)

X7R

OPTION (VCCD, M17UB) NON-GRAPHIC SKU: MULTI SITE TO USE 0 OHM

6

5

OUT

14

BPAGE DRAWING

frostburg_fabc.sch_1.16

Sun Mar 18 18:43:11 2007

4 2

3

[PAGE_TITLE=PLL & CRT FILTERS]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

16

1

3.01

CR-17 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE17

8

7

89

1417

85

3438

D

3438

V_FSB_VTT

7

89

IN

14

17

85

C

B

7

891417

IN

85

3438

FSB COMP SIGNAL

TERMINATION

A

PCIE COMP SIGNAL TERMINATION

14

18

IN

7

V_FSB_VTT

IN

CAD NOTE:

CAP (C30UB) ON GTLREF SHOULD BE CLOSE TO MCH PIN
USE 10MIL TRACE, ISOLATE W/7MIL SPACE AFTER 250 MIL BREAKOUT

CAD NOTE:

HX_SWING VOLTAGE 10MIL TRACE, 10 MIL SPACE AFTER 250 MIL BREAKOUT.

1

PLACE DIVIDER RESISTORS NEAR VTT.

R49UB

301
1%

CH
402

2

HXSWING_DIVIDER

1

1

R48UB

100
1%

CH

2

402

2

CAD NOTE:

USE 4MIL TRACE, ISOLATE W/14MIL SPACE AFTER 300 MIL BREAKOUT

V_FSB_VTT

CAD NOTE:

49.9
402

49.9
402

C31UB

0.1UF
20%
16V
Y5V
402

R39UB

1

1

R46UB

R88UB

2

49.9
402

2

1%
CH

2

1%
CH

USE 5MIL TRACE, ISOLATE W/5MIL SPACE; IF >250MILS INCREASE TO 10/7

V_1P25_PCIEXPRESS

24.9

R53UB

1

402

1

R45UB

100
1%

CH
402

2

MCH_GTLREF0_DIVIDER

1

1

C32UB

R47UB

1%

CH

DESIGN NOTE:

1.0UF

200

20%

1%

10V

2

Y5V

CH

603

402

2

1

HXSWING

OUT

HX_SWING S/B 1/4*VTT +/- 2%

HXSCOMPB

2

1

C29UB

2.7PF

9.25%
25V
EMPTY
402

16.5
402

1%

CH

R50UB

1

2

1

2

2

HXRCOMP

1%

CH

GRCOMP

HXSCOMP

C26UB

2.7PF

9.25%
25V
EMPTY
402

OUT

OUT

OUT

OUT

6

R38UB

1

2

CPU_MCH_GTLREF

5%

0

EMPTY

402

R41UB

1

2

5%

51

CH

402

DESIGN NOTE:

MCH_GTLREF VOLTAGE SHOULD BE 0.67 * VTT = 0.8V
100 OHMS OVER 200 OHMS (072905)

10

10

10

10

10

C146UB

C30UB

220PF

EMPTY

6.3V

EMPTY

10%
50V

402

1

1UF
20%

DESIGN NOTE:

2

STUFF FOR CPU LEGACY

402

MCH_GTLREF

1

2

OUT

45

6

IN

10

DACREFSET & RGB MCH-SIDE TERMINATION

13

20

20

20

BOM NO TE:

VGA_DACREFSET

OUT

VGA_RED

1319

IN

VGA_GREEN

1319

IN

VGA_BLUE

1319

IN

CAD NOTE:

PLACE VGA RGB RESISTORS CLOSE
TO MCH: <250 MILS TO MCH BALLS

BOM NO TE:

VGA RGB RESISTORS (R54UB-R56UB): REPLACE 150 OHM WITH
0 OHM (A93549-001) FOR NON-GRAPHICS SKUS

STUFF R93UB FOR NON-GRAPHICS SKUS

BOM NO TE:

3

R56UB

R55UB

1

1

150

150

1%

1%

CH

2

CH

2

402

402

13

141618

213438

76

82838698

105

13

29

13

29

STUFF R98UB FOR NON-GRAPHICS SKUS

CAD NOTE:

HSYNC/VSYNC; LOCATE SERIES RESISTOR STRAPS (R52UB, R51UB) WITHIN 750 MILS OF MCH

BOM NO TE:

UN-STUFF 39 OHM SERIES RES (R52UB, R51UB) FOR NON-GRAPHICS SKUS

13

IN

13

IN

BOM NO TE:

HSYNC/VSYNC SLEW RATE & EMI CONTROL

VGA_VSYNC

VGA_HSYNC

39

402

39

402

R52UB

1

R51UB

1

2

5%
CH

2

5%
CH

2

R54UB

1

150
1%

CH

2

402

V_1P25_CORE

IN

CK_96M_DREF_DP

IN

CK_96M_DREF_DN

IN

M25UB

1

MULTI

EMPTY

402

MODULE REV DETAILS

MODULE NAME

CAD NOTE:

PLACE DACREFSET RES (R44UB) CLOSE
TO MCH: <500 MILS TO MCH BALL

R44UB

1

1.3K
1%

CH

2

402

BOM NO TE:

DACREFSET RESISTOR (R44UB): REPLACE 1.3K
WITH 0 OHM FOR NON-GRAPHICS SKUS

1

2

1

2

VGA_VSYNC_3V

VGA_HSYNC_3V

M26UB

1

2

402

MULTI

2

EMPTY

R93UB

10K
5%

EMPTY
402

R98UB

0
5%

EMPTY
402

1

REV

DATE

D

C

20

OUT

OUT

20

B

STUFF 0 OHM RES (M25UB, M26UB) FOR NON-GRAPHICS SKUS

DESIGN NOTE:

MULTI-SITES TO BE USED FOR SLEW RATE/EMI CAPS ON GRAPHIC SKUS

CAD NOTE:

DDC_DATA/DDC_CLK; LOCATE PULL-UPS
ANYWHERE ON ROUTE OF TRACE

BOM NO TE:

DDC MCH SIDE
TERMINATION

STUFF R42UB, R43UB FOR GRAPHICS/NON-GRAPHICS SKUS

VGA_MCH_DDCSDA

1320

IN

VGA_MCH_DDCSCL

1320

IN

VCC3 VCC3

1

2

R42UB

2.2K
5%

CH
402

1

2

R43UB

2.2K
5%

CH
402

A

BPAGE DRAWING

frostburg_fabc.sch_1.17

Sun Mar 18 18:43:12 2007

8

7

6

5

4 2

[PAGE_TITLE=MCH DECOUPLING AND COMP]

INTEL

CONFIDENTIAL

3

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

1

PAGE REV

17

3.01

CR-18 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE18

8

7

6

45

3

PCI EXPRESS DECOUPLING

V_SM

1419

2425

27

D

IN

80

81

8286

2

1

MCH MEMORY DECOUPLING

CAD NOTE:

SERIES RESISTOR ON SIGNAL MCH_DDR_RCOMPYPU
PLACE 2.2UF CAP (C64UB) ON V_SM CLOSE TO 20 OHM

C68UB

2.2UF
10%

6.3V
X5R
603

V_1P25_CORE

I163

IN

V_1P25_PCIEXPRESS

1

C70UB

10UF
20%

6.3V

2

X5R
805

OUT

1

C72UB

10UF
20%

6.3V

2

X5R
805

2

1

C61UB

2.2UF
10%

6.3V

X5R
603

C67UB

2.2UF
10%

6.3V

1

1

X5R
603

C66UB

2.2UF
10%

6.3V
X5R
603

C65UB

2.2UF
10%

6.3V

1

X5R
603

2

C64UB

2.2UF
10%

6.3V

1

X5R
603

2

2

2

2

MODULE REV DETAILS

MODULE NAME

14

17

1

REV

DATE

D

PCI-E SIGNAL TRANSITION STICHING CAPS

C

98105

3438

76

131416
171821
828386

IN

V_1P25_CORE

1

1

C36UB

0.1UF
20%
16V

2

2

Y5V
402

C37UB

0.1UF
20%

16V
Y5V
402

1

2

C135UB

0.1UF
20%
16V
Y5V
402

1

2

C136UB

0.1UF
20%

16V
Y5V
402

B

A

VCC_HVGIO DECOUPLING

VCC3

1

2

C62UB

.1UF
20%
25V
Y5V
603

VCC3

1

2

C35UB

4.7UF
20%
10V
Y5V
805

C

B

A

BPAGE DRAWING

frostburg_fabc.sch_1.18

Sun Mar 18 18:43:13 2007

8

7

6

5

4 2

3

[PAGE_TITLE=MCH DCPL & VGA TERMINATION]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

18

1

3.01

CR-19 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE19

8

25

27
24

81

D

CAD NOTE:

PLACE RESISTORS CLOSE TO MCH
ON MCH_VREF

V_SM

1418

IN

19
80

1

8286

C141UB

.1UF
10%
10V

2

EMPTY
402

R75UB

1

19.1
4021%CH

2

MODULE REV DETAILS

MODULE NAME

MCH_DDR_RCOMPYPD

2

7

R72UB

1

1

2

1K

1%

402

CH

R71UB

2

1%

1K

CH

402

CAD NOTE:

PLACE 0.1UF CAP CLOSE TO MCH

1

2

C76UB

0.1UF
20%
16V
Y5V
402

MCH_VREF

6

12

OUT

45

3

1

REV

DATE

D

12

OUT

25

27
24

81

V_SM

1418

IN

19
80

1

8286

2

CAD NOTE:

C

PLACE RESISTORS CLOSE TO CH_B DIMMS
ON DIMM_VREF_B

8286
25

27
24

81

V_SM

1418

IN

19
80

1

2

CAD NOTE:

B

PLACE RESISTORS CLOSE TO CH_A DIMMS

ON DIMM_VREF_A

V_1P25_CL_MCH

1416

86

IN

C60MY

.1UF
10%
10V
EMPTY
402

C59MY

.1UF
10%
10V
EMPTY
402

1

1K 1%

402

1

1K

4021%CH

1

1K

402

1

1K

402

A

R69MY

R70MY

R67MY

R68MY

R57UB

R58UB

2

CH

2

2

1%
CH

2

1%
CH

1

DESIGN NOTE:

1K
1%

CL VREF TARGET: 0.349V

CH

2

402

CL_N_VREF_MCH

1

392

1%

CH

402

2

CAD NOTE:

PLACE 0.1UF CAP ON DIMM_VREF_B
CLOSE TO DIMM PIN

DIMM_VREF_B

1

C58MY

.1UF
20%
25V

2

Y5V
603

CAD NOTE:

PLACE 0.1UF CAP ON DIMM_VREF_A
CLOSE TO DIMM PIN

DIMM_VREF_A

1

C52MY

.1UF
20%
25V

2

Y5V
603

13

1

C73UB

0.1UF
20%
16V

2

Y5V
402

OUT

OUT

1317
20

1317
20

1317
20

25

24

IN
IN
IN

VGA_RED
VGA_GREEN
VGA_BLUE

VCC3

1

C80UB
.1UF
20%
25V
Y5V
603

2

CR3UB
GP

3

SOT23S SOT23S SOT23S

EMPTY

2

1

CR4UB
GP

3

EMPTY

2

1

19

2425

278081

8286

81

8286

81

8286

RGB ESD PROTECTION

CR5UB
GP

3

EMPTY

2

1

DESIGN NOTE:

MAX 0.5 PF

BOM NO TE:

STUFF FOR CRB

R70UB

R73UB

1

19.1
402

2

MCH_DDR_RCOMPYPU

1%

CH

402

MCH_DDR_RCOMPXPD

2

1%

CH

R74UB

1

19.1

2

1%

CH

402

CAD NOTE:

PLACE CAPS CLOSE
TO RCOMPXPU
AND VOH/VOL RESISTORS

1

R60UB

1K
1%

CH
402

2

MCH_DDR_RCOMPVOH

1

R61UB

3.01K
1%

CH
402

2

MCH_DDR_RCOMPVOL

1

R62UB

1K
1%

CH
402

2

MCH_DDR_RCOMPXPU

DESIGN NOTE:

DDR_RCOMPVOH: 0.8 * VSM

1

C133UB

.01UF
10%

25V

2

X7R
402

DESIGN NOTE:

DDR_RCOMPVOL: 0.2 * VSM

1

C134UB

.01UF
10%

25V

2

X7R
402

OUT

OUT

OUTOUT

OUT

OUT

12

C

12

12

B

12

A

12

.1UF

V_SM

C77UB
.1UF
20%
25V
Y5V
603

V_SM

1

2

1

19.1

C132UB

.01UF
10%
25V
EMPTY
402

1418

V_SM

IN

24252780

1

C145UB
20%

25V

2

Y5V
603

141819

IN

1

2

141819

24252780

IN

BPAGE DRAWING

frostburg_fabc.sch_1.19

Sun Mar 18 18:43:14 2007

8

7

6

5

4 2

3

[PAGE_TITLE=MCH VREFS & TERMINATION]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

19

1

3.01

BW_ATX_CORE

CR-20 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE20

8

BOM NO TE:

VGA_RED

131719

IN

13

IN

131719

IN

VGA_HSYNC_3V
VGA_VSYNC_3V

VGA_GREEN
VGA_BLUE

17

19

D

17

IN

17

IN

CHANGE FOR BANDWIDTH OPTIMIZE FOR CRB

C

693286-006

FB3UB

1

1

C89UB

10PF
5%
50V

2

COG
402

7

M13UB

1

MULTI

FB

VGA_BLUE_FB1

2

FB

BOM NO TE:

DEFAULT: STUFF 10PF <A36094-025> FOR

1

2

BOM NO TE:

C90UB

22PF

DEFAULT: STUFF 22PF <A36095-030> FOR

5%
50V
COG
402

2

REPLACE WITH 3.3PF

FOR BANDWITH >200MHZREPLACE WITH 3.3PF

6

BOM NO TE:

DEFAULT: STUFF FERRITE BEAD <693286-006> FOR <200MHZ BANDWIDTH CUTOFF
REPLACE WITH 0OHM 603 FOR >200MHZ BANDWIDTH CUTOFF

M14UB

BANDWIDTH <200MHZ

FOR BANDWITH >200MHZ

693286-006

1

1

C93UB

10PF
5%
50V

2

COG
402

BANDWIDTH <200MHZ

FB4UB

1

VGA_GREEN_FB1

2

FB

1

C81UB

22PF
5%
50V

2

COG
402

MULTI

2

FB

45

693286-006

FB5UB

1

FB

1

C85UB

10PF
5%
50V

2

COG
402

3

M15UB

1

VGA_RED_FB1

2

1

C84UB

22PF
5%
50V

2

COG
402

MULTI

2

FB

VCC

2

C92281-003

RT1UB

1

THRMSTR

1.10

VGA_THERM_9
VGA_GREEN_CONN

VGA_BLUE_CONN

MODULE REV DETAILS

MODULE NAME

M12UB

VGA_THERM_PN1

2

1

MULTI

CH

J4UB

VGA_RED_CONN

TP_VGACONN_11_CORE_R
TP_VGACONN_4_CORE

1

C87UB

100PF
5%
50V

2

EMPTY
402

1
9
2

10

3

11
4

12
5

13
6

14
7

15
8

1

C88UB

100PF
5%
50V

2

EMPTY
402

1

REV

DATE

5-5-061.06.00BW_ATX_CORE

2

1

C94UB

805

.1UF

D

20%
25V

2

Y5V
603

16

RCPT

17

C

1

C92UB

BOM NO TE:

10PF
5%

DEFAULT: STUFF 10PF <A36094-025> FOR

50V

2

COG
402

EMPTY

FOR BANDWITH >200MHZ

BANDWIDTH <200MHZ

A36094-025

B

1

R84UB

150

CAD NOTE:

1%

CH

PLACE RESISTORS CLOSE

402

2

(CAPS / FERRITE-BEADS)

TO FILTERS

VCC3

R112UB

VGA_MCH_DDCSDA_R

2

VGA_MCH_DDCSDA

13

17

A

70

BI

70

BI

8

BI

VGA_MCHSIO_DDCSDA

BI

VGA_MCH_DDCSCL

13

17

VGA_MCHSIO_DDCSCL

R114UB

0

402

7

1

R115UB

1

0

402

5%
CH

1

5%

0

EMPTY

402

VCC3

2

R113UB

2

1

VGA_MCH_DDCSCL_R

0

5%

EMPTY

402

2

5%
CH

BOM NO TE:

UN-STUFF ALL COMPONENTS ON PAGE FOR NON-GRAPHICS SKUS

6

1

R85UB

150
1%

CH
402

2

VGA_DDCSDA_5V_R

Q2UB

BOM NO TE:

EMPTY

REPLACE 603400-001 WITH
C79254-001 (PB FREE #)

VGA_DDCSCL_5V_R

Q3UB

EMPTY

BOM NO TE:

REPLACE 603400-001 WITH
C79254-001 (PB FREE #)

5

R110UB

1

0

402

R111UB

402

1

2

5%

EMPTY

EMPTY

2

1

R13BU

0

1A

EMPTY
603

1

R80UB

2.2K
5%

CH
402

2

VGA_DDC_5V_R

BI

BI

3

1

2

BAT54C
SOT23C

70

C83UB
10PF
5%
50V
COG
402

1

2

70

"COG""COG"

CR7UB

1

R82UB

2.2K
5%

CH
402

2

2

0

402

0

402

2

3

R83UB

R81UB

VCC

VCC3

DIO

1

2

1

5%
CH

1

5%
CH

6.2V

1346

EMPTY

CUSTOM TEXT BPAGE

1

EMPTY

CR2UB

GPGP

3

SOT23SSOT23S

2

C144UB

.1UF
10%
10V
EMPTY
402

3

1

EMPTY

CR1UB

2

VGA_DDCSDA_CONN

VGA_DDCSCL_CONN

1

C86UB

100PF
5%
50V

CR6UB

TP_TVS6_2V_PIN6

TP_TVS6_2V_PIN4

TVS6_2V

2

EMPTY
402

25

[PAGE_TITLE=VGA CONNECTOR]

INTEL

CONFIDENTIAL

DOCUMENT_NUMBER

xxxxxx

1

1

C91UB

100PF
5%
50V

2

EMPTY
402

PAGE REV

20

3.01

B

A

C82UB
10PF
5%
50V
COG
402

"COG"

1

R86UB

150
1%

CH
402

2

2

201

5%

VGA_DDCSDA_5V

R116UB

2

1

100 5%

CH

402

R117UB

2

1

100 5%

CH

402

VGA_DDCSCL_5V

VGA_SIO_DDCSDA_5V

VGA_SIO_DDCSCL_5V

BPAGE DRAWING

frostburg_fabc.sch_1.20

Sun Mar 18 18:43:15 2007

4 2

BW_ATX_CORE

CR-21 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE21

8

SLOT 1

PCI EXPRESS
16-PORT

D

RIGHT LATCH

(DEFAULT)

BOM NO TE:

STUFF J6UB
EMPTY J10UB

102

C

B

C73571-001

A

PCI RETENTION MODEL

PCIE_RM

1

GND

2

GND

1.0

E

8

70

70101

8586

87

88

47

4849

102

101

9092

J5UB

EMPTY

7

4849

4849

708284

32333436373839

47

98

101

BI

102103105

101
27

283347

22

BI

102103105

103105
53596469
9212228

IN

22

3336

OUT

2223

IN

2223

IN

10

22

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

10

22

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

13

22

OUT

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

22

27

283347

SMB_CLK_RESUME

SMB_DATA_RESUME

V_3P3_STBY\G

WAKE_N

EXP_A_TX_0_C_DP
EXP_A_TX_0_C_DN

SDVO_CTRL_CLK

EXP_A_TX_1_C_DP
EXP_A_TX_1_C_DN

EXP_A_TX_2_C_DP
EXP_A_TX_2_C_DN

EXP_A_TX_3_C_DP
EXP_A_TX_3_C_DN

SDVO_CTRL_DATA

EXP_A_TX_4_C_DP
EXP_A_TX_4_C_DN

EXP_A_TX_5_C_DP
EXP_A_TX_5_C_DN

EXP_A_TX_6_C_DP
EXP_A_TX_6_C_DN

EXP_A_TX_7_C_DP
EXP_A_TX_7_C_DN

EXP_PRSNT_N

EXP_A_TX_8_C_DP
EXP_A_TX_8_C_DN

EXP_A_TX_9_C_DP
EXP_A_TX_9_C_DN

EXP_A_TX_10_C_DP
EXP_A_TX_10_C_DN

EXP_A_TX_11_C_DP
EXP_A_TX_11_C_DN

EXP_A_TX_12_C_DP

EXP_A_TX_12_C_DN

EXP_A_TX_13_C_DP
EXP_A_TX_13_C_DN

EXP_A_TX_14_C_DP
EXP_A_TX_14_C_DN

EXP_A_TX_15_C_DP

EXP_A_TX_15_C_DN

7

22

22

22
22

6

VCC3 +12V +12V VCC3

B1
B2
B3
B4
B5
B6
B7

TP_3G16_JTAG1

TP_3G16_RSVD_B12

TP_3G16_RSVD_B80
TP_16PRSNT_B82

B10
B11

B12
B13
B14
B15
B16
B17
B18

B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32

B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49

B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82

B8
B9

6

12V
12V

12V
GND
SMCLK
SMDAT
GND

3.3V

JTAG1

3.3VAUX

WAKE*

RSVD
GND

HSOP0

HSON0
GND
PRSNT2*
GND

HSOP1

HSON1
GND
GND

HSOP2

HSON2
GND
GND

HSOP3

HSON3
GND
RSVD
PRSNT2*
GND

HSOP4

HSON4
GND
GND

HSOP5

HSON5
GND
GND

HSOP6

HSON6
GND
GND

HSOP7

HSON7
GND
PRSNT2*
GND

HSOP8

HSON8
GND
GND

HSOP9

HSON9
GND
GND

HSOP10

HSON10
GND
GND

HSOP11

HSON11
GND
GND

HSOP12

HSON12
GND
GND

HSOP13

HSON13
GND
GND

HSOP14

HSON14
GND
GND

HSOP15

HSON15
GND
PRSNT2*
RSVD

5

J6UB

3GIO_X16

REV=2.0

KEY

1OF1

PRSNT1*

JTAG2
JTAG3
JTAG4
JTAG5

3.3V

3.3V

PWRGD

REFCLK+
REFCLK-

HSIP0
HSIN0

RSVD

HSIP1
HSIN1

HSIP2
HSIN2

HSIP3
HSIN3

RSVD

RSVD

HSIP4
HSIN4

HSIP5
HSIN5

HSIP6
HSIN6

HSIP7
HSIN7

RSVD

HSIP8
HSIN8

HSIP9
HSIN9

HSIP10
HSIN10

HSIP11
HSIN11

HSIP12
HSIN12

HSIP13
HSIN13

HSIP14
HSIN14

HSIP15
HSIN15

12V
12V
GND

GND

GND

GND

GND

GND
GND

GND
GND

GND

GND

GND
GND

GND
GND

GND
GND

GND

GND

GND
GND

GND
GND

GND
GND

GND
GND

GND
GND

GND
GND

GND
GND

GND

CONN

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

A12
A13
A14
A15
A16
A17
A18

A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32

A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49

A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82

45

TP_3G16_JTAG2
TP_3G16_JTAG3
TP_3G16_JTAG4
TP_3G16_JTAG5

PLTRST_PCIE_SLOTS_N

CK_PE_100M_16PORT_DP

CK_PE_100M_16PORT_DN

EXP_A_RX_0_DP
EXP_A_RX_0_DN

TP_3G16RSVD_A19

EXP_A_RX_1_DP
EXP_A_RX_1_DN

EXP_A_RX_2_DP
EXP_A_RX_2_DN

EXP_A_RX_3_DP
EXP_A_RX_3_DN

TP_3G16_RSVD_A32

TP_3G16_RSVD_A33

EXP_A_RX_4_DP
EXP_A_RX_4_DN

EXP_A_RX_5_DP
EXP_A_RX_5_DN

EXP_A_RX_6_DP
EXP_A_RX_6_DN

EXP_A_RX_7_DP
EXP_A_RX_7_DN

TP_3G16_RSVD_A50

EXP_A_RX_8_DP
EXP_A_RX_8_DN

EXP_A_RX_9_DP
EXP_A_RX_9_DN

EXP_A_RX_10_DP
EXP_A_RX_10_DN

EXP_A_RX_11_DP
EXP_A_RX_11_DN

EXP_A_RX_12_DP
EXP_A_RX_12_DN

EXP_A_RX_13_DP
EXP_A_RX_13_DN

EXP_A_RX_14_DP
EXP_A_RX_14_DN

EXP_A_RX_15_DP
EXP_A_RX_15_DN

22
22
22
22

22

22

22

22

Sun Mar 18 18:43:16 2007

4 2

3

22

47 70 101

IN

22 29

IN

22 29

IN

10

22

OUT

10

22

OUT

47

48

49

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

BPAGE DRAWING

frostburg_fabc.sch_1.21

3

102

82848586878890

2

MODULE REV DETAILS

MODULE NAME

BW_ATX_CORE 5-5-061.06.00

1

REV

VCC3

C98UB

2

1

20%

.1UF

25V

EMPTY

603

+12V

C97UB

2

1

.1UF 20%

25V
Y5V

V_3P3_STBY\G

IN

1

.1UF

2

16V

13

IN

83

2

C46BU

0.1UF
20%

16V

1

Y5V
402

2

C51BU

0.1UF
20%
16V

1

Y5V
402

DOCUMENT_NUMBER

603

C96UB

2

20%
25V
Y5V
603

VCC3+12V

C95UB

100UF

1

20.0%

14 161718
86 98 105

2

C47BU

0.1UF
20%
16V

1

Y5V
402

xxxxxx

2

25V

ELEC

RDL

DESIGN NOTE:

ATX FF ONLY

34 387682

2

C48BU

0.1UF
20%

16V

1

EMPTY
402

1

92

101

102103105

32333436373839

70

CAD NOTE:

PLACE NEAR EDGE OF PEG SLOT
FOR SIGNAL TRANSITION REF

9212228

53

596469

DESIGN NOTE:

ALWAYS STUFF C99UB & C95UB
EVEN IF J6UB IS EMPTY
FOR X1 DECOUPLING

C99UB

470.0UF

1

20%

ALUM

RDL

V_1P25_CORE

2

2

C44BU

C45BU

0.1UF

0.1UF

20%

20%

16V
Y5V
402

C49BU

0.1UF
20%
16V
Y5V
402

16V

1

EMPTY
402

2

C50BU

0.1UF
20%

16V

1

EMPTY
402

1

2

1

[PAGE_TITLE=PCI EXPRESS X16]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DATE

PAGE REV

21

3.01

D

C

B

A

BW_ATX_CORE

CR-22 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE22

8

SLOT 1

PCI EXPRESS
16-PORT

D

LEFT LATCH

BOM NO TE:

STUFF J6UB
EMPTY J10UB

59

64

C

B

A

8

70101

70101

102103

87

889092

101

47

484953

102

102103105

7

4849

4849

32333436373839

47

98

101

BI

102103105

21

27

283347

BI

105

69

70

82848586

92128

IN

213336

OUT

21

23

IN

21

23

IN

10

21

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

23

21

IN

21

23

IN

10

21

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

23

21

IN

13

21

OUT

21

23

IN

21

23

IN

23

21

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

23

21

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

21

27

283347

SMB_CLK_RESUME

V_3P3_STBY\G

WAKE_N

EXP_A_TX_0_C_DP
EXP_A_TX_0_C_DN

SDVO_CTRL_CLK

EXP_A_TX_1_C_DP
EXP_A_TX_1_C_DN

EXP_A_TX_2_C_DP
EXP_A_TX_2_C_DN

EXP_A_TX_3_C_DP
EXP_A_TX_3_C_DN

SDVO_CTRL_DATA

EXP_A_TX_4_C_DP
EXP_A_TX_4_C_DN

EXP_A_TX_5_C_DP
EXP_A_TX_5_C_DN

EXP_A_TX_6_C_DP
EXP_A_TX_6_C_DN

EXP_A_TX_7_C_DP
EXP_A_TX_7_C_DN

EXP_PRSNT_N

EXP_A_TX_8_C_DP
EXP_A_TX_8_C_DN

EXP_A_TX_9_C_DP
EXP_A_TX_9_C_DN

EXP_A_TX_10_C_DP
EXP_A_TX_10_C_DN

EXP_A_TX_11_C_DP
EXP_A_TX_11_C_DN

EXP_A_TX_12_C_DP

EXP_A_TX_12_C_DN

EXP_A_TX_13_C_DP
EXP_A_TX_13_C_DN

EXP_A_TX_14_C_DP
EXP_A_TX_14_C_DN

EXP_A_TX_15_C_DP

EXP_A_TX_15_C_DN

7

21

21

21
21

6

VCC3 +12V +12V VCC3

B1
B2
B3
B4
B5
B6
B7

TP_3G16_JTAG1

B8
B9

B11

TP_3G16_RSVD_B12

TP_3G16_RSVD_B80
TP_16PRSNT_B82

B12
B13
B14
B15
B16
B17
B18

B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32

B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49

B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82

6

12V
12V

12V
GND
SMCLK
SMDAT
GND

3.3V

JTAG1

3.3VAUX

WAKE*

RSVD
GND

HSOP0

HSON0
GND
PRSNT2*
GND

HSOP1

HSON1
GND
GND

HSOP2

HSON2
GND
GND

HSOP3

HSON3
GND
RSVD
PRSNT2*
GND

HSOP4

HSON4
GND
GND

HSOP5

HSON5
GND
GND

HSOP6

HSON6
GND
GND

HSOP7

HSON7
GND
PRSNT2*
GND

HSOP8

HSON8
GND
GND

HSOP9

HSON9
GND
GND

HSOP10

HSON10
GND
GND

HSOP11

HSON11
GND
GND

HSOP12

HSON12
GND
GND

HSOP13

HSON13
GND
GND

HSOP14

HSON14
GND
GND

HSOP15

HSON15
GND
PRSNT2*
RSVD

5

J10UB

3GIO_X16

REV=2.0

KEY

1OF1

PRSNT1*

JTAG2
JTAG3
JTAG4
JTAG5

3.3V

3.3V

PWRGD

REFCLK+
REFCLK-

HSIP0
HSIN0

RSVD

HSIP1
HSIN1

HSIP2
HSIN2

HSIP3
HSIN3

RSVD

RSVD

HSIP4
HSIN4

HSIP5
HSIN5

HSIP6
HSIN6

HSIP7
HSIN7

RSVD

HSIP8
HSIN8

HSIP9
HSIN9

HSIP10
HSIN10

HSIP11
HSIN11

HSIP12
HSIN12

HSIP13
HSIN13

HSIP14
HSIN14

HSIP15
HSIN15

12V
12V
GND

GND

GND

GND

GND

GND
GND

GND
GND

GND

GND

GND
GND

GND
GND

GND
GND

GND

GND

GND
GND

GND
GND

GND
GND

GND
GND

GND
GND

GND
GND

GND
GND

GND

EMPTY

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10B10
A11

A12
A13
A14
A15
A16
A17
A18

A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32

A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49

A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82

45

TP_3G16_JTAG2
TP_3G16_JTAG3SMB_DATA_RESUME
TP_3G16_JTAG4
TP_3G16_JTAG5

PLTRST_PCIE_SLOTS_N

CK_PE_100M_16PORT_DP

CK_PE_100M_16PORT_DN

EXP_A_RX_0_DP
EXP_A_RX_0_DN

TP_3G16RSVD_A19

EXP_A_RX_1_DP
EXP_A_RX_1_DN

EXP_A_RX_2_DP
EXP_A_RX_2_DN

EXP_A_RX_3_DP
EXP_A_RX_3_DN

TP_3G16_RSVD_A32

TP_3G16_RSVD_A33

EXP_A_RX_4_DP
EXP_A_RX_4_DN

EXP_A_RX_5_DP
EXP_A_RX_5_DN

EXP_A_RX_6_DP
EXP_A_RX_6_DN

EXP_A_RX_7_DP
EXP_A_RX_7_DN

TP_3G16_RSVD_A50

EXP_A_RX_8_DP
EXP_A_RX_8_DN

EXP_A_RX_9_DP
EXP_A_RX_9_DN

EXP_A_RX_10_DP
EXP_A_RX_10_DN

EXP_A_RX_11_DP
EXP_A_RX_11_DN

EXP_A_RX_12_DP
EXP_A_RX_12_DN

EXP_A_RX_13_DP
EXP_A_RX_13_DN

EXP_A_RX_14_DP
EXP_A_RX_14_DN

EXP_A_RX_15_DP
EXP_A_RX_15_DN

21
21
21
21

21

21

21

21

Sun Mar 18 18:43:17 2007

4 2

3

47 70 101

21

IN

21

29

IN

21

29

IN

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

BPAGE DRAWING

frostburg_fabc.sch_1.22

3

102

DESIGN NOTE:

PCIE X16 GRAPHIC CONNECTOR WITH LEFT LATCH

2

MODULE REV DETAILS

MODULE NAME

BW_ATX_CORE 5-5-061.06.00

[PAGE_TITLE=PCI EXPRESS X16]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

1

REV

1

DATE

PAGE REV

22

3.01

D

C

B

A

BW_ATX_CORE

CR-23 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE23

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

5-5-061.06.00BW_ATX_CORE

D

10

IN

10

IN

EXP_A_TX_0_DN
EXP_A_TX_0_DP

C103UB

1

.1UF

C102UB

2

1

.1UF

2

10%

10V
X5R
402

BOM NO TE:

10%

10V
X5R
402

EXP_A_TX_0_C_DN
EXP_A_TX_0_C_DP

OUT
OUT

21

22

21

22

D

STUFF ALL THE CAPS
EVEN UNSTUFF THE PCIEX16

C101UB

1

10

IN

10

IN

10

IN

10

IN

10

IN

10

C

IN

10

IN
IN

10

IN

10

IN

10

IN

10

IN

10

IN

10

IN

EXP_A_TX_1_DN
EXP_A_TX_1_DP

EXP_A_TX_2_DN
EXP_A_TX_2_DP

EXP_A_TX_3_DN
EXP_A_TX_3_DP

EXP_A_TX_4_DN
EXP_A_TX_4_DP

EXP_A_TX_5_DN
EXP_A_TX_5_DP

EXP_A_TX_6_DN
EXP_A_TX_6_DP

EXP_A_TX_7_DN
EXP_A_TX_7_DP

B

10

IN

10

IN

10

IN

10

IN

10

IN

10

IN

10

IN

10

IN

10

IN

10

IN

10

IN

10

A

IN

10

IN

10

IN

10

IN

10

IN

EXP_A_TX_8_DN
EXP_A_TX_8_DP

EXP_A_TX_9_DN
EXP_A_TX_9_DP

EXP_A_TX_10_DN
EXP_A_TX_10_DP

EXP_A_TX_11_DN
EXP_A_TX_11_DP

EXP_A_TX_12_DN
EXP_A_TX_12_DP

EXP_A_TX_13_DN
EXP_A_TX_13_DP

EXP_A_TX_14_DN
EXP_A_TX_14_DP

EXP_A_TX_15_DN
EXP_A_TX_15_DP

.1UF

C107UB

1

.1UF

C116UB

1

.1UF

C112UB

1

.1UF

C122UB

1

.1UF

C118UB

1

.1UF

C128UB

1

.1UF

C124UB

1

.1UF

2

C100UB

1

.1UF

X5R
402

C106UB

1

.1UF

X5R
402

C115UB

1

.1UF

X5R
402

C111UB

1

.1UF

X5R
402

C121UB

1

.1UF

X5R
402

C131UB

1

.1UF

X5R
402

C127UB

1

.1UF

X5R
402

C123UB

1

.1UF

X5R
402

2

10%

10V

2

10%

10V

2

10%

10V

2

10%

10V

2

10%

10V

2

10%

10V

2

10%

10V

2

10%

10V

C109UB

1

.1UF

C104UB

1

.1UF

10V
X5R
402

C120UB

1

.1UF

10V
X5R
402

C130UB

1

.1UF

10V
X5R
402

C126UB

1

.1UF

10V
X5R
402

10V
X5R
402

C105UB

1

.1UF

X5R
402

C114UB

1

.1UF

X5R
402

2

C108UB

1

.1UF

C110UB

1

.1UF

X5R
402

C119UB

1

.1UF

X5R
402

C129UB

1

.1UF

X5R
402

C125UB

1

.1UF

X5R
402

10V
X5R
402

C117UB

1

.1UF

C113UB

1

.1UF

10V

10V

10V

10V

2

10%

2

10%

10V
X5R
402

2

10%

10V
X5R
402

2

10%

2

10%

2

10%

2

10%

10%

2

10%

10V

2

10%

10V

2

10%

2

10%

2

10%

2

10%

10%

10V
X5R
402

2

10%

10V
X5R
402

2

10%

10V
X5R
402

2

10%

10V
X5R
402

2

10%

10V
X5R
402

2

10%

10V
X5R
402

2

10%

10V
X5R
402

2

10%

10V
X5R
402

EXP_A_TX_1_C_DN
EXP_A_TX_1_C_DP

EXP_A_TX_2_C_DN
EXP_A_TX_2_C_DP

EXP_A_TX_3_C_DN

EXP_A_TX_3_C_DP

EXP_A_TX_4_C_DN
EXP_A_TX_4_C_DP

EXP_A_TX_5_C_DN
EXP_A_TX_5_C_DP

EXP_A_TX_6_C_DN
EXP_A_TX_6_C_DP

EXP_A_TX_7_C_DN

EXP_A_TX_7_C_DP

EXP_A_TX_8_C_DN

EXP_A_TX_8_C_DP

EXP_A_TX_9_C_DN
EXP_A_TX_9_C_DP

EXP_A_TX_10_C_DN

EXP_A_TX_10_C_DP
EXP_A_TX_11_C_DN

EXP_A_TX_11_C_DP

EXP_A_TX_12_C_DN
EXP_A_TX_12_C_DP

EXP_A_TX_13_C_DN
EXP_A_TX_13_C_DP

EXP_A_TX_14_C_DN
EXP_A_TX_14_C_DP

EXP_A_TX_15_C_DN
EXP_A_TX_15_C_DP

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

2210

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

C

B

A

BPAGE DRAWING

frostburg_fabc.sch_1.23

Sun Mar 18 18:43:18 2007

8

7

6

5

4 2

[PAGE_TITLE=PCI EXPRESS X16 COUPLING]

INTEL

CONFIDENTIAL

3

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

23

1

3.01

24

112411

24

D

2426

C

24

24

B

A

CR-24 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE24

8

11

BI

M_DQS_A_DP<7..0>M_DQS_A_DP<7..0>

BI

M_ODT_A<3..0>

11

BI

11

11

112426

1

19

102

77

68

IO

NC

NC

ODT1

NC/TEST

VSS

VSS

VSS

VSS

VSS

852

M_DQS_A_DN<7..0>

BI

M_DQS_A_DP<7..0>

BI

M_ODT_A<3..0>

BI

19

102

68

IO

NC

NC

NC/TEST

VSS

VSS

VSS

VSS

852

0

195

ODT0

VSS

171411

3

77

ODT1

VSS

VSS

20

2

195

ODT0

VSS

171411

TP_SA_CB0_6

TP_SA_CB0_3

TP_SA_CB0_4

TP_SA_CB0_5

TP_SA_CB0_1

TP_SA_CB0_2

TP_SA_CB0_0

167

162

161

494843

42

CB<5>

CB<4>

CB<3>

CB<2>

CB<1>

CB<0>

VSS

VSS

VSS

VSS

VSS

VSS

383532

41

292623

TP_SA_CB_1

TP_SA_CB_0

TP_SA_CB_3

TP_SA_CB_4

TP_SA_CB_5

TP_SA_CB_2

161

494843

42

CB<4>

CB<3>

CB<2>

CB<1>

CB<0>

VSS

VSS

VSS

VSS

VSS

VSS

292623

20

TP_SA_CB0_7

CB<6>

VSS

TP_SA_CB_6

162

CB<5>

VSS

383532

168

CB<7>

VSS

167

CB<6>

VSS

41

VSS

TP_SA_CB_7

168

CB<7>

VSS

7

1

0

1

0

15

16

7

6

DQS<1>

DQS<0>

DQS*<1>

DQS*<0>

VSS

VSS

VSS

VSS

VSS

82796665504744

0

1

0

16

7

6

DQS<1>

DQS<0>

DQS*<0>

VSS

VSS

VSS

VSS

VSS

CHANNEL A

8

7

6

3

36

DQS*<3>

VSS

100

3

37

DQS<3>

VSS

9794918885

11

VSS

103

3

36

DQS*<3>

VSS

100

BI

4

84

DQS<4>

VSS

106

VSS

103

M_DQM_A<7..0>

5

4

6

5

105

93

92

83

DQS<5>

DQS<6>

DQS*<4>

DQS*<5>

VSS

VSS

VSS

VSS

VSS

VSS

124

121

118

115

112

109

M_DQM_A<7..0>

BI

5

4

5

4

92

83

93

84

DQS<5>

DQS<4>

DQS*<4>

DQS*<5>

VSS

VSS

VSS

VSS

VSS

VSS

121

118

115

112

109

106

6

104

DQS*<6>

VSS

127

6

105

DQS<6>

VSS

124

VSS

130

6

104

DQS*<6>

VSS

127

7

114

DQS<7>

VSS

133

VSS

130

7

113

DQS*<7>

VSS

136

7
114

DQS<7>

VSS

133

VSS

139

8286

7

113

DQS*<7>

VSS

136

TP_SA_DQS0_8

46

DQS<8>

VSS

142

VSS

139

8286

TP_SA_DQSB0_8

45

DQS*<8>

VSS

145

TP_SA_DQS_8

46

DQS<8>

VSS

142

VSS

148

TP_SA_DQSB_8

45

DQS*<8>

VSS

145

81

0

125

DM0/DQS9

VSS

151

VSS

148

126

154

80

NC/DQS9*

VSS

278081

0

125

DM0/DQS9

VSS

151

VSS

157

126

NC/DQS9*

VSS

154

27

1

134

DM1/DQS10

VSS

160

VSS

157

135

NC/DQS10*

VSS

163

1

134

DM1/DQS10

VSS

160

VSS

166

2425

135

NC/DQS10*

VSS

163

27
27

2

146

DM2/DQS11

VSS

169

VSS

166

2425

147

NC/DQS11*

VSS

198

2

146

DM2/DQS11

VSS

169

VSS

201

24

147

NC/DQS11*

VSS

198

19

27
27

3

155

DM3/DQS12

VSS

204

2425
2425

VSS

201

156

NC/DQS12*

VSS

207

141819
19

3

155

DM3/DQS12

VSS

204

24

VSS

210

156

NC/DQS12*

VSS

207

4

202

213

BI
BI

210

1418
19

2425
2425

203

DM4/DQS13

NC/DQS13*

VSS

VSS

216

IN
IN

4

202

DM4/DQS13

VSS

VSS

213

5

212

211

DM5/DQS14

NC/DQS14*

VSS

VSS

VSS

VSS

222

219

225

22851237

V_SM

DIMM_VREF_A

SMB_CLK_MEM

SMB_DATA_MEM

5

211

212

203

DM5/DQS14

NC/DQS14*

NC/DQS13*

VSS

VSS

VSS

VSS

225

222

219

216

V_SM

IN

DIMM_VREF_A

IN
BI
BI

7

6

224

232

223

DM6/DQS15

NC/DQS15*

DM7/DQS16

VSS

VSS

VSS

VDDQ

234

231

27

6

224

223

DM6/DQS15

NC/DQS15*

VSS

VSS

VSS

VSS

237

231

228

234

SMB_CLK_MEM
SMB_DATA_MEM

27

233

NC/DQS16*

VDDQ

56

2425

7

232

DM7/DQS16

VDDQ

51

VDDQ

62

233

NC/DQS16*

VDDQ

56

2425

164

DM8/DQS17

VDDQ

IN

VDDQ

62

165

NC/DQS17*

VDDQ

164

DM8/DQS17

VDDQ

IN

VDDQ

787572

165

NC/DQS17*

VDDQ

M_DATA_A<63..0>M_DQS_A_DN<7..0>

1

0

3

9

4

DQ<1>

DQ<0>

DQ<2>

VDDQ

VDDQ

VDDQ

181

194

191

V_3P3_MEM

3

4

DQ<1>

DQ<0>

VDDQ

VDDQ

VDDQ

787572

194

191

11

24

2

3

2

37

27

28

DQS<2>

DQS<3>

DQS*<2>

VSS

VSS

VSS

VSS

VSS

9794918885

24

1

2

2

15

27

28

DQS<2>

DQS*<1>

DQS*<2>

VSS

VSS

VSS

VSS

VSS

82796665504744

[PAGE_TITLE=240P CONN DDR2, CH A]

6

5

45

10

111213141516171819

9

8765432

13

12

129

128

123

122

10

DQ<4>

DQ<3>

VDDQ

VDDQ

170

175

TP_CH_A1_RC1_RCU
TP_CH_A1_RC0_RFU

22

21

DQ<9>

DQ<8>

DQ<5>

DQ<6>

DQ<7>

DQ<11>

DQ<10>

VDD

VDD

VDD

VDD

VDD

VDD

VDD

69

64

59

53

187

172

197

M_DATA_A<63..0>

10

9

876543210

13

12

129

128

123

122

9

DQ<2>

VDDQ

181

10

DQ<3>

VDDQ

175

21

DQ<9>

DQ<8>

DQ<4>

DQ<5>

DQ<6>

DQ<7>

DQ<10>

VDD

VDD

VDD

VDD

VDD

VDDQ

VDD

69

64

59

53

170

172

197

TP_CH_A2_RC1_RCU
TP_CH_A2_RC0_RFU

V_3P3_MEM

4 2

131

DQ<12>

VDD

184

22

DQ<11>

VDD

187

132

DQ<13>

VDD

178

131

DQ<12>

VDD

184

140

189

131211

132

178

BI

30

141

25

24

DQ<15>

DQ<16>

DQ<14>

DQ<17>

DQ<18>

RC0

RC1

VDD

VDD

18

67

55

BI

1416151719

141

140

25

24

DQ<15>

DQ<16>

DQ<13>

DQ<14>

DQ<17>

RC1

VDD

VDD

VDD

18

67

189

11

24

202122232425262728

31

149

144

143

DQ<21>

DQ<20>

DQ<19>

DQ<22>

SCL

SDA

VREF

VDDSPD

1

119

120

238

11

24

18

21

20222324262527

31

30

144

143

DQ<21>

DQ<20>

DQ<19>

DQ<18>

RC0

SCL

VREF

VDDSPD

1

55

120

238

Sun Mar 18 18:43:19 2007

3

303132333435363738

29

393433

159

158

153

152

150

101

DQ<25>

DQ<26>

DQ<23>

DQ<24>

SA2

SA0

SA1

240

239

40

190

81

80

DQ<27>

DQ<30>

DQ<29>

DQ<28>

DQ<31>

DQ<32>

DQ<33>

BA1

BA0

CKE0

CKE1

S1*

76

71

52

171

1

31333235343637

283029

393433

159

158

153

152

150

149

DQ<22>

SDA

119

DQ<23>

SA2

101

DQ<24>

SA1

240

DQ<25>

SA0

239

80

40

DQ<26>

DQ<27>

DQ<30>

DQ<29>

DQ<28>

DQ<31>

DQ<32>

BA1

BA0

CKE0

CKE1

71

52

171

190

1

BPAGE DRAWING

frostburg_fabc.sch_1.24

3

86

193

01010

76

87

DQ<34>

DQ<35>

S0*

DQ<34>

DQ<33>

S0*

S1*

193

23230

199

DQ<36>

CK2*/RFU

221

878681

DQ<35>

200

DQ<37>

CK2/RFU

220

199

DQ<36>

CK2*/RFU

221

205

DQ<38>

CK1*/RFU

138

200

DQ<37>

CK2/RFU

220

39

206

DQ<39>

CK1/RFU

137

384039

205

DQ<38>

CK1*/RFU

138

404142434445464748

DQ<42>

DQ<41>

DQ<40>

CK0

CK0*

186

185

41

206

DQ<41>

DQ<40>

DQ<39>

CK0

CK1/RFU

CK0*

137

186

185

2

505152535455565758

49

108

107

218

217

215

214

209

20896959089

99

98

DQ<43>

DQ<46>

DQ<47>

DQ<44>

188

DQ<45>

A0

63

183

182

DQ<52>

DQ<51>

DQ<50>

DQ<49>

DQ<53>

DQ<48>

A10/AP

A9A8A7A6A5A4A3A2A1

70

60

61

177

17958180

10

9

876543210

42444345474649485051525453

108

107

99

98

215

214

209

20896959089

DQ<43>

DQ<42>

DQ<44>

DQ<45>

63

183

188

CONFIDENTIAL

CUSTOM TEXT BPAGE

DQ<46>

182

DQ<47>

DQ<48>

61

60

INTEL

217

DQ<52>

DQ<51>

DQ<50>

DQ<49>

177

17958180

9

876543210

MODULE REV DETAILS

MODULE NAME

636261

60

59

117

116

111

226

DQ<54>

A11

57

218

DQ<53>

A10/AP

70

10

227

DQ<55>

A12

176

226

DQ<54>

A11A9A8A7A6A5A4A3A2A1A0

57

110

DQ<56>

A13

196

131211

55

227

DQ<55>

A12

176

236

235

230

229

DQ<57>

DQ<58>

DQ<62>

DQ<61>

DQ<60>

DQ<59>

A15

A14

A16/BA2

RAS*

CAS*

74

73

54

M_RAS_A_N

192

173

174

M_CAS_A_N

2

M_SBS_A<2..0>

TP_M_MAA_A15

14

M_MAA_A<14..0>
CK_M_DDR0_A_DP
CK_M_DDR0_A_DN
CK_M_DDR1_A_DP
CK_M_DDR1_A_DN
CK_M_DDR2_A_DP
CK_M_DDR2_A_DN
M_SCS_A_N<3..0>
M_SCKE_A<3..0>
M_SBS_A<2..0>

56585759616063

62

117

116

111

110

235

230

229

DQ<56>

DQ<57>

DQ<58>

DQ<61>

DQ<60>

DQ<59>

A15

A14

A13

A16/BA2

CAS*

74

54

192

173

174

196

2

M_CAS_A_N

M_SBS_A<2..0>

TP_M1_MAA_A15

14

131211

M_MAA_A<14..0>

CK_M_DDR3_A_DP
CK_M_DDR3_A_DN
CK_M_DDR4_A_DP
CK_M_DDR4_A_DN
CK_M_DDR5_A_DP

CK_M_DDR5_A_DN
M_SCS_A_N<3..0>
M_SCKE_A<3..0>
M_SBS_A<2..0>

DOCUMENT_NUMBER

xxxxxx

REV

DQ<63>

ADDRESS: 000

X

0A0

J1MY

DDRII_240P

WE*

M_WE_A_N

236

DQ<63>

DQ<62>

ADDRESS: 001
0A2

J2MY

DDRII_240P

RAS*

WE*

M_WE_A_N

73

M_RAS_A_N

1

IN
IN
IN
BI

BI
IN
IN
IN
IN
IN
IN
BI
BI
BI

X

IN
IN
IN

BI

BI
IN
IN
IN
IN
IN
IN

BI

BI

BI

1

DATE

112426
112426

24

26

11

112426

112426
11
11
11
11
11
11

112426

112426

112426

11

24 26

11

24 26

11

24 26

11

24 26

11

24 26

11
11
11
11
11
11

11

24 26

11

24 26

11

24 26

PAGE REV

24

3.01

D

C

B

A

CR-25 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE25

8

M_DQS_B_DN<7..0>

12

25

BI

M_DQS_B_DP<7..0>

12

25

BI

12

M_ODT_B<3..0>

BI

68

IO

NC

VSS

102

NC/TEST

VSS

1

02

195

19

77

NC

ODT1

ODT0

VSS

VSS

VSS

VSS

852

171411

20

TP_SB_CB0_6

TP_SB_CB0_3

TP_SB_CB0_4

TP_SB_CB0_5

TP_SB_CB0_1

TP_SB_CB0_2

TP_SB_CB0_0

167

162

161

494843

42

CB<5>

CB<4>

CB<3>

CB<2>

CB<1>

CB<0>

VSS

VSS

VSS

VSS

VSS

VSS

VSS

383532

41

292623

2526

D

C

M_DQS_B_DN<7..0>

12

25

BI

M_DQS_B_DP<7..0>

12

25

BI

M_ODT_B<3..0>

12

2526

B

BI

3

19

195

102

77

68

IO

NC

NC

ODT1

ODT0

NC/TEST

VSS

VSS

VSS

VSS

VSS

VSS

852

171411

20

TP_SB_CB_6

TP_SB_CB_3

TP_SB_CB_4

TP_SB_CB_5

TP_SB_CB_1

TP_SB_CB_2

TP_SB_CB_0

167

162

161

494843

42

CB<5>

CB<4>

CB<3>

CB<2>

CB<1>

CB<0>

VSS

VSS

VSS

VSS

VSS

VSS

VSS

383532

41

292623

7

3

36

DQS*<3>

VSS

100

3

36

DQS*<3>

VSS

100

103

103

BI

4

84

DQS<4>

VSS

VSS

106

BI

4

84

DQS<4>

VSS

VSS

106

M_DQM_B<7..0>

5

4

5

93

92

83

DQS<5>

DQS*<4>

DQS*<5>

VSS

VSS

VSS

VSS

121

118

115

112

109

M_DQM_B<7..0>

5

4

5

92

83

93

DQS<5>

DQS*<4>

DQS*<5>

VSS

VSS

VSS

VSS

121

118

115

112

109

25

12

1

0

2

TP_SB_CB0_7

0

168

7

6

CB<6>

CB<7>

DQS<0>

DQS*<0>

VSS

VSS

VSS

VSS

VSS

VSS

0

TP_SB_CB_7

0

168

7

6

CB<6>

CB<7>

DQS<0>

DQS*<0>

VSS

VSS

VSS

VSS

VSS

VSS

3

1

2

37

15

16

27

28

DQS<1>

DQS<2>

DQS<3>

DQS*<1>

DQS*<2>

VSS

VSS

VSS

VSS

VSS

VSS

VSS

9794918885

82796665504744

12

25

1

2

3

1

2

37

15

16

27

28

DQS<1>

DQS<2>

DQS<3>

DQS*<1>

DQS*<2>

VSS

VSS

VSS

VSS

VSS

VSS

VSS

9794918885

82796665504744

6

M_DATA_B<63..0>

0

125

151

2

126

134

NC/DQS9*

DM0/DQS9

DM1/DQS10

VSS

VSS

VSS

VSS

160

157

154

25

135

NC/DQS10*

VSS

163

27
27

166

156

147

155

146

NC/DQS11*

DM2/DQS11

DM3/DQS12

NC/DQS12*

VSS

VSS

VSS

VSS

VSS

VSS

VSS

198

169

210

207

204

201

14181924

IN

19

25

IN

2425

BI

2425

BI

7

6

TP_SB_DQSB0_8

TP_SB_DQS0_8

7

6

114

105

113

104

46

45

DQS<6>

DQS<7>

DQS<8>

DQS*<6>

DQS*<7>

DQS*<8>

VSS

VSS

VSS

127

124

130

VSS

VSS

VSS

VSS

VSS

VSS

VSS

148

145

142

139

136

133

27

80

81

8286

5

4

212

203

211

202

DM4/DQS13

DM5/DQS14

NC/DQS14*

NC/DQS13*

VSS

VSS

VSS

VSS

VSS

VSS

228

225

222

219

216

213

V_SM

DIMM_VREF_B

SMB_CLK_MEM

SMB_DATA_MEM

6

223

231

224

DM6/DQS15

NC/DQS15*

VSS

VSS

VSS

237

234

3

1

7

232

DM7/DQS16

VDDQ

51

233

56

0

3

165

164

9

4

DQ<1>

DQ<0>

NC/DQS16*

VDDQ

DQ<2>

NC/DQS17*

DM8/DQS17

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

787572

62

194

191

181

24

2527

IN

1

M_DATA_B<63..0>

3

1

0

7

6

TP_SB_DQSB_8

TP_SB_DQS_8

7

6

126

45

145

135

134

125

DQS*<8>

NC/DQS9*

DM0/DQS9

NC/DQS10*

DM1/DQS10

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

166

163

160

157

154

151

148

113

104

114

105

46

DQS<6>

DQS<7>

DQS<8>

DQS*<6>

DQS*<7>

VSS

VSS

124

127

VSS

VSS

VSS

VSS

VSS

VSS

142

139

136

133

130

2

146

169

4

156

147

155

203

202

NC/DQS11*

DM2/DQS11

DM3/DQS12

NC/DQS12*

DM4/DQS13

NC/DQS13*

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

198

201

204

207

210

213

216

219

5

211

DM5/DQS14

VSS

222

212

NC/DQS14*

VSS

225

228

7

6

3

165

164

233

224

223

232

DM6/DQS15

NC/DQS15*

DM7/DQS16

NC/DQS16*

VSS

VSS

VSS

VSS

VDDQ

VDDQ

56

51

237

234

231

9

4

DQ<1>

DQ<0>

DQ<2>

NC/DQS17*

DM8/DQS17

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

78

75

72

62

194

191

181

A

V_SM

141819

2425

27

80

81

8286

27
27

IN

25

DIMM_VREF_B

19

IN
BI
BI

SMB_CLK_MEM

SMB_DATA_MEM

27

2425

2425
2425

45

101112131415161718

9

8765432

1312129

128

123

122

10

DQ<4>

DQ<3>

VDDQ

VDDQ

170

175

TP_CH_B1_RC1_RCU
TP_CH_B1_RC0_RFU

22

21

DQ<9>

DQ<8>

DQ<5>

DQ<6>

DQ<7>

DQ<11>

DQ<10>

VDD

VDD

VDD

VDD

VDD

VDD

VDD

69

64

59

53

187

172

197

V_3P3_MEM

10

9

876543210

1312129

128

123

122

10

DQ<3>

VDDQ

175

IN

21

22

DQ<9>

DQ<8>

DQ<4>

DQ<5>

DQ<6>

DQ<7>

DQ<11>

DQ<10>

VDD

VDD

VDD

VDD

VDD

VDD

VDDQ

VDD

69

64

59

53

170

TP_CH_B2_RC1_RCU
TP_CH_B2_RC0_RFU

197

172

187

V_3P3_MEM

141

140

132

131

DQ<12>

DQ<13>

DQ<14>

VDD

VDD

VDD

67

184

189

178

1416151719

131211

141

140

132

131

DQ<12>

DQ<13>

DQ<14>

VDD

VDD

VDD

67

184

189

178

BI

25

24

DQ<15>

DQ<16>

DQ<17>

RC1

VDD

18

BI

25

24

DQ<15>

DQ<16>

DQ<17>

RC1

VDD

18

25

12

19

202122232425262728

31

30

149

144

143

DQ<21>

DQ<20>

DQ<19>

DQ<18>

DQ<22>

RC0

SCL

SDA

VREF

VDDSPD

1

55

119

120

238

12

25

18

21

20222324262527

31

30

149

144

143

DQ<21>

DQ<20>

DQ<19>

DQ<18>

DQ<22>

RC0

SCL

SDA

VREF

VDDSPD

1

55

119

120

238

150

101

150

101

3

303132333435363738

29

393433

159

158

153

152

80

40

DQ<25>

DQ<26>

DQ<27>

DQ<23>

DQ<24>

DQ<30>

DQ<29>

DQ<28>

DQ<31>

DQ<32>

SA2

SA0

SA1

BA1

BA0

CKE0

CKE1

71

52

190

171

240

239

1

31333235343637

283029

393433

159

158

153

152

80

40

DQ<25>

DQ<26>

DQ<27>

DQ<23>

DQ<24>

DQ<30>

DQ<29>

DQ<28>

DQ<31>

DQ<32>

SA2

SA0

SA1

BA1

BA0

CKE0

CKE1

71

52

171

190

240

239

1

39

404142434445464748

199

206

205

200

81

87

86

DQ<34>

DQ<35>

DQ<36>

DQ<37>

DQ<33>

S0*

S1*

76

193

CK2*/RFU

221

220

DQ<42>

DQ<41>

DQ<40>

DQ<39>

DQ<38>

CK0

CK1/RFU

CK1*/RFU

CK2/RFU

CK0*

138

137

186

185

01010

384039

41

42444345474649485051525453

199

206

205

200

878681

DQ<34>

DQ<35>

DQ<36>

DQ<37>

DQ<33>

S0*

S1*

76

193

CK2*/RFU

221

220

DQ<42>

DQ<41>

DQ<40>

DQ<39>

DQ<38>

CK0

CK1/RFU

CK1*/RFU

CK2/RFU

CK0*

138

137

186

185

23230

CHANNEL B

[PAGE_TITLE=240P CONN DDR2, CH B]

8

7

6

5

4 2

BPAGE DRAWING

frostburg_fabc.sch_1.25

Sun Mar 18 18:43:25 2007

3

2

505152535455565758

49

108

107

215

214

209

20896959089

99

98

DQ<43>

DQ<46>

DQ<47>

DQ<44>

DQ<45>

DQ<50>

DQ<49>

DQ<48>

A0

60

61

63

17958180

182

183

188

876543210

108

107

215

214

209

20896959089

99

98

DQ<43>

DQ<46>

DQ<47>

DQ<44>

DQ<45>

DQ<50>

DQ<49>

DQ<48>

60

61

63

17958180

182

183

188

876543210

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

MODULE REV DETAILS

MODULE NAME

636261

60

59

117

116

111

110

227

226

218

217

DQ<52>

DQ<51>

DQ<56>

DQ<53>

DQ<54>

DQ<55>

A13

A12

A11

A10/AP

A9A8A7A6A5A4A3A2A1

70

57

177

196

176

131211

10

9

CK_M_DDR0_B_DP
CK_M_DDR0_B_DN
CK_M_DDR1_B_DP
CK_M_DDR1_B_DN
CK_M_DDR2_B_DP

CK_M_DDR2_B_DN
M_SCS_B_N<3..0>
M_SCKE_B<3..0>
M_SBS_B<2..0>

56585759616063

55

110

226

218

217

227

DQ<52>

DQ<51>

DQ<56>

DQ<53>

DQ<54>

DQ<55>

A10/AP

A13

A12

A11A9A8A7A6A5A4A3A2A1A0

70

57

177

196

176

131211

10

9

CK_M_DDR3_B_DP

CK_M_DDR3_B_DN

CK_M_DDR4_B_DP

CK_M_DDR4_B_DN

CK_M_DDR5_B_DP

CK_M_DDR5_B_DN

M_SCS_B_N<3..0>
M_SCKE_B<3..0>
M_SBS_B<2..0>

236

235

230

229

DQ<57>

DQ<58>

DQ<62>

DQ<61>

DQ<60>

DQ<59>

A15

A14

A16/BA2

RAS*

CAS*

74

73

54

192

173

174

M_RAS_B_N

M_CAS_B_N

22

M_SBS_B<2..0>

TP_M_MAA_B15

M_MAA_B<14..0>

62

117

116

111

236

235

230

229

DQ<57>

DQ<58>

DQ<62>

DQ<61>

DQ<60>

DQ<59>

A15

A14

A16/BA2

RAS*

CAS*

74

73

54

192

173

174

M_RAS_B_N

M_CAS_B_N

M_SBS_B<2..0>

TP_M_MAA0_B15

14 14

M_MAA_B<14..0>

DQ<63>

ADDRESS: 010
0A4

J3MY

DDRII_240P

WE*

M_WE_B_N

DQ<63>

ADDRESS: 011

J4MY

0A6

DDRII_240P

WE*

M_WE_B_N

DOCUMENT_NUMBER

xxxxxx

REV

X

X

1

IN
IN
IN

BI

BI
IN
IN
IN
IN
IN
IN
BI
BI
BI

IN
IN

IN

BI

BI
IN
IN
IN
IN
IN
IN
BI
BI
BI

PAGE REV

1

12 25
12 25
12 25

122526

122526
12
12
12
12
12
12

12

12

12

12 25
12 25

12 25

122526

122526
12
12
12
12
12
12

12

12

12

25

25
25
25

25
25
25

DATE

D

26
26

C

26

26
26
26

B

26
26

26

A

26
26
26

3.01

CR-26 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE26

8

14

D

13

12

11

10

9

8

C

7

6

5

4

3

B

2

1

M_MAA_A<14..0>

11

24

IN

11

24

IN

11

24

IN

11

24

A

IN

11

24

IN

0

M_RAS_A_N

M_CAS_A_N

M_WE_A_N

M_SBS_A<2..0>

8

262781

R1MY

1

33

CH

R11MY

1

33

CH

R47MY

1

33

CH

R54MY

1

33

CH

R17MY

1

33

CH

R48MY

1

33

CH

R22MY

1

33

CH

R45MY

1

33

CH

R23MY

1

33

CH

R49MY

1

33

CH

R24MY

1

33

CH

R15MY

1

33

CH

R18MY

1

33

CH

R25MY

1

33

CH

R5MY

1

33

CH

R7MY

1

33

CH

R21MY

1

33

CH

R19MY

1

33

CH5%402

0

1

2

IN

7

402

402

402

402

402

402

402

5%

402

5%

402

5%

402

5%

402

5%

402

5%

402

5%

402

5%

402

5%

402

5%

402

1

33

402

1

33

402

1

33

402

7

5%

5%

5%

5%

5%

5%

5%

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

R36MY

R6MY

R46MY

V_SM_VTT

2

5%
CH

2

5%
CH

2

5%
CH

6

IN

11

IN

IN

IN

V_SM_VTT

M_SCS_A_N<3..0>

3

2

1

0

M_SCKE_A<3..0>

3

2

1

0

M_ODT_A<3..0>

3

2

1

0

6

1

R8MY

1

43

CH

R13MY

1

43

CH

R20MY

1

43

CH

R52MY

1

R50MY

1

R51MY

1

R53MY

1

R14MY

1

1

R16MY

1

R10MY

1

R12MY

43

CH

43

CH

43

CH

43

CH

43

CH

43

CH

R9MY

43

CH

43

CH

43

CH

2

5%

402

2

5%

402

2

5%

402

2

5%

402

2

5%

402

2

5%

402

2

5%

402

2

5%

402

2

5%

402

2

5%

402

2

5%

402

2

5%

402

5

262781

24

11

24

11

24

45

27

81

M_MAA_B<14..0>

12

25

IN

M_RAS_B_N

12

25

IN

M_CAS_B_N

12

25

IN

M_WE_B_N

12

25

IN

M_SBS_B<2..0>

12

25

IN

Sun Mar 18 18:43:30 2007

4 2

3

V_SM_VTT

26

IN

R2MY

14

1

2

5%

33

402

CH

R32MY

1

13

1

12

1

11

1

10

1

9

1

8

R65MY

1

7

CH

R58MY

1

6

CH

R56MY

1

5

CH

R37MY

1

4

33

CH

R38MY

1

3

CH

R39MY

1

2

33

CH
R40MY

1

1

CH

R42MY

1

0

CH

R27MY

1

CH

R28MY

1

CH

R26MY

1

CH

BPAGE DRAWING

frostburg_fabc.sch_1.26

33

CH

R63MY

33

CH

R64MY

CH33402

R41MY

33

CH

R66MY

33

CH

R57MY

33

CH

33

33

33

5%

402

33

33

33

33

33

33

0

1

2

2

5%

402

2

5%

402

2

5%

2

5%

402

2

5%

402

2

5%

402

2

5%

402

2

5%

402

2

5%

402

2

2

5%

402

2

5%

402

2

5%

402

2

5%

402

2

5%

402

2

5%

402

2

5%

402

R43MY

1

33

402

R44MY

1

402

R62MY

1

402

3

81

2

5%
CH

2

5%33
CH

2

5%33
CH

[PAGE_TITLE=DDR VTT TERMINATION]

2

2627

IN

12

25

IN

M_SCKE_B<3..0>

1225

IN

M_ODT_B<3..0>

1225

IN

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

MODULE REV DETAILS

MODULE NAME

V_SM_VTT

M_SCS_B_N<3..0>

R31MY

3

2

1

0

3

2

1

0

3

2

1

0

1

43

CH

R30MY

1

CH

R35MY

1

43

CH

R29MY

1

43CH5%

R60MY

1

43CH5%

R59MY

1

43CH5%

R55MY

1

43CH5%

R61MY

1

CH

R4MY

1

43CH5%

R3MY

1

43

CH

R34MY

1

43CH5%

R33MY

1

43CH5%

5%

402

5%43

402

5%

402

402

402

402

402

5%43

402

402

5%

402

402

402

DOCUMENT_NUMBER

xxxxxx

REV

2

2

2

2

2

2

2

2

2

2

1

2

2

PAGE REV

1

DATE

D

C

B

A

26

3.01

CR-27 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE27

8

7

6

45

3

DECOUPLING CAPACITORS FOR DDR TERMINATION RESISTORS

8286
25

V_SM_VTT

262781

IN

D

DESIGN NOTE:

CH A V_SM_VTT DECOUPLING CAPS

V_SM_VTT

26

27

81

IN

C

DESIGN NOTE:

CH B V_SM_VTT DECOUPLING CAPS

DESIGN NOTE:

CH A ADDRESS/CONTROL STITCHING CAPS (V_SM_VTT - V_SM)

V_SM_VTT

262781

IN

B

82

2425

278081

82

IN

86

DESIGN NOTE:

CH B ADDRESS/CONTROL STITCHING CAPS (V_SM_VTT - V_SM)

27

81

V_SM_VTT

26

IN

V_SM

141819

IN

86

V_SM

141819

2425

278081

A

V_SM

27

808182

86

1418192425

IN

10.0UF

C63MY

1

6.3V

EMPTY

1206

1

2

1

2

1

2

1

2

2

20%

C40MY

0.1UF
20%

16V
Y5V
402

C51MY

0.1UF
20%
16V
Y5V
402

C42MY

0.1UF
20%

16V
Y5V
402

C28MY

0.1UF
20%

16V
Y5V
402

1

2

1

2

1

2

1

2

C25MY

0.1UF
20%

16V
Y5V
402

C24MY

0.1UF
20%
16V
Y5V
402

C43MY

0.1UF
20%

16V
Y5V
402

C49MY

0.1UF
20%

16V
Y5V
402

1

1

C6MY

0.1UF
20%
16V

2

2

Y5V
402

1

C30MY

0.1UF
20%
16V

2

Y5V
402

1

C23MY

0.1UF
20%
16V

2

Y5V
402

1

C7MY

0.1UF
20%
16V

2

Y5V
402

1

2

1

2

1

2

C41MY

0.1UF
20%
16V
Y5V
402

C22MY

0.1UF
20%
16V
Y5V
402

C32MY

0.1UF
20%
16V
Y5V
402

C44MY

0.1UF
20%
16V
Y5V
402

1

2

1

C26MY

0.1UF
20%

16V

2

Y5V
402

1

C9MY

0.1UF
20%
16V

2

Y5V
402

1

C19MY

0.1UF
20%

16V

2

Y5V
402

1

C53MY

0.1UF
20%

16V

2

Y5V
402

102103105 28

1

2

1

2

70101

C20MY

0.1UF
20%
16V
Y5V
402

1

2

49

C10MY

0.1UF
20%
16V
Y5V
402

C11MY

0.1UF
20%

16V
Y5V
402

C27MY

0.1UF
20%

16V
Y5V
402

1

2

4748

C21MY

0.1UF
20%
16V
Y5V
402

1

2

33

C12MY

0.1UF
20%
16V
Y5V
402

48

1

C29MY

0.1UF
20%
16V

2

Y5V
402

1

C8MY

0.1UF
20%
16V

2

Y5V
402

588892
28

333438

IN

4056

57

39

49

70101
2228
47

2228

SMB_CLK_RESUME

21

IN

33
102103105

SMB_DATA_RESUME

21

IN

DESIGN NOTE:

VCC3

V_3P3_EPW

1

0

402

1

402

R73MY

R74MY

0

UNSTUFF FOR NON-ME SKU

[PAGE_TITLE=DDR VTT DECOUPLING]

8

7

6

5

4 2

27

1418

IN

19

24

80

81

R71MY

1

5%

0

EMPTY

402

R72MY

1

0

5%
CH

402

CAD NOTE:

OVERLAP PAD

2

5%

EMPTY

2

5%

EMPTY

FOR ME SKUSTUFF R73MY AND R74MY

BPAGE DRAWING

frostburg_fabc.sch_1.27

Sun Mar 18 18:43:31 2007

3

V_SM

C14MY

1

1.0UF
10V
Y5V
603

C39MY

1

1.0UF
10V
Y5V
603

C34MY

1

1.0UF
10V
Y5V
603

C18MY

1

1.0UF
10V
Y5V
603

C38MY

1

1.0UF
10V
Y5V
603

2

2

R75MY

1

2

5%

0

CH

402

R76MY

1

2

0

5%
CH

402

DESIGN NOTE:

STUFF FOR NON-ME SKU
UNSTUFF FOR ME SKU

SMB_CLK_MEM

SMB_DATA_MEM

2

C15MY

1

2

1.0UF

20%

20%

20%

20%

20%

10V
Y5V
603

C17MY

1

2

1.0UF
10V
Y5V
603

C35MY

2

1

1.0UF
10V
Y5V
603

C47MY

2

1

1.0UF
10V
Y5V
603

C46MY

2

1

1.0UF
10V
Y5V
603

V_3P3_MEM

C62MY

C61MY

0.1UF

0.1UF
20%

20%

16V

16V

Y5V

Y5V

402

402

SMB_CLK_MAIN

SMB_DATA_MAIN

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

MODULE REV DETAILS

MODULE NAME

C16MY

2

1

1.0UF

20%

10V
Y5V
603

C13MY

1

20%

1.0UF
10V
Y5V
603

C3MY

1

20%

1.0UF
10V
Y5V
603

C4MY

1

20%

1.0UF
10V
Y5V
603

C36MY

1

20%

1.0UF
10V
Y5V
603

C37MY

1

20%

1.0UF
10V
Y5V
603

24 25

DESIGN NOTE:

2

2

2

2

2

2

20%

2

20%

2

20%

2

20%

2

20%

OUT

DEFAULT: STUFF R72MY

28

IN

IN

24 25

OUT

24 25

OUT

DOCUMENT_NUMBER

xxxxxx

REV

70 97

70 97

1

PAGE REV

27

1

DATE

D

C

B

A

3.01

D

BOM NO TE:

EMPTY FOR NON AMT

BOM NO TE:

DUAL FOOTPRINT
FOR C112CK AND C113CK
STUFF ONLY ONE OF THEM

C

88
39
86
89

88
40

33

57

B

33

49

70

102

33

47

A

33
31

CR-28 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE28

8

BW_ATX_CORE

VCC3

SLP_M_CKL_R

1

C113CK

1.0UF
20%
10V

2

EMPTY
603

SLP_M

IN

58

39

27

IN

3438
56
92

7813

277097

102103

2227

277097

101

21

2227

48

4970

103105

IN

1

2

1

2

28

101
21
4748
105

R105CK

1

0

EMPTY

603

V_3P3_STBY\G

C112CK

4.7UF
20%
10V
EMPTY
805

R97CK

0
5%

EMPTY
402

V_3P3_EPW

IN

IN

BI

BI

BI

BI

2

1A

1

G

VDD_CLK_R

CK_PWRGD_R

H_FSBSEL1

SMB_DATA_MAIN

SMB_DATA_RESUME

SMB_CLK_MAIN

SMB_CLK_RESUME

BOM NO TE:

UNSTUFF R105CK FOR NON AMT

R10CK

1

2

0

1A
CH

603

2

Q2CK
EMPTY

S

D

3

R100CK

1

2

0

1A

EMPTY

603

R9CK

2

1

1A

0

EMPTY

603

DESIGN NOTE:

COST SAVING

1

C8CK

4.7UF
20%

16V

2

Y5V

1206

VDD_CLK

28

OUT

R60CK

1

0

402

14.318MHZ

5%
CH

402

R103CK

0

603

0

603

0

603

2

R109CK

402

R110CK

1

0

402

Y1CK

1

R18CK

1

0

202170-024

1

R101CK

1

R102CK

1

1

0

EMPTY

SM

2

C12CK

27PF
5%
50V

1

COG
603

VDD_CLK

28

IN

28

IN

28

IN

CK_14M_ICH

CK_48M_USB_ICH

1

2

1

2

R75CK

47K
5%

CH
402

R76CK

33K
5%

CH
402

2

2

1

1

R77CK

47K
5%

CH
402

R78CK

33K

5%
CH

402

8

603

2

R104CK

1

0

5%
CH

2

1A

CH

1A

CH

1A

CH

5%

EMPTY

2

5%

XTAL

7

2

1A
CH

2

2

2

R12CK

1

1K

402

2

R62CK

0

402

7

1

C10CK

.1UF
10%
16V

2

X7R
603

C13CK

4.7UF
20%
16V
Y5V
1206

C2CK

.1UF
10%
16V
X7R
603

C4CK

.1UF
10%
16V
X7R
603

C1CK

.1UF
10%
16V
X7R
603

2

5%
CH

2

5%
CH

OSC_CK14M_XTALOUT

OSC_CK14M_XTALIN

C11CK

27PF
5%
50V
COG
603

28

IN

33

IN

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

DESIGN NOTE:

BSEL BIASING RES

ALWAYS STUFF

VDD_CK_VDD_PCI

VDD_CK_VDD_48

C9CK

.1UF
10%
16V
X7R
603

VDD_CK_VDD_SRC

C3CK

.1UF
10%
16V
X7R
603

VDD_CK_VDD_CPU

VDD_CK_VDD_REF

SMB_FSBSEL_CK505

SMB_DATA_CK505
SMB_CLK_CK505

DESIGN NOTE:

ENGINEERING

TESTING PURPOSE

R67CK

VDD_CLK

1

0

603

CK_PWRGD

1A

EMPTY

6

2

1K

402

6

VDD_CLK_IO

R98CK

1

2

5%
CH

28

28

28

28

OUT

CK_PWRGD_R

45

7813

IN

7813

IN

28

IN

28

IN

7813

IN

7813

IN

2

9
16
39

55
61

56
57
63

64
59

60

28
29

OUT

402

402

402

4.7K
402

4.7K
402

R71CK

1

0

R72CK

1

1K

R69CK

1

1K

R73CK

1

R70CK

1

H_FSBSEL0

VDD_CLK

VDD_CLK

H_FSBSEL2

H_FSBSEL0

VDD_PCI
VDD_48
VDD_PLL3
VDD_SRC
VDD_CPU
VDD_REF

CKPWRGD/PWRDWN*
FSB/TESTMODE
SDA

SCL
XTAL_OUT

XTAL_IN

1.01

CK505_IO_VOUT_PIN48

28

IN

R2CK

CK505_IO_VOUT_R

1

2

33

5%

1

CH

402

C26CK

100.0PF
5%
50V

2

COG
603

28

402

2

5%

EMPTY

MBT3904DUAL

2

5%
CH

2

5%
CH

MBT3904DUAL

GATE1_FSBSEL2

2

5%
CH

GATE1_FSBSEL0

2

5%
CH

U1CK

CK505_64PIN

REF/FSC/TESTSEL

VDD_CLK

1

R74CK

2

1

5%

0

EMPTY

Q3CK

5

GATE2_FSBSEL2

Q4CK

5

PCIF5/ITP_EN
PCI4/SRC5_EN

PCI1/CR_B*
PCI0/CR_A*

R3CK

1

15
5%

CH

2

805

VDD-CLK_R_3

3

Q1CK

MMBT3904
XSTR

2

VDD_CLK_IO

3

4

3

4

PCI2/LTE

USB/FSA
VSS_PCI

VSS_48

VSS_REF

IO_VOUT

1of 2

CK_FSBSEL2H_FSBSEL2

CK_FSBSEL0

6

1

GATE2_FSBSEL0

6

1

PCI3

31

28
28

30

2868
2869
2853
28103
2848
2849

OUT

[PAGE_TITLE=CK505 PAGE 1 OF 2]

5

4 2

2

XSTR

2

XSTR

IC

IN
IN
IN
IN
IN
IN
IN
IN

28

62

CK_REF_R

CK_PCI5_R

7

CK_PCI4_R

6

CK_PCI3_R

5

CK_PCI2_R

4

CK_PCI1_R

3

CK_PCI0_R

1

CK_USB_R

10
8

11
58

48

CK_48M_USB_ICH
CK_P_33M_ICH
CK_P_33M_TPM
CK_P_33M_PA
CK_P_33M_1394
CK_P_33M_S3
CK_P_33M_S1
CK_P_33M_S2

29

3

28

OUT

28

OUT

CAD NOTE:

OVERLAP PADS

BPAGE DRAWING

frostburg_fabc.sch_1.28

Sun Mar 18 18:43:33 2007

3

VCC3

1

2

C20CK

22PF
5%
50V
EMPTY
402

2

MODULE REV DETAILS

MODULE NAME

STRAP MODE STUFF UNSTUFF

CK505 ATX BLB 9/7/2006

LT ENABLED

LTE

LT DISABLED
ITP ENABLED (SRC8 DISABLED)

ITP_EN

SRC8 ENABLED (ITP DISABLED)
SRC5 ENABLED

SRC5_EN

SCR5 DISABLED

R26CK

1

1

10K

5%

2

2

EMPTY
402

R24CK

1

10K

5%

2

CH
402

R11CK

R15CK

R20CK

R25CK

R17CK

BOM NO TE:

STUFF FOR ATX ONLY

R13CK

2

5%
CH

1

C15CK

22PF
5%
50V

2

EMPTY
402

CUSTOM TEXT BPAGE

R106CK

10K
5%

CH
402

R107CK

10K
5%

EMPTY
402

2

1

5%

1K

CH

402

2

1

5% 22
CH

402

1

2

10

5%
CH

402

2

1

22

5%
CH

402

2

1

5% 22
CH

402

1

1K

402

1

C6CK

22PF
5%
50V

2

EMPTY
402

CONFIDENTIAL

1

2

1

2

INTEL

R4CK

10K

5%
CH

402

R5CK

10K

5%
EMPTY

402

R14CK

2

R19CK

2

5%
CH

EMPTY

R22CK

2

5%
CH

1

2

R65CK

1

10K

5%

2

CH
402

DO NOT STUB OFF MORE THEN 250 MILS

R66CK

1

10K

5%

2

EMPTY
402

1

22CH5%

402

1

10

402

R21CK

2

1

5%

22

402

R23CK

2

1

22

5%
CH

402

R16CK

2

1

22

5%
CH

402

1

33

402

1

C7CK

C18CK

10PF

10PF

5%

5%

50V

50V

2

EMPTY

EMPTY

402

402

DOCUMENT_NUMBER

0.0.1

R65CK
R66CK
R26CK
R24CK

R5CK

CK_FSBSEL2

CK_14M_PA

CK_14M_ICH

CK_P_33M_ICH

CK_P_33M_1394

CK_P_33M_TPM

CK_P_33M_S2

CK_P_33M_S1

CK_P_33M_S3

CK_P_33M_PA

CK_48M_USB_ICH

CK_FSBSEL0

1

C17CK

10PF
5%
50V

2

EMPTY
402

xxxxxx

REV

R66CK
R65CK
R24CK
R26CK
R5CKR4CK
R4CK

CAD NOTE:

1

2

1

OUT

OUT

OUT

OUT

OUT

OUT

C14CK

10PF
5%
50V
EMPTY
402

PAGE REV

28

1

OUT

OUT

OUT

OUT

IN

DATE

D

C

28

IN

69

28

33

28

30

28 53

28 68

28 49

B

28 48

28 103

28 69

28

31

28

A

1

C16CK

10PF
5%
50V

2

EMPTY
402

3.01

BW_ATX_CORE

CR-29 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE29

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

CK505 ATX BLB 9-7-2006

0.0.1

1

REV

DATE

D

C

DESIGN NOTE:

STUFF C104CK AND C110CK
FOR 64 PINS CLOCK ONLY

1

2

B

A

C104CK

.1UF
20%
50V
X7R
805

1

2

47

97

47

97

8

28

C110CK

.1UF
20%
50V
X7R
805

OUT

OUT

OUT

OUT

IN

CK_H_XDP_DN

CK_H_XDP_DP

VDD_CLK_IO

CAD NOTE:

1

C105CK

.1UF
20%
50V

2

X7R
805

CK_1PORT_S1_DN

CK_1PORT_S1_DP

OUT

OUT

OUT

OUT

CK_H_MCH_DN

CK_H_MCH_DP

CK_H_CPU_DN

CK_H_CPU_DP

10

10

6

6

CAD NOTE:

1

C102CK
10UF
20%

6.3V

2

X5R
805

CK505 VDD_*_IO DCPL: PLACE (1) PER PIN

1

C106CK

.1UF
20%
50V

2

X7R
805

5%
CH

CK505 VDD_*_IO BULK DCPL: PLACE AROUND CK505

1

1

1

2

1

2

R27CK

1

R7CK

1

2

33

402

402

402

33

402

C108CK

10UF

20%

6.3V
X5R
805

C103CK

.1UF
20%
50V
X7R
805

2

33CH5%

402

R37CK

1

33

402

1

33

402

R35CK

1

33

R36CK

1

33

402

R33CK

1

33

R34CK

1

EMPTY

R30CK

5%
CH

C109CK

10UF

20%

6.3V

2

X5R
805

1

C100CK

.1UF
20%
50V

2

X7R
805

CK_PE_SRC8_R_DN

2

5%

CK_PE_SRC8_R_DP

2

5%

EMPTY

2

CK_H_MCH_R_DN

5%
CH

2

CK_H_MCH_R_DP

5%
CH

2

CK_H_CPU_R_DN

5%
CH

2

CK_H_CPU_R_DP

2

1

2

7

C111CK

10UF

20%

6.3V
X5R
805

C21CK

.1UF
10%

16V
X7R
603

D

101

101

102

102

21

22

C

21

22

10

10

33

33

98

98

31

B

31

32

32

53

98

56

A

13

17

13

17

12
20
26
45
49

36
46

47
50

51
53

54

15

19
23
42
52
29

VDD_IO
VDD_PLL3_IO
VDD_SRC_IO
VDD_SRC_IO
VDD_CPU_IO
VDD_SRC_IO

SRC8-/ITP­SRC8+/ITP+

CPU1­CPU1+

CPU0­CPU0+

VSS_IO
VSS_PLL3
VSS_SRC
VSS_SRC
VSS_CPU
VSS_SRC

1.01

U1CK

CK505_64PIN

64 PIN
PART ONLY

CPU_STOP*/SRC5­PCI_STOP*/SRC5+

SRC11-/CR_G*
SRC11+/CR_H*

SRC10­SRC10+

SRC9­SRC9+

SRC7-/CR_E*
SRC7+/CR_F*

SRC6­SRC6+

SRC4­SRC4+

SRC3-/CR_D*
SRC3+/CR_C*

SRC2-/SATA­SRC2+/SATA+

SRC1-/SE2
SRC1+/SE1

SRC0-/DOT96­SRC0+/DOT96+

2of 2

R90CK

2

CK_PE_SRC11_R_DN

CK_PE_SRC11_R_DP

CK_PE_SRC10_R_DN

CK_PE_SRC10_R_DP

CK_PE_SRC9_R_DN

CK_PE_SRC9_R_DP

CK_PE_SRC7_R_DN

CK_PE_SRC7_R_DP

32
33

35
34

31
30

43
44

40
41

37
38

28
27

25
24

22
21

18
17

14
13

CK_PE_SRC6_R_DN

CK_PE_SRC6_R_DP

CK_PE_SRC5_R_DN

CK_PE_SRC5_R_DP

CK_PE_SRC4_R_DN

CK_PE_SRC4_R_DP

CK_PE_SRC3_R_DN

CK_PE_SRC3_R_DP

CK_PE_SRC2_R_DN

CK_PE_SRC2_R_DP

CK_PE_SRC1_R_DP

CK_PE_SRC1_R_DN

IC

CK_96M_DOT_R_DN

CK_96M_DOT_R_DP

DESIGN NOTE:

96M DOT CLOCK SIGNALS: STUFF 33 OHM RES STRAPS FOR MCH GRAPHIC SKU'S
EMPTY 33 OHM SITES FOR MCH NON-GRAPHIC SKU'S

5%

EMPTY

R92CK

2

5%
CH

R94CK

2

5%
CH

R31CK

2

5%
CH

R45CK

2

5%
CH

R49CK

2

5%

EMPTY

R53CK

2

5%
CH

R52CK

5%
CH

R51CK

2

5%
CH

R41CK

2

5%

EMPTY

R39CK

2

5%
CH

R42CK

2

5%
CH

1

33

402

R91CK

2

5%

EMPTY

1

33

402

R93CK

2

5%
CH

1

33

402

R95CK

2

5%
CH

1

33

402

R32CK

2

5%
CH

1

33

402

R46CK

2

5%
CH

1

1K

402

R43CK

2

5%

EMPTY

1

33

402

R48CK

2

5%
CH

1332

402

R50CK

2

5%
CH

1

33

402

R38CK

2

5%
CH

1

33

402

1

33

402

R108CK

2

5% 22

EMPTY

1

33

402

R40CK

2

5%
CH

CK_PE_100M_LAN_2_DN

1

CK_PE_100M_LAN_2_DP

33

402

CK_1PORT_S2_DN

CK_1PORT_S2_DP

1

33

402

1

33

402

CK_PE_100M_16PORT_DN

1

CK_PE_100M_16PORT_DP

33

402

1

33

402

1

1K

402

CK_PE_100M_PATA_DN

CK_PE_100M_PATA_DP

1

33

402

1

33

402

1

33

402

1

402

1

33

402

CK_1PORT_S3_DN

CK_1PORT_S3_DP

CK_PE_100M_MCH_DN

CK_PE_100M_MCH_DP

CK_CPU_STOP_N

CK_PCI_STOP_N

CK_PE_100M_ICH_DN

CK_PE_100M_ICH_DP

CK_ICHSATA_DN

CK_ICHSATA_DP

CK_XT_24M_1394

CK_XT_25M_PATA

CK_XT_25M_LAN

CK_96M_DREF_DN

CK_96M_DREF_DP

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

[PAGE_TITLE=CK505 PAGE 2 OF 2]

BPAGE DRAWING

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Sun Mar 18 18:43:34 2007

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

29

1

3.01

CR-30 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE30

8

D

C

B

7

53103106

103

103

6

U1LB

ICH9

P_PAR

484953103106

BI

P_DEVSEL_N

48495053103106

BI

CK_P_33M_ICH

28

IN

P_PCIRST_N

484953103106

OUT

P_IRDY_N

48495053103106

OUT

P_PME_N

484953103

BI

P_SERR_N

48495053103

BI

P_STOP_N

48495053103106

BI

P_PLOCK_N

484950103

BI

P_TRDY_N

48495053103106

BI

P_PERR_N

48495053103

BI

P_FRAME_N

48495053103106

BI

P_GNT_N<3..0>

36

484953103106

OUT

P_REQ_N<3..0>

4849

50

IN

P_INTA_N

50103

IN

P_INTB_N

50103

IN

P_INTC_N

50103106

IN

P_INTD_N

5053103

IN

P_INTE_N

4849

50

IN

P_INTF_N

4849

50

IN

P_INTG_N

4849

50

IN

P_INTH_N

4849

50

IN

E3

PAR

C6

DEVSEL#

B3

PCICLK

R2

PCIRST#

J8

IRDY#

R3

PME#

K5

SERR#

F10

STOP#

H8

PLOCK#

E6

TRDY#
PERR#
FRAME#

GNT0#
GNT1#/GPIO51
GNT2#/GPIO53
GNT3#/GPIO55

REQ0#
REQ1#/GPIO50
REQ2#/GPIO52
REQ3#/GPIO54

PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

PCI

C/BE0#
C/BE1#
C/BE2#
C/BE3#

1OF6

F5

G12

H5

0
1

A7

2

C7

3

F7

K7

0

G13

1
2

F13

3

G8

J5
E1
F1
A3
K6
L7
F2 F11
G2

REV=1.00

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8

AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

45

P_AD<31..0>

C10

0

C8

1

E9

2

C9

3

A5

4

E12

5

E10

6

B7

7

B6

8

B4

9

E7

10

A4

11

H12

12

F8

13
14

C5
D2

15

E5

16

G7

17

E11

18

G10

19

G6

20

D3

21

H6

22

G5

23

C1

24
25

C2
C3

26
27

D1
J7

28

F3

29

G1

30

H3

31

P_C/BE_N<3..0>

0

G9

1
2

C4
E8

3

IC

3

BI

BI

48 49 53 103 106

48 49 53 103 106

2

MODULE REV DETAILS

MODULE NAME

ICH9

0.2.1

1

REV

DATE

08/30/06

D

C

B

J1LB

ICH6_HSK

NC_2

NC_3

C46655-001

IC

J2LB

1

A13494-008

2
3

A

HDR

1

NC_1

4

NC_4

NOTE:
NO PHYSICAL PINS

A

ON ALLEGRO MODEL

J3LB

1

NC NC

HDR

A13494-008

[PAGE_TITLE= ICH9 1 0F 6 CONTROL]

BPAGE DRAWING

frostburg_fabc.sch_1.30

Sun Mar 18 18:43:35 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

30

1

3.01

CR-31 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE31

8

CAD NOTE:

PLACE ALL NEAR ICH

IN

IN

IN

IN

IN

IN

IN

IN

CAD NOTE:

IN

IN

IN

IN

8

HSO1_DP

HSO1_DN

HSO2_DP

HSO2_DN

HSO3_DP

HSO3_DN

HSO4_DP

HSO4_DN

ATX: HSO5 ROUTE TO 2ND PCIEX1

HSO5_DP

HSO5_DN

HSO6_DP

HSO6_DN

31

D

31

31

31

C

31

31

31

B

31

31

31

BOM NO TE:

STUFF C44LB AND C45LB FOR TEST TOOL

A

31

31

1

.1UF

1

.1UF

C54LB

1

.1UF

C51LB

1

.1UF

C55LB

1

.1UF

C53LB

1

.1UF

C49LB

1

.1UF

C48LB

1

.1UF

C46LB

1

.1UF

C47LB

1

.1UF

C44LB

10V
X5R
402

C45LB

10V
X5R
402

1

.1UF

1

.1UF

10V
X5R
402

10V
X5R
402

10V
X5R
402

10V
X5R
402

10V
X5R
402

10V
X5R
402

10V
X5R
402

10V
X5R
402

C52LB

10V
X5R
402

C50LB

10V
X5R
402

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

2

TP_HSO1_DP

2

TP_HSO1_DN

2

2

2

HSO3_C_DP

2

HSO3_C_DN

2

2

2

HSO5_C_DP

2

HSO5_C_DN

2

10%

2

10%

7

HSO2_C_DP

HSO2_C_DN

HSO4_C_DP

HSO4_C_DN

HSO6_C_DP

HSO6_C_DN

7

HSI6_C_DN
HSI6_C_DP
HSO6_DN
HSO6_DP
TP_HSI1_DN
TP_HSI1_DP
HSO1_DN
HSO1_DP
HSI2_DN
HSI2_DP
HSO2_DN
HSO2_DP
HSI3_DN
HSI3_DP
HSO3_DN
HSO3_DP
HSI4_DN
HSI4_DP
HSO4_DN
HSO4_DP
HSI5_DN
HSI5_DP
HSO5_DN
HSO5_DP

R9LB

1

24.9

45

DMICOMP

2

CH

1%

52

52

52

91

91

91

98

OUT

98

OUT

OUT

OUT

47

OUT

47

OUT

OUT

OUT

OUT

TO LAN

OUT

6

IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN

IN
OUT
OUT

IN
IN

DMI_IT_MR_3_DN
DMI_IT_MR_3_DP

56

IN

56

IN

31

OUT

31

OUT

31

OUT

31

OUT

98

IN

98

IN

31

OUT

31

OUT

102

IN

102

IN

31

OUT

31

OUT

47

IN

47

IN

31

OUT

31

OUT

101

IN

101

IN

31

OUT

31

OUT

V_1P5_FILTER

CK_PE_100M_ICH_DN

IN

CK_PE_100M_ICH_DP

IN

DMI_MT_IR_0_DN

DMI_MT_IR_0_DP

DMI_IT_MR_0_DN
DMI_IT_MR_0_DP
DMI_MT_IR_1_DN

DMI_MT_IR_1_DP

DMI_IT_MR_1_DN

DMI_IT_MR_1_DP

DMI_MT_IR_2_DN
DMI_MT_IR_2_DP

DMI_IT_MR_2_DN
DMI_IT_MR_2_DP
DMI_MT_IR_3_DN
DMI_MT_IR_3_DP

402

10
10

10

10
10
10

10

10
10
10
10
10

10
10
10

OUT

10

OUT

102

102

323438

IN

29
29

101

101

56

56

[PAGE_TITLE=ICH9 2 OF 6 CONTROL]

6

5

4 2

W28
W26
V30

V29
AA26
AA28

Y30

Y29
AC26
AC28
AB30
AB29
AF26
AE26
AD29
AD30

D29

D30

E26

E28

P30

P29

R26

R28

M30

M29

N26

N28

K30

K29

L26

L28

H30

H29

J26

J28

F30

F29

G26

G28
AF28

AF30

U26

U25

USB_OC_FRONT1_N

IN

USB_OC_FRONT3_N

IN

USB_OC_FRONT2_N

IN

USB_OC_BACK1_N

IN

USB_OC_BACK0_N

IN

USB_OC_BACK2_N

IN

U1LB
ICH9

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP
PERn1
PERp1
PETn1
PETp1
PERn2
PERp2
PETn2
PETp2
PERn3
PERp3
PETn3
PETp3
PERn4
PERp4
PETn4
PETp4
PERn5
PERp5
PETn5
PETp5

DMI_IRCOMP
DMI_ZCOMP

DMI_CLKN
DMI_CLKP

REV=1.00

DMI

PCI-E

BPAGE DRAWING

frostburg_fabc.sch_1.31

Sun Mar 18 18:43:36 2007

3

USB

OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#/GPIO44

OC9#/GPIO45
OC10#/GPIO46
OC11#/GPIO47

USBRBIAS#

USBRBIAS

I86

I87

I89

I90

I99

I140

3

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N

USBP9P
USBP10N
USBP10P
USBP11N
USBP11P

CLK48

2OF6

I92

I139

I141

IC

I85

I84

I88

2

AD6
AD5
AE3
AE2
AD1
AD2
AB6
AB5
AC3
AC2
AB1
AB2
Y6
Y5
AA3
AA2
Y1
Y2
V6
V5
W2
W3
V1
V2

USB_OC0_R_N

P5

USB_OC1_R_N

N3

USB_OC2_R_N

P7

USB_OC3_R_N

R7

USB_OC4_R_N

N2
N1

USB_OC5_R_N

N5

USB_OC6_R_N
USB_OC7_R_N

M1
P3

USB_OC8_R_N

R6

USB_OC9_R_N

T7

USB_OC10_R_N

P1

USB_OC11_R_N

AG1

USBRBIAS_ICH

AG2

CK_48M_USB_ICH

AG3

USB_OC0_R_N

USB_OC1_R_N

USB_OC2_R_N

USB_OC3_R_N

USB_OC4_R_N

USB_OC5_R_N

USB_OC6_R_N

USB_OC7_R_N

USB_OC8_R_N

USB_OC9_R_N

USB_OC10_R_N

USB_OC11_R_N

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

MODULE REV DETAILS

MODULE NAME

ICH9

USB_FRONT1_DN
USB_FRONT1_DP
USB_FRONT2_DN
USB_FRONT2_DP
USB_FRONT5_DN
USB_FRONT5_DP
USB_FRONT6_DN
USB_FRONT6_DP
USB_FRONT4_DN
USB_FRONT4_DP
USB_FRONT3_DN
USB_FRONT3_DP

USB_BACK6_DN
USB_BACK6_DP
USB_BACK5_DN
USB_BACK5_DP
USB_BACK4_DN
USB_BACK4_DP
USB_BACK2_DN
USB_BACK2_DP
USB_BACK3_DN
USB_BACK3_DP
USB_BACK1_DN
USB_BACK1_DP

0.2.1

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN

IN

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

IN

IN

31

OUT

31

OUT

31

OUT

31

OUT

31

OUT

31

OUT

31

OUT

31

OUT

31

OUT

31

OUT

31

OUT

31

OUT

DOCUMENT_NUMBER

xxxxxx

REV

42
42
42
42
44
44
44
44
43
43
43
43
46
46
46
46
45
45
45
45
46
46
46
46

31

31

31
31
31
31
31
31
31
31
31
31

37

28

1

PAGE REV

31

1

DATE

08/30/06

D

C

B

A

3.01

CR-32 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE32

8

V_3P3_STBY\G

R301LB

1

10K
5%

EMPTY

2

402

R209LB

1394_EN

32

53

D

IN

DESIGN NOTE:

STUFF FOR DMI TERMINATION STRAP (DEFAULT)
DO NOT EMPTY

1

2.2K
402

C

76

DESIGN NOTE:

DEFENSIVE PURPOSE

B

2

MODULE REV DETAILS

MODULE NAME

ICH9 0.2.1

SER_IRQ

32

6869

OUT

OUT

OUT

A20GATE

KBRST_N

32

69

32

69

R248LB

1

10K
CH

1

R249LB

10K 5%
402

1

R250LB

10K
402

AK17
AJ17
AK19
AJ19
AJ15
AK15
AH16
AF16
AJ13
AK13
AH14
AF14
AJ11
AK11
AF12
AH12

AJ9
AK9
AF10
AH9

AJ7
AK7
AF8
AH7
AF18
AF19

AE7
AK6
AJ6

AK25
AE20
AE21
AE22
AF22
AD21

P8
AJ28

AC22
M3
AE23
AH27
AJ27
AF24
L3
N6
AH26
AJ29
AD24
AC23

45

SATAHDR_RX0_DN
SATAHDR_RX0_DP
SATAHDR_TX0_DN
SATAHDR_TX0_DP
SATAHDR_RX1_DN
SATAHDR_RX1_DP
SATAHDR_TX1_DN
SATAHDR_TX1_DP
SATAHDR_RX2_DN
SATAHDR_RX2_DP
SATAHDR_TX2_DN
SATAHDR_TX2_DP
SATAHDR_RX3_DN
SATAHDR_RX3_DP
SATAHDR_TX3_DN
SATAHDR_TX3_DP

SATAHDR_RX4_DN
SATAHDR_RX4_DP
SATAHDR_TX4_DN
SATAHDR_TX4_DP

SATAHDR_RX5_DN
SATAHDR_RX5_DP
SATAHDR_TX5_DN
SATAHDR_TX5_DP

CK_ICHSATA_DN
CK_ICHSATA_DP

ICH_SATA_LED_N

SATARBIAS_ICH

SATA0GP
SATA1GP
SATA2GP

GP37_MFG_MODE_N

SATA4GP
SATA5GP

A20GATE

H_A20M_N

H_IGNNE_N

TP_ICH_INIT_V_3P3

H_INIT_N

H_INTR

H_FERR_N

KBRST_N
SER_IRQ

ICH_H_SMI_N

H_STPCLK_ICH_N

H_THERMTRIP_N

H_PECI_ICH

H_NMI

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

IN
IN
IN
IN
IN
IN

IN

IN
IN

IN
BI

IN
IN
OUT
OUT

OUT
OUT
IN
IN

OUT

7

102 103 105
92122 28

IN

59

2

5%
CH

MCH_CLPWROK_R

13

IN

1

C203LB
220PF

50V
X7R

2

402

SST_CTL

BI

1

C128LB
220PF

10%
50V
EMPTY

2

402

33 34 36 37 38 394748 49 53

64 6970828485 868788 90 92

V_1P5_FILTER

31

3438

IN

13

BI

39

IN

13

BI

39

IN

39

IN

39

IN

13

10%

OUT

105

77

OUT

77

105

OUT

104

77

OUT

77

IN

77

IN

77

IN

36

104

IN

36

IN

36

IN

36

IN

36

IN

32

53

OUT

6

R10LB

2

1

24.9

1%

CH

402

CL_N_CLK
TP5_DEBUG
CL_N_DATA
TP4_DEBUG
CL_N_VREF_ICH
TP6_DEBUG

TP7_DEBUG
CL_RST

CPU_FAN_CTRL
FNT_REAR_FAN_CTRL
REAR_FAN_CTRL

CPU_FAN_TACH
FRONT_FAN_TACH
REAR_FAN_TACH

ICH_GP7_PU

ICH_SGP22_PU
ICH_SGP38_PU
ICH_SGP39_PD
ICH_SGP48_PU
1394_EN

101

GLAN_BIAS

A29
B29
G22
C18
H21
E19
C27
A16

T6
B16
G20

AJ21
AJ22
AK22

AH21
AK21
AH22
AK23

C19

AJ24
AK24
AH23

SDATAOUT0/GPIO39

AD20

SDATAOUT1/GPIO48

AJ25

GLAN_COMPO
GLAN_COMPI
CL_CLK0
TP5
CL_DATA0
TP4
CL_VREF0
TP6
CLPWROK
TP7
CL_RST0#

PWM0
PWM1
PWM2

TACH0/GPIO17
TACH1/GPIO1
TACH2/GPIO6
TACH3/GPIO7

SST

SCLOCK/GPIO22
SLOAD/GPIO38

GPIO49

U1LB

ICH9

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP

SATA

SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN

SATA5TXP
SATA_CLKN
SATA_CLKP

SATALED#

SATARBIAS#

SATARBIAS

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA3GP/GPIO37

SATA4GP
SATA5GP

A20GATE

IGNNE#

HOST

INIT3_3V#

SERIRQ

STPCLK#

THRMTRIP#

A20M#

INIT#

INTR

FERR#

NMI

RCIN#

SMI#

PECI

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN

41
41

41

41
41
41

41

41
41
41

41

41
41
41

41

41

41
41

41

41

41
41

41

41

29

29

36

37

36
36
36
36 37
36
36

32

69

6

6

6
6
68
6
32

69
326869
6
33
68

105

3

70

1

REV

DATE

08/30/06

D

VCC3

2

5%

402

2

CH

2

5%
CH

C

B

A

[PAGE_TITLE=ICH9 3 OF 6 CONTROL]

8

7

REV=1.00

3OF6

IC

A

BPAGE DRAWING

frostburg_fabc.sch_1.32

Sun Mar 18 18:43:38 2007

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

32

1

3.01

CR-33 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE33

8

D

C

SPI_MOSI

33

IN

SPI_CLK

33

IN

SPI_CS0_N

33

IN

B

BOM NO TE:

STUFF TO ENABLE NO-REBOOT OPTION AT
POWER-UP (CONFIGURATION STRAPPING).

60

A

SPKR

3337

IN

8

VCC3

1

2

7

CAD NOTE:

PLACE AT ICH

DESIGN NOTE:

DO NOT STUFF CIRCUIT. INTERNAL PULL-UP EXIST IN ICH9.

CAD NOTE:

PLACE 15 OHM SERIES STRAPS CLOSE TO ICH

R158LB

SPI_MOSI_PRI_SEC_FLSH

2

1

1%15

CH

402

R159LB

SPI_CLK_PRI_SEC_FLSH

2

1

15 1%

CH

402

R17LB

1K

5%
EMPTY

402

1

1K

402

R18LB

R201LB

1

47

402

2

5%
CH

2

5%
CH

CORE_SPKR_R

1

C1LB

1000PF
10%
50V

"X7R"

2

EMPTY
603

SPI_CS0_ISOLATE_N

1

7

102103105
102103105

OUT

OUT

OUT

VCC

2

1

2

70101
70101

3

Q1LB

MMBT3904
XSTR

SPKR_OUT_R

R16LB

47
5%

EMPTY
402

6

VCC3

1

R270LB

10K

5%
EMPTY

402

2

69

IN

64
64

64
64

40

40

40

27

28474849

27

28474849

VCC3

1

R15LB

10K
5%

EMPTY
402

2

L_DRQ1_N

L_AD<3..0>

6869

IN

L_FRAME_N

6869

OUT

37
37
37
37
3651

IN

OUT

IN
IN
IN

OUT
OUT

IN

21
21
36

33
40
33
33
36

56

56

39

56

56

56
56
56
56

OUT

IN
IN

36
36

AUD_LINK_BCLK_R
AUD_LINK_RST_R_N
AUD_LINK_SDI0

AUD_LINK_SDI1

AUD_LINK_SDI2
TP_AUD_LINK_SDI 3
AUD_LINK_SDO_R
AUD_LINK_SYNC_R
CK_14M_ICH

ICH_LAN_JCLK

IN

ICH_LAN_JRST

OUT

LAN_PWROK

IN

ICH_LAN_JRX0

IN

ICH_LAN_JRX1

IN

ICH_LAN_JRX2

IN

ICH_LAN_JTX0

OUT

ICH_LAN_JTX1

OUT

ICH_LAN_JTX2

OUT

ICH_RTCX1

IN

ICH_RTCX2

ICH_RTCRST_PULLUP

ICH_SRTCRSTB_PULLUP

ICH_PORT80_LED

IN

SMB_CLK_RESUME

BI

SMB_DATA_RESUME

BI

SMLALERT_ICH

IN

SMLINK0_ICH

IN

SMLINK1_ICH

IN

SPI_MOSI

OUT

SPI_MISO

IN

SPI_CS0_N

OUT

SPI_CLK

OUT

SPI_CS1_N

OUT

37
37
64
64
60

3637
3637
28

22
22

L_DRQ_N

J3

LDRQ1#/GPIO23

0

K3

FWH0/LAD0

H1

1

FWH1/LAD1

M7

2

FWH2/LAD2

J1

3

FWH3/LAD3

L6

LDRQ0#

L5

FWH4/LFRAME#

AH3

HDA_BIT_CLK

AJ1

HDA_RST#

AK3

HDA_SDIN0

AH4

HDA_SDIN1

AH1

HDA_SDIN2

AJ3

HDA_SDIN3

AJ2

HDA_SDOUT

AK1

HDA_SYNC

M5

CLK14

F25

GLAN_CLK

E14

LAN_RSTSYNC

C21

LAN_RST#

G15

LAN_RXD0

H14

LAN_RXD1

E13

LAN_RXD2

F15

LAN_TXD0

F14

LAN_TXD1

G14

LAN_TXD2

A21

RTCX1

B21

RTCX2

A25

RTCRST#

H20

SRTCRST#

C16

SMBALERT#/GPIO11

H16

SMBCLK

E16

SMBDATA

F18

LINKALERT#/GPIO60/CLGPIO4

A15

SMLINK0

B15

SMLINK1

C26

SPI_MOSI

B26

SPI_MISO

E25

SPI_CS0#

G23

SPI_CLK

F23

SPI_CS1#/GPIO58/CLGPIO6

45

U1LB
ICH9

LPC

AUDIO

S4_STATE#/GPIO26
QRT_STATE0/GPIO27
QRT_STATE1/GPIO28

SATACLKREQ#/GPIO35

LAN

RTC

SMB

SPI

WOL_EN/GPIO9

ALERT#/GPIO10

GPIO14/CLGPIO2

GPIO24/CLGPIO0

GPIO57/CLGPIO5

CPUPWRGD

LAN100_SLP

VRMPWRGD

MCH_SYNC#

SUS_STAT#/LPCPD

MISC

SYS_RESET#

INTRUDER#

INTVRMEN

CK_PWRGD

4OF6

REV=1.00

R283LB

2

1

0

R280LB

5%

EMPTY

EMPTY

1

5%

H_SKTOCC_N

Sun Mar 18 18:43:39 2007

6

2

30

402

R309LB

ICH9_MGP1

33

LS1LB

SPKR_OUT

1

5%
CH

2

J8LB

EMPTY

1X2HDR

1

1
2

XDCR

+

AT-08

IN

58
40

5

OUT

DESIGN NOTE:

STUFF R283LB FOR ME ON CPU PRESENT DETECTION

56

57

V_3P3_EPW

272834

IN

3839

8892

DESIGN NOTE:

STUFF TO ENABLE ITPM

402

2

10K
402

4 2

3

N7

GPIO0

A20

GPIO8

A18
C17

THRM#

RI#

WAKE#

PWROK

SPKR

TP0
TP1
TP2
TP3

A8
A19
A9
C15
M2
K1
AF5
A14
B18
C11
A11
G18
K2
AF6
AH5
L1
F16

TP_SATA_HOT_SWAP_POWER_CTRL

C12
AD23
E21
AK26
C22
AH25
T3
G19
R1
R5
F19
C14
E20
G21
C25
F22

ICH_INTVRMEN

E23

SPKR

N8
A13

B13
G17
F17
T8
C13
AK28
AE24
F20

GPIO12
GPIO13

GPIO15
GPIO16
GPIO18
GPIO20

GPIO25

GPIO32
GPIO33
GPIO34

GPIO56

PWRBTN#

SUSCLK

PLTRST#

RSMRST#

SLP_S3#
SLP_S4#
SLP_S5#

SLP_M#

IC

IN

SPI_MOSI

BPAGE DRAWING

frostburg_fabc.sch_1.33

OUT

33

3

FP_AUD_DETECT

TPEV_ICH_GPIO8

WOL_ONLY

ICH9_MGP1

LAN_DISABLE_N
IO_PME_N
1_WATT_CTRL_2
CK_PCI_STOP_N
BOARDID<0>
BOARDID<1>
TP_ICH_GP20
GPIO_VSM_AMT_LED

CK_CPU_STOP_N

S4_STATE_N
ICH_QRT0
ICH_QRT1

CDC_DWN_DISABLE
GP33_SOP
ICH_CONFIG_JUMPER
2X12_POWER_DETECT
ICH_GP56

H_PWRGD
ICH_LAN100SLP_EN

ICH_THRM_N

ICH_VRMPWRGD
ICH_SYNC_R_N
SW_ON_N
ICH_RI_PU
LPCPD_N
SUSCLK
FP_RST_N
PLTRST_N_R
WAKE_N

ICH_INTRUDER_HDR_N
PWRGD_3V
ICH_RSMRST_N

SLP_S3_ICH_N
SLP_S4_N
TP_SLP_S5_N
ICH_SLP_M_N

CK_PWRGD

ICH_BATLOW_PU
TP_DPRSTP
TP_DPSLP_N

TP_DFXTEST_N

3339

6
70

13

32

2

MODULE REV DETAILS

MODULE NAME

ICH9

V_3P3_STBY\G

2

CH

R281LB

1

10K 5%

R11LB

1

0

2

5%
CH

2

5%
CH

2

ICH_SYNC_R_N

5%
CH

2

H_STPCLK_N

1A

CH

1

2

SLP_S3_N

402

PLTRST_N

C202LB
100PF
5%
50V
EMPTY
402

VCC3

OUT

IN

IN

IN

OUT

IN
IN
IN
IN
IN
IN

OUT

OUT

IN

IN

37

IN

135370

IN

39

IN

37

IN

33 37

33 39

OUT

80

OUT

39

OUT

28

OUT

36

IN

SLP_S3_ICH_N

ICH_SYNC_N

H_STPCLK_ICH_N

IN

IN

OUT
OUT

OUT
OUT

IN
IN

OUT
OUT
OUT
OUT
OUT
OUT

IN
IN
IN

OUT

68
37
37
39
33
51
36

7
51

70

36

64

36

33

56

36

89
29
37
37

80

36
29
70
51
51
59
37
37
90

36 37

68

69

69

R217LB

36

70 97

1

0

402

60

402

R12LB

1

0

402

R14LB

1

0

603

[PAGE_TITLE=ICH9 4 OF 6 - CONTROL]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

1

2

0.2.1

2

R313LB

1

10K 5%

R222LB

1K

5%
EMPTY

402

REV

EMPTY

402

OUT

OUT

OUT

1

IN

OUT

IN

OUT

70

33

6

PAGE REV

33

1

DATE

08/30/06

86
70
53 59
39
34 36
92122
28
37 38
48 49
64 69
84 85
92
102 103
105

37

69

136869
98

3.01

87
82

47

90

32

88

D

101

88

C

B

A

CR-34 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE34

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

ICH9 0.2.1

1

REV

DATE

08/30/06

D

V_1P5_STBY_INT

3438

IN

V_1P05EP_INT

38

IN

3738

9212228

7

84

9

OUT

3738
3738

9
3438
34

34

IN

9

IN

38

IN

38

IN

38

IN

9212228

IN
IN

31

IN

31

IN
IN

9

IN

9

IN

V_3P0_BAT_VREG

IN

V_3P3_STBY\G

IN

V_3P3_EPW_R

IN

V_FSB_VTT

IN

V_1P05_ICH_CORE

IN

V_1P5_ICH

IN

V_1P05_VCCAUX

V_REF5V

IN

V_REF5V_SUS

IN

V_1P5_ICH

IN

V_1P5_CL_INT

IN

V_AZSUS

IN

V_AZCORE
V_1P5_ICH
VCCSATA_PLL_ICH
VCCDMI_PLL_ICH
GLCI_PLL
V_3P3_STBY\G
V_3P3_EPW
V_1P5_FILTER
V_1P5_FILTER
V_1P25_CORE
V_1P5_ICH
V_1P5_ICH

VCC3

TP_V_1P05_B_STBY

TP_V_1P05_A_STBY

U1LB

ICH9

H24

H23

Vcc1_05

VCC1_05

VccSus3_3

AF2

J23

Vcc1_05

M12

M13

Vcc1_05

VccCL3_3

B23

C23

M15

Vcc1_05

Vcc1_05

VccCL3_3

M17

M18

Vcc1_05

Vcc1_05

VccGLAN1_5

VccGLAN1_5

C29

C30

M19

Vcc1_05

VccGLAN1_5

C28

AA7

B10

A10

AB7

AB8T1AC14

AC15

AC16

A24

B24

F24

E24

C24

VccUSBPLL

AK5

Vcc1_05

Vcc1_05

VccSATAPLL

AK20

Vcc1_05

T30

Vcc1_05

Vcc1_05

VccDMIPLL

G24

Vcc1_05

VccGLANPLL

A28

AA8

Vcc1_5_A

Vcc1_5_A

Vcc1_5_A

Vcc1_5_A

VccLAN1_05

VccLAN1_05

Vcc1_5_A

Vcc1_5_A

Vcc1_5_A

Vcc1_5_A

V5REF_Sus

V5REF

A6

AF1

H10

H11

Vcc1_5_A

AC11

AB23

AC18

Vcc1_5_A

AC20

VccCL1_5

A26

VccSusHDA

AC9

Vcc1_5_A

VccHDA

Vcc3_3

AC10

AD10

Vcc3_3

AC19

Vcc1_5_A

Vcc1_5_A

Vcc3_3

Vcc3_3

AH24

AC21

AF21

Vcc1_5_A

Vcc3_3

N19

N12

Vcc1_05

VccGLAN1_5

B30

R12

Vcc1_05

Vcc1_05

Vcc1_5_B

AA23

U12

R19

U19

Vcc1_05

Vcc1_05

Vcc1_5_B

Vcc1_5_B

AA24

AB24

AA25

V12

Vcc1_05

Vcc1_05

Vcc1_5_B

Vcc1_5_B

AB25

W12

V19

Vcc1_05

Vcc1_05

Vcc1_5_B

Vcc1_5_B

AD25

AC25

W13

W15

Vcc1_05

Vcc1_05

Vcc1_5_B

Vcc1_5_B

AD26

AD28

W19

W17

W18

Vcc1_05

Vcc1_05

Vcc1_5_B

Vcc1_5_B

AE30

AE29

AE28

AH28

Vcc1_05

Vcc1_5_B

Vcc1_5_B

J24

J25

AJ30

V_CPU_IO

V_CPU_IO

Vcc1_5_B

Vcc1_5_B

Vcc1_5_B

K23

K24

AK4

AH30

Vcc3_3

Vcc3_3

Vcc1_5_B

Vcc1_5_B

K25

L24

A27

VccGLAN3_3

Vcc1_5_B

L25

A2B9G11

Vcc3_3

Vcc1_5_B

Vcc1_5_B

M24

M23

B1

Vcc3_3

Vcc3_3

Vcc1_5_B

Vcc1_5_B

N24

M25

H7

G3

Vcc3_3

Vcc3_3

Vcc1_5_B

Vcc1_5_B

N25

P23

P24

K8

J2

Vcc3_3

Vcc3_3

Vcc3_3

Vcc1_5_B

Vcc1_5_B

Vcc1_5_B

R24

P25

L8

Vcc3_3

Vcc1_5_B

Vcc1_5_B

T23

R25

Vcc1_5_B

Vcc1_5_B

T24

T25

A12

B12

VccLAN3_3

VccLAN3_3

Vcc1_5_B

Vcc1_5_B

T26

T28

Vcc1_5_B

Vcc1_5_B

U24

U28

U1

VccSus3_3

VccSus3_3

Vcc1_5_B

Vcc1_5_B

U29

V23

U30

VccSus3_3

VccSus3_3

Vcc1_5_B

Vcc1_5_B

V25

V24

VccSus3_3

VccSus3_3

Vcc1_5_B

Vcc1_5_B

W25

W24

V8U8U7U6U5U3U2

VccSus3_3

VccSus3_3

Vcc1_5_B

Vcc1_5_B

Y23

W7

Y8

W8

VccSus3_3

VccSus3_3

Vcc1_5_B

Vcc1_5_B

Y24

Y25

VccSus3_3

A17

VccSus3_3

B20

VccSus3_3

C20

VccSus3_3

VccDMI

AG29

E17

VccSus3_3

VccDMI

AG30

H15

VccSus3_3

A22

VccRTC

Vcc1_5_A

Vcc1_5_A

AC13

AD11

H17

AC7

VCCSUS1_05

VCCSUS1_05

Vcc1_5_A

Vcc1_5_A

AE11

AD13

AD12

A23

VccCL1_05

Vcc1_5_A

Vcc1_5_A

Vcc1_5_A

AH10

AF11

H18

VCCSUS1_5

Vcc1_5_A

Vcc1_5_A

AH11

AJ10

AD8

VCCSUS1_5

Vcc1_5_A

Vcc1_5_A

AC17

AK10

Vcc1_5_A

Vcc1_5_A

AD17

AE17

Vcc1_5_A

Vcc1_5_A

AH17

AF17

Vcc1_5_A

Vcc1_5_A

AH18

AJ18

Vcc1_5_A

AK18

5OF6

MATERIAL=IC

REV=1.00

VCC3

92

90

85

86

84
59

64

69

39

47

48

333436

V_3P3_STBY\G

92122

IN

28

32

37

38

49

53

70

82

87

88

101
102
103
105

U1BC

MIC5235

1

IN

3

EN

2

GND

ADJ
OUT

4
5

EMPTY

TP_U1BC_PIN4

V_1P5_STBY

C8BC

2.2UF
10%

6.3V

EMPTY

603

R26BC

1

2

V_1P5_STBY_INT

1A

0

EMPTY

603

1

R24BC

2

1

0

603

2

1A

EMPTY

V_1P5_CL_INT

OUT

OUT

34
38

34
38

VCC3

R311LB

2

R310LB

2

1

5%

0

CH

402

C204LB

.1UF

10%
16V

EMPTY

603

7

OUT

1

2

6

1

0

402

5%
CH

V_AZCOREV_AZSUS

C205LB

EMPTY

5

.1UF

3434

OUT

1

10%
16V

2

603

4 2

BPAGE DRAWING

frostburg_fabc.sch_1.34

Sun Mar 18 18:43:40 2007

3

[PAGE_TITLE=ICH 5 OF 6 - CONTROL]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

34

1

90

82

848586

8788

9092

323334363738

47

484953

59

6469

70

85

39
101

102103105

89141738

3438

829298

38

C

B

3438

829298

3438

829298

9092

101

102103105

8687

88

53

5964

4056

57

58

A

2138

76

82

102103105

87

88

8586
53596469

36373839

9212228

323334

47

4849

70

8284

101

9092

3233343637
4849

IN

69

70

828485
47

3839

323438
323438

3438

829298

3438

829298

V_3P3_STBY\G

2728333839
8892

1314161718
838698105

8

D

C

B

A

3.01

CR-35 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE35

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

0.2.1ICH9

DATE

08/30/06

D

C

F9F6F28

G30

G29

F21

G25

G16

F26

E15

D28B8B5

E22

E29

E2

E30

F12

B25

B28B2B22

E18

B19

B17

AK2

AK14

AJ8

AK8

AK12

AK30

AK29

AK16

AJ26

AJ20

AH6

AH8

AH2

AH20

AH19

AH13

AH15

AF7

AF9

AG28

AF25

AF15

AF20

AF23

AE9

AF13

AE8

AE5

AE6

AE19

AE25

AE18

AE16

AE15

AE12

AE13

AE14

AE1

AE10

AD3

AD9

AD7

AD19

AD22

AD15

AD18

AD16

AC8

AC30

AC24

AC29

AJ12

AJ14

AJ16

AJ23

AJ5

AF29

AD14

AC6

AC5

AC12

B14

B11

AC1

AB3

AA30

AA1

A30

A1

AA29

AA6

AB28

AB26

AA5

D

C

IC

Vss

Vss

Vss

Vss

Vss

VSS_102

VSS_100

VSS_101

VSS_103

VSS_104

VSS_105

VSS_106

VSS_107

VSS_108

VSS_109

VSS_110

VSS_111

VSS_113

VSS_115

VSS_114

VSS_092

VSS_093

H9

H28

VSS_091

J29

VSS_090

J30

VSS_089

J6

VSS_088

K26

VSS_112

VSS_087

K28

VSS_086

L2

L23

VSS_085

VSS_084

L29

U1LB

ICH9

VSS_095

VSS_098

VSS_094

VSS_096

VSS_097

VSS_099

H26

H25

H22H2H19

B

H13

VSS_116

VSS_083

L30

VSS_117

VSS_082

M14

VSS_118

VSS_081

M16

VSS_119

VSS_080

M26

VSS_121

VSS_120

VSS_079

VSS_078

M6

M28

VSS_122

VSS_077

M8

VSS_123

VSS_076

N13

VSS_124

VSS_075

N14

VSS_125

VSS_074

N15

VSS_126

VSS_073

N16

VSS_127

VSS_072

N17

VSS_129

VSS_128

VSS_070

VSS_071

N23

N18

VSS_130

VSS_069

N29

VSS_131

VSS_068

N30

VSS_132

VSS_067

P12

VSS_133

VSS_134

VSS_066

VSS_065

P14

P13

VSS_135

VSS_064

P15

VSS_136

VSS_063

P16

P17

VSS_139

VSS_138

VSS_137

VSS_061

VSS_062

VSS_060

P18P2P28

P19

VSS_140

VSS_141

VSS_058

VSS_059

P26

VSS_143

VSS_142

VSS_057

VSS_056

P6

VSS_144

VSS_055

R13

VSS_145

VSS_146

VSS_053

VSS_054

R15

R14

VSS_147

VSS_052

R16

VSS_148

VSS_051

R17

VSS_149

VSS_050

R18

VSS_151

VSS_150

VSS_048

VSS_049

R29

R23

VSS_153

VSS_152

VSS_046

VSS_047

VSS_154

VSS_045

T12R8R30

VSS_155

VSS_044

T13

VSS_156

VSS_043

T14

VSS_158

VSS_157

VSS_042

VSS_041

T15

T16

VSS_159

VSS_040

T17

VSS_160

VSS_039

T18

VSS_161

VSS_038

T2

T19

VSS_162

VSS_163

VSS_037

VSS_036

T29T5U13

VSS_165

VSS_164

VSS_035

VSS_034

VSS_166

VSS_033

U14

VSS_167

VSS_032

U15

U16

VSS_169

VSS_168

VSS_030

VSS_031

U17

VSS_170

VSS_029

U18

VSS_171

VSS_028

U23

VSS_172

VSS_173

VSS_026

VSS_027

V14

V13

VSS_174

VSS_025

V15

VSS_175

VSS_024

V16

VSS_176

VSS_023

V17

VSS_177

VSS_022

V18

VSS_178

VSS_021

V26

VSS_179

VSS_020

V3

V28

VSS_181

VSS_180

VSS_018

VSS_019

V7

VSS_182

VSS_017

W1

VSS_183

VSS_016

W14

VSS_184

VSS_015

W16

VSS_185

VSS_186

VSS_013

VSS_014

W23

W29

VSS_187

VSS_012

W30

VSS_188

VSS_011

W6

W5

VSS_190

VSS_189

VSS_009

VSS_010

Y26

VSS_191

VSS_008

Y28

VSS_192

VSS_007

Y3

VSS_193

VSS_006

Y7

VSS_005

AK27

AH29

VSS_003

VSS_004

AJ4

VSS_002

AF3

VSS_001

B27

6OF6

REV=1.00

B

A

A

[PAGE_TITLE=ICH 6 OF 6 - GROUND BODY]

BPAGE DRAWING

frostburg_fabc.sch_1.35

Sun Mar 18 18:43:41 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

35

1

3.01

CR-36 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE36

8

D

BOOT SELECT STRAPS

7

6

BOM NO TE:

47

4849

8687

8890

DEFAULT EMPTY: STUFF 10K OHM RES (R54LB) FOR ICH PORT80 LED FEATURE (TDE EXPERIMENT)

70

828485

1

BOM NO TE:

STUFF FOR
PRODUCT

P_GNT_N<3..0>

3036

484953103106

OUT

SPI_CS1_N

33

OUT

0

R34LB

2

1K

5%
CH

402

R32LB

2

1K

4025%EMPTY

1

1

2

32333436373839

R198LB

10K

5%
CH

402

101

102103105

45

92
9212228

IN

53596469

1

1

R54LB2R51LB

10K
5%

CH
402

2

V_3P3_STBY\G

10K
5%

CH
402

1

2

R53LB

10K

5%
CH

402

3

1

1

1

R55LB

R52LB

10K

10K

5%

5%

CH

CH

402

2

402

2

1

R50LBCHR49LB

1K

5%
402

2

2

VCC3

C

2

1

1

1

1

1

1

1

1

R46LB

VCC3

2

R29LB

3.24K
1%

EMPTY

402

1

B

R30LB

2

5%

EMPTY

1

1K

402

R31LB

1

5%

EMPTY

2

R33LB

3.24K
1%

EMPTY

402

1

AUD_LINK_SDO_R

AUD_LINK_SYNC_R

P_GNT_N<3..0>

2

2

1

1K

402

OUT
OUT
OUT

33 37

33 37

30 36
106

64

64

48 4953103

10K

5%
CH

402

1

2

R47LB

10K

5%
CH

402

R35LB

R36LB

R37LB

10K
5%

CH
402

R38LB R39LB

10K
5%

CH
402

2

10K

10K

5%

5%
CH

CH

402

402

2

2

2

R210LB

10K

10K

5%

5%

CH

CH

402

402

2

2

1

R40LB

R41LB R45LB

10K

10K

5%

5%

CH

EMPTY

402

2

402

2

R19LB

1

10K

5%

2

EMPTY
402

2

MODULE REV DETAILS

MODULE NAME

1

1

R44LB

10K

10K

5%

5%

CH

CH

402

402

2

1

1

10K

5%
CH

402

2

2

1

R28LB

220
5%

CH
402

2

2

ICH_PORT80_LED
ICH_RI_PU

1

R42LB2R43LB

10K

10K

5%

5%

CH

CH

402

402

ICH_GP7_PU
ICH_SGP22_PU
ICH_SGP38_PU
ICH_SGP39_PD
ICH_SGP48_PU

R48LB

10K

5%
CH

402

TPEV_ICH_GPIO8

FP_RST_N
ICH_GP56
1_WATT_CTRL_2

WAKE_N

ICH_BATLOW_PU

SMLALERT_ICH
SMLINK0_ICH
SMLINK1_ICH

1

REV

0.2.1ICH9

DATE

08/30/06

D

33

OUT

7

33 51
97
33 37

33

89

212233
98

101

33
33
33
33
33 51
33

104

70

47

102

C

OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

32
32
32
32
32

B

SATA4GP

SATA5GP
SATA0GP
SATA1GP
SATA2GP

GP37_MFG_MODE_N

FP_AUD_DETECT

ICH_SATA_LED_N

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

32
32
32
32
32
32 37
33
32

64
70

V_3P3_STBY\G

IN

A

GPIO_VSM_AMT_LED

33

IN

80

[PAGE_TITLE=GPIO TERMINATION & RST STRAPS]

8

7

6

5

1

2

1

2

R229LB

10K

5%
CH

402

R230LB

2.7K
5%

EMPTY
402

DESIGN NOTE:

DEFAULT: CRYPTO ENGINE ENABLED

STUFF PU (R229LB) AND UN-STUFF PD (R230LB)

4 2

BPAGE DRAWING

frostburg_fabc.sch_1.36

Sun Mar 18 18:43:43 2007

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

36

1

A

3.01

CR-37 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE37

8

CAD NOTE:

VCC3

ONLY ROUTE BID<1..0>, NEED TO CLEAN UP SIO

R78LB

D

1

2

1
2

10K

5%
EMPTY

402

R79LB

10K

5%
EMPTY

402

R67LB

1

10K
5%

2

EMPTY
402

0

1

1

R66LB
10K
5%

2

EMPTY
402

7

BOARDID<1..0>

OUT

6

33

BOARD ID STRAPS

80

C

73
69

V_5P0_STBY\G

51

IN

66
70
74
88
89
90
91
92

102
90
86

70

82

IN

64

47

4849

333436

92122

32

28

3839

5359

70

69
8485
87

88

B

92

101

103105

34 38

OUT

V_REF5V_SUS

V_REF5V_SUS_SIO

V_3P3_STBY\G

IN

OUT

V_REF5V

V_REF5V_SIO

70

IN

V_3P0_BAT_VREG

3437

IN

38

90

A

DESIGN NOTE:

INTVRMEN: ALWAYS STUFF TO ENABLE INTERNAL VRM
LAN100SLP: ALWAYS STUFF TO ENABLE INTERNAL LAN VRM
EXTERNAL VRM IS NOT SUPPORTED

DESIGN NOTE:

STUFF R212LB TO BYPASS
THERMAL EVENT REPORTING
FEATURE (DEFAULT EMPTY)

0-OHM RESISTOR (R212LB) IS IN PLACE SHOULD THE ICH BE MODIFIED TO INCLUDE THRMB PIN ON THE VTT WELL (ON-DIE)

68

IN

95

DESIGN NOTE:

H_PROCHOT_N

8

R219LB

VCC3

390K

402

390K

402

34
38

2

2

10K

402

10K

402

10
5%

CH

402

VCC

R82LB

R83LB

R59LB

1

R57LB

1

1

2

1

3

2

2

R220LB

1

2

0

5%

EMPTY

402

R221LB
10

5%

3

CH
402

2

R218LB

1

2

5%

0

EMPTY

402

ICH_INTVRMEN

1

5%
CH

ICH_LAN100SLP_EN

1

5%
CH

VCC3

R214LB

2

10K

5%
CH

402

ICH_THRM_XSTRGATE1

2

5%
CH

1

7

Q10LB

MMBT3904
EMPTY

1

Q9LB

MMBT3904
XSTR

1

2

5%
CH

R215LB

0

402

VCC3

OUT

OUT

MBT3904DUAL

1

2

5%

EMPTY

33

33

Q8LB

5

DESIGN NOTE:

RTC: FLIP-LID XTAL HOLDER (XY1LB)
USES STANDARD XTAL (Y1LB)

XY1LB

XTAL_TH_RM

REV=1

1

RM1

1OF1

ICH XTAL

CAD NOTE:

USBRBIAS (R63LB): TIE TRACES TOGETHER CLOSE TO PINS,
WITH LENGTH NO LONGER THAN 200 MILS TO RESISTOR

CAD NOTE:

SATARRBIAS (R81LB): TIE TRACES TOGETHER CLOSE TO PINS,
WITH LENGTH NO LONGER THAN 200 MILS TO RESISTOR

ICH_THRM_XSTRGATE2

3

6

XSTR

4

1

6

RM2

RM

2

J115LB

1X3HDR

EMPTY

Y1LB

32.768KHZ

2

R77LB

1

10M

603

1

C42LB

18PF
5%
50V

2

COG
603

USBRBIAS_ICH

R63LB

1

402

22.6

SATARBIAS_ICH

1

R81LB

24.9
402

ICH_THRM_N

WOL_ONLY

33

88

IN

PROTECTED RTC JUMPER

TP_CLR_RTC

1

ICH_SRTCRSTB_PULLUP

2

NET_CLR_RTC_JUMPER

3

TH
XTAL

2

RTC (10 MOHMRES): DO NOT CHANGE

5%
CH

R77LB TO 0402 PACK_TYPE

1

2

OUT

2

CH

1%

OUT

2

1%
CH

OUT

1

R261LB

4.7K
5%

EMPTY
402

2

BOM NO TE:

RTC XTAL: ADD (MOD-FILE INSERTION)
XTAL A91451-001 (32.768KHZ) USING
REF-DES W/OUT X (Y1LB)

ICH_RTCX1

OUT

33

DESIGN NOTE:

C41LB

18PF
5%
50V
COG
603

ICH_RTCX2

31

32

33

OUT

33

5

1

R107LB

100K

5%
CH

402

2

33 37

OUT

1-2

2-3

NORMAL *
CLR RTC

* = DEFAULT

45

3336

64

64

3336

59

33

64 59

IN

DESIGN NOTE:

INTRUDER HEADER (J 5LB): NO SUITCASE JUMPER
REMOVE J5LB IF 2X12 BACKSIDE DMI LAI CONN (J10BC) IS STUFFED.

90

DESIGN NOTE:

90

90

3

AUD_LINK_SDO_R

IN

AUD_LINK_SYNC_R

IN

AUD_LINK_BCLK

IN

AUD_LINK_RST_R_N AUD_LINK_RST_CDC

V_3P0_BAT_VREG

343738

IN

1 MOHM INTRUDER PULL-UP (R80LB)
20K RTC PULL-UP (R68LB)

V_3P0_BAT_VREG

343738

IN

V_3P0_BAT_VREG

343738

IN

R71LB

1

33

402

R72LB

1

40233CH

R70LB

2

33

402

R192LB

1

33

402

5%
CH

5%

5%
CH

5%
CH

R80LB

1M

402

R68LB

20K
402

R253LB

20K
402

2

2

1

2

1

1

1

AUD_LINK_SDO

AUD_LINK_SYNC

AUD_LINK_BCLK_R

2

5%
CH

2

1%

CH

2

1%

CH

DESIGN NOTE:

5%

EMPTY

2

CR1LB

2

IM_LB_SOP_EN_CNTSOP_EN_CNT

R224LB

1

2.2K
402

IM_LB_ICH_CONFIG_JUMPER

J7LB

1

2

MFG MODE PADS: J4LB

1

RECOVER/CONFIGURE HEADER

JUMPER ON 1-2 *

2

JUMPER ON 2-3

5%

EMPTY

JUMPER REMOVED
* DEFAULT JUMPER SETTING

1X3HDR

1

2

RECOVERY_CONFIGURE_PULLUP

3

HDR

2.2K
402

[PAGE_TITLE=ICH PIN STRAPS]

CONFIDENTIAL

CUSTOM TEXT BPAGE

VCC3

R225LB

1

4.7K
5%

2

EMPTY
402

R226LB

1

1K

402

5

GP33_SOP

R312LB

3

6

IM_LB_CONFIG_CNT

EMPTY

4

1

Q11LB

1

2.2K

402

3

5%
CH

2

BAT54C
DIO
SOT23_C

MBT3904DUAL

R223LB

1

2.2K
EMPTY

402

3337

2

5%

IM_LB_SPKR_CNT

OUT

IM_LB_SPKR

60

33

4 2

SPKR

IN

Sun Mar 18 18:43:44 2007

CONFIG / RECOVERY JUMPER

BPAGE DRAWING

frostburg_fabc.sch_1.37

3

2

1

1

C139LB

1

IM_LB_SOP_EN_CNT_Q

3

Q12LB
EMPTY

2

R227LB

4.7K
402

R228LB

1

INTEL

MODULE REV DETAILS

MODULE NAME

ICH9 0.2.1

59

OUT

CAD NOTE:

SOFT AUDIO TERMINATION: PLACE CLO SE TO ICH

59

OUT

33

64

OUT

TERMINATION FOR SOFT AUDIO

OUT

J5LB

1X2HDR

2

HDR

ICH_INTRUDER_HDR_N

ICH_RTCRST_PULLUP

C40LB

2

20%

1UF

6.3V
X5R
603

ICH_SRTCRSTB_PULLUP

2

20%

1UF

6.3V
X5R
603

VCC3

R60LB

1

4.7K
5%

2

CH
402

J4LB

1

2

5%
CH

JUMPER

EMPTY

726841-001

2

5%
CH

1

402

2

ICH_CONFIG_JUMPER

R73LB

470

5%

VCC3

CH

402

R302LB

2

1

5%

0

EMPTY

R303LB

1

2

0

5%
CH

402

CONFIGURE= SAFE MODE

1

R74LB

20K

402

2

DOCUMENT_NUMBER

xxxxxx

REV

0

402

EMPTY

5%

R300LB

1

0

5%

EMPTY

402

GP33_SOP

GP37_MFG_MODE_N

NORMAL
CONFIGURE
RECOVERY

1

5%
CH

2

1

OUT

1

R285LB

2

ICH_GP56

2

MODE

PAGE REV

1

OUT

37

DATE

08/30/06

33

OUT

OUT

OUT

OUT

D

C

33
37

33

IN

36

B

33
37

32
36

A

33

3.01

CR-38 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE38

8

PCI

VCC3

D

PCI EXPRESS DECOUPLING FILTER

C

323438

CAD NOTE:

V_1P5-FILTER CAPS: PLACE NEAR
ENDS OF POWER CORRIDOR

SATA BG

B

LAN VCCPAUX

3839

V_3P3_EPW

27

28

IN

3334
4056
57

58

8892

VCC3

A

8

31

C12LB

1

.1UF

25V
Y5V
603

C13LB

1

.1UF 20%

25V
Y5V
603

C14LB

1

.1UF 20%

25V
Y5V
603

IN

C11LB

1

.1UF 20%

25V
Y5V
603

C126LB

1

.1UF

25V
Y5V
603

C125LB

1

25V
Y5V
603

2

20%

2

2

V_1P5_FILTER

C24LB

1

22UF

6.3V
X5R
1206

C25LB

2

2.2UF

6.3V
X5R
603

C26LB

1

22UF

6.3V

EMPTY

1206

VCC3

2

C31LB

1

20%.1UF

25V

EMPTY

603

2

20%

2

GENERAL PURPOSE DCPL CAPS

20%.1UF

2

20%

1

10%

2

20%

2

DESIGN NOTE:

7

PCI-E

VCC3

VCC3

82

82

98

SATA RX/TX

3438
82

92

58

7

3438

92

C16LB

1

.1UF

98
9

101

70

2

20%
25V
Y5V
603

C15LB

1

2

.1UF 20%

25V
Y5V
603

C20LB

1

2

.1UF

20%
25V
Y5V
603

V_1P5_ICH

9

3438

IN

9298

DESIGN NOTE:

DEFAULT: 1UH INDUCTOR M2LB
WITH IPN 201005-546

V_1P5_ICH

9

IN

IN

DESIGN NOTE:

DEFAULT: 1UH INDUCTOR M13LB WITH IPN 201005-546
NON-LAN SKU: CHANGE M13LB TO 0OHM RES
NON-LAN SKU: EMPTY C2LB AND C3LB

40

5657

V_1P5_ICH

2

C8LB

1.0UF
20%
10V

1

Y5V
603

1

28

33343839

6

105

87

889092

53

596469

82848586

323334363738

9212228

47

4849

39
102103

CAD NOTE:

PLACE V3P3_STBY DCPL
CAPS AT ENDS OF POWER
CORRIDOR (VCCP_USB)

V_1P5_ICH

L1LB

1

721891-026

IN

CAD NOTE:

PLACE VCCSATA DCPL
CAPS AT ENDS OF POWER
CORRIDOR

DMI PLL FILTER

M2LB

1

IND

M13LB

MULTI

27
8892

MULTI

1

SMIND

IN

C111LB

C33LB

1UF

6.3V
X5R
603

2

.1UF

SM

C28LB

1

.01UF

2

20%

20%
25V
Y5V
603

2

VCCA_PWR_GPLL_PN1_ICH

2

20%
50V
X7R
603

V_1P5_ICH_R

2

1

6

USB CLASSIC FILTER

V_3P3_STBY\G

IN

C120LB

1

2

10%

.022UF

50V
X7R
603

SATA PLL FILTER

10UH

2

IND

14

1

R20LB

0

402

DESIGN NOTE:

DEFAULT STUFFED; 0 OHM 0603 TRAP (R22LB)
OPTION: EMPTY (R22LB) FOR NON-INTEL LAN

R22LB

1

0

603

R27LB

1

0

4025%CH

C27LB

1

10.0UF

6.3V
X5R
805

85
7

89
173438

2

GLCI_PLL

5%
CH

C2LB

10UF

20%

6.3V
X5R
805

1A
CH

20%

2

VCCSATA_PLL_ICH

2

2

IN

1

2

5

C21LB

1

10UF

6.30V

C22LB

1

1.0UF220%

V_FSB_VTT

1

2

1

.022UF

1

.022UF

2

1206

10%

X7R

10V
Y5V
603

VCCDMI_PLL_ICH

1

C29LB

4.7UF
20%
10V

2

Y5V
805

OUT

1

C3LB

2.2UF
10%

6.3V

2

X5R
603

V_3P3_EPW_RV_3P3_EPW

R21LB

0

1A
EMPTY

603

C17LB

C18LB

2

10%
50V
X7R
603

2

10%
50V
X7R
603

PCI-E FILTER

34

98

OUT

82

9

34
38

92

34

OUT

2

C30LB

.1UF
20%
25V

1

Y5V
603

34

BOM NO TE:

STUFF R21LB FOR
NON-INTEL LAN

1

2

C112LB

4.7UF
10%

6.3V

X5R
603

3

82838698

V_1P25_CORE

131416

17
76

IN

18

2134

105

45

V_1P5_FILTER

31

32

IN

3438

CAD NOTE:

PLACE C112LB
NEAR NE CORNER
OF ICH

ICH

M4LB

IN

90

85

89

14

1734

CAD NOTE:

PLACE 0.1UF DCPL CAPS (C36LB TO
C39LB) WITHIN 40 MILS OF ICH.

34

3437

IN

3437

IN

38
7

IN

3437

IN

V_1P05_VCCAUX

IN

1

2

C201LB

0.1UF

CH

V_3P0_BAT_VREG

V_REF5V

V_FSB_VTT

V_REF5V_SUS

C102LB

0.1UF
20%
16V
Y5V
402

20%

16V
Y5V
402

1

V_1P5_ICH

4 2

2

MULTI

V_1P5_FILTER

805

1

C23LB

220UF
20%

6.3V
ALUM

2

RDL

603

2

C10LB

1.0UF
20%
10V

1

Y5V
603

34 39

OUT

1

2

BPAGE DRAWING

frostburg_fabc.sch_1.38

Sun Mar 18 18:43:46 2007

31

32 34 38

OUT

DESIGN NOTE:

DEFAULT M4LB: 0 OHM RES A93552-002
OPTIONAL WITH 0.5UH FB 656554-026

C39LB

1

.1UF

C38LB

1

.1UF

C37LB

1

C36LB

1

.1UF

Y5V
603

2

20%
25V
Y5V

2

20%
25V
Y5V
603

2

20%.1UF
25V
Y5V
603

2

20%
25V

USB HS (HI-SPEED) FILTER

98

9

3438

8292

8284

85

4953

59

363738

28

323334

4748

39

6469

70

86

8788

9092

101

102

103105

3

IN

USB VCCUABG

92122

CUSTOM TEXT BPAGE

2

MODULE REV DETAILS

MODULE NAME

ICH9 0.2.1

1

2

C137LB

22UF
20%

6.3V
X5R

1206

1

C61LB

0.1UF
20%

16V

2

Y5V
402

V_1P5_STBY_INT

1

C35LB

.1UF
10%
16V

2

X7R
603

V_1P5_ICH

V_3P3_STBY\G

IN

C32LB

1

.1UF

25V
Y5V
603

BOM NO TE:

CAD NOTE:

2

PLACE DCPL CAP (C32LB)

20%

AT PIN F3 OF ICH

4.7UF (C34LB) STUFF FOR SIGNAL QUALITY

C19LB

1

2

.1UF

10%

16V
X7R
603

C9LB

1

2

10%

.1UF

16V
X7R
603

V_1P5_CL_INT

1

C4LB

1.0UF

20%

10V

2

EMPTY
603

V_1P05EP_INT

1

C6LB

1.0UF

20%

10V

2

EMPTY
603

[PAGE_TITLE=ICH DECOUPLING]

INTEL

CONFIDENTIAL

DOCUMENT_NUMBER

xxxxxx

1

REV

OUT

OUT

2

C5LB

.1UF
20%
25V

1

Y5V
603

OUT

2

C7LB

.1UF
20%
25V

1

Y5V
603

08/30/06

34

34

34

PAGE REV

38

1

DATE

D

C

B

A

3.01

CR-39 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE39

8

47

4849

87

DESIGN NOTE:

D

47

87

7

8
93

3339

C

BOM NO TE:

102103105

32333436373839

64

69

70

82848586

VR_READY

IN

SLP_S3_ICH_N

IN

47

4849

87

8890

8890

VRMPWRGD SEQUENCE CIRCUIT

889092

101

9212228

IN

48495359

R200LB

1

2

0

5%
CH

402

R199LB

1

2

5%

0

EMPTY

402

70

82848586

EMPTY FOR NON-AMT

DESIGN NOTE:

CL DEBUG FEATURE, MAY NOT NEED FOR PRODUCT

R194LB

SLP_S3_ICH_N

3339

IN

ICH_SLP_M_N

33

IN

B

33

70

IN

V_3P3_EPW_R

3438

IN

1

0

402

2

10K
402

ICH_RSMRST_N

A

V_3P3_STBY\G

SLP_S3_VR_READY

102103105

32333436373839

2

5%

EMPTY

R98LB

5%

EMPTY

BOM NO TE:

7

92

101

102103105

1

2

R216LB

10K

5%
CH

402

9212228

IN

53596469

32333436373839

70

82848586

MBT3904DUAL

R90LB

1

2

5%

10K

CH

402

SLP_S3_VR_READY_PIN5

101

92

V_3P3_STBY\G

9212228

IN

53596469

1

R97LB

150

5%
EMPTY

402

2

3

ICH_SLP_M_N_PIN5

1

2

C127LB

1.0UF

20%

10V

1

EMPTY
603

STUFF R203LB &
EMPTY R103LB FOR NON AMT

R203LB

2

1

5%

0

402

CH

R103LB

2

1

15K

1%

EMPTY

402

Q4LB

1

MMBT3904
EMPTY

2

R105LB

1

0
5%

2

EMPTY
402

V_3P3_STBY\G

VCC3

1

R91LB

10K
5%

EMPTY
402

2

Q2LB

3

5

461

SLP_M

LAN_PWROK

BOM NO TE:

STUFF FOR
NON INTEL

LAN

6

1

2

VCC3_3P3STBY_PIN2

28 86 88

OUT

1

C119LB

1.0UF
20%
10V

2

EMPTY
603

R92LB

1K

5%
EMPTY

402

2

XSTR
C59LB

EMPTY

OUT

.1UF

20%
25V

603

45

3

VCC3

2

R93LB

1K

5%
CH

402

1

ICH_VRMPWRGD

2

2

C58LB

1.0UF
20%

10V

EMPTY

603

2

R94LB

100K
5%

1

CH
402

1

OUT

33

87

889092

101

70

484953596469

DESIGN NOTE:

FORCE MEPWR BEFORE PS_ON IS VALID

1

MCH_CLPWROK

13

86

IN

2

3339

IN

82848586

9212228323334363738

IN

39

47

102103105

DEBUG CL FEATURE

R100LB

2

1K

402

EMPTY

MODULE REV DETAILS

MODULE NAME

ICH9

SLP_S3_ICH_N
V_3P3_STBY\G

MBT3904DUAL

1

MCH_CLPWROK_PIN5

5%

Q3LB

5

1

R99LB

3.3K

5%
EMPTY

402

2

1

REV

0.2.1

R282LB

1

402

22 5%

MCH_CLPWROK_XSTR_GATES

MCH_CLPWROK_DUAL2

6

3

EMPTY

1

4

DATE

08/30/06

D

2

EMPTY

2

C

CL VREF

R110LB

1

R108LB

1K 1%

402

R109LB

3.24K
402

3.24K

1

1

402

R111LB

1

453
402

EMPTY

1%

EMPTY

2

1%
CH

2

1%

C56LB

1

2

CH

20%

0.1UF

16V

Y5V

402

CL_N_VREF_ICH

OUT

32

B

2

2

C57LB

1

2

0.1UF

20%

16V

EMPTY

402

TP6_DEBUG

OUT

32

A

V_3P3_EPW

4056575888

89

TP5_DEBUG

32

IN

TP4_DEBUG

32

IN

33

92101

102103105

47

84

8586

32333436373839

59

64697082

2728333438

IN

92

R87LB

1

2

1K

5%

EMPTY

402

R88LB

1

2

5%

1K

EMPTY

402

87

8890

484953

9212228

IN

V_3P3_STBY\G

DESIGN NOTE:

DEBUG PURPOSE.

[PAGE_TITLE=ME & CONTROL BUFFERS/ICH CIRCUITS]

BPAGE DRAWING

frostburg_fabc.sch_1.39

Sun Mar 18 18:43:47 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

39

1

3.01

CR-40 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE40

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

ICH9

0.2.1

1

REV

DATE

08/30/06

D

C

33

OUT

33

IN

33

IN

33

40

IN

SPI_MISO

SPI_MOSI_PRI_SEC_FLSH

SPI_CLK_PRI_SEC_FLSH

SPI_CS0_ISOLATE_N

B

PRIMARY SERIAL FLASH

CAD NOTE:

PLACE CLOSE
TO SPI 1

R169LB

1

15

402

R164LB

1

0

402

R165LB

1

402

40

5657

58

2

1%

CH

2

5%
CH

2

5%CH0

272833343839
8892

40
40

SPI_CLK_FLSH

V_3P3_EPW

IN

SPI_MISO_FLSH

40

OUT

40

OUT

SPI_MOSI_FLSH

SPI_WP0_N

IN

SPI_HOLD0_N

IN

U3LB

SPI_FLASH

VCC
SI
SCK
CS*

SO

WP*

HOLD*

VSS

IC

DESIGN NOTE:

OVERLAPPING PARTS: ONLY STUFF ONE(XU3LB) OR (U2LB)

CAD NOTE:

CAD NOTE:

OVERLAY SPI PARTS WITH EACH OTHER

40

IN

DESIGN NOTE:

SCHEMATICS SPI SOCKET (SOIC8) IPN :D62233-001
USE MOD FILE INSERT 8MB WINBOND IPN: D85790-001
USE MOD FILE INSERT 8MB SPI IPN: C96495-006
USE MOD FILE IF 16MB SPI IPN: D23556-001

D

C

B

OVERLAY SPI (XU3LB) & (U2LB) WITH EACH OTHER

V_3P3_EPW

4056

57

58

40

V_3P3_EPW

4056

57

A

272833343839

IN

588892

1

R170LB

R171LB

EMPTY

1K

5%
CH

402

1K

5%

402

1

R163LB

1K

5%

2

CH

2

SPI_WP0_N

402

1

2

SPI_HOLD0_N

BOM NO TE:

DEFAULT EMPTY (R171LB)
DESIGN FEATURE
FOR DISABLING EXTERNAL
FLASH PROTECTION

OUT

OUT

V_3P3_EPW

40

40

1

2

C79LB

1.0UF
20%
10V
Y5V
603

1

C78LB

.1UF
20%
25V

2

Y5V
603

IN

40

IN

33

40

IN

40

IN

40

IN

272833 34 38 39

IN

88 92

272833343839
8892

SPI_MOSI_FLSH

SPI_CLK_FLSH
SPI_CS0_ISOLATE_N
SPI_WP0_N

SPI_HOLD0_N

IN

40 565758

U2LB

AT26DF321

VCC
SI

SCK
CS*
WP*
NC

GND

OPTION 2

SO
NC

NC
NC
NC
NC
NC
NC
NC

EMPTY

2

15
16

7
9
1

10

REV=1

8
3

4
5
6
14
13
12
11

SPI_MISO_FLSH

OUT

40

A

[MODULE=ICH]
[PAGE_TITLE=SERIAL FLASH PRIMARY]

8

7

6

5

4 2

BPAGE DRAWING

frostburg_fabc.sch_1.40

Sun Mar 18 18:43:49 2007

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

40

1

3.01

CR-41 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE41

8

DESIGN NOTE:

BIOS & SILK SCREEN DENAOTE AS PORT0

D

J2BU

1X7HDR

SATA

2

TXP

1

GND

4

GND

7

GND

C92545-001

DESIGN NOTE:

BIOS & SILK SCREEN DENAOTE AS PORT2

C

1

GND

4

GND

7

GND

C92545-001

DESIGN NOTE:

BIOS & SILK SCREEN DENAOTE AS PORT4

B

1
4
7

C92545-001

A

1
4
7

C92545-001

J3BU

1X7HDR

SATA

1X7HDR

GND
GND
GND

1X7HDR

GND
GND
GND

TXN
RXN
RXP

TXP
TXN
RXN
RXP

J4BU

SATA

J7BU

SATA

HDR

HDR

TXP
TXN
RXN
RXP

EMPTY

TXP
TXN
RXN
RXP

EMPTY

3
5
6

2

3
5
6

2

3
5
6

2

3
5
6

8

7

SATAHDR_TX0_R_DP

SATAHDR_TX0_R_DN

SATAHDR_RX0_R_DN

SATAHDR_RX0_R_DP

SATAHDR_TX1_R_DP

SATAHDR_TX1_R_DN

SATAHDR_RX1_R_DN

SATAHDR_RX1_R_DP

SATAHDR_TX2_R_DP

SATAHDR_TX2_R_DN

SATAHDR_RX2_R_DN

SATAHDR_RX2_R_DP

SATAHDR_TX3_R_DP

SATAHDR_TX3_R_DN

SATAHDR_RX3_R_DN

SATAHDR_RX3_R_DP

7

6

BOM NO TE:

DEFAULT 0.01UF, 0402, A36096-008, 10%, 25V, X7R
OPTIONAL 0 OHM, 0402, A36093-001

C202BU

1

.01UF

.01UF

.01UF

.01UF

.01UF

.01UF

C203BU

1

C204BU

1

C205BU

1

25V
X7R

C206BU

1

.01UF

C207BU

1

.01UF

C208BU

1

C209BU

1

.01UF

.01UF

.01UF

.01UF

25V
X7R

25V
X7R

25V
X7R

25V
X7R

25V
X7R

25V
X7R

25V
X7R

C210BU

1

EMPTY

C211BU

1

EMPTY

C212BU

1

EMPTY

C213BU

1

EMPTY

10%

402

25V

25V

25V

25V

.01UF

10%

402

10%

402

10%

402

2

10%

10%

10%

402

10%

402

.01UF

.01UF

.01UF

2

2

2

2

402

2

402

2

2

2

10%

402

2

10%

402

2

10%

402

2

10%

402

C222BU

1

25V

EMPTY

C223BU

1

25V

EMPTY

C224BU

1

25V

EMPTY
C225BU

1

25V

EMPTY

2

10%

402

2

10%

402

2

10%

402

10%

402

2

SATAHDR_TX0_DP

SATAHDR_TX0_DN

SATAHDR_RX0_DN

SATAHDR_RX0_DP

SATAHDR_TX1_DP

SATAHDR_TX1_DN

SATAHDR_RX1_DN

SATAHDR_RX1_DP

SATAHDR_TX2_DP

SATAHDR_TX2_DN

SATAHDR_RX2_DN

SATAHDR_RX2_DP

SATAHDR_TX3_DP

SATAHDR_TX3_DN

SATAHDR_RX3_DN

SATAHDR_RX3_DP

6

45

32

IN

DESIGN NOTE:

BIOS & SILK SCREEN DENAOTE AS PORT1

3

SATAHDR_TX4_R_DP

32

IN

32

OUT

32

OUT

32

IN

32

IN

32

OUT

32

OUT

32

IN

32

IN

32

OUT

32

OUT

32

IN

32

IN

32

OUT

32

OUT

5

J6BU

1X7HDR

SATA

2

TXP

1

GND

4

GND

7

GND

C92545-001

DESIGN NOTE:

BIOS & SILK SCREEN DENAOTE AS PORT3

1
4
7

C92545-001

J5BU

1X7HDR

SATA

GND
GND
GND

TXN
RXN
RXP

HDR

TXP
TXN
RXN
RXP

3
5
6

2

3
5
6

HDR

SATAHDR_TX4_R_DN

SATAHDR_RX4_R_DN

SATAHDR_RX4_R_DP

SATAHDR_TX5_R_DP

SATAHDR_TX5_R_DN

SATAHDR_RX5_R_DN

SATAHDR_RX5_R_DP

BPAGE DRAWING

frostburg_fabc.sch_1.41

Sun Mar 18 18:43:50 2007

4 2

3

.01UF

.01UF

.01UF

.01UF

C215BU

1

2

MODULE REV DETAILS

MODULE NAME

C217BU

2

25V
X7R

C216BU

2

25V
X7R

C214BU

1

25V
X7R

25V
X7R

C221BU

2

.01UF

C220BU

2

.01UF

.01UF

.01UF

10%

402

10%

402

10%

402

2

10%

402

25V
X7R

25V
X7R

C219BU

2

25V
X7R

C218BU

2

25V
X7R

1

1

2

1

10%

402

1

10%

402

1

10%

402

1

10%

402

SATAHDR_TX4_DP

SATAHDR_TX4_DN

SATAHDR_RX4_DN

SATAHDR_RX4_DP

SATAHDR_TX5_DP

SATAHDR_TX5_DN

SATAHDR_RX5_DN

SATAHDR_RX5_DP

[PAGE_TITLE=SATA CONNECTORS]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

REV

1

PAGE REV

41

1

OUT

OUT

OUT

OUT

DATE

IN

IN

IN

IN

3.01

D

32

32

32

32

C

32

B

32

32

32

A

CR-42 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE42

8

7

FRONT PANEL HEADER #1

D

6

CR3BU

6.0V

TVS6V

6

5VDUAL_USB

43444546

91

92

5288

52

IN

4

1

3

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

D

CAD NOTE:

DO NOT CHANGE TO 402
OVERLAPPING FOOTPRINTS

1

2

R14BU

0

1A

603

CH

752402-015

C

31

31

BI

BI

USB_FRONT1_DN

USB_FRONT1_DP

L1BU

4

90OHM

EMPTY

ACM2012

L1BU

3

90OHM

ACM2012 EMPTY

R15BU

1

2

1A

0

CH

603

1

USB_FRONT1_R_DN
USB_FRONT1_R_DP

2

B

USB_FP1_PWR

52

IN

EMPTY

D16982-001

J8BU

2X5HDR_9

1
3
56
7

2
4

8
10

HDR

1

C226BU

470PF
10%
50V

2

EMPTY
603

R18BU

1

0

603

EMPTY

BOM NO TE:

STUFF FOR PRODUCT
WITH FUSE ON
FRONT PANEL

R20BU

1

2

1A

0

603

CH

BOM NO TE:

STUFF FOR PRODUCT
WITH FUSE ON BOARD
NOT ON FP

USB_FRONT2_R_DN
USB_FRONT2_R_DP

USB_OC_FRONT34

2

1A

USB_OC_FRONT1_R_N

1

2

R19BU

0
5%

EMPTY
402

DESIGN NOTE:

CAUTION: 0 OHM TO GND

BOM NO TE:

STUFF FOR CUSTOM
FUSED (OPT-P10-GND)
FRONT PANEL SUPPORT

A

CAD NOTE:

DO NOT CHANGE TO 402
OVERLAPPING FOOTPRINTS

1

2

R16BU

0

1A

603

CH

752402-015

L2BU

1

4

90OHM

ACM2012

EMPTY

L2BU

3

2

90OHM

EMPTY

ACM2012

R17BU

1

2

1A

0

CH

603

52

OUT

USB_FRONT2_DN

USB_FRONT2_DP

31

BI

31

BI

C

B

A

[PAGE_TITLE=USB FP HDR 1]

8

BPAGE DRAWING

frostburg_fabc.sch_1.42

Sun Mar 18 18:43:51 2007

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

42

1

3.01

CR-43 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE43

8

7

6

45

3

FRONT PANEL HEADER #2

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

D

CR4BU

6.0V

TVS6V

1

25

3

C

31

31

USB_FRONT4_DN

BI

USB_FRONT4_DP

BI

B

A

CAD NOTE:

DO NOT CHANGE TO 402
OVERLAPPING FOOTPRINTS

1

2

R21BU

0

1A

603

CH

L3BU

1

0

L3BU

R22BU

EMPTY

4

1A

CH

3

2

2

90OHM

ACM2012

90OHM

ACM2012 EMPTY

1

603

USB_FRONT4_R_DP

USB_FP2_PWR

IN

R27BU

1

0

603

BOM NO TE:

STUFF FOR PRODUCT
WITH FUSE ON BOARD
NOT ON FP

D16982-001

J9BU

2X5HDR_9

1

3
56
7

HDR

1

C227BU
470PF
10%
50V

2

EMPTY
603

R26BU

1

0

603

BOM NO TE:

STUFF FOR PRODUCT
WITH FUSE ON
FRONT PANEL

2

1A

CH

6

4

EMPTY

2
4

8

USB_OC_FRONT2_PIN10

10

2

1A

EMPTY

USB_OC_FRONT2_R_N

5VDUAL_USB

USB_FRONT3_R_DNUSB_FRONT4_R_DN
USB_FRONT3_R_DP

R25BU

1

0
5%

2

EMPTY
402

42 44 45 46 52 889192

IN

DESIGN NOTE:

CAUTION: 0 OHM TO GND

BOM NO TE:

STUFF FOR CUSTOM
FUSED (OPT-P10-GND)
FRONT PANEL SUPPORT

5252

OUT

CAD NOTE:

DO NOT CHANGE TO 402
OVERLAPPING FOOTPRINTS

1

2

R23BU

1A

0

CH

603

L4BU

4

1

90OHM

ACM2012

EMPTY

L4BU

3

2

90OHM

ACM2012 EMPTY

R24BU

1

2

1A

0

603

CH

USB_FRONT3_DN

USB_FRONT3_DP

31

BI

31

BI

D

C

B

A

[PAGE_TITLE=USB FP HDR 2]

8

BPAGE DRAWING

frostburg_fabc.sch_1.43

Sun Mar 18 18:43:52 2007

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

43

1

3.01

CR-44 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE44

8

7

6

45

3

FRONT PANEL HEADER #3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

D

CR8BU

6.0V

TVS6V

1

3

C

31

31

USB_FRONT6_DN

BI

USB_FRONT6_DP

BI

B

A

CAD NOTE:

DO NOT CHANGE TO 402
OVERLAPPING FOOTPRINTS

ACM2012

1

603

2

90OHM

90OHM

1

603

0

L11BU

L11BU

1

0

R91BU

R90BU

1A

CH

EMPTY

4

EMPTYACM2012

1A

CH

2

3

2

USB_FRONT6_R_DP

USB_FP3_PWR

52

IN

R85BU

1

0

603

BOM NO TE:

STUFF FOR PRODUCT
WITH FUSE ON BOARD
NOT ON FP

2X5HDR_9

1

3
5
7

1

2

2

1A

CH

J19BU

C303BU
470PF
10%
50V
EMPTY
603

1

6030EMPTY

D16982-001

HDR

R86BU

BOM NO TE:

STUFF FOR PRODUCT
WITH FUSE ON
FRONT PANEL

6

52

4

EMPTY

2
4
6
8

USB_OC_FRONT3_PIN10

10

2

1A

USB_OC_FRONT3_R_N

5VDUAL_USB

USB_FRONT5_R_DNUSB_FRONT6_R_DN
USB_FRONT5_R_DP

R87BU

1

0
5%

2

EMPTY
402

42 43 45 46 52 88

IN

DESIGN NOTE:

CAUTION: 0 OHM TO GND

BOM NO TE:

STUFF FOR CUSTOM
FUSED (OPT-P10-GND)
FRONT PANEL SUPPORT

52

OUT

91

92

CAD NOTE:

DO NOT CHANGE TO 402
OVERLAPPING FOOTPRINTS

R88BU

2

1

0

1A

603

CH

L12BU

1

4

90OHM

EMPTY

ACM2012

L12BU

2

3

90OHM

EMPTYACM2012

R89BU

2

1

0

1A

CH

603

USB_FRONT5_DN

USB_FRONT5_DP

31

BI

31

BI

D

C

B

A

[PAGE_TITLE=USB FP HDR 2]

8

BPAGE DRAWING

frostburg_fabc.sch_1.44

Sun Mar 18 18:43:53 2007

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

44

1

3.01

CR-45 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE45

8

BACK PANEL

7

USB

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

D

C

CAD NOTE:

DO NOT CHANGE TO 402
OVERLAPPING FOOTPRINTS

BI

BI

USB_BACK4_DN

USB_BACK4_DP

B

31

31

A

31

31

USB_BACK2_DN USB_BACK2_R_DN

BI

USB_BACK2_DP

BI

8

7

R28BU

1

2

0

1A
CH

603

L5BU

R29BU

1

0

603

R30BU

2

1A

CH

R31BU

2

CH

L5BU

L6BU

L6BU

1A

EMPTY

2

1A
CH

0

603

603

EMPTY

1

EMPTY

EMPTY

1

0

4

3

3

4

1

90OHM

ACM2012

2

90OHM

ACM2012

CAD NOTE:

DO NOT CHANGE TO 402
OVERLAPPING FOOTPRINTS

2

90OHM

ACM2012

1

90OHM

ACM2012

USB_BACK4_R_DN

USB_BACK4_R_DP

CR5BU

6.0V

TVS6V

1

25

3

D16982-001

6

6

5VDUAL_USB

4

EMPTY

45

BI

45

BI

52 88
42 43

IN

44 46
91

92

45

BI

USB_BACK2_R_DP

45

BI

CAD NOTE:

PLACE CAP AS CLOSE AS POSSIBLE
TO USB CONNECTOR

VREG_USB_BP0_STACK

45

91

IN

45

BI

45

BI

45

IN

VREG_USB_BP0_STACK

45
45

91

BI
BI

1

C230BU
470PF

10%

50V

X7R

2

402

USB_BACK4_R_DN
USB_BACK4_R_DP

USB_BACK2_R_DN
USB_BACK2_R_DP

J21BU

2XUSB

1
2

3

4

5
6
7
8

A91996-001

9

10

11

12

CONN

[PAGE_TITLE=BACK PANEL USB]

BPAGE DRAWING

frostburg_fabc.sch_1.45

Sun Mar 18 18:43:54 2007

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

45

1

D

C

B

A

3.01

CR-46 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE46

8

7

[PAGE_TITLE=BACK PANEL USB WITH ESATA]

DESIGN NOTE:

D

MJ/USB DUAL

USB_BACK1_DN

31

BI

USB_BACK1_DP

31

BI

C

USB_BACK3_DN

31

BI

USB_BACK3_DP

31

BI

B

DESIGN NOTE:

USB/ESATA DUAL STACK

USB_BACK5_DN

31

BI

USB_BACK5_DP

31

BI

A

BI

BI

USB_BACK6_DP

USB_BACK6_DN

31

31

8

CAD NOTE:

DO NOT CHANGE TO 402
OVERLAPPING FOOTPRINTS

R32BU

2

1

1A

0

CH

603

L7BU

1

4

90OHM

EMPTY

ACM2012

L7BU

2

3

90OHM

EMPTYACM2012

R33BU

2

1

0

1A

CH

603

R34BU

2

1

0

1A

CH

603

L8BU

1

4

90OHM

EMPTY

ACM2012

L8BU

2

3

90OHM

EMPTY

ACM2012

R35BU

2

1

1A

0

CH

603

CAD NOTE:

DO NOT CHANGE TO 402
OVERLAPPING FOOTPRINTS

7

BOM NO TE:

CONNECTOR STUFFING OPTIONS:

RJ45/2 USB - C73572-001 (DEFAULT)
DOUBLE STACK USB - 749193-001, NOT 642575-124

DOUBLE-STACK CONNECTOR FOR USB/LAN IS ON OTHER PAGE
WITH THE REST OF THE CONNECTOR

USB_BACK1_R_DN

USB_BACK1_R_DP

1

2

3

USB_BACK3_R_DN

USB_BACK3_R_DP

R36BU

1

0

603

L9BU

2

90OHM

ACM2012

L9BU

1

90OHM

ACM2012

R37BU

1

0

603

R38BU

1

0

603

L10BU

1

90OHM

ACM2012

L10BU

2

90OHM

ACM2012

R39BU

1

0

603

2

1A
CH

EMPTY

EMPTY

2

1A
CH

2

1A
CH

EMPTY

2

1A
CH

4

EMPTY

CR6BU

3

4

3

TVS6V

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

D

57

46

6.0V

6

5

4

EMPTY

BI

46

57

BI

5VDUAL_USB

BI

BI

CAD NOTE:

OVERLAP WITH MAGJACK FOOTPRINT

BOM NO TE:

EMPTY, EXCEPT FOR USB W/NO-LAN OPTION
CONNECTOR STUFFING OPTIONS:
RJ45/2 USB - A11509-001 (OLDER DESIGNS,
PRE-GIGABIT LAN)

42

43 44 45 4652889192

IN

46

57

46

57

CAD NOTE:

PLACE CAP AS CLOSE AS POSSIBLE
TO USB CONNECTOR

46

IN

VREG_USB_BP_MJ

1

C405BU
470PF
10%
50V

2

EMPTY
402

57

91

DOUBLE STACK USB (NO LAN) - 749193-001

1

C229BU
470PF

10%
50V
X7R

2

402

465791

4657

BI

4657

BI

465791

4657

BI

4657

BI

VREG_USB_BP_MJ

IN

USB_BACK1_R_DN
USB_BACK1_R_DP

VREG_USB_BP_MJ

IN

USB_BACK3_R_DN
USB_BACK3_R_DP

J11BU

2XUSB

1
2
3
4

5
6
7
8

EMPTY

9

10

11

12

C

B

CAD NOTE:

PLACE CAP AS CLOSE AS POSSIBLE
TO USB CONNECTOR

91

BI

BI

4 2

VREG_USB_BP1_STACK

46

IN

46

46

BPAGE DRAWING

frostburg_fabc.sch_1.46

Sun Mar 18 18:43:56 2007

3

1

C228BU
470PF

10%

50V

2

X7R

402

91

46
46
46

46
46

CONFIDENTIAL

CUSTOM TEXT BPAGE

IN
BI
BI

BI
BI

INTEL

VREG_USB_BP1_STACK
USB_BACK6_R_DN
USB_BACK6_R_DP

USB_BACK5_R_DN

USB_BACK5_R_DP

DOCUMENT_NUMBER

xxxxxx

J12BU

2XUSB

1
2
3
4

5
6
7
8

A91996-001

9

10

11

12

CONN

PAGE REV

46

1

A

3.01

92
42434445

91

465288

USB_BACK6_R_DP

USB_BACK5_R_DN

USB_BACK5_R_DP

5VDUAL_USB

IN

6.0V

6

52

4

EMPTY

TVS6V

46

BI

46

BI

CR7BU

1

3

USB_BACK6_R_DN

6

5

CR-47 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE47

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

D

EXPANSION SLOT 2

CAD NOTE:

D

PCI-E X1 SLOT 1 CLOSEST TO PEGX16

PCI EXPRESS

1-PORT

25V

EMPTY

603

25V
Y5V
603

20%

20%

+12V

+12V

J13BU

3GIO_X1

12V
12V
12V
GND
SMCLK
SMDAT
GND

3.3V
JTAG1

3.3VAUX
WAKE*

RSVD
GND
HSOP0
HSON0
GND
PRSNT2*
GND

C233BU

1

25V

EMPTY

603

2

20%.1UF

1.0

PRSNT1*

KEY

REFCLK+
REFCLK-

1OF1

VCC3

B1
B2
B3
B4
B5
B6
B7
B8
B9

B11

B12
B13
B14
B15
B16
B17
B18

VCC3

2

2

JTAG2
JTAG3
JTAG4
JTAG5

3.3V

3.3V

PWRGD

HSIP0
HSIN0

C234BU

1

.1UF

25V
Y5V
603

12V
12V
GND

GND

GND

GND

20%

CONN

2

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10B10
A11

A12
A13
A14
A15
A16
A17
A18

TP_PCIE_JTAG2_1
TP_PCIE_JTAG3_1
TP_PCIE_JTAG4_1
TP_PCIE_JTAG5_1

PLTRST_PCIE_SLOTS_N

CK_1PORT_S1_DP
CK_1PORT_S1_DN

HSI4_DP
HSI4_DN

+12V

C235BU

2

1

.1UF

20%

25V

EMPTY

603

VCC3

212270 101

IN

29

IN

29

IN

31

OUT

31

OUT

47

4849

8687

8890

102

101

102103105

828485

53596469

92
21

2228

32333436373839

70

9

IN

V_3P3_STBY\G

C236BU

1

25V
Y5V
603

2

20%.1UF

C

B

A

C

102103105

28

33

4849

70101

102103105

474849

87

8890

32333436373839

B

BI

212227

BI

92

101

102103105

21

2228

9

IN

53

5964697082848586

OUT

31

IN

31

IN

CAD NOTE:

PLACE AT PCI SLOTS

SMB_DATA_RESUME

VCC3

V_3P3_STBY\G

WAKE_N

HSO4_C_DP
HSO4_C_DN

1

2

TP_PCIE_JTAG1_BP_1

TP_PCIE_RSVD_B12_1

TP_PCIE_PRSNT_B16_1

C304BU

.1UF
20%
25V
EMPTY
603

SMB_CLK_RESUME

212227

28

33

4849

70101

VCC3

C231BU

1

.1UF

C232BU

1

A

.1UF

[PAGE_TITLE=PCI EXPRESS X1 #1]

BPAGE DRAWING

frostburg_fabc.sch_1.47

Sun Mar 18 18:43:58 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

47

1

3.01

CR-48 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE48

8

7

6

45

EXPANSION SLOT 3

D

101

102103105

53

596469708284

323334

47

49

889092

103

9212228

IN

36373839

87

8586

30

49

50

OUT

30

49

50

OUT

V_3P3_STBY\G

P_INTF_N
P_INTH_N

C308BU

.1UF
20%
25V
Y5V
603

VCC3 VCC

TP_PCI1_A9

+12V

TP_PCI1_A11

30

4953103106

C

53

103

B

53

103106

47

49

70101

47

49

70101

IN

3036

4953103106

IN

30

49

OUT

30

495053103106

BI

30

495053103106

BI

30

495053103106

BI

30

49

BI

21

22

272833

102103105

21

22

272833

102103105

A

30

49

53

103106

103106

BI

30

49

53

BI

8

P_PCIRST_N
P_GNT_N<3..0>

P_PME_N

P_FRAME_N
P_TRDY_N
P_STOP_N

P_PAR

SMB_CLK_RESUME

BI

SMB_DATA_RESUME

BI

P_AD<31..0>

P_C/BE_N<3..0>

PCI2.2 COMPATIBLE

VCC

R41BU

1

2.7K
402

7

DESIGN NOTE:

2

R101BU

5.6K
5%

EMPTY
402

1

2

R103BU

0
5%

CH
402

1

2

5%
CH

VCC3

2

R100BU

5.6K
5%

EMPTY
402

1

I_CLK_RESUME_RES_1

I_DATA_RESUME_RES_1

2

R102BU

0
5%

CH
402

1

REQ64B_N

0

30
28

26
24

16
22

20
18

16

15
13

11
9

0

6
4

2
0

6

PCI SLOT 1

J20BU

PCI CONN2_2

A1

TRST*

A2

P12V_1

A3

TMS
TDI

A5

P5V_2

A6

INTA*

A7 B7

INTC*

A8

P5V_3

A9

RSVD1

A10

P5V_4

A11

RSVD3

A12

GND10

A13

GND16

3.3VAUX

A15

RST*

A16

P5V_6

A17

GNT*

A18

GND5

A19

PME
AD30

A21

P3_3V

A22

AD28
AD26

A24

GND6

A25

AD24

A26

IDSEL

A27

P3_3V

A28

AD22
AD20

A30

GND9

A31

AD18
AD16

A33

P3_3V

A34

FRAME*

A35

GND13

A36

TRDY*

A37

GND22

A38

STOP*

A39

P3_3V

A40

SMB_CLK

A41

SMB_DAT

A42

GND25

A43

PAR

A44

AD15

A45

P3_3V

A46

AD13
AD11

A48

GND17

A49

A52
A53
A54

A56
A57

A59
A60
A61
A62

AD09

KEY

KEY
C_BE0*
P3_3V
AD06
AD04
GND21
AD02
AD00
P5V_8

P5V_12

P5V_10

A50
A51

B50
B51

NC=1,2

DESIGN NOTE:

IRQ MAP

IRQ MAPABCD

IDSEL 16
REQ/GNT 0

5

FGHE

M12V_1

GND1

P5V_0
P5V_1
INTB*
INTD*

PRST1*

RSVD2

PRST2*

GND2
GND3

RSVD5

GND4
GND7

REQ*

P5V_11

AD31
AD29
GND8
AD27
AD25

P3_3V

C_BE3*

AD23

GND12

AD21
AD19

P3_3V

AD17

C_BE2*

GND14
IRDY*
P3_3V

DEVSL*

GND15
LOCK*
PERR*
P3_3V
SERR*
P3_3V

C_BE1*

AD14

GND23

AD12
AD10

GND24

AD08
AD07

P3_3V

AD05
AD03

GND19

AD01

P5V_9

ACK64*REQ64*

P5V_5
P5V_7

TCK
TDO

CLK

KEY
KEY

CONN

-12V

VCC

VCC3

B1
B2
B3
B4A4
B5
B6

B8
B9
B10
B11
B12
B13
B14A14
B15
B16
B17
B18
B19
B20A20
B21
B22
B23A23
B24
B25
B26
B27
B28
B29A29
B30
B31
B32A32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47A47
B48
B49

B52
B53
B54
B55A55
B56
B57
B58A58
B59
B60
B61
B62

TP_PCI1_B4

TP_PCI1_B9
TP_PCI1_B10
TP_PCI1_B11

TP_PCI1_B14

31
29

27
25

23
21

19
17

14
12

10

8
7

5
3

1

0

3

2

1

Sun Mar 18 18:44:00 2007

4 2

3

VCC VCC

C245BU

1

2

20%

.1UF

25V

EMPTY

603

VCC

C249BU

1

2

20%

.1UF

25V
Y5V
603

NOTE: PCI SLOTS= VCC3 SHOULD GET 470UF DECOUPLING,
VCC SHOULD GET 100UF (ALLOWS 1000UF OPTION FOR VCC3)

P_INTG_N
P_INTE_N

CK_P_33M_S1

P_REQ_N<3..0>

VCC3

C246BU

20.0%

100UF

1

EMPTY

RDL

C250BU

1

.1UF

2

25V

20%
25V
Y5V
603

P_IRDY_N
P_DEVSEL_N

P_PLOCK_N
P_PERR_N

P_SERR_N

49 103

OUT

ACK64_N

[PAGE_TITLE=PCI CONN 1]

BPAGE DRAWING

frostburg_fabc.sch_1.48

3

2

VCC3

VCC3

2

OUT
OUT

OUT

R10BU

5%

2.7K
CH

402

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

MODULE REV DETAILS

MODULE NAME

2

10V

2

20%

304950
304950

28
304950

304950

304950
304950
304950

304950

VCC3

+12V

103

53 103 106

53 103 106

53 103 106

103

53 103

53 103

C248BU

1

.1UF

25V
Y5V
603

C52BU

1

.1UF 20%

25V
Y5V
603

C247BU

470UF

1

20%
EMPTY

C251BU

1

.1UF

25V

EMPTY

603

IN

BI
BI

BI

OUT
OUT

RDL

VCC

DOCUMENT_NUMBER

xxxxxx

20%

2

REV

2

1

PAGE REV

48

1

DATE

D

C

B

A

3.01

CR-49 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE49

8

7

6

45

EXPANSION SLOT 4 (FURTHEST FROM CPU)

D

101

102103105

53

596469708284

323334

47

48

889092

103

9212228

IN

36373839

87

8586

30

48

50

OUT

30

48

50

OUT

V_3P3_STBY\G

P_INTG_N
P_INTE_N

VCC3 VCC

TP_PCI2_A9

+12V

TP_PCI2_A11

30

4853103106

C

53

103

B

53

103106

47

48

70101

47

48

70101

IN

3036

4853103106

IN

30

48

OUT

30

485053103106

BI

30

485053103106

BI

30

485053103106

BI

30

48

BI

21

22

272833

102103105

21

22

272833

102103105

A

30

48

53

103106

103106

BI

30

48

53

BI

8

P_PCIRST_N
P_GNT_N<3..0>

P_PME_N

P_FRAME_N
P_TRDY_N
P_STOP_N

P_PAR

SMB_CLK_RESUME

BI

SMB_DATA_RESUME

BI

P_AD<31..0>

P_C/BE_N<3..0>

PCI2.2 COMPATIBLE

VCC

R154BU

1

2.7K
402

7

DESIGN NOTE:

2

R159BU

5.6K
5%

EMPTY
402

1

2

R152BU

0
5%

CH
402

1

2

5%
CH

VCC3

2

R151BU

5.6K
5%

EMPTY
402

1

I_CLK_RESUME_RES_2

I_DATA_RESUME_RES_2

2

R153BU

0
5%

CH
402

1

REQ64INV_N

1

30
28

26
24

17
22

20
18

16

15
13

11
9

0

6
4

2
0

6

PCI SLOT 2

J15BU

PCI CONN2_2

A1

TRST*

A2

P12V_1

A3

TMS
TDI

A5

P5V_2

A6

INTA*

A7 B7

INTC*

A8

P5V_3

A9

RSVD1

A10

P5V_4

A11

RSVD3

A12

GND10

A13

GND16

3.3VAUX

A15

RST*

A16

P5V_6

A17

GNT*

A18

GND5

A19

PME
AD30

A21

P3_3V

A22

AD28
AD26

A24

GND6

A25

AD24

A26

IDSEL

A27

P3_3V

A28

AD22
AD20

A30

GND9

A31

AD18
AD16

A33

P3_3V

A34

FRAME*

A35

GND13

A36

TRDY*

A37

GND22

A38

STOP*

A39

P3_3V

A40

SMB_CLK

A41

SMB_DAT

A42

GND25

A43

PAR

A44

AD15

A45

P3_3V

A46

AD13
AD11

A48

GND17

A49

A52
A53
A54

A56
A57

A60
A61
A62

AD09

KEY

KEY
C_BE0*
P3_3V
AD06
AD04
GND21
AD02
AD00
P5V_8

P5V_12

P5V_10

A50
A51

B50
B51

NC=1,2

DESIGN NOTE:

IRQ MAP

IRQ MAPABCD

IDSEL 17
REQ/GNT 1

5

GFEH

M12V_1

GND1

P5V_0
P5V_1
INTB*
INTD*

PRST1*

RSVD2

PRST2*

GND2
GND3

RSVD5

GND4
GND7

REQ*

P5V_11

AD31
AD29
GND8
AD27
AD25

P3_3V

C_BE3*

AD23

GND12

AD21
AD19

P3_3V

AD17

C_BE2*

GND14
IRDY*
P3_3V

DEVSL*

GND15
LOCK*
PERR*
P3_3V
SERR*
P3_3V

C_BE1*

AD14

GND23

AD12
AD10

GND24

AD08
AD07

P3_3V

AD05
AD03

GND19

AD01

P5V_9

ACK64*REQ64*

P5V_5
P5V_7

TCK
TDO

CLK

KEY
KEY

CONN

-12V

VCC

VCC3

B1
B2
B3
B4A4
B5
B6

B8
B9
B10
B11
B12
B13
B14A14
B15
B16
B17
B18
B19
B20A20
B21
B22
B23A23
B24
B25
B26
B27
B28
B29A29
B30
B31
B32A32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47A47
B48
B49

B52
B53
B54
B55A55
B56
B57
B58A58
B59A59
B60
B61
B62

TP_PCI2_B4

TP_PCI2_B9
TP_PCI2_B10
TP_PCI2_B11

TP_PCI2_B14

31
29

27
25

23
21

19
17

14
12

10

8
7

5
3

1

1

3

2

1

Sun Mar 18 18:44:02 2007

4 2

3

VCC VCC

C309BU

2

1

20%

.1UF

25V
Y5V
603

VCC

C313BU

2

1

20%

.1UF

25V
Y5V
603

NOTE: PCI SLOTS= VCC3 SHOULD GET 470UF DECOUPLING,
VCC SHOULD GET 100UF (ALLOWS 1000UF OPTION FOR VCC3)

P_INTF_N
P_INTH_N

CK_P_33M_S2

P_REQ_N<3..0>

VCC3

C310BU

20.0%

100UF

1

EMPTY

RDL

C314BU

1

.1UF

EMPTY

2

25V

20%

25V
603

P_IRDY_N
P_DEVSEL_N

P_PLOCK_N
P_PERR_N

P_SERR_N

ACK64_N

[PAGE_TITLE=PCI CONN 2]

BPAGE DRAWING

frostburg_fabc.sch_1.49

3

2

VCC3

C311BU

VCC3

C315BU

OUT
OUT

OUT

1

.1UF

IN

2

BI
BI

BI

OUT
OUT

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

MODULE REV DETAILS

MODULE NAME

2

10V

2

20%

304850
304850

28
304850

304850

304850
304850
304850

304850

OUT

VCC3

+12V

103

53 103 106

53 103 106

53 103 106

103

53 103

53 103

48 103

C312BU

1

.1UF 20%

25V
Y5V
603

C316BU

1

25V

EMPTY

603

2

2

20%.1UF

470UF

1

20%
EMPTY

RDL

25V
Y5V
603

DOCUMENT_NUMBER

xxxxxx

REV

1

PAGE REV

49

1

DATE

D

C

B

A

3.01

CR-50 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE50

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

VCC

D

53103

53103106

53103106

103

53103

OUT

P_DEVSEL_N

30

48

49

OUT

P_IRDY_N

30

48

49

OUT

P_PLOCK_N

30

48

49

OUT

P_PERR_N

304849

OUT

P_SERR_N

30

48

49

C

P_FRAME_N

30

48

49

53103106

53103106

53103106

OUT

P_TRDY_N

30

48

49

OUT

P_STOP_N

30

48

49

OUT

PCI PULL-UPS

R43BU

1

2.7K
402

1

2

R45BU

5%

2.7K
402

CH

1

R47BU

2.7K
402

1

2.7K
402

5%
CH

5%
CH

R49BU

1

2

R42BU

5%

2.7K
CH

402

2

1

2

R44BU

2.7K

5%

402

CH

1

2

R46BU

5%

2.7K
CH

402

D

C

2

1

2

R48BU

2.7K

5%

402

2

5%
CH

CH

.063W

.063W

.063W

.063W

VCC

1

2

3

1

2

R51BU

2

2.7K

5%

402

CH

1

1

2

R53BU

0

P_REQ_N<3..0>

30

48

49

53103106

OUT

2.7K

5%
CH

402

2.7K

2.7K

R50BU

5%

402

CH

1

2

R52BU

5%
CH

402

B

A

B

P_INTC_N

30

103106

OUT

P_INTB_N

30

103

OUT

P_INTD_N

30

53103

OUT

P_INTA_N

30

103

OUT

P_INTE_N

30

4849103

OUT

P_INTF_N

30

4849

OUT

P_INTG_N

30

4849

OUT

P_INTH_N

30

4849103

OUT

A

RP1BU

7

2

2.7K

5%
IC

SM

RP1BU

54

2.7K

5%
IC

SM

RP2BU

1

8

5%

2.7K
SM

IC

RP2BU

54

2.7K

5%
IC

SM

.063W

.063W

.063W

.063W

RP1BU

6

3

5%

2.7K
IC

SM

RP1BU

8

1

5%

2.7K
IC

SM

RP2BU

6

3

5%

2.7K
IC

SM

RP2BU

2

7

5%

2.7K
IC

SM

[PAGE_TITLE=PCI TERMINATION]

BPAGE DRAWING

frostburg_fabc.sch_1.50

Sun Mar 18 18:44:04 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

50

1

3.01

CR-51 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE51

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

D

R71BU

1

2

SW_ON_R_N

51

IN

33

402

VCC

1

C265BU

470PF

R72BU

1

330CH5%
402

2

CP3BU

4

470PF
20%
50V
EMPTY

5

SM

BOM=CORE_STDFNTPNL_E

R206LB

1

0

402

R11BU

1

0

402

VCC

HD_LED_G_N

51

IN

FP_RST_N

7

3336

C

B

7097

BOM NO TE:

OUT

DEFAULT EMPTY: STUFF 0 OHM RES (R206LB) FOR ICH PORT80 LED FEATURE (TDE EXPERIMENT)

ICH_PORT80_LED

3336

IN

33

ICH_QRT0

IN

GPIO_GRN_BLNK_HDR

70

IN

A

GPIO_YLW_BLNK_HDR

70

IN

2

2

7

2

5%

EMPTY

2

5%

EMPTY

R77BU

1

5%

4020CH

102276-304

R78BU

1

5%

4020CH

10%
50V
EMPTY
402

VCC_HDLED_PWR

CP3BU

470PF
20%
50V
EMPTY
SM

2

J18BU

1X3HDR2

HDR

2

CP1BU

3

470PF
20%
50V
EMPTY

6

SM

GPIO_GRN_BLNK_HDR_R

1

1

3

2

C263BU

470PF
10%
50V
EMPTY
603

1

C264BU

2

R12BU

1

IN

ICH_QRT1

7

3351

8

2

0

5%

402

EMPTY

GPIO_YLW_BLNK_HDR_R

6

5%
CH

470PF
10%
50V
EMPTY
603

SW_ON_N

1

C261BU

1.0UF
20%
10V

2

Y5V
603

OUT

BOM NO TE:

STUFF FOR EL

10K

402

OUT

51

R79BU

1

51

VCC

1

8

5

2

5%
CH

CP1BU

470PF
20%
50V
EMPTY
SM

EL_FET_R

OUT

8088

89

90

33

J16BU

2X5HDR_10

1
3
56
7
9

HDR

VCC

CP1BU

2

470PF
20%
50V
EMPTY

7

SM

3

Q6BU

1

MMBT3904
XSTR

2

1

2

37
91

V_5P0_STBY\G

IN

1

8

OUT

IN

CP3BU

470PF
20%
50V
EMPTY
SM

51

70

470
402

R75BU

1

3

6

2

5%
CH

CP3BU

470PF
20%
50V
EMPTY
SM

R74BU

1

2

5%

470
402

CH

GPIO_GRN_BLNK_HDR_R
GPIO_YLW_BLNK_HDR_R
SW_ON_R_N

ICH_QRT1

3351

IN

DESIGN NOTE:

707374

2
4

8

HD_LED_G_N

R80BU

0
5%

BOM NO TE:

EMPTY

EMPTY FOR EL

402

HD_LED_N

66

69

92

CP1BU

4

470PF
20%
50V
EMPTY

5

SM

CUSTOM FEATURE

[PAGE_TITLE=STD FRONT PANEL HDR]

BPAGE DRAWING

frostburg_fabc.sch_1.51

Sun Mar 18 18:44:06 2007

4 2

3

CONFIDENTIAL

CUSTOM TEXT BPAGE

10K
402

R9BU

1

EMPTY

INTEL

ICH_QRT1_R

2

5%

51

IN

51

IN

51

OUT

J5LH

1X2HDR

ICH_QRT1_Q

1

3

Q7BU

1

EMPTY
MMBT3904

2

DOCUMENT_NUMBER

xxxxxx

EMPTY

VCC

R104BU

2

ICH_QRT1_J

PAGE REV

51

1

D

C

B

2

EMPTY

1

330 5%

402

A

3.01

CR-52 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE52

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

D

R54BU

1

15K

5%

2

CH

USB_OC_FRONT1_N

402

R55BU

1

10K

5%

2

CH

USB_OC_FRONT1_R_N

42

IN

402

OUT

DESIGN NOTE:

STUFFING THE THERMISTOR ASSUMES FRONT PANEL CARD
HAS NO FUSE AND DOES NOT PROVIDE OVER-CURRENT PROTECTION

88
46
44

43
45
52
91
92

31

CAD NOTE:

DUAL FOOTPRINT: PLACE 0 OHM
1206 IN PARALLEL WITH THERMISTOR

BOM NO TE:

STUFF 0 OHM INSTEAD OF THERMISTOR FOR
PRODUCT WITH FUSE ON FRONT PANEL

5VDUAL_USB

IN

1.50

RT1BU

1

THRMSTR

C92281-001

R58BU

1

0

1206

EMPTY

2

2

5%

C

FRONT PANEL POWER #1

USB_FP1_PWR

1

R60BU

1

10K

5%

2

CH
402

C253BU

470UF
20%
10V
ALUM

2

RDL

CAD NOTE:

PLACE DECOUPLING AS CLOSE AS POSSIBLE

TO USB CONNECTOR

OUT

4242

D

C

FRONT PANEL POWER #2

DESIGN NOTE:

STUFFING THE THERMISTOR ASSUMES FRONT PANEL CARD
HAS NO FUSE AND DOES NOT PROVIDE OVER-CURRENT PROTECTION

92
4652

5VDUAL_USB

4243

IN

4445

91

R56BU

1

15K

5%

2

CH

USB_OC_FRONT2_N

402

R57BU

1

10K

B

43

USB_OC_FRONT2_R_N

IN

5%

2

CH
402

OUT

31

88

CAD NOTE:

DUAL FOOTPRINT: PLACE 0 OHM

1206 IN PARALLEL WITH THERMISTOR

BOM NO TE:

STUFF 0 OHM INSTEAD OF THERMISTOR FOR
PRODUCT WITH FUSE ON FRONT PANEL

1.50

RT2BU

1

THRMSTR

C92281-001

R59BU

1

0

EMPTY

1206

2

R61BU

1

10K

5%

2

CH

2

5%

402

CAD NOTE:

PLACE DECOUPLING AS CLOSE AS POSSIBLE

1

2

C254BU

470UF
20%

10V
ALUM
RDL

USB_FP2_PWR

OUT

43

B

TO USB CONNECTOR

FRONT PANEL POWER #3

DESIGN NOTE:

STUFFING THE THERMISTOR ASSUMES FRONT PANEL CARD
HAS NO FUSE AND DOES NOT PROVIDE OVER-CURRENT PROTECTION

92
4652

5VDUAL_USB

4243

IN

4445

91

R81BU

1

15K

5%

2

2

1

CH
402

R82BU

10K

5%
CH

402

USB_OC_FRONT3_N

OUT

31

A

44

USB_OC_FRONT3_R_N

IN

88

CAD NOTE:

DUAL FOOTPRINT: PLACE 0 OHM

1206 IN PARALLEL WITH THERMISTOR

BOM NO TE:

STUFF 0 OHM INSTEAD OF THERMISTOR FOR
PRODUCT WITH FUSE ON FRONT PANEL

1.50

RT8BU

1

THRMSTR

C92281-001

R83BU

1

0

1206

EMPTY

2

R84BU

1

10K

5%

2

CH

2

5%

402

1

2

CAD NOTE:

PLACE DECOUPLING AS CLOSE AS POSSIBLE

C307BU

470UF
20%

10V
ALUM
RDL

USB_FP3_PWR

OUT

44

A

TO USB CONNECTOR

BPAGE DRAWING

frostburg_fabc.sch_1.52

Sun Mar 18 18:44:07 2007

8

7

6

5

4 2

3

[PAGE_TITLE=USB_FP_HEADER_POWER]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

1

52

3.01

CR-53 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE53

D

1394 RESET CONTROL

C

13

33

IN

70

B

CHIP PWR SUPPLY

VCC3

A

8

3233343637

47

4849596469

102103105

PWRGD_3V

4849

49103

50

2

1

8

53
28

48

4849

C3FW

8284858687889092

20%
25V
Y5V
603

3839
101

.1UF

30

805

1

30

IN
IN

70
9212228

3036

0

R5FW

CK_P_33M_1394

IN

MBT3904DUAL

R8FW

2

10K

CH

402

5%

32

IN

IN

BI

OUT

1A
CH

2

1394_GRST

1

C2FW

49

22PF
5%
50V

2

<EMPTY>

603

V_3P3_STBY\G

R10FW

CH

5%

10K

402

Q1FW

5

1

1394_RST_INT2

1394_EN

2

EMPTY

P_GNT_N<3>

P_PME_N

P_REQ_N<3>

VA_3P3_1394

7

50103

106

30

48

IN

103

2

2

402

1

1

1394_RST_INT1

3

4

R6FW

1

0

402

5%

OUT

7

30

P_PCIRST_N

R9FW

CH

5%

10K

6

XSTR

1

53 55

OUT

2

P_INTD_N

1394_GRST

53

55

R15FW

1

0

402

OUT

1

R4FW

10K

402

1

R14FW

5%

0

EMPTY

402

V_3P3_1394_FILTERED

IN

6

6

5%
CH

CH

5%

2

4950103106
4950103106

2

53

30

48

49

103106

2

30

48

30

48

1

C10FW

0.1UF
20%
16V

2

EMPTY
402

IN

1394_CLKRUN_N

484950103
106

30

484950103106

BI

30

4849103106

BI

30

484950

BI

103

BI
BI
BI

55

IN

55

IN

55

IN

55

IN

55

IN

55

OUT

55

BI

1

1K

4025%CH

30

4849

BI

103106

P_C/BE_N<3..0>

30

BI

30

BI

484950103106

P_IRDY_N

P_PAR
P_PERR_N
P_PME_1394_N

P_SERR_N
P_STOP_N
P_TRDY_N

1394_CYCLEIN
1394_CYCLEOUT

1394_GPIO2

1394_GPIO3

R55FW

2

1

R1FW

1K

5%
CH

402

2

1

2

P_PCIRST_1394_R_N

P_AD<31..0>

19

1

R13FW

100

5%
CH

402

2

P_DEVSEL_N
P_FRAME_N

PCI_IDSEL_1394

1394_CNA

1394_SCL
1394_SDA

1394_PIN10_11

1394_TEST_089
1394_TEST_123

1

R2FW

1K
5%

CH
402

2

5

C1FW

22PF
5%
50V
EMPTY
402

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

0
1
2
3

45

U1FW

G_RST*
PCI_CLK
PCI_INTA*
PCI_RST*

PCI_AD<31>
PCI_AD<30>
PCI_AD<29>
PCI_AD<28>
PCI_AD<27>
PCI_AD<26>
PCI_AD<25>
PCI_AD<24>
PCI_AD<23>
PCI_AD<22>
PCI_AD<21>
PCI_AD<20>
PCI_AD<19>
PCI_AD<18>
PCI_AD<17>
PCI_AD<16>
PCI_AD<15>
PCI_AD<14>
PCI_AD<13>
PCI_AD<12>
PCI_AD<11>
PCI_AD<10>
PCI_AD<9>
PCI_AD<8>
PCI_AD<7>
PCI_AD<6>
PCI_AD<5>
PCI_AD<4>
PCI_AD<3>
PCI_AD<2>
PCI_AD<1>
PCI_AD<0>

PCI_C_BE0*
PCI_C_BE1*
PCI_C_BE2*
PCI_C_BE3*

PCI_CLKRUN*
PCI_DEVSEL*
PCI_FRAME*
PCI_GNT*
PCI_IDSEL
PCI_IRDY*
PCI_PAR
PCI_PERR*
PCI_PME*
PCI_REQ*
PCI_SERR*
PCI_STOP*
PCI_TRDY*

CNA
CYCLEIN
CYCLEOUT
GPIO2
GPIO3
SCL
SDA

TEST17
TEST16
TEST9
TEST8
TEST3
TEST2
TEST1
TEST0

TSB43AB22A

AVDD<5>
AVDD<4>
AVDD<3>
AVDD<2>
AVDD<1>

DVDD<8>
DVDD<7>
DVDD<6>
DVDD<5>
DVDD<4>
DVDD<3>
DVDD<2>
DVDD<1>

PLLVDD

VDDP<5>
VDDP<4>
VDDP<3>
VDDP<2>
VDDP<1>

FILTER0
FILTER1

TPA0P
TPA0M

TPA1P
TPA1M

TPB0P
TPB0M

TPB1P
TPB1M

TPBIAS0
TPBIAS1

AGND<7>
AGND<6>
AGND<5>
AGND<4>
AGND<3>
AGND<2>
AGND<1>

REG18
REG18

REG_EN*

DGND<10>

DGND<9>
DGND<8>
DGND<7>
DGND<6>
DGND<5>
DGND<4>
DGND<3>
DGND<2>
DGND<1>

PLLGND

XI
XO

CPS

PC0
PC1
PC2

R0
R1

14
16
13
85

22
24
25
26
28
29
31
32
37
38
40
41
42
43
45
46
61
63
65
66
67
69
70
71
74
76
77
79 99
80
81
82
84

73
60
47
34

12
53
49
18
36
50
58
56
21
19
57
54
52

96
87
86
90
89
91
92

10
11
94

95
101
102
104
105

NC=129

4 2

3

120
108
107
2

VA_3P3_1394

1
100

88

V_3P3_1394_FILTERED

72
59
51
39
27
15

1394_PLLVDD

7
78

62
48
35
20

5
6

1394_CPS

106

1394_FILTER0

3

1394_FILTER1

4

1394_PC0

98

1394_PC2

97
115

114
124

123
113

112
122

121
116

125
118

119

128
127
126
117
111
110
109

93
30
9
103
83
75
68
64
55
44
33
23
17

R16FW

1

1394_PC1

402

1

402

1394_TPA0P

1394_TPA0N
1394_TPA1P

1394_TPA1N

1394_TPB0P
1394_TPB0N

1394_TPB1P
1394_TPB1N

1394_TPBIAS0
1394_TPBIAS1

1394_R0
1394_R1

CAD NOTE:

GROUND REFERENCE TOP LAYER
UNDER PART INSTEAD OF CREATING AGND PLANE

REG18_30

8

IC

BPAGE DRAWING

frostburg_fabc.sch_1.53

Sun Mar 18 18:44:08 2007

3

470

R18FW

1

6.34K
603

REG18_93

2

1

1394_XI
1394_XO

2

CH

5%

CH

5%470

R12FW

C11FW

.1UF
20%
25V
Y5V
603

C8FW

2

20%

16V

1

2

402

1%

CH

53

IN

VCC

1

R3FW

390K

402

1

0.1UF
Y5V

402

R17FW

2

CH

470

5%

54

BI

54

BI

54

BI

54

BI

54

BI

54

BI

54

BI

54

BI

BI
BI

2

2

C9FW

.1UF
20%
25V

1

Y5V
603

CUSTOM TEXT BPAGE

54
54

55

5%

CH

OUT

BOM NO TE:

2

VCC3

2

53 55

1

1

402

1

R11FW

402

R56FW

R57FW

402

0

EMPTY

+12V

0

0

EMPTY

5%

MODULE REV DETAILS

MODULE NAME

TI_1394A_2

1

C7FW

10UF
20%

6.3V

2

X5R
805

NEVER STUFF BOTH

2

CK_XT_24M_1394

5%

CH

2

5%

1394_XI_R

1

2

R7FW

1.0M
5%

EMPTY
603

2

1394_XO_R

DESIGN NOTE:

IRQ MAP

ABCD
DCFG

1.05.00

1

Y1FW

24.576MHZ
SM
EMPTY

2

VCC3

1

2

1

2

REV

FB1FW
FB

C6FW

1000PF

10%
50V
X7R
402

22PF

50V

C4FW

1

22PF

EMPTY

50V

1

C5FW

1

EMPTY

603

603

[PAGE_TITLE=1394 CONTROLLER]

INTEL

CONFIDENTIAL

DOCUMENT_NUMBER

xxxxxx

12.30.05

IN

2

5%

2

5%

PAGE REV

53

1

DATE

D

29

C

B

A

3.01

CR-54 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE54

53

D

53

BI

53

BI

CAD NOTE:

PLACE CLOSE TO CONTROLLER

C

53

53

53

B

53

BI

53

BI

CAD NOTE:

PLACE CLOSE TO CONTROLLER

A

53

53

BI

BI

BI

BI

BI

BI

8

1394_TPBIAS0

1394_TPA0N

1394_TPA0P

1394_TPB0N

1394_TPB0P

1394_TPBIAS1

1394_TPA1N

1394_TPA1P

1394_TPB1N

1394_TPB1P

8

CAD NOTE:

PLACE CLOSE TO CONTROLLER

1

1

C12FW

1UF

20%

6.3V

2

X5R
603

2

1394_TPB0_PD

1

1

2

1

2

R31FW

C14FW

5.11K

220PF
10%
50V
X7R
402

CAD NOTE:

PLACE CLOSE TO CONTROLLER

1394_TPB1_PD

C16FW
220PF
10%
50V
X7R
402

1

1%

CH
402

2

2

1

1

C15FW

1UF

20%

6.3V

2

X5R
603

2

1

R41FW

5.11K

1

1%

CH
402

2

2

7

R34FW

54.9
1%

CH
402

R27FW

54.9
1%

CH
402

R37FW

54.9
1%

CH
402

R39FW

54.9
1%

CH
402

7

1

R25FW

54.9
1%

CH
402

2

1

R29FW

54.9
1%

CH
402

2

CAD NOTE:

TRACE WIDTH = 3.9 MIL
SPACING = 8.1 MIL
SPACING TO OTHER
LINES = 15 MIL

1

R38FW

54.9
1%

CH
402

2

1

R40FW

54.9
1%

CH
402

2

CAD NOTE:

TRACE WIDTH = 3.9 MIL
SPACING = 8.1 MIL
SPACING TO OTHER
LINES = 15 MIL

6

603

603

603

CAD NOTE:

PLACE CLOSE TO 1394 HDR

603

603

603

6

603

603

R19FW
1

0

R20FW
1

0

R21FW
1

0

0

R42FW
1

0

R43FW
1

0

R44FW
1

0

0

1

1

R22FW

R45FW

2

1A

CH

2

1A

CH

2

1A

CH

2

1A

CH

2

1A

CH

2

1A

CH

2

1A

CH

2

1A

CH

L2FW

2

90OHM

ACM2012

90OHM

ACM2012

2

90OHM

ACM2012

90OHM

ACM2012

2

90OHM

ACM2012 EMPTY

1

90OHM

ACM2012

ACM2012

ACM2012

3

EMPTY

L2FW

4

1

EMPTY

L1FW

3

EMPTY

L1FW

4

1

EMPTY

L5FW

3

L5FW

4

EMPTY

L6FW

2

90OHM

1

90OHM

3

EMPTY

L6FW

4

EMPTY

CAD NOTE:

PLACE CLOSE TO 1394 HEADER

5

TPA0M_1394

TPA0P_1394

TPB0M_1394

TPB0P_1394

45

CAD NOTE:

TRACE WIDTH = 3.9 MIL
SPACING = 8.1 MIL
SPACING TO OTHER
LINES = 15 MIL

TPB1M_1394

TPB1P_1394

CAD NOTE:

TRACE WIDTH = 3.9 MIL
SPACING = 8.1 MIL
SPACING TO OTHER
LINES = 15 MIL

Sun Mar 18 18:44:10 2007

4 2

3

TPA1M_1394

TPA1P_1394

BPAGE DRAWING

frostburg_fabc.sch_1.54

3

55

IN

2

1394_PWR0

FW
1394

J12FW

1394VERT_6PIN

5

TPA-

6

TPA+

1

PWR GND

CASE_GND
CASE_GND
CASE_GND

1394_PWR1

1

C17FW
470PF
10%
50V

2

X7R
402

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

1

MODULE REV DETAILS

MODULE NAME

TI_1394A_2

J1FW

2X5HDR_9

1
3
56
7

A91836-021

2
4

8
10

1.05.00

REV

DATE

12.30.05

HDR

3

TPB-

4

TPB+

2
7

8
9

CONN

55

IN

CAD NOTE:

PLACE CAP AS CLOSE AS POSSIBLE
TO CONNECTOR

[PAGE_TITLE=1394 BP REV1]

DOCUMENT_NUMBER

xxxxxx

PAGE REV

54

1

D

C

B

A

3.01

CR-55 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE55

8

1

R53FW

D

BOM NO TE:

STUFF BOTH RESISTORS FOR
1394 DOWN W/O EEPROM

220
5%

CH
402

2

53

IN

C

1394_SDA

1394_SCL

BI

1

2

53

R52FW

220
5%

CH
402

1

2

1

2

C49FW

100PF
5%
50V

<EMPTY>

402

C18FW

100PF
5%
50V

<EMPTY>

402

2

MODULE REV DETAILS

MODULE NAME

TI_1394A_2

1394_PWR0

CAD NOTE:

PLACE NEAR
THE HEADER

1394_PWR1

CAD NOTE:

PLACE NEAR
THE HEADER

+12V

+12V

45

CR3FW
MRA4003T3

1394_PWR0_DIO

2

1

SM
DIO

CR1FW
MRA4003T3

1394_PWR1_DIO

2

1

SM
DIO

7

6

EEPROM

RT3FW

1

1.5

657448-018

RT2FW

1

1.5

657448-018

3

2

THRMSTR

2

THRMSTR

2

2

1

1

C48FW

.1UF
20%
50V
X7R
805

C19FW

.1UF
20%
50V
X7R
805

1.05.00

OUT

OUT

1

REV

DATE

12.30.05

54

D

54

C

7

1

2

R49FW

4.7K
5%

CH
402

1

R47FW

4.7K
5%

CH
402

2

1

R48FW

220
5%

EMPTY
402

2

53

OUT

53

OUT

1

R46FW

4.7K
5%

CH
402

B

53

OUT

53

OUT

53

OUT

1394_CNA
1394_CYCLEIN
1394_CYCLEOUT

2

A

- GLOBAL RESET IS A POWER ON RESET

- 1394 CONTROLLER IS COMPLETELY NON-FUNCTIONAL WHEN ASSERTED

- ALL REGISTERS ARE SET TO THEIR DEFAULT STATES, INCLUDING ONES NOT RESET BY PCI_RST

8

V_3P3_1394_FILTERED

BOM NO TE:

STUFF FOR CARDBUS MODE

1

1394_GPIO2

1394_GPIO3

R51FW

220
402

1

R50FW

220
402

6

53 55

IN

1

1

1

C45FW

10UF

20%

6.3V

2

EMPTY

2

805

53 55

OUT

C30FW
10UF
20%

6.3V
EMPTY
805

1

1

C27FW

C26FW
1000PF

1000PF

10%

10%

50V

50V

2

2

X7R

X7R

402

402

1

1

2

C29FW

1000PF

10%
50V
X7R
402

C28FW

0.1UF
20%
16V

2

2

Y5V
402

V_3P3_1394_FILTERED

1

C39FW

0.1UF
20%
16V

2

Y5V

C31FW

0.1UF
20%
16V
Y5V
402

402

1

2

1

2

1

C35FW

0.1UF
20%
16V

2

Y5V
402

1

2

C42FW

100UF

20.0%
25V
EMPTY
RDL

1

C43FW
.01UF
10%
25V

2

X7R

C38FW

10UF

20%

6.3V
X5R
805

402

1

2

1

C34FW

0.1UF
20%

C47FW

0.1UF
20%

16V
Y5V
402

16V

2

Y5V
402

1

2

C23FW

0.1UF
20%
16V
Y5V
402

C44FW

0.1UF
20%

16V
Y5V
402

VA_3P3_1394

1

C32FW

0.1UF
20%

16V

2

Y5V
402

1

2

1

C36FW

0.1UF
20%
16V

2

Y5V
402

1

C41FW

0.1UF
20%
16V
Y5V
402

FB2FW

53

IN

VCC3

2

FB

B

VCC

2

5%
CH

1

1

1

1

2

5%
CH

2

C22FW

.001UF
20%
50V
X7R
603

C33FW

C46FW

.001UF

.001UF
20%

20%

50V

50V

2

2

X7R

X7R
603

603

1

C40FW

C37FW

.001UF

.001UF

20%

20%

50V

2

50V

2

X7R

X7R
603

603

A

1394 DECOUPLING

[PAGE_TITLE=1394 PWR/DCPL]

5

BPAGE DRAWING

frostburg_fabc.sch_1.55

Sun Mar 18 18:44:11 2007

4 2

3

CONFIDENTIAL

CUSTOM TEXT BPAGE

INTEL

DOCUMENT_NUMBER

xxxxxx

PAGE REV

55

1

3.01

CR-56 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE56

8

56

D

BOM NO TE:

STUFF FOR NINEVEH
EMPTY FOR EKRON

R5LN

1

2

1.4K

1%

402

CH

01.03.00
INTEL_LAN

R6LN

RES_TESTPROBE

A

B

1

EMPTY

LAN_DISABLE_N

2

603

1

C

33

IN

BOM NO TE:

STUFF 0 OHM STRAP (BETWEEN LAN_DISABLE_N AND LAN_DISABLE_N_R FOR EKRON
EMPTY FOR NINEVEH

B

HSI6_DP

56

IN

HSI6_DN HSI6_C_DN

56

IN

CAD NOTE:

PLACE NEAR LAN / NINEVEH CONTROLLER

1

R2LN

649

1%

EMPTY
402

A

2

BOM NO TE:

STUFF (A93548-011) 649 OHM FOR EKRON
EMPTY FOR NINEVEH

01.03.00

1

INTEL_LAN

R3LN

619

1%

EMPTY
402

BOM NO TE:

2

STUFF 619 1% FOR EKRON
EMPTY 619 OHM FOR NINEVEH

56

31
31

56
56

58

IEEE_TEST_LAN_P
IEEE_TEST_LAN_N

56
56

56

R38LN

2

1

0

1A

EMPTY

C1LN

1

.1UF 10%

10V
X5R
402

C2LN

1

.1UF210%

10V
X5R
402

OUT
OUT

IN
IN

IN
IN

OUT

IN
IN

IN

LAN_DISABLE_N_R

8

7

HSI6_DP

HSI6_DN

HSO6_C_DP

HSO6_C_DN

TP_LAN_J6
TP_LAN_J7

KMRN_RCOMP_DP
KMRN_RCOMP_DN

LAN_RBIAS_P

TP_LAN_1P0_CTRL

LAN_1P8_CTRL

LAN_ISOL_TCK_R
LAN_ISOL_TI_R

TP_LAN_JTDO_G3

LAN_ISOL_EXEC_R

2

HSI6_C_DP

7

TP_LAN_THERM_DP
TP_LAN_THERM_DN

OUT

1

R7LN

1.4K
1%

CH
402

2

H2
J2
J4
H4

J6
J7

G7
H7

E7
E6

C3
B2

A2
A3

A7
B7

G1
H1
G3
G2

56

OUT

OUT

BOM NO TE:

EMPTY FOR EKRON
STUFF FOR NINEVEH

KMRN_RCOMP_DP

KMRN_RCOMP_DN

BOM NO TE:

EMPTY FOR EKRON
STUFF FOR NINEVEH

GLAN_TXP/NC
GLAN_TXN/NC
GLAN_RXP/NC
GLAN_RXN/NC

RSVD_J6/NC
RSVD_J7/NC

KBIAS_P/RBIAS100
KBIAS_N/RBIAS10

RBIAS_P/NC
RBIAS_N/NC

CTRL_10/NC
CTRL_18/NC

THERM_D_P/NC
THERM_D_N/NC

IEEE_TEST_P/NC
IEEE_TEST_N/NC

JTAG_TCK/ISOL_TCK
JTAG_TDI/ISOL_TI
JTAG_TDO/TOUT
JTAG_TMS/ISOL_EXEC

1

31

31

OUT

OUT

6

BOM NO TE:

FOR EKRON USE IPN D23402-001

MDI_PLUS0/TDP

MDI_MINUS0/TDN

MDI_PLUS1/RDP

MDI_MINUS1/RDN

MDI_PLUS2/NC

MDI_MINUS2/NC

MDI_PLUS3/NC

MDI_MINUS3/NC

JKCLK/JCLK

JRSTSYNC

LED0/LINK_UP*
LED1/ACT_LED*

LED2/SPEED_LED*

XTAL1/X1
XTAL2/X2

TEST_EN

RSVD_C5/NC

1of 2

R1LN

2

1

1A

0

CH

603

B1
D7
D4
E4
E8
E5
G4
F7
H3

C2
D5
F5
G5

F2
B3

JTXD0
JTXD1
JTXD2
JRXD0
JRXD1
JRXD2

RSVD

IC

D20909-002

NINEVEH0P99B

V1P0_OUT/NC
VDD1P0/VCCR
VCC
VCC/VCC
VDD1P0/VCCT
VCCF1P0/VCC
VCC1P0/VCCA2
VDD1P0/VCCA
VCCFC1P0/VCC

VCC1P8/NC
VCC1P8/NC
VCC1P8/NC
VCC1P8/NC

VCC3P3/VCCP
VCC3P3/VCC

B8
B9
D9
D8
F9
F8
H8
H9

D1
F3
F1
D3
D2
C1
E2
E3

A4
B4
A5

H6
H5

B6
B5
A6
C5

U1LN

92
56
58

92
56
58

57
58
88
57
40
38
33
27
28
34
39
56
58
92

NINEVEH0P99B

LAN_V_1P0

OUT

LAN_V1P0_OUT
LAN_V_1P0

IN

IN

V_3P3_EPW

IN

D20909-002

U1LN

RSVD_A6/ADV10-LAN_DIS*

LAN_V_1P8

1

56

[PAGE_TITLE= LAN NINEVEH]

6

5

45

LAN_MDI0_DP
LAN_MDI0_DN
LAN_MDI1_DP
LAN_MDI1_DN
LAN_MDI2_DP
LAN_MDI2_DN
LAN_MDI3_DP
LAN_MDI3_DN

ICH_LAN_JTX0
ICH_LAN_JTX1
ICH_LAN_JTX2
ICH_LAN_JRX0
ICH_LAN_JRX1
ICH_LAN_JRX2
ICH_LAN_JCLK_R
ICH_LAN_JRST

LAN_LED0
LAN_LED1
LAN_LED2

LAN_XTL_DP
LAN_XTL_DN

LAN_TESTEN
TP_LAN_TEST0
LAN_DISABLE_N_R
TP_LAN_C5

VSS/NC

VSS

VSS/VSSP

VSS/VSS
VSSA/NC
VSSA/NC

VSSA/VSSA2

VSSA/VSS

VSSA/NC
VSSA/VSS
VSSA/VSS
VSSA/VSS
VSSA/VSS
VSSA/VSS
VSSA/VSS
VSSA/VSS
VSSA/VSS
VSSA/VSS

VSSA/VSSR

VSSA/NC
VSSA/VSS

2of 2

57

BI

57

BI

57

BI

57

BI

57

BI

57

BI

57

BI

57

BI

33

IN

33

IN

33

IN

33

OUT

33

OUT

33

OUT

56

OUT

33

IN

57

OUT

57

OUT

57

OUT

56

IN

56

OUT

56

IN

56

IN

A1
C4
E1
F4
J9
J8
J5
J3
J1
G9
G8
G6
F6
E9
D6
C9
C8
C7
C6
A9
A8

IC

Sun Mar 18 18:44:12 2007

4 2

3

BOM NO TE:

EKRON MODE SELECT OPTIONS: FOLLOW BELOW FOR
RESISTOR STUFFING CONFIGURATION

TESTEN
ISOL_TCK
ISOL_TI
ISOL_EXEC

33

27

IN

28

34
38

39
40
56
57
58
88
92

BOM NO TE:

PLACE JCLK TERMINATION (R16LN) CLOSE TO LAN

33

TO ICH

LAN CRYSTAL

25.000MHZ

1

LAN_XTL_DN

56

IN

BPAGE DRAWING

frostburg_fabc.sch_1.56

3

MODE 0

NOT SUPPORTED
NOT SUPPORTED
NOT SUPPORTED 1 (EXTERNAL)
NOT SUPPORTED

V_3P3_EPW

R36LN

220
5%

EMPTY
402

1

2

1

2

2

1

ICH_LAN_JCLK

OUT

0

402

BOM NO TE:

STUFF R46LN FOR CRYSTAL, EMPTY FOR CLK GEN
STUFF C35LN, EMPTY FOR CRYSTAL

Y1LN

2

A93545-056

SM
XTAL

R37LN

220
5%

EMPTY
402

R39LN

1K

5%
EMPTY

402

R46LN

2

MODE 1

0(EXTERNAL)
0 (INTERNAL)

1(EXTERNAL)

CUSTOM TEXT BPAGE

MODE 2

1(EXTERNAL)
0(EXTERNAL)
0(EXTERNAL)
1(EXTERNAL)

R45LN

1

220
5%

2

EMPTY
402

R40LN

2

1K

5%

1

EMPTY
402

R16LN

1

33

402

5%

C35LN

CH

5%

10PF

50V

EMPTY

402

C22LN

1

2

27PF

5%
50V
COG
402

INTEL

CONFIDENTIAL

MODULE REV DETAILS

MODULE NAME

MODE 4MODE 3

1(EXTERNAL)

1 (EXTERNAL)

1(EXTERNAL)0 (INTERNAL)
0 (INTERNAL)

1 (EXTERNAL)

0 (INTERNAL)

1 (EXTERNAL)

R41LN

1

220
5%

2

EMPTY
402

LAN_TESTEN

LAN_ISOL_TCK_R

LAN_ISOL_TI_R

LAN_ISOL_EXEC_R

R11LN

2

100

5%

1

CH
402

BOM NO TE:

STUFF R11LN FOR NINEVEH
ALL OTHERS ARE EMPTY

2

ICH_LAN_JCLK_R

5%
CH

CK_XT_25M_LAN_R

C36LN

10PF
5%
50V
EMPTY
402

33 5%

402

C23LN

1

27PF

50V
COG
402

R47LN

EMPTY

2

5%

DOCUMENT_NUMBER

xxxxxx

1

REV

56

OUT

56

OUT

56

OUT

56

OUT

IN

FROM LAN

LAN_XTL_DPLAN_XTL_DP_R

CK_XT_25M_LAN

1

DATE

12-08-0601.03.00BL_INTEL_LAN

56

OUT

PAGE REV

56

D

C

B

56

29

IN

A

3.01

CR-57 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE57

8

D

7

6

BOM NO TE:

DEFAULT: STUFF C24LN FOR NINEVEH
EMPTY (UN-STUFF) CAP FOR EKRON

58

LAN_V_1P8

56

IN

1

C24LN

1000PF
10%
50V

2

X7R
402

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

12-08-0601.03.00BL_INTEL_LAN

D

LAN CONNECTOR

DEFAULT GIGABIT

MAGJACK BI-COLOR SPEED LED

10 MBPS OFF

100 MBPS GREEN

C

1000 MBPS YELLOW

USB STACK

VREG_USB_BP_MJ

4657

IN

91

USB_BACK3_R_DN

46

BI

USB_BACK3_R_DP

46

BI

VREG_USB_BP_MJ

4657

IN

91

USB_BACK1_R_DN

46

BI

USB_BACK1_R_DP

46

BI

B

56

56

56

56

LAN_MDI0_DP

BI

LAN_DIFF_TAP_0

1

2

LAN_MDI0_DN

BI

LAN_MDI1_DP

BI

LAN_DIFF_TAP_1

1

2

LAN_MDI1_DN

BI

C33LN

.1UF
10%

10V
X5R
402

C32LN

.1UF

10%

10V
X5R
402

57

57

57

A

57

DEFAULT: STUFF FOR NINEVEH
EMPTY (UN-STUFF) CAPS FOR EKRON

DIFFERENTIAL PAIR TERMINATONS

8

LAN_MDI0_DP

BI

LAN_MDI0_DN

BI

LAN_MDI1_DP

BI

LAN_MDI1_DN

BI

LAN_MDI2_DP

BI

LAN_MDI2_DN

BI

LAN_MDI3_DP

BI

LAN_MDI3_DN

BI

BOM NO TE:

DEFAULT (JA1LN): C73572-005 (NINEVEH)
OPTIONAL(JA1LN): C51242-005 (EKRON-N)

JA1LN

2XUSB

1
2

3

4

5
6
7
8

1000

56

57

56

57

56

57

56

57

56

57

56

57

56

57

56

57

IO

R35LN

1

49.9
1%
CH

2

402

R34LN

1

49.9
1%

2

CH

402

R33LN

1

49.9
1%

2

CH

402

R32LN

1

49.9
1%

2

CH

402

BOM NO TE:

DEFAULT: STUFF (4) RES WITH 49.9 OHM

(A93548-045) FOR NINEVEH

CHANGE (4) RES TO 54.9 OHM

(A93548-279) FOR EKRON

7

C73572-005

JA1LN

GBE_MAGJACK3_10

10
11

12
13

14
15

16
17

57

57

57

57

TD0+
TD0-

TD1+
TD1-

TD2+
TD2-

TD3+
TD3-

GND=23..30

56

56

56

56

9

VCT

18

SGND

1

2

IO

BOM NO TE:

DEFAULT: STUFF FOR NINEVEH
EMPTY (UN-STUFF) CAP/RES FOR EKRON

LAN_MDI2_DP

BI

LAN_DIFF_TAP_2

1

C31LN

.1UF
10%
10V

2

X5R
402

LAN_MDI2_DN

BI

LAN_MDI3_DP

BI

BI

BOM NO TE:BOM NO TE:

DEFAULT: STUFF FOR NINEVEH
EMPTY (UN-STUFF) CAPS, RESISTORS FOR EKRON

LAN_DIFF_TAP_3

1

C30LN

.1UF
10%
10V

2

X5R
402

LAN_MDI3_DN

6

LAN_VCT

CAD NOTE:

PLACE CAP/RES NEAR MAGJACK_PIN9

C27LN

470PF
10%
50V
X7R
402

R27LN

1

0

805

1A
CH

1

2

1

2

1

2

1

2

2

R31LN

49.9
1%

CH

402

R30LN

49.9
1%

CH

402

R29LN

49.9
1%

CH

402

R28LN

49.9
1%

CH

402

[PAGE_TITLE= LAN NINEVEH]

5

R23LN

1

R25LN

1

0

402

BOM NO TE:

STUFF RES (R24LN, R26LN)
FOR EKRON

2

5%CH0

R24LN

1

2

0

5%

EMPTY

402

R26LN

1

2

0

5%

EMPTY

402

2

5%
CH

3

V_3P3_R_LAN

LAN_R_LED1

BOM NO TE:

STUFF RES (R23LN, R25LN)
FOR NINEVEH

IN

92
88

LAN_LED1

58

56

57

IN

57
56
40
39
38
33

V_3P3_EPW

27

IN

28
34

LAN_LED1

56

IN

57

402

BPAGE DRAWING

frostburg_fabc.sch_1.57

Sun Mar 18 18:44:14 2007

4 2

1

C29LN

470PF
10%
50V

2

X7R
402

1

C26LN

470PF
10%
50V

2

X7R
402

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

JA1LN

GRN_LED

20

IO

JA1LN

GRN_LED

22

YLW_LED

DOCUMENT_NUMBER

19

21

IO

xxxxxx

LAN_LED0V_3P3_EPW

1

C28LN

470PF

10%

50V

2

X7R
402

LAN_LED2

1

C25LN

470PF

10%

50V

2

X7R
402

OUT

BI

PAGE REV

57

1

C

56

56

B

A

3.01

CR-58 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE58

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

BL_INTEL_LAN 01.03.00 12-08-06

1

REV

DATE

D

DESIGN NOTE:

0 OHM BYPASS RESISTOR: REQUIRED AS 0603, PER DESIGN ENGINEER

92
88

BOM NO TE:

58
57

EMPTY (UN-STUFF) 0 OHM BYPASS RESISTOR FOR NINEVEH LAN

56
40

STUFF 0 OHM BYPASS RESISTOR FOR EKRON
38
33

27
28

34
39

BOM NO TE:

NINEVEH LAN; STUFF C15LN, C16LN, C17LN

C

B

1

C20LN

0.1UF
20%

16V

2

EMPTY
402

3839

27

28

3334
4056
57

58

8892

CAD NOTE:

PLACE V_3P3_EPW DECOUPLING
CAPS NEAR XSTR

IN

LAN_1P8_CTRL

56

IN

1

C18LN

4.7UF
20%
10V

2

EMPTY
805

V_3P3_EPW

1

C12LN

4.7UF
20%
10V

2

Y5V
805

EKRON LAN: STUFF ALL

1

C15LN

C9LN

470PF

0.1UF

10%

20%

50V

2

16V

X7R

EMPTY

402

402

1

R8LN

C5LN

1.5

0.1UF
20%
16V

2

Y5V

2010

402

1

C34LN

.01UF
10%

25V

2

X7R
402

CAD NOTE:

0.5INCH X 0.5INCH THERMAL RELIEF
PAD NEEDS ON TRANSISTOR
PLACE C34LN NEAR XSTR

A

BOM NO TE:

NINEVEH LAN; STUFF CAPACITORS, RESISTOR, XSTR
EKRON LAN: UN-STUFF CAPACITORS, RESISTOR, XSTR

IN

1

2

R44LN

1

1%
CH

2

LAN_V3P3_EPW_XSTR_DRAIN

1

C17LN

0.1UF

1.5

2010

20%

16V
Y5V
402

1%
CH

Q1LN

BCP69T1
XSTR
432

V_3P3_EPW

LAN_V_1P0

1

2

1

2

C16LN

4.7UF

R14LN

2

1

0

1A

EMPTY

603

56

1

C8LN

10UF

20%

20%

10V

6.3V

2

Y5V

EMPTY

805

805

OUT

1

2

58

92

1P8 VOLT VREG

C4LN

470PF
10%
50V
X7R
402

LAN_V_1P8

1

1

C3LN

10UF
20%

6.3V

2

2

X5R
805

BOM NO TE:

EKRON LAN: UN-STUFF CAPACITORS

1

1

C21LN
470PF
10%
50V

2

2

X7R
402

C7LN

0.1UF
20%
16V
Y5V
402

8892

V_3P3_EPW

27

28

333438

IN

40

5657

39

1

1

2

C10LN

4.7UF
20%

10V
Y5V
805

C11LN

4.7UF
10%

6.3V

2

X5R
603

OUT

1

2

56

1

C13LN

C6LN

0.1UF

4.7UF

20%

20%

16V

10V

2

Y5V

Y5V

402

805

57

D

C

B

A

BPAGE DRAWING

[PAGE_TITLE= LAN NINEVEH]

8

7

6

5

4 2

frostburg_fabc.sch_1.58

Sun Mar 18 18:44:15 2007

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

58

1

3.01

CR-59 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE59

8

D

C

B

BOM NO TE:

DEFAULT: STUFF 0 OHM (108506-004, 0603)
OPTIONAL: FERRITE BEAD (693286-014, 0603)

VCC3

M17AU

1

CH

A

CAD NOTE:

PLACE NEXT
TO PIN 1

MULTI

2

603

2

C1AU

10UF
20%

6.3V

1

X5R
805

8

OUT

7

AUD_CODEC_VREF

60

IN

37

OUT

60

37

IN

C98AU

10PF

5%

50V

EMPTY

402

59

2

C5AU

.1UF
10%
16V

1

X7R
603

37

1

59

2

60

61

67

60

6264

606263

6066

V_AUD_DIGITAL

2

C3AU

.1UF
10%
16V

1

X7R
603

CAD NOTE:

PLACE NEXT TO
PINS 9

OUT

IN
IN

IN

OUT

OUT

OUT

IN

2

1

C4AU

2

5%

10PF
50V
COG
402

AUD_LINK_BCLK
AUD_LINK_SDI2_R

AUD_LINK_SYNC
AUD_LINK_RST_N

AUD_PC_BEEP

TP_AUD_CD_IN_L
TP_AUD_CD_GND
TP_AUD_CD_IN_R

TP_AUD_SPDIF_IN

AUD_SPDIF_OUT

AUD_SENSE_A

AUD_SENSE_B

V_AUD_ANALOG

TP_AUD_GPIO1

C110AU

10UF

20%

6.3V
X5R
805

7

6

BOM NO TE:

ALC268- D72688-001
ALC888- D72853-001

1

27

VREF

6

BCLK

8

SDATA_IN

5

SDATA_OUT

10

SYNC

11

RESET*

12

BEEP

18

CD_L

19

CD_GND

20

CD_R

47

SPDIFI/EAPD

48

SPDIFO

13

SENSE_A

34

SENSE_B

U1AU

ALC885

REV=1

PORT_A_VREFO/DCVOL

25

AVDD1

38

AVDD2

3

GPIO1

1

DVDD

9

DVDD_IO

1OF1

STAC9271D- D35875-004

PORT_A_L
PORT_A_R

PORT_B_L
PORT_B_R

PORT_C_L
PORT_C_R

PORT_D_L
PORT_D_R

PORT_E_L
PORT_E_R

PORT_F_L
PORT_F_R

PORT_G_L
PORT_G_R

PORT_H_L
PORT_H_R

PORT_B_VREFO
PORT_C_VREFO
PORT_D_VREFO
PORT_E_VREFO
PORT_F_VREFO

JDREF

AVSS1
AVSS2
GPIO0

DVSS
DVSS

VRP

AUD_PORT_A_L

39

AUD_PORT_A_R

41

AUD_PORT_B_L

21

AUD_PORT_B_RAUD_LINK_SDO

22

AUD_PORT_C_L

23

AUD_PORT_C_R

24

AUD_PORT_D_L

35

AUD_PORT_D_R

36

AUD_PORT_E_L

14

AUD_PORT_E_R

15

AUD_PORT_F_L

16

AUD_PORT_F_R

17

AUD_PORT_G_L

43

AUD_PORT_G_R

44

TP_AUD_PORT_H_L

45

TP_AUD_PORT_H_R

46

TP_AUD_VREF_37

37

AUD_VREF_28

28

TP_AUD_VREF_29

29

AUD_VREF_32

32

AUD_VREF_31

31

AUD_VREF_30

30

AUD_FILTER_33

33

AUD_DVDD_CORE_40

40

26
42
2

TP_AUD_VOL_2

4
7

IC

6

5

45

64

BI

64

BI

64

BI

64

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

62

BI

63

BI

63

BI

65

OUT

65

OUT

65

OUT

65

OUT

60

OUT

R148AU

402

R149AU

AUD

1

20K
1%

2

CH
402

AUD

Sun Mar 18 18:44:16 2007

4 2

3

SURR REAR L/R

PORT F

CEN / LFE

S/PDIFF OUT

HEADPHONE PORT A

MIC PORT B

DESIGN NOTE:

70

8284

323334

47

48

63

63

1

0

EMPTY

BOM NO TE:

DEFAULT: ALC268/888- R148AU= EMPTY, R149AU=STUFF
OPTION: STAC9271D- R148AU=STUFF, R149AU=EMPTY

BPAGE DRAWING

frostburg_fabc.sch_1.59

9092

DESIGN NOTE:

GPIO LOW=CODEC DOWN ENABLE
GPIO HIGH=CODEC DOWN DISABLE

BOM NO TE:

STUFF:MEDIA SKU
EMPTY:CLASSIC SKU

37

IN

2

V_AUD_DIGITAL

5%

3

CODEC DOWN DISABLE CIRCUIT

101
49536469
9212228

IN

36373839

8788

8586

102103105

R74AU

2

1

AUD_LINK_RST_N_PIN5

5%

100

EMPTY

402

33

IN

AUD_LINK_RST_CDC

59

IN

2

MODULE REV DETAILS

MODULE NAME

LINE IN / SURR SIDE
PORT C

FRONT / LINE OUT
PORT DPORT G

MIC IN
PORT F/E

FACING BACK PANEL

SIGMATEL, REALTEK

DESIGN NOTE:

AZALIA:
SIGMATEL-STAC9271D (5 STACKS)
REALTEK- ALC268/888 (3 STACKS)

V_3P3_STBY\G

R71AU

1

AUD_LINK_RST_N_PIN3

3

1

2

EMPTY

Q3AU

1K
5%

2

EMPTY
402

AUD_LINK_RST_N

AUD_LINK_RST_N_PIN2

R75AU

1

0

402

BOM NO TE:

STUFF:CLASSIC SKU
EMPTY:MEDIA SKU

Q4AU

EMPTY

1

CDC_DWN_DISABLE

2

1

3

2

R70AU

1K
5%

EMPTY
402

[PAGE_TITLE=AUDIO CODEC]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

5%
CH

2

0.06.00BL AUDIO

R73AU

1

100
402

REV

EMPTY

5%

1

2

PAGE REV

1

10-12-06

OUT

59

DATE

D

C

59

B

A

3.01

CR-60 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE60

8

CAD NOTE:

PLACE NEAR CDC PINS

7

6

45

3

JACK DETECT NETWORK

D

AUD_LINK_SDI2_R

59

IN

C

B

R14AU

AUD_LINK_SDI2

1

2

5%

33

CH

402

CAD NOTE:

PLACE NEXT TO PIN 25

1

1

C11AU

.1UF

10UF

10%

20%

6.3V

2

10V

2

X5R

X5R

805

402

33

OUT

CAD NOTE:

PLACE NEXT TO PIN 38

1

1

C16AUC13AU

C17AU

10UF

.1UF

20%

10%

6.3V

2

10V

2

X5R

X5R

805

402

C20AU

V_AUD_ANALOG

AUD_FILTER_33

BOM NO TE: CAD NOTE:

1

2

DEFAULT: ALC268/888 EMPTY PLACE NEAR PIN 34

C9AU

OPTION: STAC9271D STUFF

10UF
20%

CAD NOTE:

6.3V
EMPTY

PLACE CIRCUIT NEXT TO PIN 33

805

OUT

59

BOM NO TE:

DEFAULT:ALC268/888 EMPTY
OPTION:STAC9271D STUFF

AUD

BOM NO TE:

DEFAULT:ALC268/888 EMPTY
OPTION:STAC9271D STUFF

CAD NOTE:

C19AU

10UF

6.3V

20%
X5R

805

1

2

VREF SUPPLY

CAD NOTE:

PLACE NEAR PIN 27

1

.1UF

10%
10V

2

X5R
402

AUD_CODEC_VREF

OUT

59

AUD

60

66

59

OUT

PLACE NEAR PIN 13

3337

IN

PC BEEP

5960
66

596066

SPKR

IN

IN

V_AUD_ANALOG

V_AUD_ANALOG

402

R13AU

1

1

2

AUD

1

C15AU

1000PF
10%
50V

2

EMPTY
402

AUD

2

AUD_PC_BEEP_PN1

5%10K

R12AU

CH

1

100

5%
CH

2

402

2

MODULE REV DETAILS

MODULE NAME

BL AUDIO 0.06.00

R9AU

1

5.11K
1%

EMPTY

2

402

AUD_SENSE_B

C10AU

1000PF
10%
50V
EMPTY
402

R11AU

1

5.11K
1%

EMPTY

2

402

AUD_SENSE_A

C18AU

1

2

10%

.1UF

C8AU

.01UF
10%
25V
EMPTY
402

10V
X5R
402

2

1

AUDAUD

OUT

OUT

AUD_PC_BEEP

1

REV

59

59 62 64

62

OUT

10-12-06

63

59

DATE

D

C

B

AUD

A

SUPPLY DECOUPLING

8

7

BPAGE DRAWING

frostburg_fabc.sch_1.60

Sun Mar 18 18:44:18 2007

6

5

4 2

3

[PAGE_TITLE=AUDIO DECOUPLING & JACK SENSE]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

60

1

A

3.01

CR-61 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE61

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

BL AUDIO 0.06.00

1

REV

DATE

10-12-06

D

BOM NO TE:

OPTIONNAL: 5-STACK STUFF
DEFAULT: 3-STACK EMPTY

BOM NO TE:

DEFAULT: ALC268/888: 10 OHM
OPTIONAL:9271D: 33 OHM(A93549-005)

C

AUD_SPDIF_OUT

59

67

IN

B

CAD NOTE:

PLACE NEXT TO PIN 48

1

33

402

R108AU

2

1

10K

5%

EMPTY

402

R88AU

5%

EMPTY

2

1

2

C84AU
470PF
10%
50V
EMPTY
402

VCC

AUD_SPDIF_VIN

1

C76AU
470PF
10%
50V

2

X7R
402

JA5AU

DFP_AUD5STK

F3

VIN

F2

VCC

F1

GND

EMPTY

NC=40,41
GND=36,37,38,39,42,43

D

C

B

A

A

[PAGE_TITLE=AUDIO SPDIF]

BPAGE DRAWING

frostburg_fabc.sch_1.61

Sun Mar 18 18:44:19 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

61

1

3.01

CR-62 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE62

8

D

402

0

402

R31AU

1

0

R30AU

1

0

402

R92AU

1

0

402

R91AU

1

EMPTY

5%
CH

EMPTY

402

2

5%
CH

5%

R38AU

0

402

2

5%

AUD_PORT_C_L_PN1

2

AUD_PORT_C_R_PN1

2

1

2

5%
CH

R39AU

2

1

0

5%
CH

AUD_PORT_LINE_CPL_L_D

AUD_PORT_LINE_C PL_R_D

AUD_PORT_F_L

5962

63

BI

AUD_PORT_C_L

59

BI

AUD_PORT_C_R

59

BI

C

63

5962

59

59

BI

BI

BI

AUD_PORT_F_R

AUD_PORT_D_L

AUD_PORT_D_R

B

63
62
59

59

A

63
59
62

AUD_PORT_F_L

BI

AUD_PORT_E_L

BI

AUD_PORT_E_R

59

BI

AUD_PORT_F_R

BI

BOM NO TE:

DEFAULT: ALC268/888 STUFF R150AU, R151AU
OPTION:STAC9271D STUFF R34AU, R35AU

R150AU

0

402

5.10
402

5.10
402

402

1

R35AU

1

EMPTY

R34AU

1

EMPTY

R151AU

1

0

2

5%
CH

2

5%

5%

5%
CH

AUD_PORT_EB_L

2

2

AUD_PORT_EB_R

7

BOM NO TE:

ALC268:STUFF C113AU, C114AU
ALC888/9271D:STUFF C102AU, C103AU

CAD NOTE:

DUAL SITE C113AU WITH C102AU.
DUAL SITE C114AU AND C103AU

C113AU

1

2

20%

4.7UF

6.3V

EMPTY

805

AUD_PORT_LINE_L_C

C102AU

1

2

20.0%

4.7UF
16V

ALUM

TH

AUD_PORT_LINE_R_C

C103AU

1

2

20.0%

4.7UF
16V

ALUM

TH

C114AU

1

2

4.7UF

20%

6.3V

EMPTY

805

C37AU

2

1

25V

C36AU

25V

BOM NO TE:

ALC268/9271D:STUFF C115AU, C116AU
ALC888:STUFF C104AU, C105AU

CAD NOTE:

DUAL SITE C115AU WITH C104AU.
DUAL SITE C116AU AND C105AU

C115AU

1

4.7UF
EMPTY

C104AU

1

4.7UF
16V

ALUM

TH

C105AU

1

4.7UF
16V

ALUM

TH

100UF

20.0%

ELEC

RDL

100UF

2

1

20.0%

ELEC

RDL

2

20%

6.3V
805

2

AUD_PORT_LINE_L_MIC

20.0%

2

AUD_PORT_LINE_R_MIC

20.0%

C116AU

1

4.7UF

6.3V

EMPTY

805

20%

AUD_PORT_LINE_L_D

BOM NO TE:

NON DOLBY: STUFF A93544-018
DOLBY:STUFF A93540-076(470UF)

AUD_PORT_LINE_R_D

2

6

BOM NOTE:

FB OPTION: 0.2AMP (693286-014), 0603
RES OPTION: 0 OHM (108506-004), 0603

AUD_PORT_LINE_L_C

AUD

62

BI

AUD_PORT_LINE_R_C

62

BI

R43AU

1

2

5%

20K

EMPTY

402

R36AU

1

2

20K

5%

EMPTY

402

AUD_PORT_LINE_L_D

62

BI

AUD_PORT_LINE_R_D

62

BI

R42AU

1

2

5%

20K

CH

402

R48AU

1

2

5%

20K

CH

402

62

BI

62

BI

62

BI

62

BI

1

1

1

1

AUD

62

65

62 65

65

65

BI

BI

AUD_PORT_LINE_L_MIC

62

BI

AUD_PORT_LINE_R_MIC

62

BI

R44AU

1

2

20K

5%

EMPTY

402

R37AU

1

2

20K

5%

EMPTY

402

1

1

AUD

[PAGE_TITLE=AUDIO JACK (BLUE GREEEN PINK]

8

7

6

5

M7AU

MULTI

M4AU

MULTI

M6AU

MULTI

M3AU

MULTI

M8AU

MULTI

M5AU

MULTI

45

BOM NO TE:

DEFAULT: STUFF JA5AU WITH C94525-001 5-STACK
OPTIONAL: STUFF JA6AU WITH C73570-001 3-STACK

600

0.2A
BROAD

2

AUD_L_LINEOUT_C

600

0.2A
BROAD

FB

FB

2

AUD_R_LINEOUT_C

AUD

2

470PF

2

470PF

C41AU

C34AU

AUD

BOM NO TE:

DEFAULT: ALC888 STUFF 470PF

600

0.2A
BROAD

600

0.2A
BROAD

2

FB

2

FB

AUD_L_LINEOUT_D

AUD_R_LINEOUT_D

OPTIONAL: 9271D STUFF 0.01UF(A36096-045)

1

470PF

AUD

1

470PF

AUD

600

0.2A
BROAD

2

AUD_L_MIC

600

0.2A
BROAD

FB

2

AUD_R_MIC

FB

AUD

2

470PF

2

470PF

C43AU

C38AU

AUD

BOM NO TE:

DEFAULT: ALC268/888 STUFF A93548-181(20K 1%)
OPTION:STAC9271D STUFF A93548-124 (39.2K 1%)

Sun Mar 18 18:44:20 2007

4 2

3

R45AU

1

AUD

10K
402

1

10%
50V
X7R
402

1

10%
50V
X7R
402

62
59

OUT

60
64

C40AU

50V
X7R
402

C44AU

50V
X7R
402

50V
X7R
402

50V
X7R
402

BPAGE DRAWING

frostburg_fabc.sch_1.62

AUD

2

10%

2

10%

59606263

OUT

1

10%

1

10%

R47AU

1

AUD

20K
402

3

AUD

AUD

1%
CH

AUD_JACK_33

AUD_JACK_34

2

1%
CH

AUD_SENSE_A

R46AU

1

2

AUD_JACK_24

5.11K

1%
CH

402

AUD_SENSE_B

AUD_JACK_4

AUD

2

2

JA5AU

DFP_AUD5STK

32
33
34
35

1

R93AU

1

2

0

5%
CH

402

JA6AU

3 STACK AUDIOJACK_SW

32
35
33
34

1

JA5AU

DFP_AUD5STK

22
23
24
25

1

JA6AU

3 STACK AUDIOJACK_SW

22
25
23
24

1

2
3
4
5
1

3 STACK AUDIOJACK_SW

2
5
3
4
1

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

1

MODULE REV DETAILS

MODULE NAME

BL AUDIO 0.06.00

REV

C94525-001

TOP

PORT C

EMPTY

AUD_SENSE_A

R104AU

1

0

5%

EMPTY

402

2

OUT

AUD_SENSE_B

59 60 62

OUT

JACK

C94525-001

MIDDLE

PORT D

EMPTY

JACK

JA5AU

DFP_AUD5STK

C94525-001

BOTTOM

PORT F/E

EMPTY

JA6AU

JACK

DOCUMENT_NUMBER

xxxxxx

PAGE REV

1

10-12-06

64

59 60

62

DATE

D

62

63

C

B

A

3.01

CR-63 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE63

8

BOM NO TE:

STUFF THIS PAGE FOR 5-STACK

D

BI

BI

AUD_PORT_F_L

AUD_PORT_F_R

5962

C

7

BOM NO TE:

5STACK:STUFF C106AU,C107AU
3STACK:EMPTY ALL

R60AU

AUD_PORT_F_C_L

1

2

0

5%

EMPTY

402

R61AU

2

1

AUD_PORT_F_C_R

0

5%

EMPTY

402

4.7UF

C118AU

1

6.3V

EMPTY

805

4.7UF

20%

4.7UF

4.7UF

C107AU

1

16V

EMPTY

TH

2

C117AU

1

6.3V

EMPTY

805

C106AU

1

16V

EMPTY

TH

2

20.0%

20%

20.0%

6

2

2

AUD_PORT_REAR_L

AUD_PORT_REAR_R

R66AU

1

20K

EMPTY

402

R64AU

AUD

1

20K

EMPTY

402

AUD

45

BOM NOTE:

FB OPTION: 0.2AMP (693286-014), 0603
RES OPTION: 0 OHM (108506-004), 0603

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

0.06.00BL AUDIO

DATE

10-12-06

D

600

0.2A
BROAD

M12AU

AUD_PORT_REAR_L

63

BI

BI

AUD_PORT_REAR_R

635962

BI

BI

2

5%

2

5%

1

1

MULTI

600

0.2A
BROAD

M14AU

MULTI

2

AUD_PORT_REAR_L_JACK

EMPTY

2

AUD_PORT_REAR_R_JACK

EMPTY

470PF

AUD

470PF

C54AU

1

EMPTY

C51AU

1

EMPTY

62
59

OUT

60
63

AUD

2

10%

50V
402

2

10%

50V
402

AUD_SENSE_B

R62AU

AUD_JACK_D3

1

2

20K

1%

EMPTY

402

DFP_AUD5STK

D1
D2
D3
D4
G1

JA5AU

EMPTY

C94525-001

PORT F

TOP

C

AUD

B

BOM NO TE:

5STACK:STUFF C108AU,C109AU
3STACK:EMPTY ALL

R59AU

2

1

BI

AUD_PORT_G_L

59

A

BI

AUD_PORT_G_R

59

8

402

0

402

EMPTY

R58AU

1

0

5%

5%

EMPTY

2

7

AUD_PORT_FG_L

AUD_PORT_FG_R

4.7UF

4.7UF

C108AU

1

16V

EMPTY

TH

C109AU

1

16V

EMPTY

TH

4.7UF

20.0%

20.0%

4.7UF

C119AU

1

2

2

C120AU

1

6.3V

EMPTY

805

6.3V

EMPTY

805

20%

20%

2

600

0.2A
BROAD

M11AU

AUD_PORT_CNT_L

AUD_PORT_LFE_R

R114AU

2

1

20K

2

AUD

402

20K
402

EMPTY

R130AU

1

EMPTY

5%

2

5%

1

1

AUD

6

5

MULTI

600

0.2A
BROAD

M13AU

MULTI

2

AUD_PORT_CNT_L_JACK

EMPTY

2

EMPTY

1

470PF

AUD

AUD_PORT_LFE_R_JACK

1

470PF

AUD

4 2

OUT

C53AU

2

10%

50V

EMPTY

402

C56AU

2

10%

50V

EMPTY

402

BPAGE DRAWING

frostburg_fabc.sch_1.63

Sun Mar 18 18:44:21 2007

AUD

[PAGE_TITLE=AUDIO JACK (BLACK ORANGE]

3

10K
402

R67AU

1

EMPTY

AUD_SENSE_B

AUD_JACK_E3

2

1%

CUSTOM TEXT BPAGE

JA5AU

DFP_AUD5STK

E1
E2
E3
E4
G1

EMPTY

INTEL

CONFIDENTIAL

C94525-001

PORT G

BOTTOM

DOCUMENT_NUMBER

xxxxxx

PAGE REV

63

1

B

A

3.01

CR-64 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE64

8

AUD_LINK_BCLK_R

3337

D

IN

AUD_LINK_RST_R_N

3337

IN

AUD_LINK_SYNC_R

333637

IN

AUD_LINK_SDO_R

333637

IN

BOM NO TE:

DEFAULT: EMPTY FOR CLASSIC SKU
OPTION: STUFF FOR MEDIA SKU

C

BOM NO TE:

ALC26/888- 0OHM A93549-001
STAC9271D- 5.1OHM A93549-060

AUD_PORT_B_R

59

BI

B

R80AU

1

33

4025%EMPTY

R69AU

1

33

402

EMPTY

R81AU

1

33

5%

402

EMPTY

R72AU

1

33

5%

402

EMPTY

R89AU

1

0

402

7

EMI CAP

2

PLACE NEXT TO PIN 1

2

5%

2

2

AUD_PORT_B_R_C_HDR

2

5%
CH

CAD NOTE:

AUD_LINK_BCLK_HDR

AUD_LINK_RST_HDR

AUD_LINK_SYNC_HDR

AUD_LINK_SDO_HDR

C67AU

1

4.7UF

6.3V
X5R
805

2

AUD_PORT_B_R_HDR

20%

6

C100AU

2

10PF

50V

EMPTY

402

TP_AUD_RSVD3
TP_AUD_RSVD2

AUD_LINK_R

5%

1

R156AU

1

0

402

EMPTY

BI

2

5%

6465
6465
64

64

J7AU

2X8HDR12

1

3
5
7
9

11
13
15

A91836-016

AUD_LINK_SDI1

AUD_LINK_SDI0

BI
BI
BI

BI

64 65

V_3P3_STBY\G

IN

2
4
6
8

10
14

16

EMPTY

AUD_PORT_B_L_HDR
AUD_PORT_B_R_HDR
AUD_PORT_A_R_HDR

AUD_PORT_A_L_HDR

2

1

AUD

+12VVCC3

OUT

OUT

R146AU

20K
5%

CH
402

45

BOM NO TE:

ALC268/888- EMPTY
STAC9271D-STUFF

3

AUD_SENSE_A

2

2

1

AUD

C57AU

220PF
EMPTY

R144AU

20K
5%

EMPTY
402

10%

50V

1

402

AUD

2X5HDR_8

1
3

7
9

J6AU

AUD

2
4
65

10

AUD_FP_DETECT_HDR

HDR

2

R143AU

20K
5%

EMPTY
402

1

AUD

33

33

2

R145AU

20K
5%

CH
402

1

AUD

2

59 60 62

OUT

2

0

AUD_FP_SENSE_MIC
AUD_FP_SENSE_HP

4025%CH

MODULE REV DETAILS

MODULE NAME

R94AU

1

FP_AUD_DETECT

1

2

R95AU

39.2K
1%

CH
402

1

2

AUDAUD

R96AU

20K
1%

CH
402

1

REV

0.06.00BL AUDIO

DATE

10-12-06

D

33 36

OUT

C

B

2

C60AU

470PF

10%

50V

R85AU

AUD_PORT_B_L_C_HDR

2

AUD_PORT_B_L

59

BI

BI

AUD_PORT_A_R

59

A

BI

AUD_PORT_A_L

59

8

402

5.10
402

5.10
402

1

0

R90AU

1

R86AU

1

5%
CH

5%
CH

5%
CH

2

2

AUD_PORT_A_R_C_ HDR

AUD_PORT_A_L_C_HDR

7

1

4.7UF

C93AU

100UF

1

25V

ELEC

C94AU

100UF

1

25V

ELEC

C70AU

6.3V
X5R
805

20.0%

RDL

20.0%

RDL

2

AUD_PORT_B_L_HDR

20%

BOM NO TE:

NON DOLBY: STUFF A93544-018
DOLBY:STUFF A93540-076(470UF)

AUD_PORT_A_R_HDR

2

AUD_PORT_A_L_HDR

2

64 65

BI

64

BI

64

BI

6

5

1

X7R
402

AUD

BOM NO TE:

DEFAULT: ALC888 STUFF 470PF
OPTION: 9271D STUFF 0.01UF(A36096-045)

CAD NOTE:

PLACE 220PF CAPS CLOSE TO 2X5 AUDIO FRONT PANEL CONNECTOR

2

1

AUD AUD

4 2

C65AU

470PF

10%
50V
X7R
402

2

1

C58AU

220PF
10%
50V
X7R
402

2

1

AUD

C59AU

220PF
10%
50V
X7R
402

2

1

AUD

C66AU

220PF
10%
50V
X7R
402

2

1

AUD

C64AU

220PF

10%
50V
EMPTY
402

2

1

AUD

[PAGE_TITLE=AUDIO FP HEADERS & HDA HEADER]

BPAGE DRAWING

frostburg_fabc.sch_1.64

Sun Mar 18 18:44:23 2007

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

C61AU

220PF
10%
50V
EMPTY
402

DOCUMENT_NUMBER

xxxxxx

PAGE REV

64

1

A

3.01

CR-65 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE65

8

7

6

REAR MIC BIAS

45

3

2

MODULE REV DETAILS

MODULE NAME

BL AUDIO 0.06.00

1

REV

DATE

10-12-06

D

C

BOM NO TE:

ALC268/888: STUFF R152AU EMPTY R113AU
9271D: STUFF R113AU, EMPTY R152AU

AUD_VREF_30

59

IN

59

IN

AUD_VREF_31

AUD_VREF_31_R

C80AU

4.7UF
20%

6.3V
X5R
805

402

2

1

R152AU

1

1K

R113AU

1

1K

402

2

5%
CH

5%

EMPTY

2

R153AU

2

1

0

5%
CH

402

Q1AU

3

2

MMBT3906

1

EMPTY

AUD_VREF_31_R_BASE

2

5%

EMPTY

R141AU

33K

402

1

AUD

AUD_MIC2_DIODE

CR1AU

AUD_MIC1_DIODE_MIC_BIAS

BAW56S
SOT363

1

6

2

DIO

2.2K
402

AUD_MIC1_DIODE

R121AU

1

2

AUD_PORT_LINE_R_MIC

5%
CH

R117AU

AUD_PORT_LINE_L_MIC

2

1

5%

2.2K
CH

402

D

62

OUT

OUT

62

C

AUD

B

B

FRONT MIC BIAS

R154AU

2

IN

AUD_VREF_32

59

A

AUD_VREF_28

59

IN

8

1

1K

5%

EMPTY

402

R107AU

1K

402

AUD_VREF_FP_MIC

C83AU

4.7UF
20%

6.3V
X5R
805

7

2

C112AU

4.7UF
20%

6.3V

1

EMPTY

805

1

AUD

2

5%
CH

2

1

AUD

BAW56S
SOT363

3

DIO

R155AU

0

402

CR1AU

1

5%

EMPTY

R110AU

AUD_VREF_FP_MIC_R

4

5

AUD_VREF_FP_MIC_L

2.2KCH5%
402

1

R111AU

1

2.2KCH5%
402

AUD_PORT_B_R_HDR

2

AUD_PORT_B_L_HDR

2

OUT

OUT

64

64

A

2

[PAGE_TITLE=AUDIO MIC BIAS]

6

5

4 2

BPAGE DRAWING

frostburg_fabc.sch_1.65

Sun Mar 18 18:44:24 2007

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

65

1

3.01

CR-66 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE66

8

V_5P0_STBY\G

37

D

8088

5169707374

IN

89

909192

7

6

BOM NO TE:

ONLY STUFF CR2AU IF U2AU IS STUFF

CR2AU
1N4148

3

1

SOT23
EMPTY

45

3

2

MODULE REV DETAILS

MODULE NAME

BL AUDIO 0.06.00

1

REV

DATE

10-12-06

D

BOM NO TE:

OPTION FOR FERRITE BEAD (693286-014, 0603)

M15AU

MULTI

603

3

2

AUD

U2AU

C83150-001

LD1117DT

OUT

GND

1

AUD_VREG_OPT_GND

1

C74AU

0.1UF
20%

16V

2

EMPTY
402

AUD

2

1

U3AU

2N3904
EMPTY

EMPTY

CAD NOTE:

USE LARGE S HAPE UNDER VREG FOR THERMALS
ADD VIAS FOR THERMAL RELIEF TO OTHER LAYERS

3

R136AU

1

150
1%

2

EMPTY
402

R137AU

1

453

1%

2

EMPTY
402

V_AUD_FILTERED

1

2

AUD

C71AU

0.1UF
20%
16V
Y5V
402

1

2

AUD

C72AU
1UF
20%

6.3V
X5R
603

AUD

1

2

C75AU

100UF

20.0%
25V
ELEC
RDL

1

CH

CR4AU

1N4148

1

3

SOT23
EMPTY

BOM NO TE:

CR3AU- C79228-001

1

EMPTY

CR3AU
MBRA130

EMPTY

M18AU

MULTI

1SM2

V_AUD_12V

2

603

C

+12V

BOM NO TE:

DEFAULT: STUFF 0 OHM (A93552-004, 0603)
OPTIONAL: FERRITE BEAD (693286-014, 0603)

B

CAD NOTE:

PLACE GROUND::12V DECOUPLING SITE AS
CLOSE AS POSSIBLE TO AUDI O VREG

A

1

2

CAD NOTE:

PLACE GROUND::AUD-GROUND DECOUPLING SITE AS
CLOSE AS POSSIBLE TO AUDIO TRIPLE-STACK CONNECTOR

AUD

C77AU

470PF
10%
50V
X7R
402

1

C111AU

470PF
10%
50V

2

X7R
402

1

2

C73AU

4.7UF
20%

16V

EMPTY

1206

BOM NO TE:

CHANGE THIS TO 78L05
IF NEED TO STUFF

2

IN

CAD NOTE:

PLACE ETCH RESISTORS UNDER CODEC

R140AU

2

1

0OHM

SM

R138AU

1

0OHM

R134AU

SM

1

0OHM

2

SM

2

V_AUD_ANALOG

CAD NOTE:

ADD SEVERAL VIAS AFTER ETCH RESISTOR
TO V_AUD_ANALOG

C85AU

2

1

10%

.01UF

25V
X7R
402

C88AU

2

1

10%

.01UF

25V
X7R
402

CAD NOTE:

DISTRIBUTE THREE NEAR THE REAR AUDIO JACK.
ONE NEAR THE FRONT PANEL AUDIO CONNECTOR.
REMAINING ALONG ANTI-ETCH BETWEEN ANALOG / DIGITAL GROUND

AUD

AUD

.01UF

.01UF

C86AU

1

C90AU

1

OUT

2

10%
25V
X7R
402

2

10%
25V
X7R
402

59
60

C87AU

2

1

10%

.01UF

25V
X7R

.01UF

C91AU

1

402

2

10%
25V
X7R
402

AUDAUD

AUD AUD

C

B

AUD

A

BPAGE DRAWING

frostburg_fabc.sch_1.66

Sun Mar 18 18:44:25 2007

8

7

6

5

4 2

3

[PAGE_TITLE=AUDIO VREG]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

66

1

3.01

CR-67 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE67

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

0.06.00BL AUDIO

DATE

10-12-06

D

D

ATX CUSTOM SPDIF HEADER

R150BU

2

AUD_SPDIF_OUT

59

61

IN

C

B

1

0

4025%EMPTY

AUD_SPDIF_OUT_C

1

C96BU
470PF
10%
50V

2

EMPTY
402

J1BU
1X3HDR

EMPTY

SPDIF OUT

VCC

1
2
3

1

C97BU

0.1UF

CAD NOTE:

20%
16V

2

PLACE CLOSE TO HDR

Y5V
402

C

B

A

BPAGE DRAWING

frostburg_fabc.sch_1.67

Sun Mar 18 18:44:27 2007

8

7

6

5

4 2

3

[PAGE_TITLE=SPDIF HEADER]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

67

1

A

3.01

CR-68 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE68

8

TPM 1.2

D

C

B

A

VCC3

1

1

C8TM

C7TM

.1UF

.1UF

20%

20%

25V

25V

2

2

EMPTY

EMPTY
603

603

CAD NOTE:

TPM VCC3 DECOUPLING: 0.1UF CAPS.
PLACE ONE PER TPM POWER PIN (10,19,24,5)

VCC3

R14TM

1

10K 5%
402

R12TM

LPCPD_N

33

IN

69

DESIGN NOTE:

TPM FEATURE: DEFAULT STUFF R12TM, EMPTY R14TM
STUFFING OPTION TO ISOLATE LPCPD* FROM ICH

1

0

402

28

EMPTY

EMPTY

45

R10TM

1

2

0

5%

EMPTY

402

1

R6TM
0
5%

EMPTY

2

402

V3P0_BAT_TPM

U1TM

12

WPCT200

VBAT

GPIO0/XOR_OUT

GPIO1

NC
NC

GPIO2/GPX

TEST

GPIO3/BADD

PP

NC

1OF1

NC

VSS

VSS

11

18

25

EMPTY

TPM_NC_25_R

BOM NO TE:

TPM FEATURE:
ST-MICRO: R2TM EMPTY
ATMEL AND SINOSUN: R2TM 0 OHM

R2TM

1

0

EMPTY

402

2

5%

13
14

1

2

6

8
9

7

3

XTALIN_TPM

TP_TPM_PIN_14

TP_TPM_PIN_1
TP_TPM_PIN_2

TP_TPM_PIN_6

TPM_TESTIO
BADDR

TPM_PRESENCE

TP_TPM_PIN_3

BOM NO TE:

TPM FEATURE:
ST-MICRO: C6TM EMPTY
ATMEL & SINOSUN: C6TM .1UF

2

1

C4TM

.1UF
20%
25V

1

2

EMPTY
603

C6TM

.1UF
20%
25V
EMPTY
603

7

6

BOM NO TE:

TPM FEATURE:
ST-MICRO: R7TM, R6TM, R10TM EMPTY
ATMEL & SINOSUN: R7TM, R6TM, R10TM 0 OHM

VCC3

VCC3

R7TM

2

1

TPM_NC_R_10

0

5%

EMPTY

402

NC

VCC3

192410

VDD

VDD

TPM_NC_R_5

5

VSB

VSS

4

CAD NOTE:

CK_P_33M_TPM

IN

13

33

6998

IN

33

69

BI

33

69

IN

32

69

BI

2

2

5%

OVERLAP THE PIN 1 PAD

402

0

402

PLTRST_N
L_AD<3..0>

L_FRAME_N
SER_IRQ

LPCPD_PN1_N

R15TM

1

0

R16TM

1

EMPTY

5%

EMPTY

2

5%

2

CK_P_33M_PATA2

CK_P_33M_TPM_R

TPEV_TPM_CLKRUN_N

1

R11TM

4.7K
5%

EMPTY
402

2

OUT

0

1

2

3

106

21

16

26
23
20

17

22
27

28

15

VCC3

LCLK
LRESET*

LAD0
LAD1
LAD2
LAD3

LFRAME*
SERIRQ

LPCPD*

CLKRUN*/GPIO4

REV=1

3

C9TM

.1UF
10%
16V
EMPTY
402

BOM NO TE:

STUFF FOR
WINBOND ONLY

R13TM

1

2

5%

0

EMPTY

402

BOM NO TE:

TPM FEATURE:
ST-MICRO AND SINOSUN: R13TM EMPTY
ATMEL: R13TM 0 OHM

R3TM

1

2

4.7K

5%

EMPTY

402

BOM NO TE:

TPM FEATURE:
ST-MICRO: R3TM EMPTY
ATMEL AND SINOSUN: R3TM 4.7K

DESIGN NOTE:

TPM FEATURE: DEFAULT EMPTY.
STRAPS FOR PHYSICAL PRESENCE.

R8TM

2

5%

1K

EMPTY

402

2

MODULE REV DETAILS

MODULE NAME

TPM1.2

VCC3

DESIGN NOTE:

TPM FEATURE:

1

PULL-UP STRAPPING FOR
ENABLING TEST-MODE ON SINOSUN

R5TM

4.7K
5%

EMPTY
402

2

1

BOM NO TE:

R4TM

TPM FEATURE:

4.7K

ST-MICRO AND SINOSUN: EMPTY

5%

ATMEL: STUFF 4.7K

EMPTY
402

2

VCC3

1X3HDR

1
2

VCC3

R9TM

1

2

1

5%

0

EMPTY

402

3

EMPTY

BOM NO TE:

TPM FEATURE: DEFAULT EMPTY
CUSTOMER OPTION FOR PHYSICAL
PRESENCE HEADER.

J2TM

1.2.0

A91829-001

1

REV

DATE

41.4.06

D

C

B

A

[PAGE_TITLE=TPM 1.2]

BPAGE DRAWING

frostburg_fabc.sch_1.68

Sun Mar 18 18:44:28 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

68

1

3.01

CR-69 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE69

8

7

6

45

3

SIO TRIPLE SITE (SMSC LPC47M182, WINBOND PC8347L, WINBOND WPCD376I)

123
60
49
31
6

107
93
76

102
103

111
112
104
105

106
108
109

4
3
2
1
7
5

48
47

44
43
42
41
40
39
38
37

33
34
35
36
45
50
51

128
127

VCC3

TP_SIO_PIN_104

TP_PA_SIR_RX

V_3P3_STBY\G

TP_SIO_PIN_102
SIO_GPIO0_103

TP_SIO_PIN_111
TP_SIO_PIN_112

TP_SIO_PIN_105

SIO_PIN_106
SIO_PIN_108

SIO_GPIO5_109

PA_KBDATA
PA_KBCLOCK
PA_MSDATA
PA_MSCLOCK
KBRST_N
A20GATE

PA_LPT_SLCTIN_N

TP_PA_LPT_PD0
TP_PA_LPT_PD1
TP_PA_LPT_PD2
TP_PA_LPT_PD3
TP_PA_LPT_PD4
TP_PA_LPT_PD5
TP_PA_LPT_PD6
TP_PA_LPT_PD7

PA_LPT_SLCT
PA_LPT_PE
PA_LPT_BUSY
PA_LPT_ACK_N
PA_LPT_ERR_N
PA_LPT_ALF_N
PA_LPT_STROBE_N

CIR_BLTX1_TIP

BOM NO TE:

U1LH STUFFING GUIDE

103 105

87

88

85 86
69
49 53

38 39
33 34

92122

IN

28

36 37
47
59 64
82 84

101

OUT
OUT

BI
BI
BI

BI
OUT
OUT

BI
OUT

IN
IN
IN
IN

IN
OUT
OUT

OUT

MFGR

70

SMSC

92

32

90

WINBOND

48

WINBOND

102

80

OUT

10K 5%

402

9
9

32
32

73

73
73
73
73
73
73
73

73

80

OUT

72
72
72
72

R86LH

1

2

CH

LPC47M182

R87LH

1

10K 5%
402

U1LH

D

PA_FDD_DRVDEN0

71

OUT

PA_FDD_DRVDEN1

71

OUT

PA_FDD_MTR0_N

71

OUT

PA_FDD_DS0_N

71

OUT

PA_FDD_DIR_N

71

OUT

PA_FDD_STEP_N

71

OUT

PA_FDD_WDATA_N

71

OUT

PA_FDD_WGATE_N

71

OUT

PA_FDD_HDSEL_N

71

OUT

PA_FDD_INDEX_N

71

IN

PA_FDD_TRK0_N

71

IN

PA_FDD_WRTPRT_N

71

IN

PA_FDD_RDATA_N

71

IN

PA_FDD_DSKCHG_N

71

IN

IO_PME_N

33

105

92101

90
84

85

86

64

69

59

39

47

48

C

333436

V_3P3_STBY\G

92122

IN

28

32

37

38

49

53

70

82

87

88

33

OUT

13

33

68

IN

98

33

68

102103

IN

32

68

BI

L_DRQ_N
PLTRST_N
LPCPD_N

SER_IRQ

R11LH

2

1

10K

5%
402

CH

R8LH

1

0

5%
402

CH

C7LH

.1UF
20%
25V
EMPTY

603

"Y5V"

B

OUT

L_AD<3..0>

33

68

BI

L_FRAME_N

33

68

IN

2

1

2

73
73
73

73

73

73

PA_PLTRST_N

CK_P_33M_PA

28

IN

PA_COM_RXD1

74

IN

PA_COM_TXD1 PA_LPT_INIT_N

74 73

OUT

PA_COM_DSR1_N

74

IN

PA_COM_RTS1_N

74

OUT

PA_COM_CTS1_N

74

IN

PA_COM_DTR1_N

74

OUT

PA_COM_RI1_N

74

IN

PA_COM_DCD1_N

74

IN

CK_14M_PA

28

IN

SUSCLK

33

IN

CIR_RX

IN

CIR_BLTX2_SENSE

IN

CIR_BLTX1_SENSE

IN
OUT
OUT

IN

TP_PA_COM_RTS2_N

CIR_FP_LED

TP_PA_COM_DTR2_N

CIR_BLTX2_TIP
CIR_LEARN_IN

0
1
2
3

110

119
120
121
122
124
125
118
126

22
21
19
18
17
16
15
14
10
20
13
12
11

99
62

61
59
57

56
54
63
52
55
53

25
27
24
26
28

30
32

23

65
91

96
78
58
46
29

9

8

PORT ANGELES 3.0

DRVDEN0
DRVDEN1
MTR0*
DS0*
DIR*
STEP*
WDATA*
WGATE*

HDSEL*

INDEX*
TRK0*
WRTPRT*
RDATA*
DSKCHG*

IO_PME*

LAD<0>

LAD<1>

LAD<2>

LAD<3>

LFRAME*

LDRQ*
PCI_RESET*

LPCPD*
PCI_CLK
SER_IRQ

RXD1
TXD1
DSR1*
RTS1*
CTS1*
DTR1*
RI1*
DCD1*

CLOCKI14
CLOCKI32/GPIO16

VSS<7>
VSS<6>
VSS<5>
VSS<4>
VSS<3>
VSS<2>
VSS<1>

RXD2
TXD2
DSR2*
RTS2*
CTS2*
DTR2*
RI2*
DCD2*

NC=129

V_3P3_STBY<3>
V_3P3_STBY<2>
V_3P3_STBY<1>

FLOPPY

SER_CLK/GPIO17
SER_DATA/GPIO0

FANTACH1/GPIO6
FANTACH2/GPIO7
FANTACH3/GPIO1
FANTACH4/GPIO2

FAN/GPIO

FANPWM1/GPIO3
FANPWM2/GPIO4
FANPWM3/GPIO5

LPC

SERIAL 1

SERIAL 2

1OF2

PS/2

PARALLEL

CLOCK

VCC3<5>
VCC3<4>
VCC3<3>
VCC3<2>
VCC3<1>

KBDRST*

INITP*

SLCTIN*

ERROR*

STROBE*

GA20M

PD<0>
PD<1>
PD<2>
PD<3>
PD<4>
PD<5>
PD<6>
PD<7>

IRTX2
IRRX2

KDAT
KCLK
MDAT
MCLK

SLCT

PE
BUSY
ACK*

ALF*

IC

PART #

PC8374L

WPCD376I

2

CH

INTEL IPN

C81714-001
C76238-001
D76793-001

V_3P3_STBY\G

2

MODULE REV DETAILS

MODULE NAME

SIO_CIR_ICH9

DESCRIPTION

PORT ANGELES 1.6
PORT ANGELES 3.0

PORT ANGELES 3.0 + CIR

92

101

102 103 105

921222832 33 34 36 37 38 39

IN

49 53 59 64 697082 84 85

1.01.00

1

REV

DATE

01.22.07

D

47 48

86 87

88 90

C

B

DECOUPLING

A

1

1

C8LH
.1UF
20%
25V

2

2

Y5V
603

CAD NOTE:

PLACE 0.1UF CAPS
NEAR DEVICE PINS - 6,31,49,60,76,93,107

C1LH
.1UF
20%
25V
Y5V
603

V_3P3_STBY\G

1

C9LH
.1UF
20%
25V

2

Y5V
603

8

53

59

64 697082 84

92122 28

IN

37

38 394748 49

36
85

86 87

1

1

C10LH

C6LH

.1UF

.1UF

20%

20%

25V

25V

2

2

Y5V

Y5V

603

603

7

32 33 34

88 90 92

1

2

C12LH
.1UF
20%
25V
Y5V
603

VCC3

101

102 103 105

1

C11LH
.1UF
20%
25V

2

Y5V
603

89 90

V_5P0_STBY\G

1

C13LH

1

470UF

C17LH

20%

.1UF

10V

20%

ALUM

2

25V

RDL

2

Y5V
603

CAD NOTE:

PLACE NEAR PIN 71

6

73 74
37 51

IN

66

70
80 88
91

92

BPAGE DRAWING

frostburg_fabc.sch_1.69

Sun Mar 18 18:44:29 2007

5

4 2

3

[PAGE_TITLE=PORT ANGELES 1 OF 2]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

69

1

A

3.01

CR-70 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE70

8

7

6

45

3

D

VCC3

8586

87

8890

92101

102103

84

C

4849

4849

32333436373839

47

484953

59

64697082

283347

102103105

283347

102103105

97

105

272897

BI

212227

BI

101

272897

BI

212227

BI

101

20

BI

20

BI

20

BI

20

BI

51

OUT

51

OUT

51

OUT

99107

IN

3236

IN

70

IN

7

333651

IN

33

IN

33

IN

B

V_3P3_STBY\G

9212228

IN

SMB_CLK_MAIN

SMB_CLK_RESUME

SMB_DATA_MAIN
SMB_DATA_RESUME
VGA_SIO_DDCSDA_5V

VGA_SIO_DDCSCL_5V
VGA_MCHSIO_DDCSDA
VGA_MCHSIO_DDCSCL

GPIO_GRN_BLNK_HDR
GPIO_YLW_BLNK_HDR
HD_LED_N
IDE_PRI_ACT_N
ICH_SATA_LED_N

SCSI_ACT_N

FP_RST_N
SLP_S3_N

S4_STATE_N

47

4849

8788

87
88
89
90

94
95
66
67
68
69
75

85
86

98

97

PORT ANGELES 3.0

SMB_CLK_MAIN
SMB_CLK_RESUME
SMB_DAT_MAIN
SMB_DAT_RESUME

5V_DDCSDA/GPIO8
5V_DDCSCL/GPIO9
3V_DDCSDA/GPIO10
3V_DDCSCL/GPIO11

GRN_LED
YLW_LED
HD_LED*
HDD_ACT_1*
HDD_ACT_2*
HDD_ACT_3*
FPRST*/GPIO14

SLP_S3*
SLP_S4*/S5*

VBAT

F_CAP/GPIO15

NC=129

90

U1LH

REF_5V_STBY

POWER

PCIRST_OUT*

PCIRST_OUT2*

VGA DDC VT

IDE_RSTDRV*

BACKFEED_CUT*

LATCHED_BF_CUT

LED

SCK_BJT_GATE

CPU_PRESENT*

PWR SEQ

2OF2

V_5P0_STBY

1

2

R22LH

2.7K
5%

CH
402

1

R23LH

2.7K
5%

CH
402

2

TP_PA_TESTEN_1

R13LH

1

1

R21LH

8.2K

8.2K
5%

5%

CH

CH

402

402

2

2

116
114
115
113

PA_F_CAP

848586

REF_5V

PWRGD_3V
PWRGD_PS

RSMRST*

PS_ON*

GPIO12
GPIO13

GPO11

32333436373839

7082

71
72
70

84
82

73
74
64
92

77
79
80
81
83

100
101
117

IC

92

101

102103105

9212228

IN

53596469

V_5P0_STBY\G
V_REF5V_SUS_SIO
V_REF5V_SIO

PWRGD_3V
PWRGD_PS

PLTRST_PCIE_SLOTS_R_N
TP_PCIRST_OUT2_R_N

TP_IDE_RST_N
ICH_RSMRST_N

BACKFEED_CUT
LATCHED_BACKFEED_CU T
TP_SCK_BJT_GATE
PS_ON_SIO_N
H_SKTOCC_R_N

TP_SIO_PIN_100
TP_SIO_PIN_101
TP_SIO_PIN_117

V_3P3_STBY\G

1

2

R72LH

8.2K
5%

CH
402

R20LH
1K

5%
CH

402

OUT
OUT

OUT

OUT
OUT

OUT
OUT

IN

IN

37 51
91

92

37

133353

90

R19LH

1

0

4025%CH

33 39

75

80 82
85 89 90

89

90

2

66 69

37

1

2

R65LH

10K

5%
EMPTY

402

73 74 80

1

2

1

0

402

C16LH

5%
50V
COG
402

R64LH

2

88 89 90

PLTRST_PCIE_SLOTS_N

100PF

2

H_SKTOCC_N

5%
CH

1

MODULE REV DETAILS

MODULE NAME

SIO_CIR_ICH9

NOTE: DEFAULT TYPE IS LISTED FIRST

SEE PORT AN GELES SPEC P. 16 FOR TYPE DESCR IPTION

PIN

1
2

3
70
71
72
75
80
81
83
84
87
88
89
90

124
125
126
127

OUT

6

IN

REV

1.01.00

FUNCTION
TEST_EN
AUD_LINK_RST*
CDC_DWN_ENAB/GPIO12*
PRIMARY_HD*
SECONDARY_HD*
SCSI*
FPRST*
PWRGD_PS
CPU_PRESENT*
SLP_S3*
SLP_S5*
SMB_CLK_M
SMB_CLK_R
SMB_DAT_M
SMB_DAT_R
5V_DDCSDA/GPIO8
5V_DDCSCL/GPIO9
3V_DDCSDA/GPIO10

212247 101

33

01.22.07

TYPE
3IPD
5I
5I/O12
3ISPU_400
3ISPU_400
3ISPU_400
3ISPU_400
3ISPU_400
3ISPU_400
3IS_400
3IS_400
3IOD6
3IOD6
3IOD6
3IOD6
5IOD6/3IO8
5IOD6/3IO8
3IOD6/3IO8
3IOD6/3IO83V_DDCSCL/GPIO11

102

DATE

D

C

B

A

SCSI ACTIVITY HEADER

SCSI_ACT_N TP_SCSI_ACT_PIN2

70

OUT

8

J2LH

1X2HDR

1

EMPTY

1

C14LH

4.7UF
20%
16V

2

Y5V
1206

1

C15LH

CAD NOTE:

.1UF

10%
16V

PLACE AS CLOSE TO

2

X7R
603

PIN AS POSSIBLE

A

2

BPAGE DRAWING

frostburg_fabc.sch_1.70

Sun Mar 18 18:44:31 2007

7

6

5

4 2

3

[PAGE_TITLE=PORT ANGELES 2 OF 2]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

70

1

3.01

CR-71 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE71

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

SIO_CIR_ICH9

1.01.00

1

REV

DATE

01.22.07

D

CAD NOTE:

PLACE NEAR FDD CONN

C

B

69

IN

69

IN

69

OUT

69

IN

69

IN

69

IN

69

IN

69

IN

69

IN

69

OUT

69

OUT

69

OUT

69

IN

69

OUT

PA_FDD_DRVDEN0

PA_FDD_DRVDEN1
PA_FDD_INDEX_N
PA_FDD_MTR0_N

PA_FDD_DS0_N

PA_FDD_DIR_N
PA_FDD_STEP_N
PA_FDD_WDATA_N
PA_FDD_WGATE_N
PA_FDD_TRK0_N
PA_FDD_WRTPRT_N
PA_FDD_RDATA_N
PA_FDD_HDSEL_N
PA_FDD_DSKCHG_N

VCC

1

2

R24LH

1K

5%
CH

402

1

2

R25LH

1K

5%

CH
402

2

1

R26LH
1K
5%

CH
402

1

2

R27LH

1K

5%
CH

402

1

2

R28LH
1K
5%

CH
402

TP_301S

TP_302S

TP_303S

2X17HDR_3_5

1

2
4
6

7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29

30
31
32
33
34

KEY
KEY

P1
P2

P4
P6

P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34

D

J4LH

C

B

HDR

A

A

[PAGE_TITLE=FDD CONN]

BPAGE DRAWING

frostburg_fabc.sch_1.71

Sun Mar 18 18:44:32 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

71

1

3.01

CR-72 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE72

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

SIO_CIR_ICH9

1.01.00

1

REV

DATE

01.22.07

D

91

69

69

C

69

69

B

VREG_PS2

IN

PA_KBDATA

BI

PA_KBCLOCK

BI

PA_MSDATA

BI

PA_MSCLOCK

BI

DESIGN NOTE:

STUFF CAPS IF SEEING

NOISE PROBLEMS ON PS2

1

C55LH

470PF

10%
50V
X7R
402

2

1

C53LH

470PF
10%
50V
X7R
402

2

1

C52LH

470PF
10%
50V
X7R
402

2

1

C54LH

470PF
10%
50V
X7R
402

2

PLACE NEAR
PS/2 CONN

CAD NOTE:

1

R30LH

2.2K
5%

CH
402

2

64

3

1

52

CRP1LH

TVS6_2V

6.2V
EMPTY

1

2

R32LH

2.2K
5%

CH
402

1

2

R36LH

2.2K
5%

CH
402

1

2

R29LH

2.2K
5%

CH
402

R33LH

2

1

0

402

R31LH

1

0

402

R34LH

1

0

402

R35LH

1

0

402

CAD NOTE:

PLACE AS CLOSE TO PS/2
CONNECTOR AS POSSIBLE

SIO_KBDATA_FB

5%
CH

2

SIO_KBCLOCK_FB

5%
CH

2

SIO_MSDATA_FB

5%
CH

2

SIO_MSCLOCK_FB

5%
CH

1

C20LH

470PF
10%
50V

2

X7R
402

1

2

C21LH

470PF
10%
50V
X7R
402

1

2

1

2

C23LH

470PF

10%
50V
X7R
402

C19LH

1UF

20%

6.3V

X5R

603

1

2

C18LH

470PF

10%
50V
X7R
402

1

2

C22LH

470PF
10%
50V
X7R
402

TP_401S

TP_402S

TP_403S

TP_404S

A92011-001
PS2 STACK

1
2
3
4
5
6

7
8

9
10
11
12

P1
P2
P3
P4
P5
P6

P7
P8
P9
P10
P11
P12

J9LH

P13
P14
P15
P16
P17

CONN

KEYBOARD

13
14
15
16
17

MOUSE

D

C

B

A

BPAGE DRAWING

frostburg_fabc.sch_1.72

Sun Mar 18 18:44:34 2007

8

7

6

5

4 2

3

[PAGE_TITLE=PS/2 CONNECTOR]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

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PAGE REV

72

1

A

3.01

CR-73 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE73

LPT PULLUPS

D

69

69

69

C

B

69

69
69
69
69
69

8

PA_LPT_STROBE_N

IN

PA_LPT_ALF_N

IN

PA_LPT_INIT_N

IN

PA_LPT_SLCTIN_N

IN

PA_LPT_ACK_N

OUT

PA_LPT_BUSY

OUT

PA_LPT_PE

OUT

PA_LPT_SLCT

OUT

PA_LPT_ERR_N

OUT

VCC

2

1

7

R52LH

10K

5%
CH

402

VCC

2

1

2

1

R37LH

2.7K
5%

CH
402

R51LH

10K

5%
CH

402

2

1

2

1

R48LH

2.7K
5%

CH
402

R50LH

10K
5%

CH
402

2

1

2

1

6

R43LH

2.7K
5%

CH
402

R39LH

10K

5%
CH

402

2

2

1

1

R40LH

2.7K
5%

CH
402

R47LH

10K

5%
CH

402

45

BOM NO TE:

STUFF FOR CONSUMER IR SUPPORT
STUFF ONLY WITH WINBOND -376I DEVICE

FRONT PANEL RECEIVERS

VCC

J10LH

2X4HDR_7

1

808889

V_5P0_STBY\G

3751

66

IN

7074

69

91

92

90

3
5

EMPTY

2
4
6
8

CIR_FP_LED_R

R85LH

1

0

402

IPN: A91836-074

BACK PANEL BLASTERS

VCC3

R66LH

2

1

EMPTY

603

R67LH

1

10K 5%

EMPTY

603

CIR_BLTX1_SENSE

5%10K

2

CIR_BLTX2_SENSE

OUT

OUT

73

69

73

69

OUT OUT

73

69

73

VCC3

R97LH

1

1K

5%

EMPTY

2

SIO_CIR

402

R96LH

2

CIR_BLTX1_TIP

69

IN

1

CIR_BLTX1_TIP_BASE

5%

1K

EMPTY

402

3

CIR_FP_LED

2

5%

EMPTY

CIR_RX

CIR_BLTX1_TIP_DRIVE

CIR_BLTX1_SENSE

VCC

R88LH

1

324
1%

2

EMPTY
603

3

Q1LH

1

MMBT3904
EMPTY

2

1

2

IN

IN

R89LH

324

1%
EMPTY

603

69

69

J11LH

2X3HDR_4

1

3

5

R90LH

1

324
1%

2

EMPTY
603

CIR_BLTX1_TIP_DRIVE

2

MODULE REV DETAILS

MODULE NAME

SIO_CIR_ICH9

VCC3

R98LH

2

1

5%

22K

EMPTY

402

CIR_LEARN_IN

2

CIR_BLTX2_TIP_DRIVE

CIR_BLTX2_SENSE

6

EMPTY

BOM NO TE:

MOD R88LH, R89LH, R90LH,
TO A93551-036 (300 OHM,1/10W,5%)

OUT

OUT

1

1.01.00

REV

DATE

01.22.07

D

69

73

69

73

OUTOUT

73

C

B

VCC

BOM NO TE:

MOD R93LH, R94LH, R95LH,

VCC3

R92LH

1

1K

5%
EMPTY

2

SIO_CIR

A

CIR_BLTX2_TIP

69

IN

8

7

6

5

402

R91LH

2

1

CIR_BLTX2_TIP_BASE

5%

1K

EMPTY

402

Sun Mar 18 18:44:35 2007

4 2

R93LH

1

324
1%

2

EMPTY
603

3

Q2LH

1

MMBT3904
EMPTY

2

BPAGE DRAWING

frostburg_fabc.sch_1.73

3

1

2

R94LH

324

1%
EMPTY

603

1

2

TO A93551-036 (300 OHM,1/10W,5%)

R95LH

324
1%

EMPTY
603

CIR_BLTX2_TIP_DRIVE

[PAGE_TITLE=LPT SIGNALS]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

73

OUT

DOCUMENT_NUMBER

xxxxxx

PAGE REV

73

1

A

3.01

CR-74 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE74

8

D

91

92

90
74

8088

66

7073

89

C

3751

IN

69

69

OUT

69

OUT

69

OUT

69

OUT

69

OUT

69

IN

69

IN

69

IN

V_5P0_STBY\G
PA_COM_DCD1_N

PA_COM_DSR1_N
PA_COM_RXD1
PA_COM_CTS1_N
PA_COM_RI1_N
PA_COM_RTS1_N
PA_COM_TXD1
PA_COM_DTR1_N

+12V

7

BOM NO TE:

DO NOT USE NATIONAL OR
GOLDSTAR PARTS OF THIS BASE PN

U2LH

GD75232S

20

VCC

19

RY1

18

RY2

17

RY3

14

RY4

12

RY5

16

DA1

15

DA2

13

DA3 DY3

1

NOTE DIRECTION

2

RA1

3

RA2

4

RA3

7

RA4

9

RA5

5

DY1

6

DY2

8
10

VDD-VDD+

11

GND

IC

+12V

92

V_5P0_STBY\G

3751

6669

7073

-12V

91

IN

74

80888990

-12V

6

C41LH
470PF
10%
50V
X7R
402

1

C42LH
470PF

10%

50V

2

2

X7R
402

C43LH
470PF
10%
50V
X7R
402

1

2

CAD NOTE:

C46LH
470PF
10%
50V
X7R
402

1

2

1

2

1

PLACE NEAR CONNECTOR

C48LH
470PF
10%
50V
X7R
402

45

C44LH
470PF
10%
50V
X7R
402

1

C45LH
470PF
10%
50V

2

X7R
402

1

2

3

1

C47LH
470PF

10%

50V

2

X7R
402

DESIGN NOTE:

TAIWANESE TYPE HEADER

2

MODULE REV DETAILS

MODULE NAME

SIO_CIR_ICH9

SERIAL PORT A

SIO_COM_DCD1_232
SIO_COM_RXD1_232_N
SIO_COM_TXD1_232_N
SIO_COM_DTR1_232

SIO_COM_DSR1_232
SIO_COM_RTS1_232
SIO_COM_CTS1_232
SIO_COM_RI1_232

REV

1.01.00

J7LH

SERIAL PORT

2X5HDR_10

1

P1

2

P2

3

P3

4

P4

5

P5

6

P6

7

P7

8

P8

9

P9
KEY

HDR

1

DATE

01.22.07

D

C

1

C50LH

.1UF
20%
25V

2

Y5V
603

202341-017

CAD NOTE:

PLACE DECOUPLING NEAR IC PINS
1, 10, AND 20 RESPECTIVELY

1

C51LH

.1UF
20%
25V

2

Y5V
603

202341-017

B

A

8

7

1

2

6

C49LH
.1UF
20%
25V
Y5V
603

202341-017

B

A

BPAGE DRAWING

frostburg_fabc.sch_1.74

Sun Mar 18 18:44:36 2007

5

4 2

3

[PAGE_TITLE=SERIAL PORT A]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

74

1

3.01

CR-75 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE75

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1.08.01

1

REV

DATE

2.10.06SUPER_IO

D

C

D

C

PASSIVE BLEED CIRCUIT

VCC

1

RP1LH

RP1LH

22

22

5%

5%

.5W

.5W

EMPTY

EMPTY

SM

SM

8

B

BACKFEED_CUT

70

8082

IN

85

8990

2

RP1LH

22
5%

.5W

EMPTY

SM

7

PASSIVE_BLEED_PATH

3

1

2

Q3LH
EMPTY

3

RP1LH

EMPTY

6

4

22
5%

.5W

SM

5

B

A

A

[PAGE_TITLE=STUDIES PURPOSE]

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3.01

CR-76 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE76

8

SST SENSORS

D

C

B

A

105

BI

6

6

105

BI

H_TEMP_SRC_DP_HEC

H_TEMP_SRC_DP

BI

H_TEMP_RET_DN

BI

H_TEMP_RET_DN_HEC

7

6

DESIGN NOTE:

CPU/CPU VREG TEMP SENSOR.

45

3

2

MODULE REV DETAILS

MODULE NAME

SST 1.3.0

1

REV

DATE

41.3.06

VCC3

D

C

B

A

402

402

R52TH

1

0

R53TH

1

0

5%

EMPTY

5%

EMPTY

C5TH

1

2

25V

20% .1UF

CAD NOTE:

PLACE CAP NEAR
SST SENSOR PINS.

NW_ZONE_TDP
NW_ZONE_TDM

1

C13TH

100.0PF

3

Q10TH

1

MMBT3904
EMPTY

2

5%
50V

2

EMPTY
603

2

CAD NOTE:

R50TH

1

0

402

R51TH

1

0

402

2

PLACE CAP NEAR
SST SENSOR PINS.

2

5%
CH

2

5%
CH

PLACE TRANSISTOR SOUTH OF ICH
AND WEST OF MCH.

1

2

CAD NOTE:

C1TH

100.0PF
5%
50V
COG
603

H_TEMP_SRC_DP_R
H_TEMP_RET_DN_R

+12V

EMPTY

603

U2TH

ADT7484

1

VCC

2

GND

3
4

CAD NOTE:

PLACE TEMP ONLY SST
SENSOR NEAR CPU VREG.

VCC3

ADD0

D+

RSVD

D-

REV=1

DESIGN NOTE:

VOLTAGE/SYSTEM AMBIENT/MEM TEMP SENSOR.

C6TH

2

1

25V

.1UF20%

Y5V

603

U3TH

ADT7485

REV=1

1

VCC

2

GND

3

DP

4

DM

5

12V

1OF1

CAD NOTE:

PLACE TEMP/VOLTAGE COMBO
SST SENSOR NEAR DIMMS.

SST

ADD

EMPTY

8

6
5

SST

ADD
2P5V
VCCP

5V

IC

SST_CTL

SST_ADD0

7

TP_SST_PIN6

SST_ADD1

10
9
8

V_1P25_CORE
7
6

6

9495
96105

SST_ADD

VCC

IN

BI

SST_CTL

VCCP

32

76

BI

13 14 161718

IN

38

VCC3

R7TH

1

1K
5%

2

EMPTY
402

R8TH

2

1K

EMPTY

402

VCC3

R9TH

1

1K
5%

EMPTY

2

402

R10TH

2

1K

EMPTY

402

32

76

82 83 86 98 105

1

5%

1

5%

VCC3

R11TH

1

1K

5%

2

EMPTY
402

21 34

R12TH

2

1K

5%
EMPTY

1

402

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[PAGE_TITLE=SST SENSOR]

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PAGE REV

76

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3.01

CR-77 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE77

8

FAN CONFIGURATION

D

BOM NO TE:

EMPTY FOR 3-PIN FAN
STUFF FOR 4-PIN FAN
IF PWM BUFFER IS NOT

5.25V TOLERANT

402

CPU_FAN_CTRL

32

105

IN

C

32

105

IN

FNT_REAR_FAN_CTRL_HEC

B

BOM NO TE:

STUFF R42TH FOR
INDEPENDANT CTRL

A

104 105

REAR_FAN_CTRL_HEC

IN

IN

FNT_REAR_FAN_CTRL

105

R308BU

IN

402

VCC3

8

R306BU

1

0

EMPTY

402

REAR_FAN_CTRL

R307BU

1

0

402

2

1

5%

0

EMPTY

R42TH

2.2K
5%

EMPTY
402

BOM NO TE:

DEFENSIVE DESIGN
OPTION FOR 4PIN
FAN CIRCUIT.

2

5%

BOM NO TE:

STUFF R40TH, EMPTY R41TH FOR SHARED CTRL
STUFF R41TH, EMPTY R40TH FOR INDE PENDANT CTRL

R41TH

2

1

5%

0

EMPTY

402

2

5%
CH

R40TH

0CH5%

402

1

2

FNT_REAR_FAN_CTRL_HEC_R

R38TH

1

1K
5%

2

EMPTY
402

7

VCC3

R37TH

1

2.2K
5%

CH

2

402

CPU_FAN_CTRL_GATE

R36TH

CPU_FAN_CTRL_EMIT

5%

0

CH

1

C14TH

47PF
5%
50V
EMPTY

2

402

FNT_REAR_FAN_CTRL_R

R32TH

1K
5%

EMPTY
402

FNT_REAR_FAN_CTRL_BASE_1

BOM NO TE:

EMPTY FOR 3-PIN FAN
STUFF FOR 4-PIN FAN

FNT_REAR_FAN_CTRL_BASE_2

Q6TH

MBT3904DUAL

Q7TH

MBT3904DUAL

7

3

Q9TH

1

MMBT3904
XSTR

2

R34TH

1

0

EMPTY

402

BOM NO TE:

EMPTY FOR 3-PIN FAN
EMPTY FOR 4-PIN FAN
IF PWM BUFFER IS NOT

5.25V TOLERANT

VCC3

R33TH

1

2.2K
5%

EMPTY

2

402

3

5

4

VCC3

R39TH

1

2.2K
5%

2

EMPTY
402

3

5

4

6

2

5%

VCC3

FNT_REAR_FAN_CTRL_INV

6

2

EMPTY

1

FNT_REAR_FAN_CTRL_B_COL_2

6

2

EMPTY

1

6

VCC3

1

R17TH

2.2K
5%

EMPTY
402

2

1

5% 220

EMPTY

CPU_FAN_CTRL_OUT

R24TH

2.2K
5%

CH
402

BOM NO TE:

STUFF FOR 3-PIN FAN
EMPTY FOR 4-PIN FAN

C80741-001

2

R16TH

CPU_FAN_DRIVER_GATE

402

R31TH

1

2

5%

0

402

CH

R43TH

0

5%
CH

402

5

CPU_FAN_DRIVER

1

R14TH
0
1A

CH
805

3

Q2TH
EMPTY

1

2

R20TH

1

5%
CH

2

BOM NO TE:

STUFF FOR 4-PIN FAN
EMPTY FOR 3-PIN FAN

REAR_FAN_PWM_R

2

0

402

C80741-001

FRONT_REAR_FAN_CTRL_REAR

BOM NO TE:

EMPTY FOR 4-PIN FAN
STUFF FOR 3-PIN

R27TH

2

1

FRONT_FAN_PWM_R

0

5%
CH

402

C80741-001

FRONT_REAR_FAN_CTRL_FRONT

45

3

CAD NOTE:

CPU FAN:
BTX/ATX: PLACE BELOW/RIGHT OF CPU SOCKET

+12V

1

C7TH
.1UF
20%
25V

2

EMPTY
603

J3TH

1X4HDR

1
2
3

4

HDR

CPU_TACH_OUT

+12V

1

2

R18TH

3.3K

5%
CH

402

1

15K 5%
402

R13TH

CPU_FAN_TACH_R

2

1

CH

R15TH

6.2K
5%

CH
402

2

CAD NOTE:

FRONT/REAR CHASSIS FAN:

BTX: PLACE ABOVE/RIGHT OF CPU SOCKET

ATX: PLACE NEAR BACKPANEL

+12V

+12V

J4TH

1

1X4HDR

C9TH

.1UF
20%
25V
Y5V
603

+12V

C12TH

.1UF
20%
25V
EMPTY
603

1
2
3

4

HDR

J5TH

1X4HDR

1
2
3
4

HDR

REAR_TACH_OUT

FRONT_TACH_OUT

2

+12V

1

2

R23TH
5%

CH
402

R26TH

5%
CH

402

3.3K

1

R19TH

15K 5%
402

3.3K

R25TH

1

402

CH

5%15K
CH

REAR_FAN_TACH_DRIVER

3

Q3TH

FET

1

2

FRONT_FAN_TACH_DRIVER

3

Q4TH

FET

1

2

1

1

R21TH

0
1A

EMPTY

2

805

2

BOM NO TE:

STUFF FOR 4-PIN FAN
EMPTY FOR 3-PIN FAN

1

R29TH

1

0
1A

EMPTY

2

805

2

CAD NOTE:

REAR/FRONT CHASSIS FAN:
BTX/ATX: PLACE BELOW/LEFT OF DIMMS

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2

MODULE REV DETAILS

MODULE NAME

SST 1.3.0

R309BU

1

0

REAR_FAN_ TACH_R

R22TH

6.2K
5%

CH
402

FRONT_FAN_TACH_R

R28TH

6.2K
5%

CH
402

402

R310BU

0

402

1

C8TH

.01UF
20%
50V

2

X7R
603

1

C11TH

.01UF
20%
50V

2

X7R
603

1

C10TH

.01UF
20%
50V

2

EMPTY
603

2

1

2

2

1

2

[PAGE_TITLE=FAN CONFIGURATI ON]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

2

5%
CH

2

1

5%

EMPTY

R311BU

0

402

R312BU

402

R313BU

1

0

402

R314BU

402

CPU_FAN_TACH

CPU_FAN_TACH_HEC

REAR_FAN_TACH

1

2

5%
CH

REAR_FAN_TACH_HEC

2

1

5%

0

EMPTY

FRONT_FAN_TACH

2

5%
CH

FRONT_FAN_TACH_HEC

1

2

0

5%

EMPTY

DOCUMENT_NUMBER

xxxxxx

1

REV

1

41.3.06

OUT

OUT

PAGE

77

OUT

DATE

32

105

OUT

OUT

OUT

3.01

REV

D

C

B

32

105

32

A

105

CR-78 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE78

8

DESIGN NOTE:

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

PB MOUNTING HOLE

J1PB

MTG_HOLE

D

NC9

9

EMPTY

J2PB

MTG_HOLE

9

NC9

EMPTY

J8PB

MTG_HOLE

NC9

J7PB

MTG_HOLE

NC9

9

EMPTY

9

EMPTY

J9PB

MTG_HOLE

NC9

J10PB

MTG_HOLE

NC9

EMPTY

EMPTY

D

C

B

LABELS

A

1375X250_TARGET

EMPTY

J4PB

MTG_HOLE

NC9

J3PB

MTG_HOLE

NC9

DESIGN NOTE:

1500X150_TARGET

LB6PB

LABEL

A30094-001

1

DESIGN NOTE:
DESIGN NOTE:
DESIGN NOTE:
DESIGN NOTE:

LB5PB

LABEL

A19177-001

LB20PB

LABEL

1000X187

8

J6PB

MTG_HOLE

9

EMPTY

9

EMPTY

DESIGN NOTE:

200956-001 (NO CONCEPT MODEL): CE MARK SHOULD BE COVERED WITH BLANK WHITE LABEL UNTIL CERTIFIED (MAY NOT BE ON RVP DESIGNS)
628492-001: FCC MARK SHOULD BE COVERED WITH BLANK WHITE LABEL UNTIL CERTIFIED (MAY NOT BE ON RVP DESIGNS)
622954-001: C-TICK MARK SHOULD BE COVERED WITH BLANK WHITE LABEL UNTIL CERTIFIED (MAY NOT BE ON RVP DESIGNS)
KOREAN CERT (NO IPN, NO CONCEPT MODEL) SHOULD BE COVERED WITH BLANK WHITE LABEL UNTIL CERTIFIED (NOT ON RVP DESIGNS)

DESIGN NOTE:

1

1

LB5PB: ISN BLANK LABEL AND KOZ

DESIGN NOTE:

SILK TARGET FOR PRODUCT CODE LABEL

9

NC9

EMPTY

J5PB

MTG_HOLE

9

NC9

EMPTY

CAD NOTE:

LB6PB: PLACE KOZ TARGET NEAR CPU AND DIMMS FOR BUILD/WOC NOTES

7

J11PB

MTG_HOLE

NC9

EMPTY

6

CHINA_ROHS

LB25PB

LABEL

1

EMPTY

VCCI_SILK

LB17PB

LABEL

1

E210882_LB

LB16PB

LABEL

1

UL_LABEL

LB15PB

LABEL

1

MIC_CPU

LB13PB

LABEL

1

FCCSILK

LB12PB

LABEL

1

CE_LABEL

LB11PB

LABEL

1

EMPTY

LB7PB

LABEL

INTEL_LOGO

1

EMPTY

EMPTY

EMPTY

EMPTY

EMPTY

EMPTY

B2_SILK

LB19PB

LABEL

1

EMPTY

SILK

LB9PB

1

C-TICK

EMPTY

BSMI_SILK

LB10PB

LABEL

1

E2_SILK

LB18PB

LABEL

1

EMPTY

E1_SILK

LB2PB

LABEL

1

PB_FREE_2LI

LB3PB

LABEL

1

EMPTY

CANADA

LB21PB

LABEL

1

EMPTY

C

EMPTY

B

EMPTY

A

[PAGE_TITLE=MTG HOLES/LABELS]

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CR-79 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE79

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7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

BL_B_ATX

1

REV

DATE

2/8/0706.12.2

D

CORE VR MODULE

D

V_SM POWERED BY 5VDUAL
V_SM_VTT POWERED BY V_SM
V_1P5_ICH POWERED BY V_SM OR VCC3
V_1P25_CORE POWERED BY V_1P5_ICH
V_1P05_ICH_CORE POWERED BY VCC3
V_FSB_VTT POWERED BY VCC3

C

V_1P25_CL_MCH POWERED BY V_SM

C

5VDUAL_USB POWERED BY V_5P0_STBY\G AND VCC
5VDUAL POWERED BY V_5P0_STBY\G AND VCC

V_3P3_STBY\G POWERED BY V_5P0_STBY\G
V_3P3_EPW POWER ED BY V_3P3_STBY\G

B

VCC

5VDUAL_USB

V_5P0_STBY\G

5VDUAL

V_SM

V_3P3_STBY\G

V_3P3_EPW

VCC3

V_1P05_ICH_CORE

V_FSB_VTT

B

A

V_1P25_CL_MCH

V_SM_VTT

V_1P5_ICH

A

V_1P25_CORE

BPAGE DRAWING

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CR-80 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE80

8

V_SM

1418

IN

24

19
25
80
8286

92
8889
7073

3751

IN

6669
74
90

8990
7075

IN

8285

3336

IN

909192
37516669

IN

7374

+12V

1

BAT54C
SOT23_C
DIO

BV_DRV_VCC

1

2

PLACE NEAR
CONTROLLER VCC

PLACE NEAR
CONTROLLER

R158BV

EMPTY

V_5P0_STBY\G

BACKFEED_CUT

GPIO_VSM_AMT_LED

V_5P0_STBY\G

R255BV

1

0
5%

2

EMPTY
402

BV_DRV_5V DUAL

2

3

R27BV

0
5%

CH
402

CAD NOTE:

CAD NOTE:

2

EMPTY

75
5%

402

R254BV

0

402

M239BV

MULTI

27
81

D

80
91

70

808889

C

CR3BV

B

A

BOM NO TE:

R500BV -A93548-267, 6.49K(P SKU ONLY)

GPIO0 GPIO5

1
0

SIO_GPIO5_109

69

IN

V_SM

1.85V

0

1.9V

1

R502BV

1.0K
402

8

BOM NO TE:

1

STUFF LED CIRCUIT FOR AMT
EMPTY FOR NON AMT

2

BV_SM_PWR_L ED_XSTR_SOURCE

R176BV

10K15%

EMPTY

402

R196BV

1

2.2K

5%

EMPTY

402

2

2

CR7BV

2

MBT3904DUAL

BV_SM_PWR_LED_B1

R147BV

2

1

1K

5%

EMPTY

402

+12V

R183BV

1

0

M245BV

MULTI

1

2

1

2

603

1

2

5%
EMPTY

402

1

R204BV

47.5K
1%

CH
402

R500BV

EMPTY

402

0

5%

2

2

1

5%
CH

2

EMPTY

C9BV

1.0UF
10%
16V

X5R
805

603

MBT3904DUAL

2

1

SIO_GPIO5_109_R

0.1%

EMPTY

7

7

CAD NOTE:

PLACE NEXT
TO DIMMS

1

BV_SM_PWR_LED_XSTR_END

RED
EMPTY

BV_SM_PWR_LED_B2

6

3

5

1

4

R258BV

1

2

BV_DRV_12V_OPTION

CR2BV

1A

0

CH

603

BAT54C
SOT23_C

DIO

.1UF

SC2608A

1

BST

2

DH

3

GND

45

DL

BV_DRV_LDRV_VSM

BV_DRV_VCC_VSM

R501BV

1

20K

1%
EMPTY
402

BV_V_SM_DRV_FB_R1

3

6

4

1

1

C21BV

1

10%

16V
X7R
603

U1BV

COMP/SS

BV_V_SM_DRV_COMP_R

BV_V_SM_DRV_C2R

SIO_GPIO0_103_R

25

Q10BV
EMPTY

2

3

2

PHASE
SENSE

VCC

SEPARATE DIODE PACKS USED
TO MINIMIZE VOLTAGE DROP
IN S3 FROM 5VDUAL

1

1.0K

6

IN

2

Q42BV
EMPTY

DESIGN NOTE:

BV_DRV_BOOT_VSM

R13BV

1

0
1A

2

CH
603

BV_DRV_PH_VSM

8
7
6

IC

BV_OPS_VSM

R25BV

1

1

.068UF

10%
16V
X7R
603

0.1%

EMPTY

C19BV

100.0PF
50V

COG

2

603

1

0

402

R212BV

1

0
5%

2

CH
402

SIO_GPIO0_103

2

2

2

402

1

1K
5%

CH
603

C17BV

R503BV

5VDUAL

1

2

5%

R211BV

R14BV

20K

1%

EMPTY
402

5%

EMPTY

L1BV

1UH

1

IND

BV_DRV_HDRV_VSM

2

IN

2

OUT

BV_V_5P0_STBY_B1

MBT3904DUAL

1

R21BV

649
1%

CH
402

2

69

86

6

BV_5V_DUAL_FILTERED

CAD NOTE:

PLACE CLOSE
TO FET

C14BV

R213BV

1

4.7
805

R26BV

1

4.7
805

1

2.2
603

2.2
6031CH

3

5

4

BV_V_SM_DRV_FB

5

1

1UF
10%
25V

2

X5R
603

2

BV_UGATE2_R

5%
CH

2

BV_UGATE_R

5%
CH

R18BV

2

BV_LGATE_R

5%

R16BV

CH

5%

D37424-001

2

BV_LGATE2_R

V_5P0_STBY\G

R173BV

1

5.6K
5%

EMPTY

2

402

6

2

BV_SLP_S4_B1

Q5BV

1

EMPTY

1

2

1

R22BV

1A

0

603

EMPTY

DESIGN NOTE:

USE FOR ADDITIONAL COMPENSATION

45

1

C8BV

1

C281BV

3300UF

10UF

20%

10%

6.3V

10V

ALUM

2

1

C242BV

1.0UF

20%

10V
EMPTY
603

1

825

402

2

G

1

G

IN

R23BV

BV_V_SM_RC_FB

3

D

S

2

375166 69
909192

1

10K
402

2

1%
CH

2

DESIGN NOTE:

DUAL SITE THE MLCC'S WITH
THE BULK CAPACITOR

Q3BV

FET

D37424-001

3

Q4BV

D

S

2

FET

R19BV

EMPTY

RDL

805

3

Q47BV

D

1

S

G

D37424-001

2

BV_PHASE_NODE_VSM

3

D

1

S

G

2

D37424-001

70 73 74

BOM NO TE:

STUFF FOR AMT
EMPTY FOR NON AMT

2

SLP_S4_N

5%

EMPTY

BV_V_SM_RC

C16BV

1

2

10%

.1UF

16V

EMPTY

603

Sun Mar 18 18:44:45 2007

4 2

3

1

C282BV

10UF
10%
10V

2

EMPTY
805

DESIGN NOTE:

DUAL SITE THE MLCC'S WITH
THE BULK CAPACITOR

DESIGN NOTE:

DUAL SITE WITH L2BV

FET

V_SM ROD INDUCTOR:
C56005-002

Q2BV

FET

80 88 89

IN

BPAGE DRAWING

frostburg_fabc.sch_1.80

1

2

1

2

CAD NOTE:

PLACE NEAR DRAIN AND
SOURCE OF LS FET

33

DESIGN NOTE:

OVERLAPPING PADS

R172BV

1

0OHM

SM

CAD NOTE:

SENSE ON DIMM PIN 51 OR
AS FAR NORTH OF DIMM
FIELD AS POSSIBLE

3

1

C26BV

3300UF

20%

6.3V
ALUM

2

RDL

L3BV

1

DESIGN NOTE:

L2BV

1UH

1

IND

R17BV

2.2
5%

CH
805

BV_PHASE_NODE_S_RC

C10BV

4700PF
20%
50V
X7R
603

2

1

2

1.25UH

EMPTY

2

C283BV

EMPTY
805

2

10UF
10%
10V

2

MODULE REV DETAILS

MODULE NAME

1

C284BV

10UF
10%
10V

2

EMPTY
805

BL_B_ATX

CAD NOTE:

ONE NEAR OUTPUT
ONE NORTH OF DIMMS
DUAL SITE ONE NORTH
OF DIMMS WITH C198BV

2

CAD NOTE:

DUAL FOOTPRINT

1

C292BV

C11BV

10.0UF

10UF

20%

20%

6.3V

6.3V

2

X5R

EMPTY

805

1206

CAD NOTE:

PLACE NEAR OUTPUT INDUCTOR

1

C197BV

470UF

1

20%
10V
ALUM

2

2

RDL

2

CAD NOTE:

PLACE V_SM DECOUPLING NEAR DIMMS

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

1

C12BV

3300UF
20%

6.3V
ALUM
RDL

C198BV

470UF
20%
10V
EMPTY
RDL

1

C201BV

470UF
20%
10V
EMPTY
RDL

1

2

xxxxxx

V_SM

1

2

C24BV

4.7UF
20%
10V
EMPTY
805

1

C199BV

470UF
20%

10V

EMPTY

2

RDL

1

2

REV

C5BV

3300UF
20%

6.3V
ALUM
RDL

C202BV

470UF
20%
10V
EMPTY
RDL

1

OUT

1

C23BV

.1UF
20%
25V

2

EMPTY
603

1

C200BV

470UF
20%

ALUM

2

RDL

PAGE REV

80

1

DATE

2/8/0706.12.2

D

82

86
25 27
14

18
19

24
80

81

C

B

10V

A

3.01

CR-81 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE81

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

BL_B_ATX

1

REV

06.12.2 2/8/07

DATE

D

IN

BV_V_VCNTL_N

2

1A

EMPTY

2

1A

CH

V_SM

1

2

C135BV

10UF

20%

6.3V
EMPTY
805

1

2

C140BV

.1UF
10%

10V
X5R
402

3

5
6
7
8

1

C141BV

.1UF
10%
10V

2

X5R
402

RT9199

REFEN

NC
VCNTL
NC
NC

1

C134BV

470UF
20%

ALUM

2

RDL

EU6BV

1

10V

1

2

VIN

VOUT

GND

C136BV

.1UF
10%
10V
EMPTY
402

1

1

C144BV

2

1000UF
20%

6.3V
EMPTY
TH

V_SM_VTT

1

C229BV

4.7UF
10%
10V

2

X5R
1206

1

2

1

2

CAD NOTE:

PLACE 4.7UF CAPS FOR CH B
AT LEFT AND RIGHT ENDS

C230BV

OF VTT ISLANDS

4.7UF
20%
10V

BOM NO TE:

EMPTY
805

CHANGE THE C228BV TO 644066-033

C227BV

4.7UF
10%
10V
EMPTY
1206

1

2

C228BV

4.7UF
20%
10V
Y5V
805

OUT

4

1

2

R136BV

IC

1K
1%

EMPTY
603

2

1

C137BV

.1UF
10%
10V

2

X5R
402

CAD NOTE:

KEEP CLOSE TO OUTPUT

1

C143BV

470UF
20%
10V
ALUM

2

RDL

1

C142BV

2

470UF
20%
10V
ALUM
RDL

1

C133BV

470UF
20%

10V

EMPTY

2

RDL

CAD NOTE:

DUAL SITE
PUT NEAR OUTPUT
OF REGULATOR

CAD NOTE:

PLACE 4.7UF CAPS FOR CH A
AT LEFT AND RIGHT ENDS
OF VTT ISLANDS

8286

82

86

25

27
18

81

V_SM

14

IN

1924
80

1

2

R135BV

1K
1%

CH
402

14

18

19

2425

2780

81

BV_V_MEM_VTT_REF_PIN3

C

1

R134BV

1K
1%

CH
402

2

B

CAD NOTE:

MAXIMIZE GROUND SHAPE
AND VIAS
FOR THERMAL RELIEF

2

C139BV

.1UF
10%
10V

1

X5R
402

88
80

IN

86

R162BV

1

5VDUAL

0

603

VCC

R163BV

1

0

603

BOM NO TE:

FOR AMT: STUFF R162BV, EMPTY R163BV
FOR NON AMT: STUFF R163BV, EMPTY R162BV

D

26

C

27

B

A

A

[PAGE_TITLE=VREG_SM_VTT]

BPAGE DRAWING

frostburg_fabc.sch_1.81

Sun Mar 18 18:44:45 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

81

1

3.01

CR-82 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE82

8

D

14

18

19

2425

2780

86

32333436
47

4849

53

101

102

81

86

103105
59

64

69708485
28

373839

9092

8788

92122

IN

IN

V_SM

V_3P3_STBY\G

C

7

R214BV

28.7K

R215BV

24.3K

1

1%
CH

402

2

1

1%
CH

402

2

6

BV_V_1P5_ICH_OPAMP_PLUS

1

C252BV
1UF
20%

6.3V

2

X5R
603

CAD NOTE:

PLACE DECOUPLING CAP
AS CLOSE AS POSSIBLE
TO PIN 12

CAD NOTE:

AT LEAST 300 MDLS OF
V_SM ETCH TO FET Q48BV

+12V

CAD NOTE:

PLACE CLOSE
TO PIN 4

1

C256BV

1.0UF
10%
16V

2

X5R
805

U9BV

4

12

+

14

V+
V-

11

LM324D

IC

BV_V_1P5_ICH_OPAMP_OUT

-12V

CAD NOTE:

PLACE CLOSE
TO PIN 11

1

C262BV

1.0UF
10%
16V

2

EMPTY
805

13

D71406-001

R216BV

2

1K

402

1

G

1

5%
CH

45

4

Q48BV

D

FDB8878

S

EMPTY

3

1

C286BV

1000UF
20%

6.3V
EMPTY

2

TH

CAD NOTE:

PLACE CLOSE TO
Q53BV

D37424-001

1

G

1

C265BV

20%

6.3V
ALUM

2

TH

1000UF

3

D

S

2

CAD NOTE:

DUAL SITE

2

Q52BV

FET

1

3

C266BV

10UF

20%

6.3V
X5R
805

1

2

1

C267BV

.1UF
10%
16V

2

X7R
603

CAD NOTE:

PLACE CLOSE TO
FET

C263BV

.1UF
10%
16V
X7R
603

1

2

B

1

C264BV

2

CAD NOTE:

PLACE CLOSE TO

1P5_ICH FET

C268BV

.1UF
10%
16V
X7R
603

2

470UF
20%
10V
EMPTY
RDL

V_1P5_ICH

1

MODULE REV DETAILS

MODULE NAME

BL_B_ATX

OUT

06.12.2 2/8/07

9

34 38

92 98

REV

DATE

D

C

B

1

R217BV

22.1K
1%

CH

402

2

BACKFEED_CUT

7075

8085

IN

8990

A

BV_V_1P25_CORE_DIS_B1

R226BV

1

10K 5%
402

3

2

Q51BV

1

MMBT3904

CH

XSTR

2

R205BV

13.7K
1%

CH

402

BV_V_1P25_CORE_OPAMP_PLUS

1

2

1

C251BV
1UF
20%

6.3V

2

X5R
603

CAD NOTE:

PLACE DECOUPLING CAP
AS CLOSE AS POSSIBLE
TO PIN 10

CAD NOTE:

DECOUPLING CAP IS
SHARED ON V_1P5_ICH

+12V

U9BV

4

10

+

8

V+

9

V-

11

LM324D

IC

BV_V_1P25_CORE_OPAMP_OUT

-12V

D71406-001

R206BV

2

1K

402

D37424-001

4

Q49BV

D

1

FDB8878

S

G

EMPTY

3

1

5%
CH

3

Q53BV

D

1

S

G

FET

2

CAD NOTE:

DUAL SITE

A

17

1

2

C253BV

1000UF

20%

6.3V
ALUM
TH

1

2

C254BV

1000UF

20%

10V
ALUM
TH

V_1P25_CORE

OUT

76

83 86 98
13 14 16
18

21 34 38
105

[PAGE_TITLE=VREG_1P25_CORE MCH]

BPAGE DRAWING

frostburg_fabc.sch_1.82

Sun Mar 18 18:44:47 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

82

1

3.01

CR-83 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE83

8

98
83
76

34
18
16
13

D

14
17
21

38
82
86
105

IN

V_1P25_CORE

1

C210BV

10UF
20%

6.3V

2

X5R
805

1

2

C211BV

10UF
20%

6.3V
X5R
805

7

CAD NOTE:

CORE EDGE CAP DECOUPLING
PLACE IN PCIE BREAKOUT

1

2

C212BV

10UF
20%

6.3V
X5R
805

1

2

C213BV

10UF
20%

6.3V
X5R
805

1

2

C214BV

1UF

20%

6.3V
X5R
603

6

1

2

C215BV

1UF

20%

6.3V
X5R
603

1

2

C216BV

1UF

20%

6.3V
X5R
603

1

2

C217BV

1UF
20%

6.3V
X5R
603

1

2

C218BV

.1UF
10%

16V
X7R
603

45

3

2

MODULE REV DETAILS

MODULE NAME

BL_B_ATX

1

REV

06.12.2 2/8/07

DATE

D

C

V_1P25_CORE

IN

1

C219BV

10UF
20%

6.3V

2

X5R
805

CAD NOTE: CAD NOTE:

CORE DECOUPLING CAPS FOR MCH
PLACE NEXT TO PWR CORRIDOR

1

2

C220BV

10UF
20%

6.3V
X5R
805

1

2

C221BV

22.000UF
20%

6.3V
EMPTY
805

1

2

C222BV

22.000UF
20%

6.3V
EMPTY
805

1

2

C224BV

22.000UF
20%

6.3V
EMPTY
805

98
83

DECOUPLING CAPS AT OUTPUT OF REGULATOR

76

34
18
16
13

IN

14
17
21

38
82
86
105

V_1P25_CORE

1

C97BV

10.0UF
20%

6.3V

2

EMPTY
805

1

2

C103BV

4.7UF
20%
10V
EMPTY
805

1

C96BV

.1UF
20%
25V

2

EMPTY
603

B

DESIGN NOTE:

18

76

82

IN

213438
105

1

C255BV

10UF

20%

6.3V

2

EMPTY
805

838698

V_1P25_CORE

131416

17

BACKSIDE CAPS FOR SPECIFIC CORE MCH

1

2

C257BV

10UF

20%

6.3V
EMPTY
805

1

2

C258BV

10UF

20%

6.3V
EMPTY
805

1

2

C259BV

10UF
20%

6.3V
EMPTY
805

1

2

C260BV

10UF

20%

6.3V
EMPTY
805

1

2

C261BV

10UF
20%

6.3V
EMPTY
805

A

C

B

A

[PAGE_TITLE=MCH DCPL]

BPAGE DRAWING

frostburg_fabc.sch_1.83

Sun Mar 18 18:44:48 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

83

1

3.01

CR-84 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE84

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

BL_B_ATX

1

REV

06.12.2 2/8/07

DATE

D

BV_SC_INPUT_OPAMP5

C

B

105
102
92
86

87

69

70

49

53

3839
3334

V_3P3_STBY\G

92122

IN

28

32
37

36
4748
59

64

82

85

88

90

101
103

R65BV

1

1%CH29.4K

402

A

BV_V_1P05_ICH_OPAMP5_PLUS

2

1

R66BV

14K
1%

CH
402

2

1

C83BV

1UF
20%

6.3V

2

X5R
603

CAD NOTE:

PLACE DECOUPLING CAP
AS CLOSE AS POSSIBLE TO
PIN 3

+12V

CAD NOTE:

+12V DECOUPLING CAP IS
SHARED ON V_1P5_ICH

U9BV

4

5

+

7

V+

6

V-

11

LM324D

IC

+12V

CAD NOTE:

+12V DECOUPLING CAP IS
SHARED ON V_1P5_ICH

U9BV

4

3

+

1

V+

2

V-

11

LM324D

IC

-12V

CAD NOTE:

-12V DECOUPLING CAP IS
SHARED ON V_1P5_ICH

BV_1P05_ICH_GATE_DRIVE

-12V

CAD NOTE:

-12V DECOUPLING CAP IS
SHARED ON V_1P5_ICH

D

C

VCC3

1

3

D-PAK

R67BV

2

1K

5%

402

CH

Q14BV

D

S

2

C83236-001

FET

1

G

1

2

C85BV

.1UF
20%
25V
Y5V
603

1

C67BV

1000UF

20%

6.3V
ALUM

2

TH

1

C72BV

470UF
20%

10V

ALUM

2

RDL

CAD NOTE:

PLACE CLOSE 1P05_ICH_CORE FET

C68BV

4.7UF
20%

6.3V
X5R
805

1

C74BV

.047UF
10%
16V

2

EMPTY
603

1

2

1

C75BV

.022UF
10%
50V

2

X7R
603

V_1P05_ICH_CORE

OUT

B

34

A

BPAGE DRAWING

frostburg_fabc.sch_1.84

Sun Mar 18 18:44:50 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

84

1

3.01

CR-85 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE85

8

7

6

45

3

VCC3

2

MODULE REV DETAILS

MODULE NAME

BL_B_ATX

1

REV

06.12.2 2/8/07

DATE

D

105
102
92
82

84

86

49

53

59

36

37

38
28

323334

47

48

39
64

6970

8788

90

101
103

C

34

7

8

9

14

17
85

38

7

B

80

V_3P3_STBY\G

92122

IN

V_FSB_VTT

IN

VTT_SEL

IN

BV_FSB_VTT_SEL_B1

DESIGN NOTE:

STUFF FOR PENRYN CORE
BASED CPUS SUPPORT

7075

IN

82

8990

R186BV

1

1K

5%

2

CH
402

R185BV

1

1K

5%

2

CH
402

MBT3904DUAL

BACKFEED_CUT

5

VCC

R54BV

1

1K

5%

2

CH
402

3

4

R184BV

1

10K 5%

402

BV_FSB_VTT_SEL_B3_TO_R53BV

6

1

2

CH

R53BV

1

66.5K
402

BV_FSB_VTT_SEL_B2

2

Q46BV

XSTR

BV_FSB_VTT_DIS_B1

2

1%
CH

6.49K

R47BV

1

17.4K
1%

2

CH
402

BV_VTT_CORE_OPAMP_PLUS_3

3

Q45BV

1

MMBT3904
XSTR

2

R207BV

1

603

1

2

R45BV

10K
1%

CH
402

2

1%

CH

CAD NOTE:

PLACE DECOUPLING CAP
AS CLOSE AS POSSIBLE TO
PIN 3

BV_2P2_OPAMP_PLUS_12

R208BV

1

17.4K
1%

2

CH
402

CAD NOTE:

PLACE DECOUPLING CAP
AS CLOSE AS POSSIBLE TO
PIN 5

1

2

C48BV
1UF
20%

6.3V
X5R
603

1

2

C246BV
1UF
20%

6.3V
X5R
603

BV_V_VTT_CORE_OPAMP_MINUS_6

R230BV

1

0

402

EMPTY

5
6

A

R39BV

1

499

1%

EMPTY

2

402

+12V

3

D

U2BV

8

3

LM358

+

BV_2P2_OPAMP_OUT_14

1

V

2

G

IC

4

-12V

2

5%

R209BV

1

1K

402

Q50BV

1

5%
CH

C83236-001

S

G

FET

2

2

BV_2P4_FET_DRAIN_FSB_VTT

VCC3

1

C53BV

4.7UF
20%

16V

2

Y5V

1206

1

2

C249BV

470UF
20%

10V
EMPTY
RDL

1

2

C250BV

1000UF

20%

6.3V
ALUM
TH

D

C

CAD NOTE:

1

4

RP4BV

0
5%

3

Q9BV

D

S

2

1

2

.063W
EMPTY
SM

5

C83236-001

FET

C205BV

1UF

20%

6.3V
X5R
603

1

1

C206BV

2

+12V

CAD NOTE:

PLACE CLOSE
TO PIN 8

1

C247BV
1UF
20%
16V

2

Y5V
805

U2BV

8

LM358

+

BV_VTT_CORE_OPAM P_ OUT _7

7

V
G

IC

4

-12V

CAD NOTE:

PLACE CLOSE
TO PIN 4

1

C248BV

1UF

20%

16V

2

Y5V
805

R41BV

1

2

5%

0

CH

402

1K

402

R38BV

1

CAD NOTE:

DUAL SITE

2

5%
CH

1

G

C204BV

1UF
20%

6.3V
X5R
603

CAD NOTE:

PLACE NEAR MCH

2

3

RP4BV

0
5%

.063W
EMPTY
SM

7

6

4

Q56BV

D

RP4BV

0
5%
.063W
EMPTY
SM

RP4BV

0
5%
.063W
EMPTY
SM

8

NTB18N06L

S

G

EMPTY

3

A68810-001

1

1UF

20%

6.3V
X5R

2

603

1

C42BV
1UF
20%

6.3V

2

X5R
603

CAD NOTE:

PLACE CAP NEAR
SOURCE OF FET

1

C269BV

20%

6.3V
ALUM

2

TH

1000UF

DUAL SITE

1

C207BV

2.2UF
10%

6.3V

2

EMPTY
603

CAD NOTE:

PLACE NEAR CPU

V_FSB_VTT

1

C208BV

2.2UF
10%

6.3V

2

EMPTY
603

B

34 38
7

89

OUT

14

17

85

1

C209BV

2.2UF
10%

6.3V

2

X5R
603

A

BPAGE DRAWING

frostburg_fabc.sch_1.85

Sun Mar 18 18:44:51 2007

8

7

6

5

4 2

3

[PAGE_TITLE=VREG_FSB VTT & SFR]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

85

1

3.01

CR-86 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE86

8

88
80
81

D

80

5VDUAL

IN

BV_DRV_BOOT_VSM

IN

V_3P3_STBY\G

IN

+12V

2

24.3K
402

R85BV

EMPTY

1

402

2

1

1

1%

C

89
86

SLP_M

28

IN

39
88

7

R210BV

2

5%

0

EMPTY

CR8BV

3

BAT54C
SOT23_C
EMPTY

BV_1P25_CL_CONTROL_INPUT

1

R87BV

15.4K
1%

EMPTY
402

2

PLACE DECOUPLING CAP
AS CLOSE AS POSSIBLE TO
PIN 3

R154BV

2

10K
402

6

BV_V_1P25_CL_OPAMP_VPLUS

BV_V_1P25_CL_OPAMP_VPLUS

86

IN

1

C112BV

1UF

20%

6.3V

2

EMPTY
603

CAD NOTE:

3

Q41BV

1

MMBT3904
EMPTY

2

5%

EMPTY

1

BV_SLP_M_1P25_FET

1

2

C241BV

1.0UF
20%

10V
EMPTY
603

86

OUT

14

18

19

2425

2780

81

82

1

C113BV

1UF
10%
25V

2

EMPTY

U5BV

8

3

LM358

+

1

V

2

G

4

EMPTY

BV_1P25_CL_358_OUT_7

603

CAD NOTE:

PLACE CLOSE
TO PIN 8

2

1K

402

IN

R92BV

EMPTY

V_SM

1

G

1

5%

45

1

C114BV

4.7UF
20%

6.3V

2

EMPTY
805

3

Q21BV

D

C83236-001

S

EMPTY

2

CAD NOTE:

PLACE 0.1UF CAP NEAR
SOURCE PIN OF FET ON
V_1P25_CL_MCH

1

2

C119BV

.1UF
10%
16V
EMPTY
603

1

C115BV

.1UF
10%
16V

2

EMPTY
603

3

DESIGN NOTE:

DUAL SITE

1

2

C192BV
470UF
20%

10V
EMPTY
RDL

1

2

C116BV

1000UF
20%

6.3V
EMPTY
TH

2

MODULE REV DETAILS

MODULE NAME

BL_B_ATX

1

REV

06.12.2 2/8/07

DATE

D

C

V_1P25_CL_MCH

C118BV

.1UF
10%

16V
EMPTY
603

1

2

1

2

1

C226BV

10UF

20%

6.3V

2

X5R
805

DESIGN NOTE:

DECOUPLING CAPS

PLACE NEAR MCH

C225BV

10UF
20%

6.3V
X5R
805

OUT

14 16
19

86

B

98105
76

82

18

21

1314
16

17

3438
83

A

V_1P25_CORE V_1P25_CL_MCH

IN

BOM NO TE:

STUFF RP3BV, C225BV, C226BV FOR NON AMT SYSTEM
EMPTY EVERYTHING ELSE ON PAGE FOR NON AMT
USE DEFAULT STUFFING ON PAGE FOR AMT SYSTEM

8

0

SM

7

0

SM

6

0

SM

0

SM

RP3BV

RP3BV

RP3BV

RP3BV

1

5%

.063W

IC

2

5%

.063W

IC

3

5%

.063W

IC

45

5%

.063W

IC

[PAGE_TITLE=VREG 1.25 MCH CL]

8

7

OUT

B

V_1P25_CL_MCH

14161986

IN

14 16 19
86

105
101

102103

87

889092

82848586
596469

70

47

484953

36373839

V_3P3_STBY\G

9212228

IN

323334

DESIGN NOTE:

MCH_CLPWROK: DEFAULT THRE SHOLD = 1.1V (2.5K SERIES)

BOM NO TE:

CHANGE SERIES RESISTOR ON NEGATIVE PIN TO 2.7K
TO SET THRESHOLD TO 1.0VOLT

6

5

R93BV

1

2

1%

3.24K
402

20K
402

EMPTY

R94BV

1

EMPTY

1

2

86

IN

BV_PWROK_1P25_OPAMP3

BV_PWROK_3P3_OPAMP2

2

1%

R91BV

1

10K
1%

2

EMPTY
402

C185BV

1.0UF
20%
10V
EMPTY
603

BV_V_1P25_CL_OPAMP_VPLUS

4 2

82.5K

1

402

5
6

R95BV

EMPTY

+

2

1%

U5BV

8

LM358

V
G

EMPTY

4

89

7

BV_MCH_CLPWROK_OPAMP1

39
88

R96BV

1

2

475

1%

EMPTY

402

SLP_M

28

IN

86

1K

402

R98BV

1

EMPTY

1

2

2

5%

R97BV

1K
1%

EMPTY
402

BV_MCH_CLPWROK_ XSTR _ BASE

CL PWROK GENERATION

BPAGE DRAWING

frostburg_fabc.sch_1.86

Sun Mar 18 18:44:53 2007

3

CONFIDENTIAL

CUSTOM TEXT BPAGE

INTEL

3

1

2

MCH_CLPWROK

Q22BV

MMBT3904
EMPTY

DOCUMENT_NUMBER

xxxxxx

OUT

PAGE REV

86

1

13

39

A

3.01

CR-87 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE87

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

BL_B_ATX

1

REV

06.12.2 2/8/07

DATE

D

D

+12V

U11BV

8

BV_SFR_OPAMP_SC_3_2

C

3

LM358

+

1

V

2

G

IC

4

-12V

C

+12V

VCC3

B

R238BV

402

R240BV

1

0

402

BV_SFR_OPAMP_PLUS_5

1%
CH

R239BV

1

24.3K
1%

CH

2

402

BV_SFR_OPAMP_MINUS_6

2

5%
CH

1

2

R241BV

499

1%

EMPTY
402

5

+

6

92

101

102103105

4748

90

84858688

32333436373839

7082

4953596469

A

9212228

IN

V_3P3_STBY\G

9

87

IN

28.7K

V_SFR_OUT

1

C288BV

1.0UF
10%
16V

2

X5R
805

1

2

C290BV

4.7UF
20%
10V
Y5V
805

V_SFR_OUT

OUT

9

87

U11BV

8

V
G

4

LM358

IC

7

BV_SFR_OPAMPOUT_7

-12V
R242BV

1

2

1K

5%
CH

402

1

C287BV

1.0UF
10%
16V

2

X5R
805

3

Q57BV
FET

1

2

1

C289BV

1.0UF

20%

10V

2

Y5V
603

B

A

BPAGE DRAWING

frostburg_fabc.sch_1.87

Sun Mar 18 18:44:54 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

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PAGE REV

87

1

3.01

[PAGE_TITLE=CORE VREG]

D

C

CR-88 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE88

8

5V_DUAL

BOM NO TE:

NON AMT STUFF
Q34BV Q35BV

VREG_5VDUAL_PCH

89

IN

74
70

66

V_5P0_STBY\G

37

IN

51
69

73

80

BOM NO TE:

88
89
90
91
92

89

(DEFAULT) AMT STUFF

Q36BV Q35BV

VREG_5VDUAL_NCH

IN

1

VCC

1

G

3

4

G

7

3

D

Q34BV

S

PMOSFET

2

C77877-001

Q36BV

FDC638P

DRN

GATE

DRN
DRN
DRN

SOURCE

EMPTY

1.0

5VDUAL

2

D

Q35BV

S

FET

3

D37438-001

1
2
5
6

OUT

CAD NOTE:

0.1 INCH COPPER ON
DRAIN AND SOURCE

2

Q31BV
EMPTY

S

D

3

D32396-001

3

1

R140BV

0
1A

CH
805

2

BOM NO TE:

STUFF FOR
NON AMT

6

V_3P3_EPW

28

39

8689

80

81

86 88

V_3P3_STBY\G

IN

SLP_M

IN

WOL_ONLY

3337

IN

BOM NO TE:

STUFF FOR NINEVEH + AMT

86

70

828485

R137BV

1

1K

402

R138BV

1

10K 5%

402

5%

EMPTY

EMPTY

102103105

2

2

BV_WOL_CNTL_BASE

45

8890

92101

87

V_3P3_STBY\G

92122

28

32333436373839

49

53596469

1

47

48

BV_SLP_M_R

3

Q30BV

MMBT3904
EMPTY

2

IN

1

G

1

C233BV
1UF
20%

6.3V

EMPTY

2

603

VCC3

1

2

2

R139BV

0
1A

EMPTY
805

MODULE REV DETAILS

MODULE NAME

BL_B_ATX

BOM NO TE:

STUFF FOR NON-INTEL
LAN OR M0 ONLY

1

REV

06.12.2 2/8/07

V_3P3_EPW

OUT

DATE

57 58

38 39

27 28

33 34
40
92

D

56

C

CAD NOTE:

C182BV

1.0UF

OVERLAPPING SITE

1

20%
10V

2

Y5V
603

C184BV

.1UF

20%
25V

EMPTY

603

86

5VDUAL

80

IN

81
88

R235BV

B

6970
88

89

A

1

1

R143BV

0

0

1A

5%

CH

CH

603

402

2

2

BOM NO TE:

STUFF ONLY IF 5V_DUAL USB VR IS EMPTY

5V_DUAL USB VR

89

IN

91

92

90

3751

66

IN

80

7374

89

IN

RP2BV

0
5%

.063W
IC

SM

3

RP2BV

0
5%

.063W
IC

SM

6

4

5

5VDUAL_USB

VREG_USB_PCH

V_5P0_STBY\G

VREG_USB_NCH

Q33BV

VCC

1

1

G

2

RP2BV

0
5%

IC

SM

7

G

1

RP2BV

0
5%
.063W.063W
IC
SM

8

42 43 44 4546528891

OUT

3

Q32BV

D

S

EMPTY

2

C77877-001

5VDUAL_USB

2

D

0.1 INCH COPPER ON
DRAIN AND SOURCE

S

EMPTY

3

D37438-001

1

R224BV

0
5%

CH
402

2

2

BOM NO TE:

NON AMT STUFF R143BV, RP2BV, R224BV, R225BV
EMPTY Q32BV, Q33BV

(DEFAULT) AMT STUFF Q32BV, Q33BV

EMPTY R143BV, RP2BV, R224BV, R225BV

OUT

R225BV

0

1A

CH
603

2

92

43

44 45 46 52 889192

42

R234BV

0
5%

CH
402

2

R231BV

0
5%

CH
402

2

R232BV

0
5%

CH
402

1

1

1

1

1

2

R233BV

0
5%

CH
402

1

2

R236BV

0
5%

CH
402

R237BV

1

CH

0

402

2

92

5%

90
88
74
70
66

V_5P0_STBY\G V_3P3_STBY\G

37

IN

51
69
73
80
89
91

U7BV

LD1117DT

2

IN

GND

1

U8BV

AD1086

2

IN

GND

1

1

R141BV

1

0
5%

2

CH

2

402

BOM NO TE:CAD NOTE:

STUFF 453 OHM (A93548-165) FOR LD1117 (10/100 LAN SKUS)
STUFF O OHM (A93549-001) FOR EZ1086 (GB SKUS)

BOM NO TE:

STUFF FOR 10/100 LAN SKUS
EMPTY FOR GB LAN SKUS

3

OUT

EMPTY

3

OUT

SM

R142BV

1

274
1%

EMPTY

2

BV_V_STBY_ADJ

402

BOM NO TE:

STUFF FOR LD1117 (10/100 LAN SKUS)
EMPTY FOR EZ1086 (GB LAN SKUS)

1

C183BV

220UF

20.0%
25V
ELEC

2

RDL

103 105
53 59 64 697082
92122 28

OUT

36 37 38 39

85 868788 90 92

32 33 34

474849

B

84

101

102

A

[PAGE_TITLE=CORE VREG]

BPAGE DRAWING

frostburg_fabc.sch_1.88

Sun Mar 18 18:44:56 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE

REV

88

3.01

1

CR-89 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE89

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

BL_B_ATX

1

REV

06.12.2 2/8/07

DATE

D

89
82

C

70
89

B

DESIGN NOTE:

DEFENSIVE DESIGN
DEFAULT EMPTY (R105BV)

85

BACKFEED_CUT

7075

IN

80
90

IN

1

R178BV

10K

5%
CH

402

2

LATCHED_BACKFEED_CUT

1

R177BV

10K

5%
CH

402

2

BOM NO TE:

STUFF FOR NON AMT

1

2

808889

R105BV

10K

5%
EMPTY

402

86
28

39

88

70

89

66

69

707374

91

92

CAD NOTE:

DUAL FOOTPRINT

1

R103BV

10K

5%

BOM NO TE:

EMPTY

EMPTY R103BV

402

2

FOR NON AMT

MBT3904DUAL

BV_5VDUAL_MBT3904DUAL5

1

R106BV

4.7K

5%

402

CH

BV_5VDUAL_BACKFEED_CUT_L

BV_SLP_CTRL_BASE1

R109BV

1

SLP_M

IN

10K

402

LATCHED_BACKFEED_CUT

IN

BV_5VDUAL_BACKFEED_CUT_R

3751

90

R243BV

8.2K
5%

CH
402

5%

EMPTY

IN

Q23BV

5

2

V_5P0_STBY\G

+12V

R100BV

1

8.2K
5%

2

EMPTY
603

3

6

4

1

3

Q24BV

1

MMBT3904
EMPTY

2

1

R108BV

8.2K
5%

EMPTY

2

603

VREG_5VDUAL_NCH
VREG_5VDUAL_PCH

BV_5VDUAL_MBT3904DUAL2

2

XSTR

1

R107BV

0

402

BOM NO TE:

EMPTY FOR NON AMT

R244BV

8.2K
5%

CH
402

CAD NOTE:

DUAL FOOTPRINT

1

R104BV

4.7K
4025%CH

2

5%

EMPTY

D

V_5P0_STBY\G

3751

6669

707374

OUT
OUT

88

88

70

89

IN

8589
7075

IN

8082
90

BOM NO TE:

EMPTY R119BV
FOR 1-WATT
S3, S4, S5

LATCHED_BACKFEED_CUT

BACKFEED_CUT

1

R119BV

10K

5%
EMPTY

402

2

1

2

R120BV

10K

5%
EMPTY

402

808889

1

2

R121BV

10K

5%
EMPTY

402

1

2

R122BV

10K

5%
EMPTY

402

22

3336

70

89

1_WATT_CTRL_2

IN

LATCHED_BACKFEED_CUT

IN

IN

91

92

90

CAD NOTE:

DUAL FOOTPRINT

BOM NO TE:

STUFF FOR NO 1-WATT
SUPPORT IN S3 ONLY
R121BV, R122BV
AND EMPTY R120BV

MBT3904DUAL

BV_USB_MBT3904DUAL_5

R123BV

1

2

5%

4.7K
EMPTY

402

BV_USB_BACKFEED_CUT_L

BV_1_WATT_CTRL_2_BASE1

R118BV

1

4.7K
EMPTY

402

BV_USB_BACKFEED_CUT_R

Q29BV

2

5%

R246BV

8.2K
5%

EMPTY
402

1

3

4

3

Q28BV

MMBT3904
EMPTY

2

+12V

1

2

R126BV

8.2K
5%

EMPTY
603

6

1

CAD NOTE:

DUAL FOOTPRINT

R127BV

1

8.2K
5%

EMPTY

2

603

BV_USB_MBT3904DUAL_2

25

EMPTY

BOM NO TE:

STUFF FOR 1-WATT
S3, S4, S5

R245BV

8.2K
5%

EMPTY
402

1

4.7K
402

1

402

R124BV

R125BV

0

5%

EMPTY

5%

EMPTY

2

2

VREG_USB_NCH
VREG_USB_PCH

BOM NO TE:

EMPTY FOR NON AMT

OUT
OUT

C

88

88

B

A

BPAGE DRAWING

frostburg_fabc.sch_1.89

Sun Mar 18 18:44:57 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

89

1

A

3.01

CR-90 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE90

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

BL_B_ATX

1

REV

06.12.2 2/8/07

DATE

D

+12V

1
2

3
4
5
6
7
8
9
10
11

2X12_DETECT

12

C40BV

1

2

.1UF 20%

25V
Y5V
603

C39BV

100UF

2

1

25V

20.0%
ELEC

RDL

OUT

C38BV

1.0UF
20%
10V
Y5V
603

CAD NOTE:

PLACE NEAR ICH

VCC

34 37 38

C36BV

1

.1UF

25V
Y5V
603

20%

OUT

PWRGD_PS

1

C145BV
470PF
10%
50V

2

X7R
402

V_5P0_STBY\G

1

90

2

C30BV

1.0UF
20%
10V
Y5V
603

1

1

C32BV

C41BV

.1UF
20%
25V

2

Y5V
603

.1UF
20%
25V

2

Y5V
603

90

2X12_DETECT

IN

R35BV

1

5%

1K

402

CH

2X12_POWER_DETECT

1

R32BV

2.2K
5%

USED TO DETECT 2X12 PRESENCE

CH

CONNECT TO GPIO

402

2

OUT

OUT

2

DESIGN NOTE:

70

375166 69
909192

OUT

70 73 74 80

33

88 89

VCC3

06.12.02

1

1

BL_B_ATX

2

R247BV

150

5%
CH

603

2

2

06.12.02

1

BL_B_ATX

R248BV

150
5%

CH
603

2

06.12.02
BL_B_ATX

R249BV

150
5%

CH
603

1

2

PASSIVE_BLEED_PATH_VCC3

06.12.02
BL_B_ATX

3

85
80
70
75
82
89

IN

BACKFEED_CUT

Q58BV
EMPTY

1

2

06.12.02
BL_B_ATX

R250BV

150

5%
EMPTY

603

2

06.12.02

1

BL_B_ATX

R253BV

0
1A

CH
603

2

06.12.02

1

BL_B_ATX

R251BV

150

5%
EMPTY

603

VCC3_BLEEDING_CIRCUIT

06.12.02

1

BL_B_ATX

R252BV

150

5%
EMPTY

603

2

BOM NO TE:

STUFF R253BV FOR CBT
STUFF Q58BV FOR ENERGY SAVING

VCC

TP_MINUS5V

VCC3-12V

J2BV

2X12 PWR

13
14
15
16
17
18

19
20
21
22
23
24

CONN

92
88

89

7073

V_5P0_STBY\G

3751

IN

66

69

7480
90

91

70

IN

PS_ON_SIO_N

1

2

R33BV

10K

5%
CH

402

0

402

R37BV

1

2

5%
CH

1

C37BV

1UF

20%

6.3V

2

Y5V
402

BV_PS_ON_HEADER_N

1

C35BV
470PF
10%
50V

2

X7R
603

C

DESIGN NOTE:

POWER CONNECTOR DECOUPLING

92

VCC

88

89

7073

V_5P0_STBY\G

3751

IN

66

69

7480
90

91

B

102

70

323334363738

484953

59

6469

87

88

92101

A

BV_VREG_VBAT_R

THROUGH-HOLE

DO NOT PLACE BATTERY NEAR

MOUNTING HOLES, GROUND OR VIAS

R34BV

1

750
5%

CH

2

402

BV_VREG_MAIN_STBY_LED_R

2

CR5BV
GREEN
LED

1

82848586
9212228

IN

39

47

103105

R36BV

1

1K

5%

402

CH

CAD NOTE:

V_3P3_STBY\G

2

BV_VBAT_VREG_R_CR

XBT1BV

1

2PCOIN

2

C31BV

1

.1UF

C34BV

100UF

1

20.0%
ELEC

BATTERY

CR6BV

2

3

1

BAT54C

SOT23_C

DIO

BOM NO TE:

BATTERY ADDED IN MOD FILE

VCC3

2

20%
25V
Y5V
603

2

25V

RDL

V_3P0_BAT_VREG

C231BV

1

.1UF

C33BV

100UF

1

20.0%

25V
Y5V
603

ELEC

RDL

+12V -12V

2

20%

2

25V

1

2

D

C

B

A

BPAGE DRAWING

frostburg_fabc.sch_1.90

Sun Mar 18 18:44:59 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

90

1

3.01

CR-91 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE91

8

D

44

45

88

92

7

IN

5VDUAL_USB

1

C317BU

1000UF
20%

6.3V
ALUM

2

TH

4243
4652

6

R62BU

2

1

5%15K

402

CH

2

R63BU

10K

5%
CH

402

RP3BU

0
5%
.063W
IC
SM

1

2

R64BU

10K

5%
CH

402

1

RT3BU

1

THRMSTR

1.50

263

817

2

4

5

C

RT4BU

2

1

IM_BV_VREG_PS2_FB

EMPTY

RT6BU

1

RT7BU

1

1.50

2

THRMSTR

1.50

2

THRMSTR

1.50

2

402

2

402

15K

R65BU

R68BU

1

5%
CH

2

R66BU

10K

5%
CH

402

1

2

R67BU

10K

5%
CH

402

1

1

5%15K
CH

2

R69BU

10K

5%
CH

402

1

2

R70BU

10K

5%
CH

402

1

92
8889
7073

V_5P0_STBY\G

3751

IN

6669
74

80
91

90

BOM NO TE:

STUFF THERMISTOR FOR WAKE FROM
S5 BY USING PS2

1

RT5BU

EMPTY

1.50

2

THERMISTOR OPTION (PER CUSTOMER REQUEST):
STUFF SI TE AND EMPTY 0 OHM R-PACK

B

VREG_USB MUST BE SPLIT

8088

92

IN

89

90

91

1

C407BU

470UF
20%

EMPTY

2

RDL

10V

V_5P0_STBY\G

3751

6669

707374

AMONGST ALL USB CHANNELS.
DO NOT DAISY CHAIN

A

VREG_USB MUST BE SPLIT
AMONGST ALL USB CHANNELS.
DO NOT DAISY CHAIN

45

USB_OC_BACK2_N

CAD NOTE:

PLACE AS CLOSE AS POSSIBLE
TO USB CONNECTOR

1

C255BU

470UF
20%
10V
EMPTY

2

RDL

DO NOT CHANGE TO 402 SITE

M1BU

MULTI

2

VREG_PS2

603

1

CH

BOM NO TE:

FERRITE BEAD OPTION:
A51464-001
DEFAULT:0 OHM 108506-004

USB_OC_BACK1_N

CAD NOTE:

PLACE AS CLOSE AS POSSIBLE
TO USB CONNECTOR

1

C257BU

470UF
20%

10V

EMPTY

2

RDL

USB_OC_BACK0_N

CAD NOTE:

PLACE AS CLOSE AS POSSIBLE
TO USB CONNECTOR

1

C259BU

470UF
20%

10V

EMPTY

2

RDL

VREG_USB_BP1_STACK

1

2

VREG_USB_BP0_STACK

1

2

3

VREG_USB_BP_MJ

1

C256BU

470PF

10%

50V

2

X7R
603

VREG_USB MUST BE SPLIT
AMONGST ALL USB CHANNELS.
DO NOT DAISY CHAIN

DECOUPLING ON CONNECTOR PAGE,
PLACED NEAR PS2 CON NECTOR.

C258BU

470PF
10%
50V
X7R
603

C260BU

470PF
10%
50V
X7R
603

OUT

OUT

OUT

OUT

OUT

OUT

OUT

2

MODULE REV DETAILS

MODULE NAME

31

1

REV

DATE

D

46

57

C

72

31

46

31

B

A

45

[PAGE_TITLE=CORE VREG]

BPAGE DRAWING

[PAGE_TITLE=WAKE CONTROL SWITCH PS2/USB (BP RIGHT)]

8

7

6

5

4 2

frostburg_fabc.sch_1.91

Sun Mar 18 18:45:00 2007

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

91

1

3.01

CR-92 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE92

8

DESIGN NOTE:

BOARD GENERAL DCPL CAPS

D

CAD NOTE:

PEG SLOT

VCC

C41BU

1

.1UF

EMPTY

C42BU

1

.1UF

C43BU

C

1

.1UF

C167BU

1

.1UF

EMPTY

DESIGN NOTE:

CLOCK STITCHING CAPS

CAD NOTE:

VCC3 +12V

PLACE CLOSE TO Q50BV

C331BU

B

A

1

.1UF

25V
Y5V
603

CAD NOTE:

CK_P_33M_PA

PLACE NEXT TO SOUTH OF U1CK

VCC3

C70BU

1

.1UF

16V
X7R
603

VCC

C400BU

1

2

.1UF

10%

10V

X5R

VCC

402

C351BU

2

1

10%

.1UF

10V
X5R
402

25V
603

25V
Y5V
603

25V
Y5V
603

25V
603

20%

10%

C53BU

1

.1UF 20%

EMPTY

2

20%

2

20%

2

20%

2

20%

2

2

8

25V
603

+12V

2

80

CAD NOTE:

PWR CONN

CAD NOTE:

PCI SLOT

CAD NOTE:

PCI SLOT

CAD NOTE:

FP HDR

VCC3

C146BU

1

.1UF

707374
92

VCC3

+12V

C271BU

1

.1UF

VCC

2

10%

10V
X5R
402

7

3751

6669

91

IN

888990

1

C169BU

22UF

20.0%
25V
ELEC

2

RDL

"THMNT ALUM ELEC"

-12V

CAD NOTE:

FOR CK_PE_100M_PATA

C299BU

1

2

20%

.1UF

25V
Y5V
603

CAD NOTE:

CK_1PORT_S3_DN/S2_DN

PLACE NEAR LEFT SIDE OF U1LN

2

10%

10V

C31BU

X5R
402

2

1

20%.1UF
25V
Y5V
603

CAD NOTE:

CK_PE_33M_TPM

PLACE NEAR C12BV

7

CAD NOTE:

EMI CAPS
PLACE CLOSE BP AUDIO CONN

AUD_GND

C79BU

1

2

.1UF

20%
25V
Y5V
603

V_5P0_STBY\G

IN

VCC

DESIGN NOTE:

GNR BULK DCPL

4748

49

C178BV

2

1

CAD NOTE:

20%

.1UF

PWR CONN

25V

EMPTY

603

C173BV

2

1

20%

.1UF

25V

EMPTY

PCI SLOT

603

V_5P0_STBY\G

C334BU

1

0.1UF

889192

5VDUAL_USB

42

4344

IN

45

4652

BOM NO TE:

STUFF FOR ATX ONLY

VCC3

8586

878890

CAD NOTE:

OUT

2

20%

16V
Y5V
402

C354BU

1

0.1UF
16V

EMPTY

402

CAD NOTE:

CK_P_33M_TPM\PA

PLACE NEAR C72BV

C277BU

1

2

10%

.1UF

10V
X5R
402

8298

84

VCC3

20%

VCC3

6

3438

C401BU

1

.1UF

70

82

VCC3

C406BU

1

.1UF

10V

EMPTY

402

92
74

80 88

375166
69 70 73
899091

2

C355BU

1

.01UF

EMPTY

VCC3

C26BU

1

.1UF

6

+12V

9

IN

2

10%
10V
X5R

C413BU

402

1

.1UF

EMPTY

59

6469

CAD NOTE:

AZ HDR EMI CAPS
PLACE NEAR J7AU

C25BU

1

.1UF

25V

EMPTY

603

2

10%

V_3P3_EPW

C335BU

1

0.1UF

2

10%

25V
402

C71BU

2

1

.1UF

10%
16V
X7R
603

2

20%

25V
Y5V
603

C282BU

1

2

10%

.1UF

10V
X5R
402

CK_P_33M_TPM

PLACE NEXT TO C12BV

C323BU

2

1

.1UF

20%
25V
Y5V
603

V_1P5_ICH

VCC3

2

10%

10V

402

101

102103105

921222832333436373839

IN

53

2

20%

2

20%
16V
Y5V
402

+12V

C356BU

1

.1UF

VCC3

CAD NOTE:

CK_14M_ICH

PLACE NEAR C244BU

VCC

CAD NOTE:

+12V

C352BU

1

.1UF

V_3P3_STBY\G

+12V

C333BU

1

.1UF

10V
X5R
402

272833 34 38 39

OUT

88

2

20%

25V

EMPTY

603

C332BU

2

1

10%

.1UF

10V
X5R
402

5

VCC

C324BU

1

2

20%

.1UF

25V
Y5V

CAD NOTE:

603

USB AND CLOCK

C350BU

1

2

.1UF 20%

25V

EMPTY

603

2

10%

10V

EMPTY

402

CAD NOTE:

FOR HSYNC & VSYNC ABOVE
NORTH OF MCH TRANSITION

2

10%

C353BU

1

.1UF

10V

EMPTY

402

C152BU

1

.1UF

25V

EMPTY

603

CAD NOTE:

CLOSE TO PATA

40 565758

+12V

C385BU

1

10%

.1UF

10V
X5R
402

C387BU

1

2

.1UF

10%

10V
X5R
402

10%

2

20%

2

C386BU

1

.1UF

C412BU

1

.1UF

X5R
402

10V

DESIGN NOTE:

PATA STITCHING CAPS

CAD NOTE:

PLACE BETWEEN JIPT AND U1PT

+12V

C30BU

1

2

.1UF

10%

10V

EMPTY

402

C33BU

2

1

10%

.1UF

10V

EMPTY

402

45

VCC

C402BU

1

.1UF

10V
X5R
402

VCC3

2

10%

DESIGN NOTE:

STITCHING CAPS

2

10%
10V
X5R
402

2

10%

+12V

C148BU

2

1

20%

.1UF

25V
Y5V
603

+12V

LAN_V_1P0

C19BU

2

1

20%.1UF
25V
Y5V
603

C20BU

1

2

CAD NOTE:

20%.1UF
25V

GCL STITCHING CAPS

Y5V

PLACE NEAR LEFT SIDE OF U1LN

603

DESIGN NOTE:

PCIEX1 STITCHING CAPS

CAD NOTE:

PLACE NEAR SOUTH OF U1FW

2

4 2

1

.1UF

C38BU

1

.1UF

1

.1UF

1

.1UF

10V
X5R
402

C34BU

10V
X5R
402

C275BU

10V
X5R
402

C276BU

10V
X5R
402

2

10%

2

10%

2

10%

2

10%

VCC

Sun Mar 18 18:45:02 2007

3

C403BU

2

1

10%

.1UF

10V
X5R
402

CAD NOTE:

FOR ICH_LAN_JCLK

PLACE BELOW Y1LN

56 58

OUT

CAD NOTE:

PLACE NEAR SOUTH OF Y1PT

C278BU

2

1

.1UF

10%
10V
X5R
402

C279BU

2

1

10%

.1UF

10V
X5R
402

C280BU

2

1

10%

.1UF

10V
X5R
402

C281BU

2

1

10%

.1UF

10V
X5R
402

[PAGE_TITLE=VREG: DECOUPLING AND STITCHING]

BPAGE DRAWING

frostburg_fabc.sch_1.92

3

CAD NOTE:

BP USB

PLACE NEAR THE JA1LN

C15BU

2

1

20%

.1UF

25V
Y5V
603

C8BU

2

1

20%

.1UF

25V
Y5V
603

C5BU

2

1

.1UF

20%
25V
Y5V
603

+12V

C66BU

1

.1UF

25V
Y5V
603

DESIGN NOTE:

AZALIA STITCHING CAPS

VCC

+12V

CAD NOTE:

1394 STITCHING CAPS

PLACE NEXT TO J33LB

VCC3

VCC

CONFIDENTIAL

CUSTOM TEXT BPAGE

2

2

20%

C67BU

1

.1UF

25V
Y5V
603

C330BU

1

0.1UF

C305BU

1

0.1UF

C61BU

1

.1UF

C329BU

1

.1UF 20%

INTEL

MODULE REV DETAILS

MODULE NAME

C320BU

1

.1UF

C321BU

1

16V
Y5V
402

16V
Y5V
402

5VDUAL_USB

25V
Y5V
603

25V
Y5V
603

2

20%

20%

20%

2

20%

2

20%.1UF

VCC

2

2

OUT

+12V

C388BU

1

.1UF

VCC

.1UF

CAD NOTE:

FP USB STITCHING CAPS

PLACE CLOSE TO J8BU AND J9BU

C409BU

2

1

10%

.1UF

10V
X5R
402

C411BU

1

2

10%

.1UF

10V

EMPTY

402

+12V

C287BU

0.1UF
EMPTY

AUD

42 43 44 45 46 52 88
91

20%
25V
Y5V
603

C389BU

1

10V
X5R
402

+12V

20%

16V

402

C408AU

1

470PF

VCC3

+12V

2

20%
25V
Y5V
603

2

25V
Y5V
603

+12V

CAD NOTE:

STITCHING CAPS

FOR CK505

DOCUMENT_NUMBER

xxxxxx

92

10%

0.1UF

0.1UF

REV

2

2

50V
X7R
402

C102BU

1

C103BU

1

0.1UF

+12V

C410BU

1

.1UF

X5R
402

2

10%

16V
Y5V
402

16V
Y5V
402

C104BU

1

Y5V
402

10V

16V

1

2

10%

2

20%

2

20%

2

20%

PAGE REV

92

1

DATE

D

C

B

A

3.01

6

7

8

97

105

D

93

6

C

93

B

VSS/VCCSENSE: 1X2
HEADER (J1VR): NEVER
STUFF SUITCASE JUMPER

93

1

A

2

CR-93 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE93

8

VTT_OUT_RIGHT

IN

IN

H_VID<7..0>

VCC_VRM_SENSE

IN

J1VR

1X2HDR

EMPTY

A91829-020

DESIGN NOTE:

VSS_VRM_SENSE

IN

C206VR

1500PF
5%
25V
EMPTY
603

1

2

1
2

1

2

1

R1VR

680
5%

CH
402

2

0

BOM NO TE:

LL STUFFING (DEFAULT IS 1.23MOHM LL)

1.23MOHM LL: R202VR - 562K A93548-198 STUFFED

1.23MOHM LL: R201VR EMPTIED

1.00MOHM LL: R201VR 24.3K A93548-245 STUFFED

1.00MOHM LL: R202VR EMPTIED

C207VR

1500PF
5%
25V
EMPTY
603

1

R2VR

R3VR

680

680

5%

CH
402

1

5%

CH
402

2

2

CAD NOTE:

PLACE ALL COMPONENTS
CLOSE TO CONTROLLER

BOM NO TE:

FMB STUFFING
65W: R207VR - 22.1K A93548-147
95W: R207VR - 17.4K A93548-239 (DEFAULT)
105W: R207VR - 15.4K A93548-205

C202VR

2

1

CPU_VREG_VDIF F_PN1

10%470PF
50V
X7R

R210VR

603

1

750

402

R211VR

CPU_VREG_VDIFF_PN3

2

1

1%

562

CH

402

CAD NOTE:

PLACE THERMISTOR RT1VR
CLOSE TO I ND1, NEEDS TO BE
GROUND REFERENCED AND
AWAY FROM PHASE NODE
> 10MILS SO IT DOES NOT
PICK UP NOISE

8

7

6

VCC

R223VR

2

1

0

1A

CH

603

1

1

1

R4VR

R5VR

680

680

5%

5%

CH

CH

402

2

3

93

OUT

6

IN

2

1%

CH

402

2

4

VCC_IN_CPU_VREG

1

562K

402

1

24.3K
402

6

93

IN

1

2

R209VR

1

2

22.1

1%

CH

402

CPU_VREG_VDIF F_PN2

RT1VR

1

2

THRMSTR

C14407-001

R202VR

R201VR

EMPTY

H_VID<7..0>

VRD_ENABLE

C220VR

.1UF
10%
10V
EMPTY
402

.012UF

R212VR

1

750

CH

402

R213VR

1

17.4K
402

1

C205VR

1500PF
5%
25V
EMPTY

2

603

7

1

2

1%
CH

1%

2

1%

1%

CH

R6VR

680
5%

CH
402

5

C201VR

1

50V
X7R
603

2

2

2

C203VR

1

22PF

1

2

6

68

2

10%

R204VR

1

100K

402

93

R205VR

1

0

402

R207VR

1

17.4K
402

2

5%
50V
COG
603

CPU_VREG_COMP_PN1

6

R7VR

680
5%

CH
402

VRD_VIDSEL

IN

7839

OUT

82.5K

2

1%
CH

IN

2

CPU_VREG_DRSEL

5%
CH

R206VR

1

0

402

2

1%

CH

C204VR

1

820PF 5%

R8VR

680
5%

CH
402

2

7

CPU_VREG_OFS

7
6

5
4

3

2

1

0

VR_READY

R203VR

CPU_VREG_FS

1

2

1%
CH

402

CPU_VREG_REF

CPU_VREG_SS

VCC_IN_CPU_VREG

CPU_VREG_OVPSEL

2

5%
CH

CPU_VREG_IOUT

CPU_VREG_VDIFF

CPU_VREG_FB

CPU_VREG_COMP

2

50V
COG
603

49.9K
402

R236VR

1

EMPTY

1

C280VR

.1UF
10%

95

94

16V

2

X7R
603

10

VCC

12

OFS

6

VRSEL

46

VID7

47

VID6

48

VID5

1

VID4

2

VID3

3

VID2

4

VID1

5

VID0

36

EN

37

PGOOD

45

FS

11

REF

9

SS

2

1%

7

DRSEL

8

OVPSEL

15

IOUT

16

VDIFF

14

FB

13

COMP

18

VSEN

17

RGND

49

GND

IN

96

EU10VR

ISL6312A

1OF1

REV=1

5

45

DESIGN NOTE:

EMPTY R237VR FOR 2 PHASE

CAD NOTE:

PLACE C278VR CLOSE TO PIN 29
PLACE C279VR CLOSE TO PIN 42

VREG_12V_POWER

PVCC1_2

PVCC3

BOOT3

BOOT2

BOOT1

PHASE1

PHASE2

PHASE3

ISEN1+

ISEN1-

ISEN2+

ISEN2-

ISEN3+

ISEN3-

ISEN4+

ISEN4-

UGATE1
UGATE2
UGATE3

LGATE1
LGATE2
LGATE3

EN_PH4

PWM4

IC

R237VR

1

0

603

1

C278VR

1UF
10%

25V

2

X5R
603

29

42

CPU_VREG_PVCC3

CPU_VREG_BST3

40

CPU_VREG_BST2

27

CPU_VREG_BST1

31

33

25

38

CPU_VREG_ISEN1P

R215VR

1

35

1K
1%

2

EMPTY
402

34

CPU_VREG_ISEN1M

19

20

CPU_VREG_ISEN2M

44

43

CPU_VREG_ISEN3M

TP_CPU_VREG_ISEN4P

21

TP_CPU_VREG_ISEN4M

22

CPU_VREG_UGATE1

32

CPU_VREG_UGATE2

26

CPU_VREG_UGATE3

39

30

CPU_VREG_LGATE1

CPU_VREG_LGATE2

28

CPU_VREG_LGATE3

41

VCC_IN_CPU_VREG

23
24

TP_CPU_VREG_PWM4

2

1A
CH

1

2

Sun Mar 18 18:45:04 2007

4 2

3

CAD NOTE:

VCC/VSS_SENSE RESISTORS: POSSIBLE TO OVERLAP PADS (SAVE SPACE) ON FUTURE DESIGNS
OPTION FOR R11VR TO OVERLAP W/R12VR & R13VR TO OVERLAP W/14VR

6

1

C279VR

2

C211VR
.1UF
10%
16V
X7R
603

CPU_VREG_ISEN2P

OUT
OUT
OUT

IN

BPAGE DRAWING

frostburg_fabc.sch_1.93

IN

1UF
10%

25V

6

X5R

IN

603

6

IN

6

IN

R238VR

1

0

402

1

C212VR

.1UF
10%
16V

2

X7R
603

1

R217VR

1K
1%

EMPTY

2

402

1

R219VR

2

EMPTY
402

94

94

95

1

C219VR

1000PF
10%

50V

2

EMPTY
402

3

VCC_SENSE

VCC_PKGSENSE

VSS_SENSE

VSS_PKGSENSE

2

5%

CPU_VREG_ISEN1P_R

CH

R216VR

1

5.11K
402

1

C213VR

.1UF
10%
16V

2

X7R
603

CPU_VREG_ISEN3P

1K
1%

95

OUT

1

93

2

2

1%
CH

1

C215VR
.1UF
10%
16V

2

603

OUT

C218VR

1000PF
10%
50V
EMPTY
402

[PAGE_TITLE=VCCP VREG]

2

R11VR

2

0

402 EMPTY

R12VR

2

0

402

R13VR

2

0

402

R14VR

2

0

402

1

C208VR

.22UF
10%
16V

2

X7R
603

94

IN

CAD NOTE:

PLACE ALL COMPONENTS
CLOSE TO CONTROLLER

1

2

CUSTOM TEXT BPAGE

402

C214VR
.1UF
10%
16V
X7R
603

R218VR

1

5.11K
402

1

C216VR
.1UF
10%
16V

2

X7RX7R
603

94

1

C217VR

1000PF
10%

50V

2

EMPTY
402

INTEL

CONFIDENTIAL

MODULE REV DETAILS

MODULE NAME

BL_CPUVR

1

5%

VCC_VRM_SENSE

DESIGN NOTE:

1

EMPTY R11VR <ENG EXP>

5%
CH

1

5%

VSS_VRM_SENSE

EMPTY

DESIGN NOTE:

1

EMPTY R13VR <ENG EXP>

5%
CH

C209VR
.22UF
10%
16V
X7R
603

1

C210VR

.22UF
10%
16V

2

X7R
603

1

2

VREG_SW3_OUT
VREG_SW2_OUT
VREG_SW1_OUT

2

CPU_VREG_ISEN2P_R

R240VR

1

2

5%

0

CH

1

2

1%

CH

94

CPU_VREG_SENSE1

CPU_VREG_SENSE2

CPU_VREG_ISEN3P_R

CPU_VREG_SENSE3

R239VR

1

0

2

1%
CH

OUT

5%
CH

402

R220VR

5.11K
402

DOCUMENT_NUMBER

xxxxxx

5.9.3

REV

1

03-02-07

OUT

OUT

IN

PAGE REV

93

1

DATE

D

93

93

C

95

OUT

94

OUT

94

OUT

OUT

OUT

OUT

B

94

95

95

94

IN

A

3.01

CR-94 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE94

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

BL_CPUVR 03-02-07

5.9.3

1

REV

DATE

9394

IN

93949596

IN

VREG_12V_POWER

VREG_12V_POWER

93

BOM NO TE:

FMB STUFFING
65W: Q14VR - D79718-001 (IPD135N03L_G)
65W: Q16VR EMPTY
95W: DEFAULT
105W: Q 14VR - D79716-001 (IPD090N03L_G)
105W: Q15VR & Q16VR C92515-001 (FDD8896) STUFFED

CAD NOTE:

PHASE RESISTORS: PLACE ALL
GATE RESISTORS CLOSE TO FET

93

IN

BOM NO TE:

FMB STUFFING
65W: Q11VR D79718-001 (IPD135N03L_G)
65W: Q12VR EMPTY
95W: DEFAULT
105W: Q 11VR - D79716-001 (IPD090N03L_G)
105W: Q12VR & Q13VR C92515-001 (FDD8896) STUFFED

93

IN

IN

93

IN

CPU_VREG_UGATE1

CPU_VREG_LGATE1

CAD NOTE:

PLACE LGATE CAP CLOSE TO MOSFET GATE PIN
SHARE THE S AME GND WITH MOSFE T SOURCE PIN

CAD NOTE:

PHASE RESISTORS: PLACE ALL
GATE RESISTORS CLOSE TO FET

CPU_VREG_UGATE2

CPU_VREG_LGATE2

CAD NOTE:

PLACE LGATE CAP CLOSE TO MOSFET GATE PIN
SHARE THE S AME GND WITH MOSFE T SOURCE PIN

R224VR

1

2.2
603

93

IN

1

2

BOM NO TE:

FMB STUFFING
65W: C282VR STUFFED
95W & 105W: DEFAULT

R227VR

1

2.2CH5%
603

93

IN

BOM NO TE:

FMB STUFFING
65W: C283VR STUFFED
95W & 105W: DEFAULT

CPU_VREG_HS_GATE1

2

5%
CH

VREG_SW1_OUT

NTD4808

D53747-001

C282VR

2200PF
10%
50V
EMPTY
603

CPU_VREG_HS_GATE2

2

VREG_SW2_OUT

NTD4808

D53747-001

1

C283VR

2200PF
10%
50V

2

EMPTY
603

2SK4080

D79653-001

1

G

2SK4080

D79653-001

1

G

1

C224VR

4.7UF
20%

16V

2

X5R

1206

L1VR

315NH

2

IND

1

R226VR

0OHM

SM

2

CPU_VREG_SENSE1

1

C228VR

4.7UF
20%

16V

2

X5R

1206

L2VR

315NH

2

IND

1

R229VR

0OHM

SM

2

CPU_VREG_SENSE2

1

VCCP

1

2

1

VCCP

1

2

OUT

R233VR

0OHM

SM

CPU_VREG_ISEN1P_R

93

OUT

OUT

R234VR

0OHM

SM

CPU_VREG_ISEN2P_R

OUT

6

76 94

95 96 105

CAD NOTE:

PLACE R226VR AND R233VR NEAR INDUCTOR

OUT

6

76 94

95 96 105

CAD NOTE:

PLACE R229VR AND R234VR NEAR INDUCTOR

93

OUT

93

93

CPU_VREG_SNUB1

CPU_VREG_SNUB2

2

1

2

1

2

1

2

1

R225VR

2.2
5%

CH
805

C221VR

4700PF
20%
50V
X7R
603

C227VR

4.7UF
20%

16V

X5R

1206

1

2

1

2

C223VR

4.7UF
20%
16V
X5R
1206

R228VR

2.2
5%

CH
805

C225VR

4700PF
20%
50V
X7R
603

1

C222VR

4.7UF

3

Q11VR

D

1

S

G

FET

2

3

Q12VR

D

S

FET

2

SOT

3

Q14VR

D

1

S

G

FET

2

3

Q15VR

D

S

FET

2

NTD4808

D53747-001

NTD4808

D53747-001

1

G

1

G

20%
16V

2

X5R
1206

3

Q13VR

D

S

FET

2

1

C226VR

4.7UF
20%
16V

2

X5R
1206

3

Q16VR

D

S

FET

2

D

C

B

A

95

96

D

C

B

A

BPAGE DRAWING

frostburg_fabc.sch_1.94

Sun Mar 18 18:45:06 2007

8

7

6

5

4 2

3

[PAGE_TITLE=VCCP VREG]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

94

1

3.01

CR-95 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE95

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

BL_CPUVR 03-02-07

5.9.3

1

REV

DATE

D

VREG_12V_POWER

939496

IN

CPU_VREG_SNUB3

2

1%

1

C231VR

4.7UF
20%

16V

2

X5R

1206

1

R231VR

2.2
5%

CH
805

2

1

2

2

C229VR

4700PF
20%
50V
X7R
603

R61VR

2

1

1%

130

EMPTY

402

CPU_VREG_VRHOT_R

BPAGE DRAWING

frostburg_fabc.sch_1.95

Sun Mar 18 18:45:08 2007

1

2

L3VR

315NH

2

1

IND

1

R232VR

0OHM

SM

CPU_VREG_SENSE3

CPU_VREG_VRHOT_PN5

3

C232VR

4.7UF
20%
16V
X5R
1206

VCCP

1

R235VR

0OHM

SM

2

CPU_VREG_ISEN3P_R

OUT

Q10VR

MBT3904DUAL

6769496105

OUT

CAD NOTE:

PLACE R232VR AND R235VR NEAR INDUCTOR

93

OUT

93

H_PROCHOT_N

H_FORCEPH_N

3

6

1

INTEL

EMPTY

2

CPU_VREG_VRHOT_PN2

DOCUMENT_NUMBER

5

4

[PAGE_TITLE=VCCP VREG]

CONFIDENTIAL

CUSTOM TEXT BPAGE

xxxxxx

130

402

OUT

OUT

R62VR

1

EMPTY

2

1%

6837

6

1

PAGE REV

95

1

3

D

S

2

2

Q19VR

FET

R59VR

1

680
5%

EMPTY

2

402

100K

402

C230VR

4.7UF
20%
16V
X5R
1206

R60VR

1

EMPTY

2SK4080

CAD NOTE:

PHASE RESISTORS: PLACE ALL
GATE RESISTORS CLOSE TO FET

93

IN

C

93

IN

B

CPU_VREG_UGATE3

BOM NO TE:

FMB STUFFING
65W: Q17VR - D79718-001 (IPD135N03L_G)
65W: Q19VR EMPTIED
95W: DEFAULT
105W: Q 17VR - D79716-001 (IPD090N03L_G)
105W: Q18VR & Q19VR C92515-001 (FDD8896) STUFFED

CPU_VREG_LGATE3

CAD NOTE:

PLACE LGATE CAP CLOSE TO MOSFET GATE PIN
SHARE THE S AME GND WITH MOSFE T SOURCE PIN

VR HOT

R230VR

1

2.2

5%
CH

603

93

IN

BOM NO TE:

FMB STUFFING
65W: C284VR EMPTIED
95W & 105W: DEFAULT

VCC

R55VR

1

10K
1%

2

EMPTY
402

2

CPU_VREG_HS_GATE3

VREG_SW3_OUT

D53747-001

1

C284VR

2200PF

10%

50V

2

EMPTY
603

R56VR

1

10K
402

NTD4808

EMPTY

D79653-001

1

G

CPU_VREG_VRHOT_OPAMP_PLUS

2

1%

R57VR21

1

4.99K
1%

2

EMPTY
402

3

D

S

2

1

Q18VR

FET

C82VR

.1UF
10%
16V
EMPTY
603

3

Q17VR

D

S

G

FET

2

NTD4808

D53747-001

1

G

R58VR

2

1

1%

49.9K
EMPTY

402

U1VR

8

5

LM358

+

7

V
G

4

CPU_VREG_VRHOT

EMPTY
D69827-001

6

A

CPU_VREG_VRHOT_OPAMP_MINUS

1

RT2VR

EMPTY

2

DESIGN NOTE:

8

7

CAD NOTE:

PLACE NEAR PHASE 3 INDUCTOR

C14407-003

THIS IS FOR VRHOT

6

1

C83VR

.1UF
10%
16V

2

EMPTY
603

5

4 2

D

C

B

A

3.01

CR-96 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE96

8

D

VCCP

676949596105

IN

C

7

CAD NOTE:

PLACE ALL (14) 1206 CAPS INSIDE
CPU SOCKET CAVITY

1

2

1

2

C233VR

22UF
20%

6.3V
X5R

1206

C236VR

22UF
20%

6.3V
X5R

1206

1

C234VR

22UF
20%

6.3V

2

X5R
1206

1

C237VR

22UF
20%

6.3V

2

X5R
1206

1

2

1

2

C235VR

22UF
20%

6.3V
X5R

1206

C238VR

22UF
20%

6.3V
X5R

1206

6

96105

IN

VCCP

67694

95

45

CAD NOTE:

PLACE ON TOP NORTH/NORTHEAST SIDE OF SOCKET

1

C263VR

150UF
20%
2V
EMPTY

2

7343

BOM NO TE:

NIPPON (PCS 2.5VB 560QH08)
628955-074

CAD NOTE:

1

C264VR

560UF
20%

2.5V
EMPTY

2

RDL

3

1

C265VR

560UF
20%

2.5V
EMPTY

2

RDL

1

C266VR

2

560UF
20%

2.5V
ALUM
RDL

2

MODULE REV DETAILS

MODULE NAME

BL_CPUVR

1

C267VR

560UF
20%

2.5V
ALUM

2

RDL

5.9.3

1

REV

DATE

01-12-07

D

C

PLACE ON EAST/SOUTHEAST SIDE OF SOCKET

C240VR

22UF
20%

6.3V
EMPTY
1206

1

2

C241VR

22UF
20%

6.3V
X5R

1206

1

C268VR

560UF
20%

2.5V
ALUM

2

RDL

1

C269VR

560UF
20%

2.5V
ALUM

2

RDL

1

C270VR

560UF
20%

2.5V
EMPTY

2

RDL

1

C271VR

560UF
20%

2.5V
EMPTY

2

RDL

2

1

C239VR

22UF
20%

6.3V
EMPTY

1206

1

2

B

1

2

C242VR

22UF
20%

6.3V
EMPTY

1206

1

C281VR

100UF
20%
2V
ALUM

2

7343

1

2

C243VR

22UF
20%

6.3V
EMPTY
1206

1

2

1

2

C244VR

22UF
20%

6.3V
X5R

1206

C247VR

22UF
20%

6.3V
X5R

1206

VREG_12V_POWER

939495

IN

A

1

BOM NO TE:

FMB STUFFING
65W & 95W: DEFAULT
105W: STUFF C250VR

8

7

2

C250VR

22UF
20%

6.3V
EMPTY

1206

6

5

4 2

BOM NO TE:

FMB STUFFING
65W : EMPTY C269VR
95W & 105W: DEFAULT

1

C276VR

.1UF
10%
16V

2

EMPTY
402

J2VR

2X2HDR

2

1
3

4

CONN

A91848-001

BPAGE DRAWING

frostburg_fabc.sch_1.96

Sun Mar 18 18:45:09 2007

3

BOM NO TE:

RUBICON (16MHZ680M INL)
A46887-048

1

2

C277VR

.1UF
10%
16V
EMPTY
402

1

C273VR

680UF
20%

16V

ALUM

2

RDL

C274VR

680UF
20%
16V
ALUM
RDL

C275VR

680UF
20%

16V
EMPTY
RDL

[PAGE_TITLE=VREG: VCCP DECOUPLING / 2X2 CONN]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

96

1

B

A

3.01

BW_ATX_CORE

CR-97 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE97

8

68

10

IN

VTT_OUT_RIGHT

105

D

C

6789397

IN

2

BI

BI

BI

BI

1

H_BPM_N<3>

H_BPM_N<2>

H_BPM_N<0>

H_BPM_N<1>

CAD NOTE:

PLACE TRST* TERMINATION
ANYWHERE ON ROUTE.

7

97

7

97

7

97

7

97

R98PR

62
5%

CH
402

402

402

402

402

H_CPURST_N

2

1

R109PR

2

1

0

5%

EMPTY

R110PR

2

1

5%

0

EMPTY

R111PR

1

2

0

5%

EMPTY

R113PR

2

1

0

5%

EMPTY

7

R94PR

62
5%

CH
402

CAD NOTE:

H_BPM3_2

H_BPM2_2

H_BPM0_2

H_BPM1_2

R95PR

2

1K

5%

402

EMPTY

CAD NOTE: CAD NOTE:

PLACE TCK/TDI/TMS

1

TERMINATION NEAR CPU

R99PR

62
5%

CH
402

2

TERMINATION IDEALLY TO BE PLACED
NEXT TO IT OR WITHIN 1.5 OF CPU.

6

BI

6

BI

6

BI

7

BI

2

1

1

R92PR

62
5%

CH
402

6

TPEV_H_CPURST_XDP_R_N

97

97

97

97

97

OUT

PLACE TDO TERMINATION
NEAR XDP CONNECTOR

1

R126PR

62
5%

CH
402

2

H_TDO
H_TDI
H_TMS
H_TCK
H_TRST_N

OUT
OUT
OUT

OUT

1

R93PR

62
5%

EMPTY
402

2

XDP_TESTIN_N

7

97

IN

7

97

7

97

7

97

7

97

5
4

3

2

1

H_BPM_N<5..0>

0

B

9

BPM0*

7

BPM1*

6

BPM2*

4

BPM3*

3

BPM4*

1

BPM5*

16

100M_CLK_DP

18

CK_XDP_R_DP

97

IN

CK_XDP_R_DN

97

VTT_OUT_RIGHT

105

A

CK_H_XDP_DN

29

IN

CK_H_XDP_DP

29

IN

XDP_CLKOUT_DN

7

IN

XDP_CLKOUT_DP CK_XDP_R_DP

7

IN

8

6789397

IN

1

R108PR

1.5K

5%
EMPTY

7

402

2

XDP_PWRGD

I102
I103

CK_XDP_R_DN

OUT

OUT
OUT

6

2

1

R106PR

0

5%

402

EMPTY

2

1

R107PR

5%

0

EMPTY402

2

1

R104PR

0

5%

402

EMPTY

2

1

R105PR

0

5%

EMPTY

402

70
70

105

97

97

97

IN

BI
BI

6789397

IN

SMB_CLK_MAIN
SMB_DATA_MAIN

VTT_OUT_RIGHT

27

28

27

28

5

13
15

22
24

14
28

100M_CLK_DN
XDP_H_CLK_DP

XDP_H_CLK_DN
SCL

SDA
VTT
NC

45

1

R103PR

51

OUT

97

5%
CH

402

2

3

PLACE BPM TERMINATI ON NEAR CPU

678

7

97

OUT

J2BC

XDP_SSA

1

BOM NO TE:

STUFF FOR CRB BOARD

23

TDO

29

TDI

31

TMS

30

TCK

25

TRST*

DBR*

GND
GND
GND
GND
GND
GND
GND
GND

10
19
21
12

2
5
8
11
17
20
26
27

PWRGOOD

RESET*

TESTIN*

EMPTY

Sun Mar 18 18:45:11 2007

4 2

3

1

2

R102PR

51
5%

CH
402

6789397

1

2

105

2

CAD NOTE:

VTT_OUT_LEFT

IN

1

R58PR
51
5%

CH

2

402

H_TDO
H_TDI
H_TMS
H_TCK
H_TRST_N

XDP_PWRGD

TPEV_H_CPURST_XDP_R_N

FP_RST_N
XDP_TESTIN_N

BPAGE DRAWING

frostburg_fabc.sch_1.97

3

VTT_OUT_RIGHT

IN

1

R101PR

R100PR

51

51

5%

5%

CH

CH

402

402

2

0

1

1

R61PR
51
5%

CH
402

R77PR
51
5%

CH

2

402

97

IN

97

IN

7

97

IN

7

97

OUT

7

97

OUT

7

97

OUT

7

97

OUT

7

33 36 51

OUT

97

IN

1

2

[PAGE_TITLE=PRIMARY XDP-LITE]

2

1

2

R96PR

51
5%

CH
402

2

1

4

1

R78PR
51
5%

CH

2

402

70

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

MODULE REV DETAILS

MODULE NAME

BW_ATX_CORE 5-5-061.06.00

R97PR

51
5%

CH
402

5

H_BPM_N<5..0>

H_BPM0_2
H_BPM1_2
H_BPM3_2
H_BPM2_2

DOCUMENT_NUMBER

OUT
OUT
OUT
OUT

xxxxxx

BI

6

97

7

97

6

97

6

97

REV

7

1

97

PAGE REV

97

1

DATE

D

C

B

A

3.01

CR-98 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE98

8

PCIE/PATA BRIDGE

76

828386105

D

C

3438

8292

V_1P5_ICH

9

IN

B

OUT

HSI2_DP

31

OUT

10%

2

10%

10V
X5R
402

C30PT

10V
X5R
402

.1UF

.1UF

C29PT

2

HSI2_DN

31

A

IN

CK_XT_25M_PATA

29

8

7

131416

17

18

213438

VCC3

1

1

1

47101

102

69

BOM NO TE:

NEVER STUFF BOTH

1

EMPTY

M56PT

MULTI

7

M53PT

MULTI

68

402

6

M48PT

V_1P25_CORE

IN

M44PT

1

MULTI

M54PT

1

MULTI

M55PT

1

MULTI

2

1

FB

29

IN

29

IN

31

IN

31

IN

21223336

OUT

13

33

IN

2

BOM NO TE:

Y1PT: USE MOD FLE TO REPLACE WITH IPN:A93545-001

1

2

FB

2

FB

2

FB

1

C19PT2C20PT
1000PF

.01UF

10%

10%

50V

25V

2

X7R

X7R

402

4021402

CK_PE_100M_PATA_DN

CK_PE_100M_PATA_DP
HSI2_C_DN
HSI2_C_DP
HSO2_C_DN
HSO2_C_DP

WAKE_N
PLTRST_N

R57PT

1

2

CK_XT_25M_PATA_R

0CH5%

402

MULTI

V_PATA_VDDIO

1

C26PT
10UF
20%

6.3V

2

X5R
805

V_PATA_VAA1

1

C11PT
1000PF
10%
50V

2

X7R
402

1

2

1

2

C15PT
1000PF
10%
50V
X7R
402

2

C23PT

18PF
5%
50V
COG
603

FB

C21PT

X5R

2

1

2

1

C7PT

.1UF
10%
10V

2

X5R
402

1

C12PT
.01UF .1UF
10%
25V

2

X7R
402

1

C16PT
.01UF
10%
25V

2

X7R
402

1

.1UF
10%
10V

2

R49PT

1

100

EMPTY

402

R50PT

1

0

402

A93545-011

Y1PT

25.000MHZ

1

SM
XTAL

C1PT
.1UF
10%
10V
X5R
402

2

1

2

C22PT

2.2UF
10%

6.3V
X5R
603

5%

6

2

5%
CH

5

C8PT
.1UF
10%
10V
X5R
402

1

2

1

2

1

2

2

1

2

1

C2PT
.1UF
10%
10V

2

X5R
402

1

C9PT
.1UF
10%
10V

2

X5R
402

1

C13PT
10%

10V

2

X5R
402

1

C17PT
.1UF
10%
10V

2

X5R
402

P_PLTRST_N

P_XTLIN_N

P_XTLOUT_N

C24PT

18PF
5%
50V
COG
603

1

C3PT
.1UF
10%
10V

2

X5R
402 402

1

C10PT

2.2UF
10%

6.3V

2

X5R
603

C14PT

2.2UF
10%

6.3V
X5R
603

C18PT

2.2UF
10%

6.3V
X5R
603

TP_PATA_AVDD

TP_PATA_HSDAC_N
TP_PATA_HSDAC_P

TP_PATA_GPIO2

1

2

1

C4PT

.1UF
10%
10V

2

X5R

V_AVDDT_N
V_AVDDL_N

C25PT

47PF
5%
50V
EMPTY
402

3

C5PT
.1UF
10%
10V
X5R
402

45

1

C6PT

2.2UF
10%

6.3V

2

X5R
603

V_VDD_N

EU1PT

88SE6101

14
45
55
62

25
10

59

37
39

42
43

44

36

38
40
41

34

35
19
46

18
26

27
21
22

20
29

6

VDD
VDD
VDD
VDD
VDD

VAA1
VDDIO

VDDIO
AVDD
AVDDT

AVDDL
CLK-

CLK+
PTX­PTX+
PRX­PRX+
HSDAC­HSDAC+

GPIO2
WAKE*

PERST*
XTLIN_OSC

XTLOUT
CFG0
CFG1

TESTMODE
TP

REV=2

H_DD15
H_DD14
H_DD13
H_DD12
H_DD11
H_DD10

H_RESET*

H_DMARQ
H_DIOW*
H_DIOR*
H_IORDY

H_DMACK*

H_INTRQ

H_CS0*
H_CS1*

H_CBLID*

S_ISET

1OF1

P_CFG0_N

TP_PATA_TP
TP_PATA_TES TMODE

1

R35PT

10K

5%
EMPTY

402

2

P_CFG1_N

1

R37PT

10K
5%
CH

402

2

1

2

1

2

VCC3

R36PT
10K
5%

EMPTY
402

R38PT
10K
5%

CH
402

BPAGE DRAWING

frostburg_fabc.sch_1.98

Sun Mar 18 18:45:13 2007

4 2

H_DD9
H_DD8
H_DD7
H_DD6
H_DD5
H_DD4
H_DD3
H_DD2
H_DD1
H_DD0

H_DA1
H_DA0

H_DA2

ISET

UAO
UAI
VSS

GND

57

IDE_DD15_N

60

IDE_DD14_N

63

IDE_DD13_N

1

IDE_DD12_N

5

IDE_DD11_N

8

IDE_DD10_N

11

IDE_DD9_N

15

IDE_DD8_N

16

IDE_DD7_N
IDE_DD6_N

13

IDE_DD5_N

9

IDE_DD4_N

7

IDE_DD3_N

4

IDE_DD2_N

64

IDE_DD1_N

61
58

IDE_DD0_N

IDE_RESET_N

47

IDE_DMARQ_N

56

IDE_DIOW _N

2

IDE_DIOR_N

12

IDE_IORDY_N

3

IDE_DMACK_N

54

IDE_INTR Q_N

53

IDE_DA1_N

52

IDE_DA0_N

51

IDE_CS0_N

50

IDE_CS1_N

48

IDE_DA2_N

49

IDE_CBLID_N

17

IDE_ISET_N

33

IDE_S_ISET_N

28

TP_PATA_UAO

23

TP_PATA_UAI

24
30
31

NC

32

NC

65

IC

3

2

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

OUT
OUT
OUT
OUT

IN
IN

IN
OUT
OUT
OUT
OUT
OUT

IN

1

2

1

R40PT

6.04K
1%

CH
402

2

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

MODULE REV DETAILS

MODULE NAME

PCIE_PATA

99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99

99
99
99
99
99
99
99
99
99
99
99
99
99

R41PT

6.04K
1%

CH
402

DOCUMENT_NUMBER

xxxxxx

1.2.7

REV

1

39.2.06

PAGE REV

98

1

DATE

D

C

B

A

3.01

CR-99 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE99

8

PATA CONNECTOR

98

BI

98

BI

98

BI

98

D

BI

98

BI

98

BI

98

BI

98

BI

98

BI

98

BI

98

BI

98

BI

98

BI

98

BI

98

BI

98

BI

C

98

IN

98

IN

98

IN

98

IN

B

98

OUT

98

OUT

98

OUT

98

IN

98

IN

98

IN

98

IN

98

IN

98

OUT

IDE_RESET_N

IDE_DMARQ_N

IDE_DIOW_N

IDE_DIOR_N

IDE_IORDY_N

IDE_DMACK_N

IDE_INTRQ_N

IDE_DA1_N

IDE_DA0_N

IDE_CS0_N

IDE_CS1_N

IDE_DA2_N

IDE_CBLID_N

A

IDE_DD15_N
IDE_DD14_N
IDE_DD13_N
IDE_DD12_N
IDE_DD11_N
IDE_DD10_N
IDE_DD9_N
IDE_DD8_N

IDE_DD7_N
IDE_DD6_N
IDE_DD5_N
IDE_DD4_N
IDE_DD3_N
IDE_DD2_N
IDE_DD1_N
IDE_DD0_N

1

2

R33PT

5.6K
CH

402

7

VCC3

1

2

1

2

R31PT

5.6K
5%

CH
402

80.6

402

402

402

R32PT

10K

5%5%
CH

402

R18PT

1

402

R20PT

1

22

402

R22PT

1

22 5%

402

2

R24PT

33

2

R26PT

33

2

R28PT

33

6

45

3

2

MODULE REV DETAILS

MODULE NAME

PCIE_PATA

1.2.7

1

REV

DATE

39.2.06

D

1

1

R16PT

R15PT

33

33

5%

5%

CH

CH

402

402

2

2

1

2

R30PT

10K
5%

CH
402

1

R10PT

R9PT

33

33

5%

5%

CH

CH

402

402

2

2

1

1

1

1

1

1

1

1

R2PT

R1PT

33

33

5%

5%

CH

CH

402

402

2

2

R4PT

R3PT

33

33

5%

5%

CH

CH

402

402

2

2

R6PT

R5PT

33

33

5%

5%

CH

CH

402

402

2

2

R8PT

R7PT

33

33

5%

5%

CH

CH

402

402

2

2

R12PT

R11PT

33

33

5%

5%

CH

CH

402

402

2

2

R14PT

R13PT

33

33

5%

5%

CH

CH

402

402

2

2

1

1

1

1

1

C

IDE_C_DD10
IDE_C_DD9

HDR

IDE_C_DD8

2
4
65
8

IDE_C_DD11

10

IDE_C_DD12

12

IDE_C_DD13

1413
1615

IDE_C_DD14

18

IDE_C_DD15

22
2423
2625
28

30

TP_IDE_PRI_32

32
3433
3635
3837

40

70

107

OUT

1

10K
402

R46PT

5%
CH

1

C41PT

27PF
5%
50V

2

COG
402

B

2

A

1

C27PT

CAD NOTE:

.047UF
10%
16V

2

PLACE CLOSE AS POSSIBLE

EMPTY
603

TO IDE CONNECTOR

PATA

J1PT

2X20HDR_20

107

R17PT

33

R19PT

22 5%

R21PT

R23PT

R25PT

33

R27PT

33

R29PT

1

5%
CH

2

CH

2

1%
CH

2

1%
CH

1

5%
CH

1

5%
CH

2

1%
CH

1

2

C50PT

22PF
5%
50V
COG
402

1

2

1

C45PT

22PF
5%
50V

2

COG
402

C42PT

22PF
5%
50V
COG
402

1

C43PT

22PF
5%
50V
COG
402

2

1

C47PT

22PF
5%
50V

2

COG
402

2

1

C46PT

22PF
5%
50V

2

COG
402

1

1

C44PT

22PF
5%
50V
COG
402

C48PT

22PF
5%
50V

2

COG
402

2

402

2

1%

CH

1

402

2

5%
CH

1

80.6
402

2

CH

1

80.6
402

1

5%
CH

2
402

1

5%
CH

2
402

1

5%
CH

1

80.6
402

IDE_C_DD7
IDE_C_DD6
IDE_C_DD5
IDE_C_DD4
IDE_C_DD3
IDE_C_DD2
IDE_C_DD1
IDE_C_DD0

IDE_C_DMARQ
IDE_C_DIOW_N
IDE_C_DIOR_N
IDE_C_IORDY
IDE_C_DMACK_N
IDE_C_INTRQ
IDE_C_DA1
IDE_C_DA0
IDE_C_CS0_N

IDE_C_CS1_N

IDE_C_DA2

IDE_DMA66_DETECT_PRI

1

C49PT

22PF
5%
50V

2

COG
402

IDE_C_RST

1
3

7
9

11
17

19
21

27
29
31

39

IDE_PRI_ACT_N

BPAGE DRAWING

frostburg_fabc.sch_1.99

Sun Mar 18 18:45:14 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

99

1

3.01

CR-100 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE100

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

D

TP_TESTCAP1_1

1

C289BU

47PF
5%
50V

2

EMPTY

1

2

402

C290BU

.01UF
10%
25V
X7R
402

TP_TESTCAP1_2

C

TP_TESTCAP2_2

TP_TESTCAP3_1

1

C291BU

27PF
5%
50V

2

COG
402

TP_TESTCAP3_2

B

DESIGN NOTE:

FOR DFM

CORNER PROTECTION

TP_DFMCAP1_1

1

C302BU

10.0UF

20%

10V

2

EMPTY

TP_DFMCAP1_2

1206

TP_TESTCAP4_1

TP_TESTCAP4_2

TP_TESTCAP5_1

TP_TESTCAP5_2

TP_TESTCAP6_1

TP_TESTCAP6_2

1

2

1

2

1

2

C292BU

2.7PF

9.25%
25V
EMPTY
402

C293BU

3.3PF

.25%
50V
COG
402

C294BU

10PF
5%
50V
COG
402

TP_TESTCAP7_1

TP_TESTCAP7_2

TP_TESTCAP8_1TP_TESTCAP2_1

TP_TESTCAP8_2

TP_TESTCAP9_1

TP_TESTCAP9_2

1

2

1

2

1

2

C295BU

0.1UF
20%

16V
Y5V
402

C296BU

22PF
5%
50V
EMPTY
402

C297BU

1000PF

10%
50V
X7R
402

TP_TESTCAP10_1

TP_TESTCAP10_2

1

C298BU

100PF
5%
50V

2

COG
402

+12V

1

1K

1206

+12V

R125BU

1

1K 1%

1206

+12V

1

1K

1206

+12V

1

1K

1206

DESIGN NOTE:

R124BU

EMPTY

R126BU

R127BU

1%

EMPTY

1%

EMPTY

1%

EMPTY

+12V

R128BU

1

2

1206

+12V

R129BU

2

1

1K 1%

1206

+12V

2

1K 1%

1206

R130BU

1

+12V

R131BU

1

2

1K 1%

1206

LOADING RESISTORS FOR 12V

1%1K

EMPTY

EMPTY

EMPTY

EMPTY

2

2

2

2

A

D

C

B

A

BPAGE DRAWING

frostburg_fabc.sch_1.100
Sun Mar 18 18:45:16 2007

8

7

6

5

4 2

3

[PAGE_TITLE=TEST SITE CAPS]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

100

1

3.01